Semiconductor Structure and Method for Manufacturing the Same

Abstract

The present invention discloses a semiconductor structure, comprising a substrate, the substrate comprising a doped silicon substrate, a buried oxide layer and a silicon device layer. A trench capacitor comprises an inner electrode and a node dielectric layer located in a trench of the substrate. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. A select transistor is located in the silicon device layer and is close to the trench capacitor. The silicon device layer forms silicon fins. An embedded contact is located on top of the trench capacitor to electrically couple a doped region of the select transistor to the inner electrode of the trench capacitor. A first dielectric layer surrounds the select transistor. A second dielectric layer covers the first dielectric layer and the select transistor. A contact plug penetrates through the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack is electrically connected to the contact plug. The memory stack comprises a magnetic tunneling junction element.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor technology. More specifically, the present disclosure relates to a semiconductor memory structure and a method of manufacturing the same. Background Art

[0002] Magnetoresistive random access memory (MRAM) is an integration based on silicon CMOS and magnetic tunneling junction (MTJ) technology, and is a major emerging technology that competes fiercely with existing semiconductor memories such as SRAM, DRAM, Flash, etc.

[0003] An MRAM device typically includes a parallel first wire array, such as word lines on a horizontal plane, a parallel second wire array, such as bit lines located on a second horizontal plane, spaced apart in a direction perpendicular to the first wire, and MTJ elements inserted at each crossing position between the first wire and the second wire. Typically, access transistors may be provided below the first wire array to select certain MRAM cells within the MRAM array for read or write operations.

[0004] As is known in the art, a DRAM / MRAM cell-level hybrid structured memory (D-MRAM) with a three-transistor and single MTJ (3T-1MTJ) configuration has been developed to achieve effective power reduction for high-performance mobile SoCs.

[0005] With the help of advanced perpendicular magnetic tunneling junctions (pMTJs) that can reduce write energy and latency, D-MRAM is capable of reducing power consumption by replacing traditional SRAM caches. However, the leakage power improvement of the above-mentioned 3T-1MTJ D-MRAM device is limited due to the low storage capacitance, resulting in a low retention time. Summary of the Invention

[0006] One object of the present disclosure is to provide an improved D-MRAM device with a 3T-1MTJ configuration to solve the disadvantages or problems of the above-mentioned prior art.

[0007] On the one hand, the present disclosure provides a semiconductor structure, comprising: a substrate including a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer; a trench capacitor including an inner electrode and a node dielectric layer in a trench of the substrate, wherein the inner electrode and the node dielectric layer penetrate the buried oxide layer and extend into the doped silicon substrate; a select transistor located in the silicon device layer and close to the trench capacitor, wherein the silicon device layer forms a silicon fin; an embedded contact located on top of the trench capacitor to electrically couple a doped region of the select transistor to the inner electrode of the trench capacitor; a first dielectric layer surrounding the select transistor; a second dielectric layer covering the first dielectric layer and the select transistor; a contact plug passing through the second dielectric layer and the first dielectric layer and directly contacting the embedded contact; and a memory stack electrically connected to the contact plug, wherein the memory stack includes a magnetic tunneling junction element.

[0008] According to some embodiments, the node dielectric layer covers the sidewalls of the trench.

[0009] According to some embodiments, the inner electrode is surrounded by the node dielectric layer.

[0010] According to some embodiments, the inner electrode includes a doped polysilicon layer and a TiN layer between the node dielectric layer and the doped polysilicon layer.

[0011] According to some embodiments, the upper surface of the doped polysilicon layer is higher than the upper surface of the doped silicon substrate.

[0012] According to some embodiments, the embedded contact is buried in the silicon device layer, the first dielectric layer, and the buried oxide layer.

[0013] According to some embodiments, the embedded contact includes a fin-shaped contact portion, and the fin-shaped contact portion is clamped between the forked lower part of the contact plug.

[0014] According to some embodiments, a metal gate is disposed on the silicon fin.

[0015] According to some embodiments, the embedded contact includes a metal layer, the metal layer is wrapped by a silicided metal layer, and a part of the silicided metal layer is between the metal layer and the inner electrode.

[0016] According to some embodiments, the silicided metal layer is between the silicon fin and the fin-shaped contact portion.

[0017] According to some embodiments, the metal layer includes W, Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combination thereof.

[0018] According to some embodiments, the metal silicide layer comprises tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide.

[0019] According to some embodiments, the contact plug is a tungsten contact plug.

[0020] According to some embodiments, the trench capacitor comprises a stepped structure around an upper portion of the trench.

[0021] According to some embodiments, the stepped structure is constituted by the node dielectric layer and the inner electrode.

[0022] According to some embodiments, the memory stack is formed in a circuit layer, and the memory stack is electrically connected to the contact plug through the circuit layer.

[0023] According to some embodiments, the memory stack is disposed on the contact plug.

[0024] According to some embodiments, the magnetic tunneling junction element comprises a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer.

[0025] According to some embodiments, the reference layer comprises a magnetic material, and the magnetic material comprises Co and Fe.

[0026] According to some embodiments, the reference layer comprises a magnetic superlattice structure, and the magnetic superlattice structure is a repeating alternating layer comprising two or more materials, where the materials comprise (Co / Pt)n, (Co / Pd)n, (Co / Ni)n, (CoFe / Pt)n, (Co / Pt(Pd))n, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are provided to facilitate a further understanding of the present invention, and form a part of this specification. The embodiments of the present invention described together with the content of the specification help to explain the principles of the present invention. In the drawings:

[0028] Figure 1 is a top view of a substrate formed with a deep trench capacitor and a metal contact according to an embodiment of the present invention;

[0029] Figure 1A is along Figure 1 a cross-sectional view taken along the tangent I-I' in

[0030] Figure 2 is a top view of a substrate formed with a deep trench capacitor and a metal contact according to an embodiment of the present invention, showing a patterned hard mask layer;

[0031] Figure 2Aand Figure 2B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 2 respectively;

[0032] Figure 3 is a top view of a substrate with a formed deep trench capacitor and metal contacts according to an embodiment of the present invention, showing silicon fins and fin contacts;

[0033] Figure 3A and Figure 3B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively;

[0034] Figure 4A and Figure 4B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after removing the patterned hard mask layer and completing the FCVD process;

[0035] Figure 5A and Figure 5B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after forming dummy gates;

[0036] Figure 6A and Figure 6B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after depositing the POC layer and the FCVD oxide layer;

[0037] Figure 7A and Figure 7B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after completing the Siconi TM etching process;

[0038] Figure 8A and Figure 8B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after completing the HDPCVD process;

[0039] Figure 9A and Figure 9B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after completing the dummy polysilicon removal (DPR) process;

[0040] Figure 10A and Figure 10Bare cross-sectional views taken along the Figure 3 tangents I-I' and II-II' in

[0041] Figure 11A and Figure 11B respectively, showing the semiconductor structure after the replacement metal gate (RMG) process is completed; Figure 3 are cross-sectional views taken along the

[0042] Figure 12A tangents I-I' and II-II' in Figure 12B and Figure 3 respectively, showing the semiconductor structure after contact plugs are formed;

[0043] Figure 13A and Figure 13B are cross-sectional views taken along the Figure 3 tangents I-I' and II-II' in

[0044] Figure 14A and Figure 14B respectively, showing the semiconductor structure after MTJ elements are formed on the contact plugs; Figure 3 and

[0045] are cross-sectional views taken along the

[0046] tangents I-I' and II-II' in

[0047] 10 substrate

[0048] 101 doped silicon substrate

[0049] 101a upper surface

[0050] 102 buried oxide layer

[0051] 103 silicon device layer

[0052] 103a top surface

[0053] 103f silicon fin

[0054] 110 hard mask layer

[0055] 110p patterned hard mask layer

[0056] 120 Silicon oxide film

[0057] 140 POC layer

[0058] 150 FCVD oxide layer

[0059] 160 HDP oxide layer

[0060] 170 Overlayer

[0061] 180 Dielectric layer

[0062] 200 Embedded contact

[0063] 200a Top surface

[0064] 200f Fin contact

[0065] 201 Node dielectric layer

[0066] 202 Barrier layer 202

[0067] 203 Doped polysilicon layer

[0068] 203a Upper surface

[0069] 210 Metal layer

[0070] 220 Silicided metal layer

[0071] 300 Memory stack

[0072] 320 MTJ element

[0073] 410 Overlayer

[0074] 420 Dielectric layer

[0075] 420a Through hole

[0076] BE Bottom electrode

[0077] CH Contact hole

[0078] CT Trench

[0079] CW Contact plug

[0080] DD Doped region

[0081] DG dummy gate

[0082] F Forked lower part

[0083] GT Gate trench

[0084] IE Internal capacitor electrode

[0085] MG Metal Gate

[0086] S Step Structure

[0087] Top Surfaces of S1 and S2

[0088] SP Sidewall Sub

[0089] ST Select Transistor

[0090] TC Capacitor

[0091] TE Top Electrode

[0092] VA Via Plug Detailed Implementation Manner

[0093] The advantages and features of the embodiments can be more easily understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings. However, the embodiments can be embodied in many different forms and should not be construed as limited to those set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the exemplary implementation manners of the embodiments to those skilled in the art. Therefore, the embodiments will be defined only by the appended claims. Throughout the specification, the same reference numerals represent the same elements.

[0094] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0095] It should be understood that when an element or layer is referred to as "on", "connected to" or "coupled to" another element or layer, it can be directly above, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0096] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures). Accordingly, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, these embodiments should not be construed as limited to the particular shapes of regions shown herein but should include deviations in shapes that result, for example, from manufacturing. For example, an implantation region illustrated as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted to the non-implanted region. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of the device and are not intended to limit the scope of the embodiments.

[0097] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0098] Magnetic tunneling junction (MTJ) elements can be based on the tunneling magnetoresistance (TMR) effect, where the layer stack has a structural configuration of two ferromagnetic layers separated by a thin non-magnetic dielectric layer. If the non-magnetic dielectric layer is thin enough (typically a few nanometers), electrons can tunnel from one ferromagnet to the other. In an MRAM device, the MTJ element is typically formed between a bottom electrode and a top electrode. For example, it can be formed by sequentially depositing a seed layer, an antiferromagnetic (AFM) pinning layer, a ferromagnetic "pinned" layer, a thin channel barrier layer, a ferromagnetic "free" layer, and a capping layer. The AFM layer holds the magnetic moment of the pinned layer in a fixed direction.

[0099] The present disclosure relates to an improved semiconductor structure that is particularly applicable to D-MRAM devices having a 3T-1MTJ architecture. By employing a deep trench (DT) capacitor, the storage capacitance and data retention time of the D-MRAM device can be significantly increased. Since the DT capacitor can provide a larger capacitance, the retention time of the D-MRAM device is significantly increased. The proposed semiconductor structure can significantly reduce the data refresh frequency, thereby reducing the leakage power of the D-MRAM device.

[0100] Figure 1 is a top view of a substrate formed with a deep trench capacitor and a metal contact according to an embodiment of the present invention. Figure 1A is along Figure 1 the tangent I-I' in Figure 1 and Figure 1AAs shown, the substrate 10 may be a silicon-on-insulator (SOI) substrate, including a doped silicon substrate 101, a buried oxide layer 102, and a silicon device layer 103. According to one embodiment, for example, the above SOI structure may be a SIMOX wafer or a bonded wafer, both of which are commercially available.

[0101] According to one embodiment, for example, the doped silicon substrate 101 may be an N-type heavily doped silicon substrate, and the silicon device layer 103 may be a P-type silicon layer. According to one embodiment, for example, the silicon device layer 103 may have a thickness of about 50 - 500 nanometers (nm), the buried oxide layer 102 may have a thickness of about 100 - 500 nm, and the doped silicon substrate 101 may be 50 - 500 micrometers (μm), but is not limited thereto.

[0102] According to one embodiment, a hard mask layer 110 may be deposited on the top surface 103a of the silicon device layer 103. For example, the hard mask layer 110 may include silicon nitride and may be deposited by a known chemical vapor deposition (CVD) method.

[0103] A capacitor TC is formed in the substrate 10. The capacitor TC may penetrate the buried oxide layer 102 and may extend to a predetermined depth (e.g., several micrometers) in the doped silicon substrate 101. The capacitor TC includes a trench CT and a node dielectric layer 201, such as HfSiO x . The node dielectric layer 201 conformally lines the sidewalls of the trench CT. The node dielectric layer 201 may extend upward to the sidewalls of the buried oxide layer 102. The sidewalls of the buried oxide layer 102 may be partially covered by the node dielectric layer 201.

[0104] According to one embodiment, the capacitor TC further includes an internal capacitor electrode IE surrounded by the node dielectric layer 201. The node dielectric layer 201 electrically isolates the internal capacitor electrode IE from the doped silicon substrate 101, which serves as another capacitor electrode or an external electrode of the capacitor TC. According to one embodiment, the internal capacitor electrode IE may include a barrier layer 202 and a doped polysilicon layer 203 surrounded by the barrier layer 202. The barrier layer 202 is located between the node dielectric layer 201 and the doped polysilicon layer 203. The barrier layer 202 may include titanium nitride (TiN), tantalum nitride (TaN), or other metals having a low ohmic contact resistance.

[0105] According to one embodiment, the upper surface 203a of the doped polysilicon layer 203 may be higher than the upper surface 101a of the doped silicon substrate 101. In some embodiments, the upper surface 203a of the doped polysilicon layer 203 may be higher than the upper surface of the barrier layer 202. According to one embodiment, the barrier layer 202 may protrude from the upper surface 203a of the doped polysilicon layer 203. The upper end of the node dielectric layer 201, the upper end of the barrier layer 202, and the upper surface 203a of the doped polysilicon layer 203 may form a step structure S located above the trench CT.

[0106] According to one embodiment, an embedded contact 200 is provided on top of the internal capacitor electrode IE. The embedded contact 200 is buried in the silicon device layer 103 and the buried oxide layer 102. According to one embodiment, the embedded contact 200 may include a metal layer 210, such as tungsten (W), surrounded by a silicided metal layer 220, such as tungsten silicide (WSix). A portion of the silicided metal layer 220 is interposed between the metal layer 210 and the internal capacitor electrode IE. According to one embodiment, the top surface 200a of the embedded contact 200 is coplanar with the top surface 103a of the silicon device layer 103. According to one embodiment, the embedded contact 200 is covered by a hard mask layer 110.

[0107] According to one embodiment, for example, the metal layer 210 may include Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combination thereof. According to one embodiment, for example, the silicided metal layer 220 may include cobalt silicide (CoSi x )、nickel silicide (NiSi x ) or titanium silicide (TiSi x ), but is not limited thereto.

[0108] According to one embodiment, for example, to form the silicided metal layer 220, a thin metal layer (not shown), such as W, Co, Ni, or Ti, is deposited on the substrate 10. The thin metal layer conformally covers the inner surface of the trench CT, including the surface of the capacitor TC. The thin metal layer is in direct contact with the exposed sidewalls of the silicon device layer 103, the polysilicon spacer layer deposited on the sidewalls of the buried oxide layer 102, and the doped polysilicon layer 203. Subsequently, a heat treatment or annealing process is performed, for example, rapid thermal annealing (RTA) is executed, such that the thin metal layer reacts with the exposed sidewalls of the silicon device layer 103, the polysilicon spacer layer, and the doped polysilicon layer 203, thereby forming the silicided metal layer 220. The unreacted metal layer can be removed using methods known in the art.

[0109] Please refer to Figure 2 、 Figure 2A and Figure 2B . Figure 2is a top view of a substrate with a formed deep trench capacitor and metal contacts, according to an embodiment of the present invention, showing a patterned hard mask layer. Figure 2A and Figure 2B are cross-sectional views taken along the Figure 2 tangents I-I' and II-II' in Figure 2 , Figure 2A and Figure 2B respectively. As shown in Figure 2 , the hard mask layer 110 undergoes a photolithography process and an etching process to form a patterned hard mask layer 110p on the silicon device layer 103. According to one embodiment, the patterned hard mask layer 110p may have a strip pattern (see Figure 2 ), and may partially overlap with the embedded contact 200.

[0110] Please refer to Figure 3 , Figure 3A and Figure 3B . Figure 3 is a top view of a substrate with a formed deep trench capacitor and metal contacts, according to an embodiment of the present invention, showing silicon fins and fin contacts. Figure 3A and Figure 3B are cross-sectional views taken along the Figure 3 tangents I-I' and II-II' in Figure 3 , Figure 3A and Figure 3B respectively. As shown in Figure 3 , Figure 3A and Figure 3B , an anisotropic dry etching process is performed using the patterned hard mask layer 110p as an etching hard mask to etch the silicon device layer 103 and the upper part of the embedded contact 200 not covered by the patterned hard mask layer 110p, thereby forming silicon fins 103f and fin contacts 200f connected to the silicon fins 103f.

[0111] Please refer to Figure 4A and Figure 4B . Figure 4A and Figure 4B are cross-sectional views taken along the Figure 3 tangents I-I' and II-II' in Figure 4A and Figure 4B respectively. As shown in Figure 4A and Figure 4B , after the silicon fins 103f and fin contacts 200f are formed, the patterned hard mask layer 110p is removed. After removing the patterned hard mask layer 110p, a chemical vapor deposition (CVD) process, such as a flow CVD (FCVD) process, may be performed to deposit a silicon oxide film 120 on the substrate 10. Then, a chemical mechanical polishing (CMP) process is performed on the silicon oxide film 120 to form a planarized top surface of the silicon oxide film 120. At this time, the silicon fins 103f and fin contacts 200f are surrounded by the planarized silicon oxide film 120, wherein a flush surface is formed by the silicon fins 103f, fin contacts 200f, and the silicon oxide film 120.

[0112] Please refer to Figure 5A and Figure 5B . Figure 5A and Figure 5B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively. As shown in Figure 5A and Figure 5B , subsequently, a dummy gate DG is formed on the substrate 10. According to one embodiment, for example, the dummy gate DG can be a polysilicon gate. After forming sidewall spacers SP on the sidewalls of the dummy gate DG, an ion implantation process can be performed to form doped regions DD in the silicon fins 103f on both sides of the dummy gate DG. For example, N + doped regions. One of the doped regions DD is electrically connected to the fin contact portion 200f.

[0113] Please refer to Figure 6A and Figure 6B . Figure 6A and Figure 6B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively. As shown in Figure 6A and Figure 6B , after forming the dummy gate DG and the doped regions DD, a polysilicon open CMP (POC) layer 140 and an FCVD oxide layer 150 are deposited on the substrate 10. Then, a CMP process is performed on the FCVD oxide layer 150 to form a flat top surface. At this time, the dummy gate DG is surrounded by the planarized FCVD oxide layer 150.

[0114] Please refer to Figure 7A and Figure 7B . Figure 7A and Figure 7B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively. As shown in Figure 7A and Figure 7B , a selective dry etching process is performed, for example, a Siconi TM etching process, to remove the upper portion of the FCVD oxide layer 150. According to one embodiment, the Siconi TM etching process can involve using a hydrogen source, for example, ammonia (NH3), in combination with using a fluorine source, for example, nitrogen trifluoride (NF3).

[0115] Please refer to Figure 8A and Figure 8B . Figure 8A and Figure 8B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively. As shown inFigure 8A and Figure 8B As shown in Figure 8B , after the FCVD oxide layer 150 is recessed, a high density plasma CVD (HDPCVD) process is performed to deposit an HDP oxide layer 160 on the substrate 10. Then, a CMP process is performed on the HDP oxide layer 160 to form a planarized top surface.

[0116] Please refer to Figure 9A and Figure 9B . Figure 9A and Figure 9B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, which show the semiconductor structure after the dummy polysilicon removal (DPR) process is completed. As shown in Figure 9A and Figure 9B , subsequently, an etching process can be performed to remove the dummy gate DG, thereby forming a gate trench GT.

[0117] Please refer to Figure 10A and Figure 10B . Figure 10A and Figure 10B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, which show the semiconductor structure after the replacement metal gate (RMG) process is completed. As shown in Figure 10A and Figure 10B , then a metal gate MG is formed in the gate trench GT. Since the RMG process is known in the art, its details will not be described herein. For example, the RMG process can include depositing a high dielectric constant (high-k) dielectric layer, a barrier layer such as TiN, a work function metal layer, and / or a low resistance metal such as tungsten, but is not limited thereto.

[0118] A select transistor ST is formed in the silicon fin 103f. The select transistor ST includes a metal gate MG on the silicon fin 103f and a doped region DD in the silicon fin 103f that serves as a source or a drain. For example, the doped region DD can be formed by using an ion implantation process and an annealing process. Through the embedded contact 200, the internal capacitor electrode IE is electrically coupled to the doped region DD of the select transistor ST. A salicide layer 220 forms a low resistance ohmic contact between the doped region DD and the metal layer 210.

[0119] Please refer to Figure 11A and Figure 11B . Figure 11A and Figure 11B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, which show the semiconductor structure after the contact plugs are formed. As shown in Figure 11A and Figure 11BAs shown, a cover layer 170 such as a silicon nitride layer is deposited over the substrate 10. Subsequently, a dielectric layer 180 is deposited over the cover layer 170. A photolithography process and a dry etching process are performed to etch the dielectric layer 180, the cover layer 170, the HDP oxide layer 160, the FCVD oxide layer 150, the POC layer 140, and the silicon oxide film 120 surrounding the fin contact 200f, thereby forming a contact hole CH. Subsequently, the contact hole CH is filled with a conductive layer such as a tungsten layer, and a CMP process is performed on the conductive layer, thereby forming a contact plug CW in the contact hole CH. As Figure 11B shown, the fin contact 200f is sandwiched by the forked lower portion F of the contact plug CW. According to one embodiment, the top surface S1 of the contact plug CW is coplanar with the top surface S2 of the surrounding dielectric layer 180.

[0120] Please refer to Figure 12A and Figure 12B . Figure 12A and Figure 12B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, showing the semiconductor structure after forming the MTJ element on the contact plug. As Figure 12A and Figure 12B shown, a memory stack 300 can be formed on the contact plug CW. In some embodiments, the memory stack 300 can be formed in a circuit layer, wherein the memory stack 300 is electrically connected to the contact plug CW through the circuit layer. The memory stack 300 can include an MTJ element 320 sandwiched between a bottom electrode BE and a top electrode TE. The bottom electrode BE is electrically coupled to the doped region DD and the internal capacitor electrode IE through the contact plug CW. For example, the bottom electrode BE can include NiCr, Ru, Cu, Ta, TaN, Ti, TiN, or any combination thereof.

[0121] According to one embodiment, the MTJ element 320 can include a layered structure, including, but not limited to, a reference layer (or pinned layer), a tunneling barrier layer directly stacked on the reference layer, and a free layer directly stacked on the tunneling barrier layer.

[0122] According to one embodiment, the reference layer may comprise a magnetic material of Co and Fe. According to one embodiment, the reference layer may comprise CoFeB, CoFeBTi, CoFeBZr, CoFeBHf, CoFeBV, CoFeBTa, CoFeBCr, CoFeNi, CoFeTi, CoFeZr, CoFeHf, CoFeV, CoFeNb, CoFeTa, CoFeCr, CoFeMo, CoFeW, CoFeAl, CoFeSi, CoFeGe, CoFeP, or any combination thereof. According to one embodiment, the reference layer may comprise a magnetic superlattice structure comprising repeating alternating layers of two or more materials, the materials comprising (Co / Pt)n, (Co / Pd)n, (Co / Ni)n, (CoFe / Pt))n, (Co / Pt(Pd))n, or any combination thereof, where n is an integer.

[0123] According to one embodiment, for example, the tunneling barrier layer may comprise an insulator comprising MgO, AlO x , MgAlO, MgZnO, HfO, or any combination thereof. According to one embodiment, for example, the free layer comprises Fe, Co, B, Ni, or any combination thereof.

[0124] According to one embodiment, the MTJ element 320 may further comprise a capping layer disposed between the top electrode TE and the free layer, such as MgO. According to one embodiment, for example, the top electrode TE may be made of ruthenium (Ru) having a hexagonal close-packed (hcp) crystal structure. For example, during an ion beam etching process, the top electrode TE may also serve as an etch stop layer. The MTJ element 320 is electrically connected to the upper bit line through the top electrode TE.

[0125] Please refer to Figure 13A and Figure 13B . Figure 13A and Figure 13B are cross-sectional views taken along the tangents I-I' and II-II' in Figure 3 respectively, which show the semiconductor structure after forming the MTJ capping layer on the memory stack 300. As Figure 13A and Figure 13B shown, a capping layer 410 such as a silicon nitride layer is formed on the memory stack 300. Subsequently, a dielectric layer 420 is deposited on the capping layer 410. A photolithography process and a dry etching process are performed to form a via hole 420a in the dielectric layer 420 and directly above the memory stack 300. A portion of the top electrode TE may be exposed in the via 420a.

[0126] Please refer to Figure 14A and Figure 14B . Figure 14A andFigure 14B Cross-sectional views taken along the Figure 3 tangents I-I' and II-II' in Figure 14A are shown, respectively, which illustrate the semiconductor structure after forming vias in the memory stack 300. As Figure 14B shown, via plug VA is formed in via 420a and electrically connected to the top electrode TE. For example, a tungsten layer is deposited into via 420a. Then, a CMP process is performed on the tungsten layer to form a flat top surface.

[0127] It is advantageous to use the present disclosure because the storage capacitance and data retention time of the D-MRAM device can be significantly increased by incorporating deep trench (DT) capacitors. Since the DT capacitor can provide a larger capacitance, the retention time of the D-MRAM device is significantly increased. The semiconductor structure proposed by the present disclosure can significantly reduce the data refresh frequency, thereby reducing the leakage power of the D-MRAM device. In addition, since the embedded contact includes a fin-shaped contact portion clamped by the lower part of the tungsten contact plug, the capacitor charging and discharging time of the D-MRAM device can be greatly reduced.

[0128] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising: A substrate, the substrate comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer; A trench capacitor, comprising an inner electrode and a node dielectric layer in a trench of the substrate, wherein the inner electrode and the node dielectric layer penetrate the buried oxide layer and extend into the doped silicon substrate; A select transistor, located in the silicon device layer and adjacent to the trench capacitor, wherein the silicon device layer forms silicon fins; An embedded contact, located on top of the trench capacitor, electrically coupling a doped region of the select transistor to the inner electrode of the trench capacitor; A first dielectric layer, surrounding the select transistor; A second dielectric layer, covering the first dielectric layer and the select transistor; A contact plug, passing through the second dielectric layer and the first dielectric layer and making direct contact with the embedded contact; And A memory stack, electrically connected to the contact plug, wherein the memory stack comprises a magnetic tunneling junction element sandwiched between a bottom electrode and a top electrode, Wherein, the embedded contact comprises a fin-shaped contact portion, and the fin-shaped contact portion is sandwiched between forked lower portions of the contact plug, and a top surface of the contact plug is coplanar with a top surface of the first dielectric layer, A via is formed above the memory stack, a part of the top electrode is exposed in the via, and a via plug is formed in the via and electrically connected to the top electrode.

2. The semiconductor structure according to claim 1, wherein, The node dielectric layer covers sidewalls of the trench.

3. The semiconductor structure according to claim 2, wherein, The inner electrode is surrounded by the node dielectric layer.

4. The semiconductor structure according to claim 3, wherein, The inner electrode comprises a doped polysilicon layer and a TiN layer between the node dielectric layer and the doped polysilicon layer.

5. The semiconductor structure according to claim 4, wherein, An upper surface of the doped polysilicon layer is higher than an upper surface of the doped silicon substrate.

6. The semiconductor structure according to claim 1, wherein, The embedded contact is buried in the silicon device layer, the first dielectric layer, and the buried oxide layer.

7. The semiconductor structure according to claim 1, wherein, A metal gate is provided on the silicon fins.

8. The semiconductor structure according to claim 1, wherein, The embedded contact comprises a metal layer, the metal layer is wrapped by a silicided metal layer, and a part of the silicided metal layer is between the metal layer and the inner electrode.

9. The semiconductor structure according to claim 8, wherein, The silicided metal layer is between the silicon fins and the fin-shaped contact portion.

10. The semiconductor structure according to claim 8, wherein, The metal layer comprises W, Ti, TiN, Ta, TaN, Cu, Au, Ni, or any combination thereof.

11. The semiconductor structure according to claim 8, wherein, The silicided metal layer comprises tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide.

12. The semiconductor structure according to claim 1, wherein, The contact plug is a tungsten contact plug.

13. The semiconductor structure according to claim 1, wherein, The trench capacitor comprises a stepped structure around an upper portion of the trench.

14. The semiconductor structure according to claim 13, wherein, The stepped structure is constituted by the node dielectric layer and the inner electrode.

15. The semiconductor structure according to claim 1, wherein, The memory stack is formed in a circuit layer, and the memory stack is electrically connected to the contact plug through the circuit layer.

16. The semiconductor structure according to claim 1, wherein, The memory stack is disposed on the contact plug.

17. The semiconductor structure according to claim 1, wherein, The magnetic tunneling junction element comprises a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer.

18. The semiconductor structure according to claim 17, wherein, The reference layer comprises a magnetic material, and the magnetic material comprises Co and Fe.

19. The semiconductor structure according to claim 17, wherein, The reference layer includes a magnetic superlattice structure, and the magnetic superlattice structure is a repetitive alternating layer including two or more materials, wherein the materials include (Co / Pt)n, (Co / Pd)n, (Co / Ni)n, (CoFe / Pt)n, (Co / Pt(Pd))n, or any combination thereof.

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