Semiconductor memory device and method of manufacturing the same

Abstract

This invention discloses a semiconductor memory device and a method for fabricating the same, wherein the semiconductor memory device includes a substrate; a first dielectric layer located on the substrate; a bottom electrode located on the first dielectric layer; a second dielectric layer located on the first dielectric layer; a top electrode located in the second dielectric layer, the top electrode including a lower portion and a tapered upper portion, the lower portion being located around the bottom electrode; a third dielectric layer located above the bottom electrode and around the tapered upper portion of the top electrode; a resistor switching layer located between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode, and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode; and an air gap located in the third dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a resistive random access memory (RRAM) device and its fabrication method. Background Technology

[0002] Resistive random access memory (RRAM) is a general term for reprogrammable devices that can be set to low or high resistance states. RRAM typically consists of a dielectric layer disposed between two electrodes. Some types of RRAM conduct electricity by forming different filaments in confined regions of the dielectric. Other types of RRAM conduct electricity by changing their properties throughout the dielectric region.

[0003] RRAM stores information by utilizing the variable resistance of a dielectric layer between two electrodes. This dielectric layer, acting as a resistive layer, is typically insulating, but can be made conductive by filaments or conductive paths formed after a sufficiently high voltage is applied (i.e., through a formation process). The formation of conductive paths can occur through various mechanisms, including defects, metal migration, etc. Once formed, the filaments can still be reset (i.e., broken, resulting in high resistance) or set (i.e., reformed, resulting in low resistance) by applying an appropriate voltage.

[0004] High-density RRAM structures are typically formed during back-end metallization (BEOL) processes, which leads to high parasitic capacitance and RC delay. Therefore, there is still a need in this technological field for an improved RRAM structure that can mitigate the parasitic capacitance problem. Summary of the Invention

[0005] The main objective of this invention is to provide a semiconductor memory device and a method for manufacturing the same, so as to overcome the shortcomings and disadvantages of the prior art.

[0006] The present invention provides a semiconductor memory device comprising: a substrate; a first dielectric layer on the substrate; a bottom electrode on the first dielectric layer; a second dielectric layer on the first dielectric layer; a top electrode in the second dielectric layer, the top electrode comprising a lower portion and a tapered upper portion, the lower portion being located around the bottom electrode; a third dielectric layer above the bottom electrode and surrounding the tapered upper portion of the top electrode; a resistor switching layer between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode, and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode; and an air gap in the third dielectric layer.

[0007] According to an embodiment of the present invention, the semiconductor memory device further includes a dielectric barrier layer located between the second dielectric layer and the first dielectric layer.

[0008] According to an embodiment of the present invention, the top electrode is disposed on the dielectric barrier layer.

[0009] According to an embodiment of the present invention, the resistor switching layer comprises NiO. x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x 、Nb y O x Or Y y O x , where x>0, y>0.

[0010] According to an embodiment of the present invention, the top electrode comprises TiN, TaN, or Pt.

[0011] According to an embodiment of the present invention, the top surface of the second dielectric layer is flush with the top surface of the top electrode.

[0012] According to an embodiment of the present invention, the semiconductor memory device further includes a metal layer disposed in the third dielectric layer and electrically connected to the top electrode.

[0013] According to an embodiment of the present invention, the top surface of the third dielectric layer is flush with the top surface of the top electrode and the top surface of the second dielectric layer.

[0014] According to an embodiment of the present invention, the semiconductor memory device further includes a top cover layer covering the second dielectric layer, the top electrode, and the third dielectric layer; a fourth dielectric layer located on the top cover layer; and a conductive via disposed in the fourth dielectric layer and electrically connected to the top electrode.

[0015] According to an embodiment of the present invention, the thickness of the upper conical portion of the top electrode is greater than the thickness of the lower portion of the top electrode.

[0016] Another aspect of the present invention discloses a method for forming a semiconductor memory device, characterized by comprising: providing a substrate; forming a first dielectric layer on the substrate; depositing a first conductive layer on the first dielectric layer; depositing a hard mask layer on the first conductive layer; patterning the first conductive layer into a bottom electrode by forming a first opening in the hard mask layer and the first conductive layer; depositing a second dielectric layer in the first opening and on the hard mask layer and the first dielectric layer; polishing the second dielectric layer to expose a top surface of the hard mask layer; patterning the second dielectric layer by etching the second dielectric layer to form a second opening in the second dielectric layer, wherein the second opening includes a lower portion and a tapered upper portion; depositing a resistor switching layer in the second opening; depositing a second conductive layer on the resistor switching layer and the second opening; and polishing the second conductive layer and the resistor switching layer until the top surface of the hard mask layer is exposed, thereby forming a top electrode in the second opening, wherein the top electrode includes a lower portion and a tapered upper portion located around the bottom electrode.

[0017] According to an embodiment of the present invention, the method further includes: removing the hard mask layer after polishing the second conductive layer and the resistive switching layer, thereby forming a third opening on the bottom electrode; and depositing a third dielectric layer into the third opening, thereby forming an air gap in the third dielectric layer on the bottom electrode and around the tapered upper portion of the top electrode.

[0018] According to an embodiment of the present invention, the third dielectric layer covers the top electrode and the second dielectric layer.

[0019] According to an embodiment of the present invention, the method further includes: forming a metal layer in the third dielectric layer, wherein the metal layer is electrically connected to the top electrode.

[0020] According to an embodiment of the present invention, the method further includes: polishing the third dielectric layer until the top surface of the third dielectric layer is flush with the top surface of the top electrode and the top surface of the second dielectric layer.

[0021] According to an embodiment of the present invention, the method further includes: forming a top cover layer covering the second dielectric layer, the top electrode, and the third dielectric layer; forming a fourth dielectric layer on the top cover layer; and forming a conductive via in the fourth dielectric layer, wherein the conductive via is electrically connected to the top electrode.

[0022] According to an embodiment of the present invention, the resistance switching layer is disposed between the sidewall of the bottom electrode and the sidewall of the lower part of the top electrode, and between the third dielectric layer and the sidewall of the upper conical part of the top electrode.

[0023] According to an embodiment of the present invention, the method further includes: forming a dielectric barrier layer between the second dielectric layer and the first dielectric layer.

[0024] According to an embodiment of the present invention, the top electrode is disposed on the dielectric barrier layer.

[0025] According to an embodiment of the present invention, the resistor switching layer comprises NiO. x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x 、Nb y O x Or Y y O x , where x>0, y>0. Attached Figure Description

[0026] Figure 1 This is a top view of a portion of a semiconductor memory device illustrated in an embodiment of the present invention;

[0027] Figure 2 for Figure 1 A cross-sectional view along tangent I-I';

[0028] Figure 3 This is a cross-sectional view of a portion of a semiconductor memory device illustrated in another embodiment of the present invention;

[0029] Figures 4 to 19 This is a schematic diagram illustrating a method for forming a semiconductor memory device according to an embodiment of the present invention, wherein, Figure 8 This shows a top view of the semiconductor memory device after the bottom electrode patterning is completed. Figure 9 For along Figure 8 The sectional view shown by the mid-tangent II-II' Figure 12 This shows a top view of a semiconductor memory device after the opening for the predetermined formation of the top electrode has been completed. Figure 13 For along Figure 12 The sectional view shown by the mid-tangent II-II' Figure 17 This shows a top view of the semiconductor memory device after an air gap has been formed on the bottom electrode. Figure 18 For along Figure 17 The sectional view shown by the mid-tangent II-II';

[0030] Figure 20 and Figure 21 A schematic diagram illustrating another embodiment of the present invention is shown.

[0031] Explanation of main component symbols

[0032] 1. Semiconductor memory devices

[0033] 100 substrate

[0034] 110 First dielectric layer

[0035] 112, 112i metal layers

[0036] 120 Second dielectric layer

[0037] 120s Top surface

[0038] 121i conductive via

[0039] 122i metal layer

[0040] 130 Third dielectric layer

[0041] 130a air gap

[0042] 130s Top surface

[0043] 132 Metal Layer

[0044] 140 Fourth dielectric layer

[0045] 141, 141i conductive vias

[0046] 142, 142i metal layers

[0047] 300, 310 hard mask layers

[0048] 310s top surface

[0049] 310w sidewall

[0050] BE bottom electrode

[0051] BEL First Conductive Layer

[0052] BL dielectric barrier layer

[0053] BLO opening

[0054] CL top cover

[0055] D1 First Direction

[0056] D2 Second Direction

[0057] LA Logic Circuit Area

[0058] MA memory array area

[0059] OP1 First Opening

[0060] OP2 Second Opening

[0061] OP2_B (Lower Part)

[0062] OP2_U upper cone shape

[0063] OP3 Third Opening

[0064] PO1 opening

[0065] PR1 and PR2 photoresist patterns

[0066] PRO opening

[0067] RS Resistor Switching Layer

[0068] SW1, SW2, SW3 sidewalls

[0069] TE top electrode

[0070] TEL Second Conductive Layer

[0071] TEB lower part

[0072] TEU cone-shaped upper part

[0073] TES top surface

[0074] t1 thickness

[0075] t2 thickness Detailed Implementation

[0076] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0077] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0078] Please see Figure 1 and Figure 2 ,in Figure 1 This is a top view of some semiconductor memory devices illustrated according to embodiments of the present invention. Figure 2 for Figure 1 A cross-sectional view along the tangent line I-I'. (See attached image.) Figure 1 and Figure 2As shown, the semiconductor memory device 1 includes a substrate 100, such as a semiconductor substrate, but not limited thereto. The substrate 100 may include a memory array region MA and a logic circuit region LA. The semiconductor memory device 1 further includes a first dielectric layer 110 located on the substrate 100 and covering the memory array region MA and the logic circuit region LA. According to an embodiment of the present invention, the first dielectric layer 110 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, a metal layer 112 may be formed in the first dielectric layer 110, such as a copper metal layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 112 may be a third metal layer (M3) in a metal interconnect structure, but is not limited thereto. According to an embodiment of the present invention, a dielectric barrier layer BL, such as a silicon nitride layer, may be formed on the first dielectric layer 110. A plurality of openings BLO are formed in the dielectric barrier layer BL, each exposing the top surface of the corresponding metal layer 112.

[0079] According to an embodiment of the present invention, in the memory array region MA, a plurality of bottom electrodes BE are formed on the dielectric barrier layer BL and the first dielectric layer 110, wherein, as shown in the embodiment of the present invention, a plurality of bottom electrodes BE are formed on the dielectric barrier layer BL and the first dielectric layer 110. Figure 1 As shown, multiple bottom electrodes BE are arranged approximately equidistantly along a first direction D1 and extend along a second direction D2. For simplicity, Figure 1 and Figure 2 Only three bottom electrodes BE are shown as an example. Figure 2 As shown, multiple bottom electrodes BE are electrically connected to the metal layer 112 in the first dielectric layer 110 via multiple openings BLO. According to embodiments of the present invention, for example, the bottom electrodes BE may contain TiN or TaN, but are not limited thereto.

[0080] like Figure 2 As shown, the semiconductor memory device 1 further includes a second dielectric layer 120 located on the dielectric barrier layer BL and the first dielectric layer 110. The dielectric barrier layer BL is located between the second dielectric layer 120 and the first dielectric layer 110. According to an embodiment of the present invention, the second dielectric layer 120 may include a silicon oxide layer, but is not limited thereto.

[0081] According to an embodiment of the present invention, a plurality of top electrodes TE are disposed at intervals along a second direction D2 on the dielectric barrier layer BL between the middle bottom electrode BE and the right bottom electrode BE. According to an embodiment of the present invention, the plurality of top electrodes TE may be disposed at approximately equal intervals and aligned along the second direction D2. According to an embodiment of the present invention, the top electrodes TE are located in the second dielectric layer 120. Figure 1 As shown, in the second direction D2, there is a second dielectric layer 120 between the top electrode TE.

[0082] According to an embodiment of the present invention, the top electrode TE includes a lower TEB and a tapered upper TEU, with the lower TEB located around the bottom electrode BE. The width of the tapered upper TEU of the top electrode TE gradually decreases from top to bottom, connecting to the lower TEB with approximately the same width. According to an embodiment of the present invention, the thickness t1 of the tapered upper TEU of the top electrode TE is greater than the thickness t2 of the lower TEB of the top electrode TE. According to an embodiment of the present invention, the top electrode TE may contain TiN, TaN, or Pt, but is not limited thereto. According to an embodiment of the present invention, the top surface 120s of the second dielectric layer 120 is flush with the top surface TES of the top electrode TE.

[0083] like Figure 2 As shown, the semiconductor memory device 1 further includes a third dielectric layer 130, located above the bottom electrode BE and surrounding the tapered upper portion TEU of the top electrode TE, and above the second dielectric layer 120. The semiconductor memory device 1 further includes an air gap 130a located within the third dielectric layer 130. According to an embodiment of the present invention, the air gap 130a is located around the tapered upper portion TEU of the top electrode TE and extends along the second direction D2.

[0084] According to an embodiment of the present invention, the semiconductor memory device 1 further includes a resistance switching layer RS, located between a sidewall SW1 of the bottom electrode BE and a sidewall SW2 of the lower portion TEB of the top electrode TE, and between a third dielectric layer 130 and a sidewall SW3 of the tapered upper portion TEU of the top electrode TE. According to an embodiment of the present invention, the resistance switching layer RS ​​comprises NiO. x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x 、Nb y O x Or Y y O x Where x>0, y>0. According to an embodiment of the present invention, the semiconductor memory device 1 further includes a metal layer 132 disposed in the third dielectric layer 130 and electrically connected to the top electrode TE in the MA region, and electrically connected to the third metal layer 112 in the LA region. According to an embodiment of the present invention, the metal layer 132 may be a copper metal layer. For example, the metal layer 132 may be formed using a copper damascene process, but is not limited thereto.

[0085] According to another embodiment of the present invention, such as Figure 3As shown, the top surface 130s of the third dielectric layer 130 is flush with the top surface TES of the top electrode TE and the top surface 120s of the second dielectric layer 120. The semiconductor memory device 1 further includes a capping layer CL covering the second dielectric layer 120, the top electrode TE, and the third dielectric layer 130. The semiconductor memory device 1 further includes a fourth dielectric layer 140 located on the capping layer CL, and a conductive via 141 disposed in the fourth dielectric layer 140 and electrically connected to the top electrode TE. According to an embodiment of the present invention, the fourth dielectric layer 140 may further include a metal layer 142, for example, a copper metal layer, but is not limited thereto. According to an embodiment of the present invention, for example, the metal layer 142 may be the fourth metal layer (M4) in a metal interconnect structure, but is not limited thereto. A metal layer 142i and a conductive via 141i may be provided in the fourth dielectric layer 140 in the logic circuit region LA. The metal layer 142i is electrically connected to a metal layer 122i in the second dielectric layer 120 via the conductive via 141i, and the metal layer 122i is electrically connected to a metal layer 112i in the first dielectric layer 110 via the conductive via 121i.

[0086] Please see Figures 4 to 19 This is a schematic diagram illustrating a method for forming a semiconductor memory device according to an embodiment of the present invention, wherein the same regions, layers or elements are still represented by the same symbols. Figure 8 This shows a top view of the semiconductor memory device after the bottom electrode patterning is completed. Figure 9 For along Figure 8 The sectional view shown by the mid-tangent II-II' Figure 12 This shows a top view of a semiconductor memory device after the opening for the predetermined formation of the top electrode has been completed. Figure 13 For along Figure 12 The sectional view shown by the mid-tangent II-II' Figure 17 This shows a top view of the semiconductor memory device after an air gap has been formed on the bottom electrode. Figure 18 For along Figure 17 The sectional view shown by the mid-tangent II-II'.

[0087] like Figure 4 As shown, a substrate 100 is first provided, for example, a silicon substrate, but not limited thereto. Similarly, substrate 100 may include a memory array region MA and a logic circuit region LA. The semiconductor memory device 1 further includes a first dielectric layer 110 deposited on substrate 100, covering the memory array region MA and the logic circuit region LA. According to an embodiment of the invention, the first dielectric layer 110 may include a silicon oxide layer, but is not limited thereto.

[0088] According to an embodiment of the present invention, a metal layer 112, such as a copper metal layer, may be formed in the first dielectric layer 110, but is not limited thereto. According to an embodiment of the present invention, the metal layer 112 may be, for example, a third metal layer (M3) in a metal interconnect structure, but is not limited thereto. According to an embodiment of the present invention, a dielectric barrier layer BL, such as a silicon nitride layer, may be deposited on the first dielectric layer 110. Next, a photoresist pattern PR1 is formed on the dielectric barrier layer BL, wherein the photoresist pattern PR1 includes an opening PO1 within the memory array region MA, approximately aligned with the underlying metal layer 112.

[0089] like Figure 5 As shown, an etching process is then performed, for example, a dry etching process, using the photoresist pattern PR1 as an etching barrier layer, and the exposed dielectric barrier layer BL is etched away through the opening PO1, thus forming an opening BLO in the dielectric barrier layer BL, exposing a portion of the metal layer 112. Then, the remaining photoresist pattern PR1 is removed.

[0090] like Figure 6 As shown, a first conductive layer BEL is then deposited on the first dielectric layer 110 and the dielectric barrier layer BL. According to an embodiment of the invention, the first conductive layer BEL may contain TiN or TaN, but is not limited thereto. According to an embodiment of the invention, the first conductive layer BEL fills the opening BLO and directly contacts the metal layer 112. Then, a hard mask layer 300, for example, a silicon nitride layer, is deposited on the first conductive layer BEL.

[0091] like Figure 7 As shown, a photolithography process is then performed to form a photoresist pattern PR2 on the hard mask layer 300, wherein the photoresist pattern PR2 defines the pattern and position of the bottom electrode to be formed in the memory array region MA.

[0092] like Figure 8 and Figure 9 As shown, next, an etching process is performed, for example, a dry etching process, using a photoresist pattern PR2 as an etching barrier layer to etch away the exposed hard mask layer 300 and the first conductive layer BEL. By forming a first opening OP1 in the hard mask layer 300 and the first conductive layer BEL, the first conductive layer BEL is patterned into a bottom electrode BE, thus forming multiple bottom electrodes BE extending along the second direction D2 and a patterned hard mask layer 310 located directly above the bottom electrodes BE.

[0093] According to embodiments of the present invention, such as Figure 9As shown, because the patterned hard mask layer 310 has sloping sidewalls 310w that taper downwards, the first opening OP1 has a funnel-shaped cross-sectional profile. At this time, the hard mask layer 310 and the first conductive layer BEL within the logic circuit region LA are completely removed, exposing the dielectric barrier layer BL. The formation of the patterned hard mask layer 310, along with the sloping sidewalls 310w that taper downwards, can be achieved by adjusting the etching parameters; since this is prior art, it will not be described further.

[0094] like Figure 10 As shown, a second dielectric layer 120 is then deposited in the first opening OP1, on the hard mask layer 310, on the dielectric barrier layer BL, and on the first dielectric layer 110. According to an embodiment of the present invention, the second dielectric layer 120 may comprise a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, the second dielectric layer 120 may be formed using methods such as chemical vapor deposition (CVD), but is not limited thereto.

[0095] like Figure 11 As shown, the second dielectric layer 120 is polished, for example, by chemical mechanical polishing, to expose the top surface 310s of the hard mask layer 310. At this time, the top surface 310s of the hard mask layer 310 and the top surface 120s of the second dielectric layer 120 are flush and coplanar. In other embodiments, etching may be used instead of polishing.

[0096] like Figure 12 and Figure 13 As shown, next, a photolithography process is performed to form a photoresist pattern PR2 on the hard mask layer 300. The photoresist pattern PR2 has an opening PRO that defines the pattern and position of the top electrode to be formed within the memory array region MA. Figure 12 It can be seen that the opening PRO that defines the position of the top electrode is located between two adjacent bottom electrodes BE, arranged approximately equidistantly along the second direction D2, and slightly overlaps with the two adjacent bottom electrodes BE in the first direction D1.

[0097] Next, the second dielectric layer 120 is patterned by etching the opening PRO of the photoresist pattern PR2, thereby forming a second opening OP2 in the second dielectric layer 120. The second opening OP2 includes a lower portion OP2_B and a tapered upper portion OP2_U. The outline of the tapered upper portion OP2_U is defined by the sloping sidewalls 310w of the hard mask layer 310, which taper downwards. The lower portion OP2_B of the second opening OP2 has approximately the same width and exposes a portion of the dielectric barrier layer BL.

[0098] like Figure 14As shown, next, a resistance switching layer RS ​​is conformally deposited in the second opening OP2, on the top surface 310s of the hard mask layer 310, and on the top surface 120s of the second dielectric layer 120. The resistance switching layer RS ​​does not fill the second opening OP2, but is deposited on the sides and bottom surface of the second opening OP2. Next, a second conductive layer TEL is deposited on the resistance switching layer RS ​​and in the second opening OP2. According to an embodiment of the present invention, the second conductive layer TEL may contain TiN, TaN, or Pt, but is not limited thereto. According to an embodiment of the present invention, the resistance switching layer RS ​​may contain a transition metal oxide, for example, including but not limited to NiO. x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x 、Nb y O x Or Y y O x Where x>0, y>0. According to an embodiment of the present invention, the second conductive layer TEL and the resistor switching layer RS ​​together fill the second opening OP2.

[0099] like Figure 15 As shown, the second conductive layer TEL and the resistance switching layer RS ​​are polished, for example, by chemical mechanical polishing, until the top surface 310s of the hard mask layer 310 and the top surface 120s of the second dielectric layer 120 are exposed, thereby forming a top electrode TE in the second opening OP2, wherein the top electrode TE includes a lower TEB and a tapered upper TEU located around the bottom electrode BE. At this time, the top surface 310s of the hard mask layer 310, the top surface 120s of the second dielectric layer 120, and the top surface TES of the top electrode TE are flush and coplanar. In other embodiments, etching can be used instead of polishing.

[0100] like Figure 16 As shown, after polishing the second conductive layer TEL and the resistor switching layer RS, the hard mask layer 310 is then removed, thereby forming a third opening OP3 on the bottom electrode BE. According to an embodiment of the present invention, the upper width of the third opening OP3 is narrower, and the lower width is wider (gradually narrowing from bottom to top).

[0101] like Figure 17 and Figure 18As shown, a third dielectric layer 130 is then deposited into the third opening OP3, thereby forming an air gap 130a in the third dielectric layer 130 on the bottom electrode BE and around the tapered upper portion TEU of the top electrode TE. According to an embodiment of the invention, the air gap 130a is located around the tapered upper portion TEU of the top electrode TE and extends along the second direction D2. According to an embodiment of the invention, the air gap 130a overlaps with the bottom electrode BE. According to an embodiment of the invention, the third dielectric layer 130 covers and directly contacts the top electrode TE and the second dielectric layer 120. According to an embodiment of the invention, a resistance switching layer RS ​​is disposed between the sidewall SW1 of the bottom electrode BE and the sidewall SW2 of the lower portion TEB of the top electrode TE, and between the third dielectric layer 130 and the sidewall SW3 of the tapered upper portion TEU of the top electrode TE.

[0102] like Figure 19 As shown, finally, a metallization process is performed to form a metal layer 132 in the third dielectric layer, wherein the metal layer 132 is electrically connected to the top electrode TE. According to an embodiment of the present invention, the metal layer 132 may be a copper metal layer. For example, the metal layer 132 may be formed using a copper damascene process, but is not limited thereto.

[0103] Figure 20 and Figure 21 Another embodiment of the invention is illustrated. For example... Figure 20 As shown, continuing Figure 18 After depositing the third dielectric layer 130 into the third opening OP3 to form an air gap 130a, the third dielectric layer 130 can then be polished until the top surface 130s of the third dielectric layer 130 is flush with the top surface TES of the top electrode TE and the top surface 120s of the second dielectric layer 120. Subsequently, a metal layer 122i, for example a copper metal layer, can be formed in the second dielectric layer 120 within the logic circuit region LA. The metal layer 122i is electrically connected to the metal layer 112i in the first dielectric layer 110 via a conductive via 121i. Figure 21 As shown, a top cover layer CL is then formed, covering the second dielectric layer 120, the top electrode TE, the third dielectric layer 130, and the metal layer 122i. A fourth dielectric layer 140 is then formed on the top cover layer CL. A metal layer 142, such as a copper metal layer, may then be formed in the fourth dielectric layer 140, but is not limited thereto. According to an embodiment of the invention, the metal layer 142 may, for example, be the fourth metal layer (M4) in a metal interconnect structure, but is not limited thereto. The fourth dielectric layer 140 within the logic circuit region LA may contain a metal layer 142i and a conductive via 141i, wherein the metal layer 142i is electrically connected to the metal layer 122i in the second dielectric layer 120 via the conductive via 141i.

[0104] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory device, characterized by comprising: Comprising: a substrate; a first dielectric layer on the substrate; a bottom electrode on the first dielectric layer; a second dielectric layer on the first dielectric layer; a top electrode in the second dielectric layer, the top electrode comprising a lower portion and a tapered upper portion, and the lower portion being located around the bottom electrode, wherein the tapered upper portion of the top electrode tapers in width from top to bottom, connecting to the lower portion of uniform width, such that the top electrode is wider at the bottom and narrower at the top as a whole; a third dielectric layer over the bottom electrode and around the tapered upper portion of the top electrode; a resistive switching layer between sidewalls of the bottom electrode and the lower portion of the top electrode, and between sidewalls of the third dielectric layer and the tapered upper portion of the top electrode; and a gap in the third dielectric layer. Further comprising:

2. The semiconductor memory device according to claim 1, wherein a dielectric barrier layer between the second dielectric layer and the first dielectric layer. The top electrode is disposed on the dielectric barrier layer.

3. The semiconductor memory device according to claim 2, wherein The top electrode comprises TiN, TaN, or Pt.

4. The semiconductor memory device according to claim 1, wherein The resistance switching layer comprises NiO x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x Nb y O x or Y y O x wherein x>0, y>0.

5. The semiconductor memory device according to claim 1, wherein A top surface of the second dielectric layer is flush with a top surface of the top electrode.

6. The semiconductor memory device according to claim 1, wherein Further comprising:

7. The semiconductor memory device according to claim 1, wherein a metal layer disposed in the third dielectric layer and electrically connected to the top electrode. A top surface of the third dielectric layer is flush with a top surface of the top electrode and a top surface of the second dielectric layer.

8. The semiconductor memory device according to claim 1, wherein Further comprising:

9. The semiconductor memory device according to claim 8, wherein, an upper cap layer covering the second dielectric layer, the top electrode, and the third dielectric layer; a fourth dielectric layer on the upper cap layer; and a conductive via disposed in the fourth dielectric layer and electrically connected to the top electrode. The tapered upper portion of the top electrode has a thickness greater than a thickness of the lower portion of the top electrode.

10. The semiconductor memory device according to claim 1, wherein Comprising:

11. A method of forming a semiconductor memory device, comprising: providing a substrate; forming a first dielectric layer on the substrate; depositing a first conductive layer on the first dielectric layer; depositing a hard mask layer on the first conductive layer; patterning the first conductive layer into a bottom electrode by forming a first opening in the hard mask layer and the first conductive layer; depositing a second dielectric layer in the first opening and on the hard mask layer and the first dielectric layer; polishing the second dielectric layer to reveal a top surface of the hard mask layer; patterning the second dielectric layer by etching the second dielectric layer to form a second opening in the second dielectric layer, wherein the second opening comprises a lower portion and a tapered upper portion, the lower portion of the second opening exposing sidewalls of the bottom electrode; depositing a resistive switching layer in the second opening; depositing a second conductive layer on the resistive switching layer and in the second opening; and polishing the second conductive layer and the resistive switching layer until the top surface of the hard mask layer is revealed, thereby forming a top electrode in the second opening, wherein the top electrode comprises a lower portion located around the bottom electrode and a tapered upper portion, wherein the tapered upper portion of the top electrode tapers in width from top to bottom, connecting to the lower portion of uniform width, such that the top electrode is wider at the bottom and narrower at the top as a whole. Further comprising: ​ 12. The method of claim 11, wherein, ​ after polishing the second conductive layer and the resistance-switching layer, removing the hard mask layer, thereby forming a third opening on the bottom electrode; and depositing a third dielectric layer into the third opening, thereby forming an air gap in the third dielectric layer on the bottom electrode and around the tapered upper portion of the top electrode.

13. The method of claim 12, wherein, The third dielectric layer covers the top electrode and the second dielectric layer.

14. The method of claim 13, wherein, Further comprising: forming a metal layer in the third dielectric layer, wherein the metal layer is electrically connected to the top electrode.

15. The method of claim 12, wherein, Further comprising: polishing the third dielectric layer until a top surface of the third dielectric layer is flush with a top surface of the top electrode and a top surface of the second dielectric layer.

16. The method of claim 15, wherein, Further comprising: forming an upper cap layer covering the second dielectric layer, the top electrode and the third dielectric layer; forming a fourth dielectric layer on the upper cap layer; and forming a conductive via in the fourth dielectric layer, wherein the conductive via is electrically connected to the top electrode.

17. The method of claim 12, wherein, The resistance-switching layer is disposed between sidewalls of the bottom electrode and the lower portion of the top electrode, and between the third dielectric layer and the sidewalls of the tapered upper portion of the top electrode.

18. The method of claim 11, wherein, Further comprising: forming a dielectric barrier layer between the second dielectric layer and the first dielectric layer.

19. The method of claim 18, wherein, The top electrode is disposed on the dielectric barrier layer.

20. The method of claim 11, wherein, The resistance switching layer comprises NiO x Ta y O x TiO x HfO x WO x ZrO x Al y O x SrTiO x Nb y O x or Y y O x wherein x>0, y>0.

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