Memory device

Abstract

To provide a storage device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer. The switching layer comprises a compound of an oxide of a first element which is at least one element selected from the group consisting of Si, B, Ge, P, and As; a second element which is at least one element selected from the group consisting of Zn, Sn, Ga, In, and Bi; and a third element which is at least one element selected from the group consisting of Te, S, and Se, wherein the first ratio of the sum of the atomic concentrations of the first element and oxygen to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen in the switching layer is 10% or more.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a large-capacity non-volatile memory device, there is a two-terminal cross-point type memory device. The two-terminal cross-point type memory device is easy to miniaturize and highly integrate memory cells.

[0003] A memory cell of a two-terminal cross-point type memory device has, for example, a resistance change element and a switching element. By having a switching element in the memory cell, the current flowing through memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as low leakage current, high on-current, and high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a memory device having a switching element with excellent characteristics.

Means for Solving the Problems

[0007] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer, wherein the switching layer comprises an oxide of a first element which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As), and sub The switching layer comprises a compound of a second element, which is at least one element selected from the group consisting of lead (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), wherein the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 10% or more. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of the storage device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 3] A diagram illustrating the problems of the storage device according to the first embodiment. [Figure 4] A diagram illustrating the current-voltage characteristics of the switching element according to the first embodiment. [Figure 5] A schematic cross-sectional view of a memory cell of a first modified memory device according to the first embodiment. [Figure 6] A schematic cross-sectional view of a memory cell of a second modified memory device according to the first embodiment. [Figure 7] A schematic cross-sectional view of a memory cell of a third modified memory device according to the first embodiment. [Figure 8] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 9] A schematic cross-sectional view of a memory cell of a modified memory device according to the second embodiment. [Figure 10] Schematic cross-sectional view of a memory cell of the memory device according to the third embodiment. [Figure 11] Schematic cross-sectional view of a memory cell of the memory device according to a modification of the third embodiment. [Figure 12] Schematic cross-sectional view of a memory cell of the memory device according to the fourth embodiment. [Figure 13] Schematic cross-sectional view of a memory cell of the memory device according to the fifth embodiment. [Figure 14] Explanatory diagram of the current-voltage characteristics of the memory element according to the fifth embodiment. [Figure 15] Explanatory diagram of the first operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 16] Explanatory diagram of the second operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 17] Explanatory diagram of the current-voltage characteristics of the memory element according to the first modification of the fifth embodiment. [Figure 18] Explanatory diagram of the third operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 19] Explanatory diagram of the fourth operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 20] Explanatory diagram of the current-voltage characteristics of the memory element according to the second modification of the fifth embodiment. [Figure 21] Explanatory diagram of the fifth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. [Figure 22] Explanatory diagram of the sixth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. [Figure 23] Explanatory diagram of the current-voltage characteristics of the memory element according to the third modification of the fifth embodiment. [Figure 24] Explanatory diagram of the seventh operation example of the memory operation of the memory device according to the third modification of the fifth embodiment. [Figure 25] Explanatory diagram of the eighth operation example of the memory operation of the memory device according to the third modification of the fifth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] The qualitative and quantitative analysis of the chemical composition constituting the memory device in this specification can be performed, for example, by Rutherford Backscattering Spectroscopy (RBS), Secondary Ion Mass Spectroscopy (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS), or the like. In addition, for measuring the thickness of the members constituting the memory device, the distance between members, etc., for example, a Transmission Electron Microscope (TEM) can be used. Further, for identifying the constituent substances of the members constituting the memory device, measuring the abundance ratio, bonding state, local structure (interatomic distance, coordination number), and chemical state, for example, X-ray Photoelectron Spectroscopy (XPS), X-ray Absorption Fine Structure (XAFS), Raman Spectroscopy (Raman), or EELS can be used.

[0011] (First Embodiment) The memory device of the first embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer. The switching layer comprises a compound of an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As); a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi); and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). In the switching layer, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 10% or more.

[0012] Furthermore, the storage device of the first embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0013] Figure 1 is a block diagram of the storage device according to the first embodiment.

[0014] The memory cell array 100 of the first embodiment of the memory device includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102, separated by an insulating layer on a semiconductor substrate 101. The bit lines 103 are provided, for example, on top of the word lines 102. In addition, peripheral circuits such as a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100.

[0015] Word line 102 is an example of the first wiring. Bit line 103 is an example of the second wiring.

[0016] Multiple memory cells MC are provided in the region where the word line 102 and the bit line 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory having a crosspoint structure.

[0017] Multiple word lines 102 are each connected to the first control circuit 104. Multiple bit lines 103 are each connected to the second control circuit 105. The sense circuit 106 is connected to both the first control circuit 104 and the second control circuit 105.

[0018] The first control circuit 104 and the second control circuit 105 have functions such as selecting a desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, and erasing data from the memory cell MC. When reading data, the data from the memory cell MC is read out as the amount of current flowing between the word line 102 and the bit line 103, or as a change in the potential of the bit line 103. The sense circuit 106 has a function to determine the polarity of the data by determining the amount of current. For example, it determines whether the data is "0" or "1".

[0019] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are composed of electronic circuits using semiconductor devices formed on a semiconductor substrate 101, for example.

[0020] Figure 2 is a schematic cross-sectional view of a memory cell of the first embodiment of the storage device. Figure 2 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0021] As shown in Figure 2, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0022] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0023] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0024] The lower electrode 10 is connected to the word wire 102. The lower electrode 10 is, for example, a metal. The lower electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The lower electrode 10 may also be part of the word wire 102.

[0025] The upper electrode 20 is connected to the bit wire 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The upper electrode 20 may also be part of the bit wire 103.

[0026] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0027] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 toward the upper electrode 20 is, for example, 5 nm to 50 nm. More preferably, the thickness of the switching layer 40 in the first direction from the lower electrode 10 toward the upper electrode 20 is, for example, 5 nm to 20 nm.

[0028] The switching layer 40 has a function to suppress the increase in semi-selective leakage current flowing to the semi-selective cell. The switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0029] The switching layer 40 contains oxides and chalcogenides. Chalcogenides are compounds formed by bonding chalcogen elements such as tellurium (Te), sulfur (S), or selenium (Se) with other elements.

[0030] The switching layer 40 contains an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As). For example, the switching layer 40 contains at least one oxide selected from the group consisting of silicon oxide, boron oxide, germanium oxide, phosphorus oxide, and arsenic oxide.

[0031] An oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As), is a so-called glass-forming oxide. Glass-forming oxides are oxides that readily vitrify. Glass-forming oxides are, for example, oxides with relatively high crystallization temperatures or glass transition temperatures, and whose amorphous state is relatively stable.

[0032] Whether or not the switching layer 40 contains an oxide of the first element can be determined, for example, using X-ray photoelectron spectroscopy (XPS) or electron energy loss spectroscopy (EELS).

[0033] The switching layer 40 contains a chalcogenide compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). The switching layer 40 contains a chalcogenide of the second element.

[0034] The switching layer 40 includes, for example, at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, and bismuth selenide. The third element is more preferably tellurium (Te), and the switching layer 40 more preferably includes at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, and bismuth telluride. Compared to sulfides and selenides, tellurides have a smaller band gap, which allows for a relatively smaller write voltage and has the advantage of suppressing characteristic variations such as fluctuations in semi-selective leakage current and on-current when writing is repeated.

[0035] Whether or not the switching layer 40 contains a chalcogenide of the second element can be determined, for example, using X-ray absorption fine structure analysis (XAFS), Raman spectroscopy, or electron energy loss spectroscopy (EELS).

[0036] In the switching layer 40, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, 10% to 90%. For example, if the first element is silicon (Si), the second element is zinc (Zn), and the third element is tellurium (Te), then the ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) to the sum of the atomic concentrations of silicon (Si), zinc (Zn), tellurium (Te), and oxygen (O) in the switching layer 40 ((Si+O) / (Si+Zn+Te+O)) is, for example, 10% to 90%.

[0037] The above oxide and chalcogenide are, for example, the main components of the switching layer 40. The statement that the above oxide and chalcogenide are the main components of the switching layer 40 means that among the substances contained in the switching layer 40, there are no substances with a higher mole fraction than the above oxide or chalcogenide.

[0038] In the switching layer 40, the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is, for example, between 90% and 100%.

[0039] The switching layer 40 includes, for example, a mixture of the above oxide and the above chalcogenide. The above oxide and the above chalcogenide are present in the switching layer 40 in a mixed state, for example.

[0040] In the switching layer 40, the second ratio of the atomic concentration of the second element to the atomic concentration of the third element is, for example, between 50% and 200%. For example, if the second element is zinc (Zn) and the third element is tellurium (Te), the second ratio of the atomic concentration of zinc (Zn) to the sum of the atomic concentrations of tellurium (Te) in the switching layer 40 (Zn / Te) is, for example, between 50% and 200%.

[0041] The switching layer 40 includes a fourth element, which is, for example, at least one element selected from the group consisting of lithium (Li), sodium (Na), potassium (K), magnesium (Mg), calcium (Ca), barium (Ba), lead (Pb), aluminum (Al), vanadium (V), iron (Fe), and tungsten (W).

[0042] For example, an oxide of the first element containing a fourth element is also a so-called glass-forming oxide.

[0043] The atomic concentration of the fourth element in the switching layer 40 is, for example, lower than the atomic concentration of the first element. The atomic concentration of the fourth element in the switching layer 40 is, for example, 1% or more and 30% or less.

[0044] The switching layer 40 can be formed, for example, by sputtering. The switching layer 40, which contains an oxide of a first element and a chalcogenide of a second element, can be formed, for example, by co-sputtering using a target made of an oxide of the first element and a target made of a chalcogenide of the second element. Alternatively, the switching layer 40 can be formed, for example, by sputtering using a target made of a mixture of an oxide of the first element and a chalcogenide of the second element.

[0045] Since the oxide of the first element is a glass-forming oxide, for example, a glassed target can be used as a target when forming the switching layer 40.

[0046] The resistive change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistive change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistive change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0047] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0048] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined writing voltage, and the magnetization direction is fixed in a specific direction.

[0049] The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunneling effect.

[0050] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined writing voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and flowing a current between the intermediate electrode 30 and the upper electrode 20.

[0051] By changing the magnetization direction of the free layer 53, the electrical resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high-resistance state is achieved where current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low-resistance state is achieved where current is easy to flow. Note that the arrangement of the fixed layer 51 and the free layer 53 can be reversed. In other words, the layers may be stacked in the order of intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20.

[0052] Next, the operation and effects of the storage device according to the first embodiment will be described.

[0053] In the first embodiment of the memory device, as described above, the resistance of the resistance change layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state in which current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state in which current is easy to flow.

[0054] For example, the high-resistance state of the resistive change layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1." Writing to a single memory cell MC is performed by applying a voltage and current between the bit line 103 and the word line 102 connected to that memory cell MC.

[0055] Figure 3 is an explanatory diagram of the problems of the memory device according to the first embodiment. Figure 3 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. The intersections of the word line and the bit line represent each memory cell MC.

[0056] The selected memory cell MC is memory cell A (selected cell). The write voltage Vwrite is applied to the word line connected to memory cell A. Also, 0V is applied to the bit line connected to memory cell A.

[0057] The following explanation will use the example where a voltage half the write voltage (Vwrite / 2) is applied to the word line and bit line that are not connected to memory cell A.

[0058] The voltage applied to memory cell C (unselected cell), which is connected to the word line and bit line not connected to memory cell A, is 0V. In other words, no voltage is applied.

[0059] On the other hand, a voltage half the write voltage Vwrite (Vwrite / 2) is applied to memory cell B (a semi-selective cell) that is connected to the word line or bit line connected to memory cell A. Therefore, a semi-selective leakage current flows through memory cell B (a semi-selective cell).

[0060] In addition, as an alternative application method, a method may be used in which a voltage half the write voltage (Vwrite / 2) is applied to the word line connected to memory cell A, a negative voltage half the write voltage (-Vwrite / 2) is applied to the bit line, and 0V is applied to the word line and bit line not connected to memory cell A.

[0061] Figure 4 is an explanatory diagram of the current-voltage characteristics of the switching element in the first embodiment. The horizontal axis represents the voltage applied to the switching element, and the vertical axis represents the current flowing through the switching element.

[0062] A switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, between 0.5V and 3V.

[0063] The write voltage Vwrite is set such that the write voltage Vwrite is higher than the threshold voltage Vth, and half the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on current (Ion in Figure 4). The current that flows through the switching element when half the write voltage Vwrite (Vwrite / 2) is applied is the semi-selective leakage current (Ihalf in Figure 4).

[0064] Furthermore, the read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in Figure 4. Therefore, the semi-selective leakage current flowing through the semi-selective cell during reading from the memory cell MC can also be suppressed.

[0065] A high semi-selective leakage current can lead to increased power consumption of the chip, for example. Also, an increased voltage drop in the wiring can prevent a sufficiently high voltage from being applied to the selected cell, resulting in unstable writing operations to the memory cell MC. Furthermore, a low on-current can lead to insufficient current flowing to the selected cell, resulting in incomplete writing to the memory cell MC. Therefore, the current-voltage characteristics of a switching element require a balance between low semi-selective leakage current and high on-current.

[0066] Furthermore, high reliability is required for the current-voltage characteristics of the switching element. Specifically, it is necessary to suppress characteristic fluctuations such as fluctuations in semi-selective leakage current and on-current when data is repeatedly written to the memory cell MC, thereby achieving high reliability.

[0067] For example, consider a switching element in the comparative example where the switching layer is formed of zirconium oxide, which is an oxide of zirconium (Zr), and zinc telluride, which is a chalcogenide of zinc (Zn) and tellurium (Te). The switching element in the comparative example has problems such as large characteristic fluctuations when data is repeatedly written to the memory cell MC, or high semi-selective leakage current.

[0068] One reason why the above-mentioned problems occur in the switching element of the comparative example is thought to be the crystallization of zirconium oxide and zinc telluride. For example, the crystallization of zirconium oxide and zinc telluride progresses due to the heat generated when data is repeatedly written to the memory cell MC. As the crystallization of zirconium oxide and zinc telluride progresses, the separation of zirconium oxide and zinc telluride progresses. As the separation of zirconium oxide and zinc telluride progresses, for example, film peeling occurs inside the switching layer, or film peeling occurs between the switching layer and the electrodes, causing fluctuations in the characteristics of the switching element. For example, fluctuations in the semi-selective leakage current and ON current of the switching element occur.

[0069] Another reason why the above problem occurs in the switching element of the comparative example is thought to be due to the formation of chemical bonds with a smaller band gap than zinc telluride in the switching layer. When chemical bonds with a significantly smaller band gap than the Zn-Te bond of zinc telluride (Eg=2.25eV) are formed in the switching layer, these chemical bonds become a leakage source, increasing the semi-selective leakage current of the switching element. In the case of the comparative example, the chemical bonds that become leakage sources are, for example, Zr-Zr bonds (Eg=0eV), Zn-Zn bonds (Eg=0eV), Te-Te bonds (Eg=0.34eV), Zr-Zn bonds (Eg=0eV), or Zr-Te bonds (Eg=0eV).

[0070] The switching layer 40 of the switching element in the first embodiment contains an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As). By including the oxide of the first element in the switching layer 40, characteristic fluctuations can be suppressed and a low semi-selective leakage current can be achieved.

[0071] One reason why characteristic fluctuations can be suppressed in the switching element of the first embodiment is that the switching layer 40 contains an oxide of the first element, which suppresses the crystallization of the oxide and chalcogenide of the first element.

[0072] The oxide of the first element described above is a glass-forming oxide, and the oxide of the first element described above is an oxide that is more stable in an amorphous state compared to, for example, zirconium oxide. Therefore, even when data is repeatedly written to the memory cell MC, for example, it is less likely to crystallize compared to zirconium oxide. In addition, the atomic radius of the first element described above is smaller than that of zirconium (Zr), for example. Therefore, it is thought that it is easier to fill gaps in the structure of the switching layer 40 than zirconium (Zr), and that the crystallization of chalcogenides can be suppressed.

[0073] According to the switching element of the first embodiment, the crystallization of oxides and chalcogenides of the first element can be suppressed, thereby suppressing fluctuations in properties.

[0074] Another reason why a low semi-selective leakage current can be achieved in the switching element of the first embodiment is thought to be that the switching layer 40 contains an oxide of the first element, thereby suppressing the formation of chemical bonds with a small band gap in the switching layer. Hereinafter, we will consider a switching element in which the switching layer 40 is formed of silicon oxide, which is an oxide of silicon (Si), and zinc telluride, which is a chalcogenide of zinc (Zn) and tellurium (Te). That is, we will consider the case in which the first element is silicon (Si), the second element is zinc (Zn), and the third element is tellurium (Te).

[0075] When the switching layer 40 is formed of silicon oxide and zinc telluride, the chemical bonds that become sources of leakage are, for example, Zn-Zn bonds (Eg=0eV), Te-Te bonds (Eg=0.34eV), or Si-Zn bonds (Eg=0eV). For example, Si-Si bonds (Eg=1.12eV) and Si-Te bonds (Eg=2.16eV) have relatively large band gaps and do not become sources of leakage.

[0076] First, when the switching layer 40 is formed from silicon oxide and zinc telluride, there are fewer types of chemical bonds that act as leakage sources compared to the comparative example. For example, in the comparative example, Zr-Zr bonds (Eg=0eV) and Zr-Te bonds (Eg=0eV) act as leakage sources, but in the first embodiment, the corresponding Si-Si bonds (Eg=1.12eV) and Si-Te bonds (Eg=2.16eV) do not act as leakage sources. Therefore, it is considered that a low semi-selective leakage current can be achieved with the switching element of the first embodiment.

[0077] Furthermore, first-principles calculations by the inventors revealed that in the first embodiment, the proportion of chemical bonds that act as leakage sources in the switching layer 40 is lower compared to the comparative example. In particular, the difference from the comparative example becomes apparent when the first ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) is 10% or more. When the ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) is 10% or more, the proportion of Zn-Zn bonds (Eg=0eV) decreases especially compared to the comparative example.

[0078] The proportion of Zn-Zn bonds (Eg=0eV) decreases with increasing first ratio. From the viewpoint of reducing the proportion of Zn-Zn bonds (Eg=0eV) and achieving a low semi-selective leakage current, the first ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) is preferably 20% or more, and more preferably 40% or more.

[0079] Furthermore, first-principles calculations by the inventors show that the sum of the proportions of all chemical bonds that serve as leakage sources, including Zn-Zn bonds (Eg=0eV), decreases significantly when the first ratio is 55% or higher. Therefore, from the viewpoint of reducing the proportion of chemical bonds that serve as leakage sources and achieving a low semi-selective leakage current, it is even more preferable for the first ratio to be 55% or higher.

[0080] Furthermore, first-principles calculations performed by the inventors revealed that, in the first embodiment, compared to the comparative example, when the first ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) is 40% or more, the proportion of Zn-O bonds in the switching layer 40 increases. This is thought to be because Zn2SiO4 is formed in the switching layer 40. The formation of Zn2SiO4 in the switching layer 40 strengthens the bond between silicon oxide and zinc telluride, further suppressing the separation of silicon oxide and zinc telluride.

[0081] Therefore, from the viewpoint of suppressing the separation of silicon oxide and zinc telluride and preventing fluctuations in the characteristics of the switching element, it is preferable that the first ratio of the sum of the atomic concentrations of silicon (Si) and oxygen (O) is 40% or more.

[0082] The above explanation uses the example of the first embodiment where the first element is silicon (Si), the second element is zinc (Zn), and the third element is tellurium (Te). However, similar effects and benefits can be obtained even if the first, second, and third elements are other elements.

[0083] Therefore, in the switching layer 40, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is preferably 20% or more, more preferably 40% or more, and even more preferably 55% or more.

[0084] Furthermore, from the viewpoint of achieving excellent switching characteristics, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer 40 is preferably 80% or less, and more preferably 70% or less.

[0085] Furthermore, from the viewpoint of reducing the proportion of chemical bonds that serve as leakage sources in the switching layer 40, the second ratio of the atomic concentration of the second element to the atomic concentration of the third element in the switching layer 40 is preferably 50% to 200%, more preferably 80% to 140%, and even more preferably 97% to 103%.

[0086] Furthermore, in the memory device of the first embodiment, since the oxide of the first element is a glass-forming oxide, a vitrified target can be used as the target when forming the switching layer 40. Compared to a crystalline target, a vitrified target can suppress particle generation. Therefore, the memory device of the first embodiment can achieve a high manufacturing yield.

[0087] As described above, according to the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized.

[0088] (First variation) The first modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0089] Figure 5 is a schematic cross-sectional view of a memory cell of a first modified storage device according to the first embodiment. Figure 5 corresponds to Figure 2 of the first embodiment.

[0090] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0091] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0092] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0093] In the first modified memory device of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 does not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0094] As described above, according to the first modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0095] (Second variation) The second modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0096] Figure 6 is a schematic cross-sectional view of a memory cell of a second modified storage device of the first embodiment. Figure 6 corresponds to Figure 2 of the first embodiment.

[0097] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0098] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0099] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0100] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0101] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0102] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0103] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0104] In the second modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0105] As described above, according to the second modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0106] (Third variation) The third modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion, a second portion, and a fifth portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0107] Figure 7 is a schematic cross-sectional view of a memory cell of a third modified memory device of the first embodiment. Figure 7 corresponds to Figure 2 of the first embodiment.

[0108] The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

[0109] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0110] The second part 12 and the fifth part 13 include, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0111] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0112] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0113] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0114] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0115] In the third modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0116] As described above, according to the third modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0117] According to the first embodiment and its modifications, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized. Therefore, according to the first embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized.

[0118] (Second embodiment) The memory device of the second embodiment differs from the first embodiment in that the first conductive layer includes a first layer and a second layer provided between the switching layer and the first layer and in contact with the switching layer, and the second layer includes tungsten, tungsten nitride, titanium, or titanium nitride. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0119] Figure 8 is a schematic cross-sectional view of a memory cell of the second embodiment of the storage device. Figure 8 corresponds to Figure 2 of the first embodiment.

[0120] The lower electrode 10 includes a first layer 10a and a second layer 10b. The second layer 10b is provided between the first layer 10a and the switching layer 40. The second layer 10b is in contact with the switching layer 40.

[0121] The first layer 10a includes, for example, carbon, carbon nitride, or tungsten carbide. The first layer 10a is, for example, a carbon layer, a carbon nitride layer, or a tungsten carbide layer.

[0122] The second layer 10b comprises tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride. The second layer 10b is, for example, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer.

[0123] The thickness of the second layer 10b is, for example, 0.3 nm or more and 2 nm or less.

[0124] By providing a second layer 10b on the lower electrode 10, the aggregation of chalcogenides in the switching layer 40 can be suppressed. Therefore, for example, variations in the characteristics of the switching element can be suppressed.

[0125] (modified version) A modified memory device of the second embodiment differs from the memory device of the second embodiment in that the third conductive layer includes a first layer and a second layer provided between the switching layer and the first layer and in contact with the switching layer, and the second layer includes tungsten, tungsten nitride, titanium, or titanium nitride.

[0126] Figure 9 is a schematic cross-sectional view of a memory cell of a modified memory device according to the second embodiment. Figure 9 corresponds to Figure 8 of the second embodiment.

[0127] The intermediate electrode 30 includes a first layer 30a and a second layer 30b. The second layer 30b is provided between the first layer 30a and the switching layer 40. The second layer 30b is in contact with the switching layer 40.

[0128] The first layer 30a includes, for example, carbon, carbon nitride, or tungsten carbide. The first layer 30a is, for example, a carbon layer, a carbon nitride layer, or a tungsten carbide layer.

[0129] The second layer 30b includes tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride. The second layer 30b is, for example, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer.

[0130] The thickness of the second layer 30b is, for example, 0.3 nm or more and 2 nm or less.

[0131] By providing a second layer 30b on the intermediate electrode 30, the aggregation of chalcogenides in the switching layer 40 can be suppressed. Therefore, for example, variations in the characteristics of the switching element can be suppressed.

[0132] Furthermore, as in the second embodiment, the lower electrode 10 may also include a first layer 10a and a second layer 10b.

[0133] As described above, according to the second embodiment and its modifications, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment. Therefore, according to the second embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized. Furthermore, according to the second embodiment and its modifications, variations in the characteristics of the switching element can be suppressed.

[0134] (Third embodiment) The memory device of the third embodiment differs from the memory device of the first embodiment in that the switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region, the first region may or may not contain fluorine (F), the second and third regions contain fluorine (F), and the atomic concentration of fluorine (F) in the second and third regions is higher than the atomic concentration of fluorine in the first region.Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0135] Figure 10 is a schematic cross-sectional view of a memory cell of the third embodiment of the storage device. Figure 10 corresponds to Figure 2 of the first embodiment.

[0136] The switching layer 40 includes an internal region 41, a first sidewall region 42a, and a second sidewall region 42b. Hereinafter, the first sidewall region 42a and the second sidewall region 42b may be referred to as the sidewall region 42, either individually or collectively.

[0137] In a cross-section parallel to the first direction connecting the lower electrode 10 to the upper electrode 20, and in a second direction perpendicular to the first direction, the internal region 41 is provided between the first sidewall region 42a and the second sidewall region 42b. The first sidewall region 42a and the second sidewall region 42b are provided, for example, between the lower electrode 10 and the intermediate electrode 30 in the first direction. The first sidewall region 42a and the second sidewall region 42b are in contact with the lower electrode 10 and the intermediate electrode 30, respectively, in the first direction.

[0138] The internal region 41 contains oxides of the first element, and compounds of the second and third elements. The internal region 41 may or may not contain fluorine (F).

[0139] The sidewall region 42 contains the second element and fluorine (F). The sidewall region 42 may or may not contain an oxide of the first element and the third element.

[0140] The sidewall region 42 contains, for example, a compound of a second element and fluorine (F). For example, if the second element is zinc (Zn), the sidewall region 42 contains zinc fluoride (ZnF2).

[0141] The atomic concentration of fluorine (F) in the sidewall region 42 is higher than the atomic concentration of fluorine (F) in the interior region 41. The atomic concentration of fluorine (F) in the first sidewall region 42a is higher than the atomic concentration of fluorine (F) in the interior region 41. The atomic concentration of fluorine (F) in the second sidewall region 42b is higher than the atomic concentration of fluorine (F) in the interior region 41. The atomic concentration of fluorine (F) in the sidewall region 42 is, for example, more than twice but less than or equal to 100 times the atomic concentration of fluorine (F) in the interior region 41.

[0142] The atomic concentration of the second element in the sidewall region 42 is, for example, higher than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the first sidewall region 42a is higher than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the second sidewall region 42b is higher than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the sidewall region 42 is, for example, more than twice but less than or equal to 100 times the atomic concentration of the second element in the interior region 41.

[0143] The thickness of the first sidewall region 42a and the second sidewall region 42b in the second direction is, for example, 0.5 nm or more and 5 nm or less.

[0144] The sidewall region 42 can be formed, for example, by using an etching gas containing fluorine (F) when patterning the switching layer 40 using a reactive ion etching method.

[0145] For example, when patterning the switching layer 40 using a reactive ion etching method, if an etching gas containing chlorine (Cl) is used, the sidewall region 42 will contain, for example, a compound of a second element and chlorine (Cl). For example, if the second element is zinc (Zn), the sidewall region 42 will contain zinc chloride (ZnCl2).

[0146] For example, compounds of a second element with fluorine (F) have a higher melting point and a larger band gap compared to compounds of a second element with chlorine (Cl). Therefore, compounds of a second element with fluorine (F) are more stable and have higher insulating properties.

[0147] According to the third embodiment of the storage device, the presence of the side wall region 42 stabilizes, for example, the characteristics of the switching element.

[0148] (modified version) The modified memory device of the third embodiment differs from the memory device of the third embodiment in that the atomic concentration of the second element in the second and third regions is lower than the atomic concentration of the second element in the first region, and the atomic concentration of the third element in the second and third regions is lower than the atomic concentration of the third element in the first region.

[0149] Figure 11 is a schematic cross-sectional view of a memory cell of a modified memory device according to the third embodiment. Figure 11 corresponds to Figure 10 of the third embodiment.

[0150] The switching layer 40 includes an internal region 41, a first sidewall region 42x, and a second sidewall region 42y. Hereinafter, the first sidewall region 42x and the second sidewall region 42y may be referred to as the sidewall region 42, either individually or collectively.

[0151] The internal region 41 contains oxides of the first element, and compounds of the second and third elements.

[0152] The sidewall region 42 contains an oxide of the first element, the second element, and the third element.

[0153] The atomic concentration of the second element in the sidewall region 42 is lower than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the first sidewall region 42x is lower than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the second sidewall region 42y is lower than the atomic concentration of the second element in the interior region 41. The atomic concentration of the second element in the sidewall region 42 is, for example, between 1 / 100 and 1 / 2 of the atomic concentration of the second element in the interior region 41.

[0154] The atomic concentration of the third element in the sidewall region 42 is lower than the atomic concentration of the third element in the interior region 41. The atomic concentration of the third element in the first sidewall region 42x is lower than the atomic concentration of the third element in the interior region 41. The atomic concentration of the third element in the second sidewall region 42y is lower than the atomic concentration of the third element in the interior region 41. The atomic concentration of the third element in the sidewall region 42 is, for example, between 1 / 100 and 1 / 2 of the atomic concentration of the third element in the interior region 41.

[0155] The atomic concentration of the first element in the sidewall region 42 is, for example, higher than the atomic concentration of the first element in the interior region 41. The atomic concentration of oxygen (O) in the sidewall region 42 is, for example, higher than the atomic concentration of oxygen (O) in the interior region 41.

[0156] The thickness of the first sidewall region 42x and the second sidewall region 42y in the second direction is, for example, 0.5 nm or more and 5 nm or less.

[0157] The sidewall region 42 can be formed, for example, by using an etching gas containing fluorine (F) when patterning the switching layer 40 using a reactive ion etching method, similar to the third embodiment. Subsequently, the compound of the second element and fluorine (F) formed on the side surface of the switching layer 40 can be removed, for example, by a wet etching method.

[0158] For example, the sidewall region 42 has lower concentrations of the second and third elements compared to the internal region 41, resulting in higher material stability.

[0159] According to the modified storage device of the third embodiment, the characteristics of the switching element are stabilized by providing the side wall region 42.

[0160] As described above, according to the third embodiment and its modifications, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment. Therefore, according to the third embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized. Furthermore, according to the third embodiment and its modifications, the characteristics of the switching element are even more stable.

[0161] (Fourth embodiment) The storage device of the fourth embodiment differs from the storage device of the first embodiment in that it is a resistive random-access memory (ReRAM). Some of the content that overlaps with the first embodiment will be omitted below.

[0162] Figure 12 is a schematic cross-sectional view of a memory cell of a storage device according to the fourth embodiment. Figure 12 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0163] As shown in Figure 12, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0164] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0165] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0166] The configuration of the switching layer 40 is the same as that of the storage device in the first to third embodiments.

[0167] The resistance-changing layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0168] The high-resistance layer 50x is, for example, a metal oxide. The high-resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0169] The low-resistance layer 50y is, for example, a metal oxide. The low-resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0170] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0171] By applying a voltage to the resistive layer 50, the resistive layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistive layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen vacancies in the low-resistance layer 50y. The conductivity of the resistive layer 50 changes in accordance with the amount of oxygen vacancies in the low-resistance layer 50y. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0172] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0173] As described above, the storage device of the fourth embodiment can realize a switching element with excellent characteristics such as low semi-selective leakage current and high reliability, similar to the first embodiment. Therefore, the fourth embodiment can realize a storage device having a switching element with excellent characteristics.

[0174] (Fifth embodiment) The fifth embodiment of the memory device includes a memory cell comprising a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer, wherein the memory layer comprises a compound of an oxide of a first element which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As), a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), and the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 10% or more.

[0175] Furthermore, the storage device of the fifth embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0176] The fifth embodiment of the storage device differs from the first to fourth embodiments in that the memory cell does not include a third conductive layer and a resistive switching layer, and instead includes a memory layer with a configuration similar to the switching layer of the first to fourth embodiments. The following description will omit some details that overlap with the first to fourth embodiments.

[0177] Figure 13 is a schematic cross-sectional view of a memory cell of a fifth embodiment of a storage device. Figure 13 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0178] As shown in Figure 13, the memory cell MC comprises a lower electrode 10, an upper electrode 20, and a memory layer 60.

[0179] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0180] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0181] The memory layer 60 has the same configuration as the switching layer 40 of the first to fourth embodiments. That is, the memory layer 60 includes a compound of an oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As); a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi); and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se). In the switching layer, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 10% or more.

[0182] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic in which the threshold voltage changes when a predetermined voltage is applied. The memory layer 60 also has a characteristic in which its electrical resistance changes when a predetermined voltage is applied. In the fifth embodiment, the high-resistance state is a state in which the resistance of the memory layer 60 is relatively high at the read voltage. Also, in the fifth embodiment, the low-resistance state is a state in which the resistance of the memory layer 60 is relatively low at the read voltage.

[0183] The memory layer 60 has the function of suppressing the increase in semi-selective leakage current flowing to the semi-selective cells. The memory layer 60 also has the function of storing data by resistance changes. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first to fourth embodiments.

[0184] Figure 14 is an explanatory diagram of the current-voltage characteristics of the memory element in the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 14, the horizontal axis shows the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. Figure 14 shows the current-voltage characteristics of the memory layer 60 in the fifth embodiment. Figure 14 shows the current-voltage characteristics of the memory cell MC in the fifth embodiment.

[0185] The memory element of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 14, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0186] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0187] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0188] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0189] The memory element of the fifth embodiment can take on both a high-resistance state and a low-resistance state under both positive and negative voltage conditions. When a predetermined positive voltage is applied to the upper electrode 20, it enters a high-resistance state under both positive and negative voltage conditions. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a low-resistance state under both positive and negative voltage conditions. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0190] Figure 15 is an explanatory diagram of a first example of the memory operation of the storage device according to the fifth embodiment. Figure 15 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0191] In the first operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the first operational example, the negative side read voltage Vrn is used as the read voltage.

[0192] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0193] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0194] In the first example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0195] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0196] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0197] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0198] In the first example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the first example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0199] Figure 16 is an explanatory diagram of a second example of memory operation of the storage device according to the fifth embodiment. Figure 16 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0200] In the second operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the second operating example, the positive side read voltage Vrp is used as the read voltage.

[0201] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0202] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0203] In the second example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0204] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0205] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0206] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0207] In the second example of operation, if the data in the selected cell is "1", no data corruption will occur by applying the positive side read voltage Vrp. In other words, in the second example of operation, if the data in the selected cell is "1", non-destructive reading is possible.

[0208] On the other hand, if the data in the selected cell is "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data in the selected cell to "1". In other words, in the second example of operation, if the data in the selected cell is "0", a destructive read may occur. Therefore, if the data in the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data in the selected cell in order to maintain the data in the selected cell.

[0209] (First variation) The first modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0210] Figure 17 is an explanatory diagram of the current-voltage characteristics of a memory element in the first modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 17, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 17 shows the current-voltage characteristics of the memory layer 60 in the first modified example of the fifth embodiment. Figure 17 shows the current-voltage characteristics of the memory cell MC in the first modified example of the fifth embodiment.

[0211] The memory element of the first modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 17, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0212] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0213] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0214] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0215] The memory element of the first modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it enters a low-resistance state on both the positive and negative voltage sides. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a high-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0216] Figure 18 is an explanatory diagram of a third example of the memory operation of the storage device of the first modification of the fifth embodiment. Figure 18 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0217] In the third operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the third operational example, the negative side read voltage Vrn is used as the read voltage.

[0218] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0219] When writing the data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0220] In the third example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0221] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0222] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0223] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0224] In the third example of operation, if the data in the selected cell is "1", no data corruption will occur due to the application of the negative read voltage Vrn. In other words, in the third example of operation, if the data in the selected cell is "1", non-destructive readout is possible.

[0225] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the third example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0226] Figure 19 is an explanatory diagram of a fourth example of the memory operation of the storage device of the first modification of the fifth embodiment. Figure 19 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0227] In the fourth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the fourth operating example, the positive side read voltage Vrp is used as the read voltage.

[0228] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0229] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0230] In the fourth example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0231] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0232] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0233] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0234] In the fourth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fourth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0235] (Second variation) The second modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0236] Figure 20 is an explanatory diagram of the current-voltage characteristics of a memory element in a second modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 20, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 20 shows the current-voltage characteristics of the memory layer 60 in a second modified example of the fifth embodiment. Figure 20 shows the current-voltage characteristics of the memory cell MC in a second modified example of the fifth embodiment.

[0237] The memory element of the second modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 20, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0238] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0239] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0240] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0241] The memory element of the second modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0242] Figure 21 is an explanatory diagram of a fifth example of the memory operation of a storage device in the second modification of the fifth embodiment. Figure 21 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0243] In the fifth operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the fifth operating example, the negative side read voltage Vrn is used as the read voltage.

[0244] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0245] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0246] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0247] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0248] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0249] In the fifth example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fifth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0250] Figure 22 is an explanatory diagram of a sixth example of memory operation of a storage device in the second modification of the fifth embodiment. Figure 22 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0251] In the sixth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the sixth operating example, the positive side read voltage Vrp is used as the read voltage.

[0252] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0253] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0254] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0255] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0256] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0257] In the sixth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the sixth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0258] (Third variation) The third modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0259] Figure 23 is an explanatory diagram of the current-voltage characteristics of a memory element in the third modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 23, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 23 shows the current-voltage characteristics of the memory layer 60 in the third modified example of the fifth embodiment. Figure 23 shows the current-voltage characteristics of the memory cell MC in the third modified example of the fifth embodiment.

[0260] The memory element of the third modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 23, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0261] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0262] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0263] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0264] The memory element of the third modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0265] Figure 24 is an explanatory diagram of a seventh example of memory operation of a storage device in the third modification of the fifth embodiment. Figure 24 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0266] In the seventh operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the seventh operating example, the negative side read voltage Vrn is used as the read voltage.

[0267] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0268] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive-side threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0269] In the seventh example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0270] Furthermore, in the seventh example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0271] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0272] Therefore, even when the semi-selected cell is in the low-resistance state, the semi-selected leakage current flowing through the semi-selected cell can be suppressed. Thus, the memory element also functions as a switching element.

[0273] When reading the data of the selected cell, a negative-side read voltage Vrn is applied to the selected cell. The data of the selected cell can be determined by detecting a current change or a potential change caused by the difference in the current flowing between the case of data "1" and the case of data "0".

[0274] In addition, in the case of the seventh operation example, when the data of the selected cell is data "1", no data destruction occurs by applying the negative-side read voltage Vrn. In other words, in the case of the seventh operation example, if the data of the selected cell is data "1", non-destructive readout is possible.

[0275] On the other hand, when the data of the selected cell is data "0", by applying a negative-side read voltage Vrn lower than the first negative voltage-side threshold voltage Vtpn, a current may flow, and the data of the selected cell may change to data "1". In other words, in the case of the seventh operation example, when the data of the selected cell is data "0", there is a possibility of destructive readout. Therefore, when the data of the selected cell is data "0", after reading the data of the selected cell, in order to maintain the data of the selected cell, it may be necessary to rewrite the data "0".

[0276] FIG. 25 is an explanatory diagram of an eighth operation example of the memory operation of the memory device according to the third modification of the fifth embodiment. FIG. 25 shows a positive-side write voltage Vwp, a voltage (Vwp / 2) that is half of the positive-side write voltage Vwp, a negative-side write voltage Vwn, a voltage (Vwn / 2) that is half of the negative-side write voltage Vwn, and a positive-side read voltage Vrp when performing the memory operation.

[0277] In the eighth operation example, the high-resistance state and the low-resistance state on the positive voltage side are used for the memory operation. In the eighth operation example, the positive-side read voltage Vrp is used as the read voltage.

[0278] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0279] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0280] In the eighth example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0281] Furthermore, in the eighth example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0282] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0283] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0284] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0285] In the case of the eighth operating example, if the data in the selected cell is "1", no data corruption will occur by applying the positive side read voltage Vrp. In other words, in the case of the eighth operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0286] On the other hand, if the data of the selected cell is "0", applying a positive read voltage Vrp that is higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the case of the eighth example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data of the selected cell.

[0287] In the fifth embodiment and its modified versions, the memory elements of the memory cell MC have a switching function and a function for storing information. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistive switching layer 50 of the first to fourth embodiments. By having a single-layer memory layer 60 in the fifth embodiment that has both a switching function and a memory function, the structure of the memory cell MC can be made extremely simple.

[0288] Furthermore, the memory layer 60 of the fifth embodiment and its modified version has the same configuration as the switching layer 40 of the first to fourth embodiments. Therefore, according to the fifth embodiment and its modified version, a storage device with excellent switching characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first to fourth embodiments.

[0289] Furthermore, the multiple current-voltage characteristics of the memory element shown in the fifth embodiment and its modified form can be achieved, for example, by employing a memory layer 60 having an appropriate chemical composition.

[0290] In the first to third embodiments, magnetoresistive memory was described as an example of a two-terminal storage device, and in the fourth embodiment, resistive random-access memory was described as an example of a storage device. However, the present invention can be applied to other two-terminal storage devices. For example, the present invention can be applied to phase-change memory (PCM) or ferroelectric random-access memory (FeRAM).

[0291] As described above, some embodiments of the present invention have been explained. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0292] 10 Lower electrode (first conductive layer) 10a First layer 10b Second layer 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 30a First layer 30b Second layer 40 Switching layer 41 Internal region (first region) 42a First sidewall region (second region) 42b Second sidewall region (third region) 42x First sidewall region (second region) 42y Second sidewall region (third region) 50 Resistance change layer 60 Memory layer 102 Word line (first wiring) 103 Bit line (second wiring) MC Memory cell

Claims

1. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, A memory cell comprising a resistive change layer provided between the third conductive layer and the second conductive layer, The aforementioned switching layer is An oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As), A compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), Includes, A memory device in which, in the switching layer, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 10% or more.

2. The storage device according to claim 1, wherein the first ratio is 20% or more.

3. The storage device according to claim 1, wherein the first ratio is 40% or more.

4. The storage device according to claim 1, wherein the first ratio is 55% or more.

5. The memory device according to claim 1, wherein the switching layer further comprises a fourth element, which is at least one element selected from the group consisting of lithium (Li), sodium (Na), potassium (K), magnesium (Mg), calcium (Ca), barium (Ba), lead (Pb), aluminum (Al), vanadium (V), iron (Fe), and tungsten (W).

6. The storage device according to claim 1, wherein the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the switching layer is 90% or more.

7. The memory device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

8. The first conductive layer includes a first layer and a second layer provided between the switching layer and the first layer and in contact with the switching layer. The first layer comprises carbon, carbon nitride, or tungsten carbide. The storage device according to claim 1, wherein the second layer comprises tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride.

9. The third conductive layer includes a first layer and a second layer provided between the switching layer and the first layer and in contact with the switching layer. The first layer comprises carbon, carbon nitride, or tungsten carbide. The storage device according to claim 1, wherein the second layer comprises tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride.

10. The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. The first region may or may not contain fluorine (F), and the second and third regions may contain fluorine (F). The storage device according to claim 1, wherein the atomic concentrations of fluorine (F) in the second region and the third region are higher than the atomic concentration of fluorine in the first region.

11. The storage device according to claim 10, wherein the atomic concentration of the second element in the second region and the third region is higher than the atomic concentration of the second element in the first region.

12. The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. The atomic concentration of the second element in the second region and the third region is lower than the atomic concentration of the second element in the first region. The storage device according to claim 1, wherein the atomic concentration of the third element in the second region and the third region is lower than the atomic concentration of the third element in the first region.

13. The storage device according to claim 1, wherein the second ratio of the atomic concentration of the second element to the atomic concentration of the third element is 50% or more and 200% or less.

14. The storage device according to claim 1, wherein the resistance change layer includes a magnetic tunnel junction.

15. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 1, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

16. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 1, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

17. A first conductive layer and A second conductive layer, A memory cell comprising a memory layer provided between the first conductive layer and the second conductive layer, The aforementioned memory layer is An oxide of a first element, which is at least one element selected from the group consisting of silicon (Si), boron (B), germanium (Ge), phosphorus (P), and arsenic (As), A compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), Includes, A memory device in which, in the memory layer, the first ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) is 10% or more.

18. The storage device according to claim 17, wherein the first ratio is 20% or more.

19. The storage device according to claim 17, wherein the first ratio is 40% or more.

20. The storage device according to claim 17, wherein the first ratio is 55% or more.

21. The memory device according to claim 17, wherein the memory layer further comprises a fourth element, which is at least one element selected from the group consisting of lithium (Li), sodium (Na), potassium (K), magnesium (Mg), calcium (Ca), barium (Ba), lead (Pb), aluminum (Al), vanadium (V), iron (Fe), and tungsten (W).

22. The storage device according to claim 17, wherein the sum of the atomic concentrations of the first element, the second element, the third element, and oxygen (O) in the memory layer is 90% or more.

23. The storage device according to claim 17, wherein the first conductive layer or the second conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

24. The first conductive layer includes a first layer and a second layer provided between the memory layer and the first layer and in contact with the memory layer. The first layer comprises carbon, carbon nitride, or tungsten carbide. The storage device according to claim 17, wherein the second layer comprises tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride.

25. The second conductive layer includes the first layer and the second layer provided between the memory layer and the first layer and in contact with the memory layer. The first layer comprises carbon, carbon nitride, or tungsten carbide. The storage device according to claim 17, wherein the second layer comprises tungsten, tungsten nitride, titanium, titanium nitride, tantalum, or tantalum nitride.

26. The memory layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. The first region may or may not contain fluorine (F), and the second and third regions may contain fluorine (F). The storage device according to claim 17, wherein the atomic concentrations of fluorine (F) in the second region and the third region are higher than the atomic concentration of fluorine in the first region.

27. The storage device according to claim 26, wherein the atomic concentration of the second element in the second region and the third region is higher than the atomic concentration of the second element in the first region.

28. The memory layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. The atomic concentration of the second element in the second region and the third region is lower than the atomic concentration of the second element in the first region. The storage device according to claim 17, wherein the atomic concentration of the third element in the second region and the third region is lower than the atomic concentration of the third element in the first region.

29. The storage device according to claim 17, wherein the second ratio of the atomic concentration of the second element to the atomic concentration of the third element is 50% or more and 200% or less.

30. The memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, and the threshold voltage changes when a predetermined voltage is applied, as described in claim 17.

31. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 17, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

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