Photolithographic resistive switching array

Abstract

A memristor device is described. The memristor device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and a memristor interlayer connector. The first layer and the second layer are distinct. The first plurality of conductive lines and the second plurality of conductive lines are each photolithographically defined. The first plurality of conductive lines and the second plurality of conductive lines are insulated from each other. The memristor interlayer connector is memristively connected to a first portion of the first plurality of conductive lines and memristively connected to a second portion of the second plurality of conductive lines. Therefore, the memristor interlayer connector is sparsely connected to the first plurality of conductive lines and the second plurality of conductive lines. Each memristor interlayer connector includes a conductive portion and a memristor portion. The memristor portion is located between the conductive portion and a corresponding line in the first plurality of conductive lines and / or the second plurality of conductive lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 044104, filed June 25, 2020, entitled Memristor Array with Floating Electrodes, and U.S. Provisional Patent Application No. 63 / 088325, filed October 6, 2020, entitled Sparse Neural Array, both of which are incorporated herein by reference for all purposes. Background Technology

[0003] Matrix multiplication is used in a variety of computational applications. For example, multi-layered vector-matrix multiplication can be performed by multi-layered crossbar arrays. In such applications, the input signals form an input vector that is provided to the crossbar array. The input signals can be data for still images, video frames, and / or other information. The input signals are multiplied by a matrix of weights. The weight matrix is ​​provided by resistors at the crossbars between the inputs and outputs. In the crossbar array, each input is connected to all of the outputs (i.e., fully connected). The output signal is the result of the vector-matrix multiplication of the input signals and forms an output vector. The output vector can be provided as an input vector to the next crossbar array. This process continues until processing is complete. Therefore, the final output of the crossbar array is the system output. Such vector-matrix multiplication performed by crossbar arrays can also be performed in neural networks. In this case, the input to the crossbar is an input neuron, and the output to the crossbar can be an output neuron. Multiple crossbar arrays can also be used in neural network applications. In this case, the input to the first crossbar array is an input neuron. The output for the last crossbar array is an output neuron.

[0004] Memristors can provide resistance or weighting between the inputs and outputs of a cross array. The resistance of a memristor can depend on the current previously flowing through the device or the voltage driven across the device. Therefore, memristors provide programmable weighting for the cross array. For example, a cross array includes a first set of parallel metal lines and a second set of parallel metal lines in two different layers of the device. The metal lines in the first set are nominally perpendicular to the metal lines in the second set. Memristors provide connections between the first and second sets of parallel lines at the locations where the lines cross. Despite the use of such arrays, improved mechanisms are desired for performing computational operations such as matrix multiplication. Attached Figure Description

[0005] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

[0006] Figure 1A-1D A portion depicting an embodiment of a memristor device.

[0007] Figure 2An embodiment depicting a portion of a memristor device.

[0008] Figure 3 An embodiment depicting a portion of a memristor device.

[0009] Figure 4 An embodiment depicting a portion of a memristor device.

[0010] Figure 5 An embodiment depicting a portion of a memristor device.

[0011] Figure 6 This is a flowchart depicting an embodiment of a method for providing a memristor device.

[0012] Figures 7A-7G An embodiment of a memristor device during its formation is described.

[0013] Figure 8 An embodiment depicting a portion of a memristor device.

[0014] Figure 9A-9G An embodiment depicting a portion of a memristor device during manufacturing.

[0015] Figure 10 An embodiment depicting a portion of a memristor device.

[0016] Figure 11 An embodiment depicting a portion of a memristor device.

[0017] Figure 12 This is a diagram depicting an embodiment of a device comprising a sparsely connected neural array.

[0018] Figures 13A-13E This is a diagram depicting an embodiment of a device including a sparse neural array during manufacturing.

[0019] Figure 14 This is a flowchart depicting an embodiment of a method for using sparsely connected neural arrays. Detailed Implementation

[0020] This invention can be embodied in many ways, including as a process; an apparatus; a system; a component of matter; a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor configured to execute instructions stored on and / or provided by memory linked to and / or linked to the processor. In this specification, these embodiments or any other forms in which the invention may be taken are referred to as techniques. Generally, within the scope of this invention, the order of steps of the disclosed process may be varied. Unless otherwise stated, components described as being configured to perform a task, such as processors or memory, may be implemented as general components temporarily configured to perform a task at a given time or manufactured as specific components for performing a task. As used herein, the term "processor" means one or more means, circuits, and / or processing cores configured to process data such as computer program instructions.

[0021] The following detailed description of one or more embodiments of the invention, together with the accompanying drawings illustrating the principles of the invention, provides for illustrative purposes. The invention has been described in conjunction with such embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims, and the invention covers numerous alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes, and the invention may be practiced without some or all of these specific details, as described in the claims. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0022] Cross arrays are used in a variety of applications such as vector-matrix multiplication. Memristors, whose resistance can depend on the voltage previously crossed across the device or the current flowing through it, can be used to provide programmable weights in a cross array. When used as programmable weights, the memristor is located at each connection. Cross arrays are also typically densely connected. In other words, all available connections are made between the inputs and outputs of the cross array. Such densely connected networks are inherently regular, and their design, construction, and operation can be expensive and complex, consuming a relatively large amount of area, and scaling can be challenging.

[0023] A memristor device comprising multiple layers of sparsely interconnected conductive lines is disclosed. For example, the memristor device has at least a first layer and a second layer. The first layer includes a first plurality of conductive lines photolithographically defined. The second layer differs from the first layer and includes a second plurality of conductive lines. The second plurality of conductive lines are insulated from the first plurality of conductive lines. The second plurality of conductive lines are also photolithographically defined. A memristor interlayer connector is memristorically connected to a first portion of the first plurality of conductive lines and memristorically connected to a second portion of the second plurality of conductive lines. Thus, the memristor interlayer connector is sparsely connected to the first plurality of conductive lines and sparsely connected to the second plurality of conductive lines. Each memristor interlayer connector has a conductive portion and a memristor portion. The memristor portion is located between the conductive portion and a corresponding line in the first plurality of conductive lines and / or the second plurality of conductive lines. In some embodiments, the first plurality of conductive lines and / or the second plurality of conductive lines are floating.

[0024] Therefore, memristor devices can be sparsely connected. A sparsely connected network is one in which not all possible or available connections are made between the network's inputs and outputs. Thus, memristor devices can be used in applications such as neural networks, where sparse connectivity leads to improved performance, scaling, and / or compression. The density of connections can be customized by selecting the geometry of the conductive lines in the first and second layers and the layout of the memristor interlayer connectors. Furthermore, while the components of a memristor device can be fabricated deterministically (e.g., photolithographically), the connections can be inherently random. Since individual layers and memristor interlayer connectors can be photolithographically defined, memristor devices (with slightly random connections) can also be repeatedly fabricated. As a result, the fabrication and performance of such memristor devices can be improved.

[0025] The conductive portion of a memristor interlayer connector may be a conductive post with sidewalls. In some such embodiments, the memristor portion surrounds at least a portion of the sidewalls. In some embodiments, a first plurality of conductive lines and / or a second plurality of conductive lines are connected to the memristor interlayer connector by a conductive branch structure. In some such embodiments, the memristor portion of each memristor interlayer connector includes a memristor layer adjacent to the conductive branch structure.

[0026] In some embodiments, the first plurality of conductive lines have a first long axis oriented along a first direction, and the second plurality of conductive lines have a second long axis oriented along a second direction. The first direction and the second direction form a non-zero acute angle. Due to the location of the memristor interlayer connector and the geometry of the first plurality of lines and the second plurality of lines, the memristor connector is sparsely connected to the first plurality of conductive lines and the second plurality of conductive lines. In some embodiments, each of the first plurality of conductive lines and / or the second plurality of conductive lines includes a line segment having a long axis oriented along multiple directions. In some embodiments, each of the first plurality of conductive lines and / or the second plurality of conductive lines includes a non-linear segment. Therefore, the conductive lines form a non-periodic and / or irregular network.

[0027] In some embodiments, the first plurality of conductive lines have a first connectivity, and the second plurality of conductive lines have a second connectivity. The memristor device has a third connectivity that is less than the first connectivity and less than the second connectivity. Therefore, in some embodiments, not only are the conductive lines in each layer sparsely connected to the memristor interlayer connector, but the connectivity of the memristor device is also lower than the connectivity of one of its layers.

[0028] In some embodiments, the memristor device further includes conductive interlayer connectors. These conductive interlayer connectors may correspond to memristor interlayer connectors. For example, memristor interlayer connectors and conductive interlayer connectors may appear in pairs. The conductive interlayer connectors are electrically connected to a third portion of a first plurality of conductive lines and electrically connected to a fourth portion of a second plurality of conductive lines. Thus, the conductive interlayer connectors may also be sparsely connected to conductive lines in the first and / or second layers. The memristor device may also include input neurons and output neurons. Input neurons may be connected to conductive interlayer connectors, while output neurons are connected to memristor interlayer connectors. In some such embodiments, conductive lines in the first and / or second layers connected to the memristor interlayer connectors and conductive interlayer connectors may form clusters.

[0029] A neural network is also described. The neural network includes: a first layer including a first plurality of photolithographically defined conductive lines, a second layer including a second plurality of photolithographically defined conductive lines, a memristor interlayer connector, and neurons connected to the memristor interlayer connector. In some embodiments, the second layer may be omitted. The first and second layers are similar to those described relative to a memristor device. Similarly, the memristor interlayer connector is similar to those described in conjunction with a memristor device. As a result, in some embodiments, the first plurality of conductive lines and / or the second plurality of conductive lines are floating. In some embodiments, the neural network includes conductive interlayer connectors. These conductive interlayer connectors are similar to those described in the context of a memristor device. Therefore, in some embodiments, individual memristor connections between conductive lines and memristor interlayer connectors are individually addressable. In some such embodiments, conductive lines connected to the memristor interlayer connector and the conductive interlayer connector in the first and / or second layers may form clusters.

[0030] A method of providing a memristor device is also described. The method includes photolithographically defining a first plurality of conductive lines in a first layer and photolithographically defining a second plurality of conductive lines in a second layer. The second layer differs from the first layer. The second plurality of conductive lines are insulated from the first plurality of conductive lines. The method also includes providing a memristor interlayer connector that is coupled to a first portion of the first plurality of conductive lines and to a second portion of the second plurality of conductive lines. The memristor interlayer connector is sparsely coupled to the first plurality of conductive lines and sparsely coupled to the second plurality of conductive lines. Each memristor interlayer connector includes a conductive portion and a memristor portion between the conductive portion and a corresponding line in the first plurality of conductive lines and / or the second plurality of conductive lines. In some embodiments, the first plurality of conductive lines and / or the second plurality of conductive lines are floating.

[0031] In some embodiments, photolithographically defining the first plurality of conductive lines further includes defining a first long axis oriented along a first direction for the first plurality of conductive lines. In such embodiments, photolithographically defining the second plurality of conductive lines includes defining a second long axis oriented along a second direction. The first direction forms a non-zero acute angle with the second direction. In some embodiments, each of the first plurality of conductive lines and / or the second plurality of conductive lines includes a line segment having a long axis oriented along multiple directions.

[0032] In some embodiments, the method includes providing conductive interlayer connectors corresponding to a plurality of memristor interlayer connectors. The conductive interlayer connectors are electrically connected to a third portion of a first plurality of conductive lines and to a fourth portion of a second plurality of conductive lines. In some such embodiments, the method includes providing input neurons and output neurons. The input neurons are coupled to at least some of the conductive interlayer connectors. The output neurons are coupled to at least some of the memristor interlayer connectors. Some of the first plurality of conductive lines and / or the second plurality of conductive lines may form a cluster.

[0033] In some embodiments, a method includes accessing a first conductive line in a memristor device by applying a voltage to a conductive portion of a memristor interlayer connector. In some embodiments, the memristor connection can be individually programmed by providing a voltage difference between the conductive portion of the memristor interlayer connector and a corresponding conductive interlayer connector.

[0034] A neural device is also described. The neural device includes at least one layer. The layer includes conductive lines that can be photolithographically defined. The neural device also includes memristor interlayer connectors and conductive interlayer connectors corresponding to the memristor interlayer connectors. The memristor interlayer connectors are memristorically coupled to a first portion of the conductive lines, such that the memristor interlayer connectors are sparsely coupled to a plurality of conductive lines. Each memristor interlayer connector includes a conductive portion and a memristor portion between the conductive portion and a corresponding line of the first portion of the conductive line. The conductive interlayer connectors are electrically connected to second portions of the plurality of conductive lines. The neural device also includes input neurons and output neurons. Input neurons are coupled to at least a portion of the conductive interlayer connectors. Output neurons are coupled to at least a portion of the memristor interlayer connectors. In some embodiments, the first portion of the conductive lines coupled to the memristor interlayer connectors includes a cluster of conductive lines. Thus, in some embodiments, the connections between the conductive lines, the conductive interlayer connectors, and the memristor interlayer connectors form a cluster. In some embodiments, the neural device includes multiple layers of conductive lines. In some such embodiments, the layers of conductive lines are constructed in a manner similar to the memristor device described herein.

[0035] Various constructions are described herein. While specific combinations of constructions are shown, some or all of these aspects may be provided individually and / or in combinations not explicitly discussed. For example, the type of conductive lines in a particular memristor device may include conductive lines from various embodiments (e.g., straight, curved, arbitrary-shaped, including conductive branch structures, and / or formed by segments of a lattice) in one or more layers. Similarly, a particular device may include types of memristor interconnects from multiple embodiments (e.g., varying sizes, memristor cases, memristor layers, and / or memristor contacts) in one or more layers.

[0036] Figure 1A-1D A portion of an embodiment of memristor devices 100 and 100' is depicted. Figure 1A-1B A view depicting the layers of the memristor device 100. Figure 1C This is a cross-sectional view of a portion of the memristor device 100. Figure 1D An embodiment of memristor device 100 is depicted. For clarity, only a portion of memristor devices 100 and 100' is shown. Figure 1A-1D Not to scale or ratio. For simplicity, only some structures are marked.

[0037] refer to Figure 1A-1CThe memristor device includes a substrate 101, and devices 106 and 108 may be formed in or on the substrate. For example, devices 106 and 108 may be neurons such as CMOS neurons. In some embodiments, other and / or additional devices may be present. Although shown within substrate 101, devices 106 and 108 may be formed within, on, and / or over substrate 101. An insulating layer 102 is shown on substrate 101.

[0038] Memristor device 100 includes layers 111 and 121 and memristor interlayer connectors. For simplicity, only four memristor interlayer connectors 140A, 140B, 140C, and 140D (commonly or generally memristor interlayer connector 140) are labeled. Figure 1C As indicated, the memristor interlayer connector 140 penetrates and connects multiple layers 111 and 121. Each memristor interlayer connector may include a conductive portion 142 and a memristor portion 144. For simplicity, only the memristor interlayer connector 140A has the marked conductive portion 142 and memristor portion 144. The memristor portion 144 may be a memristor material, such as HfO. x and / or TiO x (Where x indicates various stoichiometry). The conductive portion 142 may be a metal or metal alloy, such as Cu, Al, and / or alloys thereof. In the illustrated embodiment, the memristor interlayer connector 140 is configured as a through-hole. Therefore, the memristor portion 144 may form a shell surrounding the sidewalls of the conductive portion 142. Furthermore, the conductive portion 142 is formed as a pillar. However, in other embodiments, the memristor interlayer connector 140 may have other configurations. For example, the memristor material 144 may only cover a portion of the sidewalls of the conductive pillar 142. In the illustrated embodiment, the interlayer connector 140 is substantially perpendicular to layers 111 and 121. However, other angles are also possible. In the illustrated embodiment, the memristor interlayer connector 140 has a pitch d1 in one direction (the distance between the centers in the illustrated embodiment), a pitch d2 in the vertical direction, and an offset of Δ.

[0039] The memristor interlayer connector 140 is also fabricated using photolithography. For example, a mask with orifices aligned with the location of the memristor interlayer connector 140 can be fabricated, the exposed structure can be etched to a desired depth, and the formed vias can be refilled with memristor portions 144 and conductive portions 142. Thus, the location, size, and shape of the memristor interlayer connector 140 are deterministically determined during fabrication.

[0040] Layer 111 includes conductive lines 110A, 110B, 110C, 110D, and 110E (common or overall conductive lines 110). Similarly, layer 121 includes conductive lines 120A, 120B, 120C, 120D, 120E, and 120F (common or overall conductive lines 120). Conductive lines 110 and 120 may be metallic wires. For example, conductive lines 110 and / or 120 may be formed of Cu, Al, alloys thereof, another metal, and / or another metal alloy. Conductive line 110 has a pitch p1 in layer 111. Conductive line 120 has a pitch p2 in layer 121. Layers 111 and 121 also include insulators 112 and 114, respectively. Insulators 112 and 122 may be insulating dielectrics. For example, silicon dioxide may be used for insulators 112 and 122. In some embodiments, insulators 112 and / or 122 comprise a silicon dioxide layer nominally 200 nanometers thick (but the thickness can vary arbitrarily). In some embodiments, some of the conductive lines 110 and / or 120 are connected to conductive lines in another layer via conductive interlayer connectors excluding memristor portions. In such embodiments, such conductive lines can be considered longer and extend into multiple layers. In the illustrated embodiment, the major axis of conductive line 120 forms a non-zero acute angle θ with the direction of the major axis of conductive line 110. In the illustrated embodiment, conductive lines 110 and 120 are floating (not directly electrically connected to another structure). In other embodiments, direct contact with one or more of conductive lines 110 and / or 120 can be made. Therefore, conductive lines 110 and / or 120 do not need to be floating. Furthermore, although shown as and referred to as “lines”, conductive lines 110 and / or 120 can have arbitrary shapes, including but not limited to incorporated line segments, curves, and / or loops.

[0041] Conductor lines 110 and 120 are also defined (e.g., fabricated) by photolithography. For example, a mask having apertures aligned with the location of conductor line 110 can be fabricated, a metal layer can be deposited, and the mask can be removed. Alternatively, a mask having apertures aligned with the location of conductor line 110 can be fabricated, an underlayer insulating layer can be etched to form trenches or apertures in the insulating layer, the trenches / apertures can be filled with metal, and the mask can be removed. In other embodiments, a metal layer can be deposited to provide a mask covering the area corresponding to conductor line 110, and the exposed metal layer can be etched. Other techniques can be used to fabricate conductor line 110. Conductor line 120 can be formed in a similar manner. Therefore, the location, size, and shape of conductor lines 110 and 120 are determined deterministically during fabrication.

[0042] Conductive lines 110 and 120 are memristively connected to memristor interlayer connector 140. In other words, conductive lines 110 and 120 are electrically connected to conductive section 142 via memristor section 144. This region of the memristor connection is generally composed of… Figure 1CThe dashed lines within the memristor portion 144 are shown. Each pair of dashed lines covering the area sandwiched between the conductive lines 110 or 120 and the metal core 142 can be considered to form a single memristor. Although each memristor interlayer connector 140 is shown as connecting to zero or one conductive line 110 or 120 in layer 111 or 121, the memristor interlayer connector 140 may be contacted by more than one conductive line in a given layer. The conductive lines 110 and 120 and the memristor interlayer connector 140 are configured such that layers 110 and 120 and the memristor device 100 are sparsely connected. In other words, conductive line 110 is sparsely and memristively connected to the memristor interlayer connector 140, and conductive line 120 is sparsely and memristively connected to the memristor interlayer connector 140. A sparsely connected network is one in which not all possible or available connections are made between the network's inputs and outputs. A sparsely connected network is the opposite of a densely connected network (e.g., a cross array) in which all available connections are made between the inputs and outputs of a cross array. For example, conductor 110A is electrically connected to only two of the three memristor interlayer connectors 140 closest to conductor 110A (in physical contact / touch in the illustrated view). Similarly, conductor 110B is electrically connected to only one memristor interlayer connector 140B. In some embodiments, connectivity may be indicated by the fraction of conductors in the layers (or devices) connected to the interlayer connectors. Thus, if conductor 110 is connected to all memristor interlayer connectors 140, the connectivity is 1. Memristor devices 100 may be constructed (i.e., densely connected). In some embodiments, the connectivity of memristor devices 100 is lower than the connectivity of any of its layers (i.e., memristor devices 100 are more sparsely connected than layers 111 and 121). In some embodiments, the sparsity of the connectivity of memristor devices 100 may be preserved for additional layers. For example, the introduction of another layer of sparsely connected conductive lines may not significantly reduce (and / or may not increase) the connection density in the memristor device 100.

[0043] The sparse connectivity between conductive line 110 and memristor interlayer connector 140 can be based on the location, size, and shape of memristor interlayer connector 140 and conductive lines 110 and 120. To achieve sparse connectivity, the geometry of conductive line 110 differs from that of conductive line 120. For example, conductive line 120 provides a current path (e.g., a major axis) at an angle θ to the current path (e.g., the major axis) used for conductive line 110. Other aspects of the geometry of layers 111 and 121 may differ. For example, for sparse connectivity, pitches p1 and p2 may be different (or the same), pitch p1 may vary across the plane of layer 111 while pitch p2 remains constant, pitch p2 may vary across the plane of layer 121 while pitch p1 remains constant, pitch p1 may vary across the plane of layer 111 in a manner different from the variation of pitch p2 across layer 121, the relative angle θ may vary, the width of conductors 110 and / or 120 may vary, the length of conductors 110 and / or 120 may vary, the distance between memristor interlayer connectors 140 (d1 and / or d2) may vary, the offset Δ may vary and / or be selected for sparse connectivity, conductors 110 and / or 120 within a layer may not be parallel, the size s of memristor interlayer connectors 140 may vary and / or be customized, and / or the shape of memristor interlayer connectors 140 may be different. In some embodiments, the shape of conductors 110 and / or 120 may be randomized.

[0044] In addition to the sparse interconnection of memristor device 100 and layers 111 and 121, the connectivity of memristor device 100 can be made increasingly random by adding more layers. For example, Figure 1DA perspective view of memristor device 100' is depicted. Memristor device 100' is similar to memristor device 100. Therefore, memristor device 100 includes layers 111' and 121' having conductive lines 110 and 120 respectively, which are similar to layers 111 and 121 having conductive lines 110 and 120 respectively. Additionally, the memristor interlayer connector 140 having conductive portion 142 and memristor portion 144 is similar to those of memristor device 100. Memristor device 100' also includes an additional layer 131. Therefore, memristor device 100' includes conductive lines 130 in layer 131. Conductive lines 130 are perpendicular to conductive lines 110. Therefore, conductive lines 130 form a non-zero acute angle (π / 2-θ) with conductive lines 120. Conductive lines 130 are also photolithographically formed. The dimensions, location, pitch, thickness, width, length, shape material used, and / or other characteristics of conductive lines 130 are similar to those of conductive lines 110 and / or 120. Conductive lines 130 are sparsely memristorly connected to memristor interlayer connectors 140, and thus to conductive lines 110 and 120. Furthermore, the connectivity between memristor interlayer connectors 140 and conductive lines 130 differs from the connectivity between memristor interlayer connectors 140 and lines 110 and / or 120. Additional layers (not shown) of conductive lines may also be added. In some embodiments, the sparsity of memristor devices 100 and / or 100' may increase, decrease, or remain substantially constant with the addition of layers. In some embodiments, the randomness and / or irregularity of memristor devices 100 and / or 100' may increase, decrease, or remain constant with the addition of more layers.

[0045] In operation, the memristor portion 144 of the interlayer connector 140 is programmed to drive current through (i.e., place voltage across) the memristor portion 144 of the memristor interlayer connector 140 with a desired weight. Conductors 110 and 120 and / or conductors 110, 120 and 130 are electrically accessed by applying voltage to the conductive portion 142 of the corresponding memristor interlayer connector 140. In some embodiments, some or all of conductors 110, 120 and / or 130 are floating. Such floating conductors 110, 120 and / or 130 are accessed only through the corresponding memristor interlayer connector 140. In some embodiments, the memristor interlayer connector 140 serves as a control electrode. In other embodiments, additional conductive interlayer connectors may be provided and used to access conductors 110, 120 and / or 130.

[0046] Memristor devices 100 and / or 100' can be used where programmable resistors are desired. Memristor devices 100 and / or 100' allow for the photolithographically and deterministically formed networks of complex, randomized, and / or sparsely connected components. Since each layer 111 / 111', 121 / 121', and 131 can be photolithographically provided, the paths of the conductive lines 110, 120, and 130 in each layer are known. Similarly, the location and geometry of the memristor interlayer connector 140 are also predetermined. However, due to the differences between layers, memristor devices comprising many layers can form inherently more random networks. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scaling. Furthermore, the fabrication of each layer in each device is simple and repeatable. Due to the differences in the geometry of the (reproducibly fabricated) layers 111, 121, 131, and any subsequent layers, irregular (e.g., random or stochastic) networks can be formed. Multiple devices with the same irregular network may be generated. Therefore, the pattern of sparse connections within memristor devices 100 and 100' can be randomized but repeatable. As a result, the performance of systems using memristor devices 100 and / or 100' can be improved.

[0047] Figure 2 This is a perspective view of a portion of an embodiment of the memristor device 200. For clarity, only a portion of the memristor device 200 is shown. Figure 2 Not to scale. For simplicity, only some structures are labeled. Memristor device 200 is similar to memristor device 100 and / or 100'. Therefore, memristor device 200 includes memristor interlayer connectors 240 and layers 211, 221, 231, which are respectively similar to memristor interlayer connector 140 and layers 111, 121 and / or 131. Therefore, memristor interlayer connector 240 includes conductive portions 242 and memristor portions 244, which are respectively similar to conductive portions 142 and memristor portions 144. Layer 211 includes conductive lines 210, which are similar to conductive lines 110. Layer 221 includes conductive lines 220, which are similar to conductive lines 120. Layer 231 includes conductive lines 230, which are similar to conductive lines 130. Memristor device 200 also includes: an additional layer 251 including conductive lines 250, which is similar to layers 211, 221 and / or 231 and conductive lines 210, 220 and / or 230. Therefore, conduction lines 210, 220, 230 and 250 are photolithographically defined.

[0048] Compared to conductive lines 110, 120, and 130, conductive lines 210, 220, 230, and 250 have more arbitrary shapes (e.g., not straight lines). However, conductive lines 210, 220, 230, and 250 can still be fabricated via photolithography. For example, straight conductive line segments extending in different directions within a layer can intersect. At the intersection, conductive lines 210, 220, 230, and 250 have corners, nodes, curves, and / or other nonlinear segments. Such conductive line segments are electrically connected and have more arbitrary shapes. Such nonlinear, arbitrarily shaped conductive lines 210, 220, 230, and 250 can more easily have irregular, disordered (e.g., random), and / or sparse connectivity with the memristor interlayer connector 240. Therefore, conductive lines 210, 220, 230, and 250 can be densely or sparsely connected. However, the fabrication of each layer 210, 220, 230 and / or 250 can still be deterministic and repeatable. Additionally, although all layers 210, 220, 230 and 250 are shown as conductive lines 210, 220, 230 and 250 with arbitrary shapes, in some embodiments, one or more layers may have straight conductive lines.

[0049] Figure 3 A top view depicting layer 311 in an embodiment of memristor device 300. For clarity, only a portion of memristor device 300 is shown. Figure 3 Not to scale. For simplicity, only some structures are labeled. Memristor device 300 is similar to memristor devices 100, 100' and / or 200. Therefore, memristor device 300 includes memristor interlayer connectors such as the labeled memristor connectors 340A, 340B, 340C and 340D (common or overall memristor connector 340) and conductive lines 310A, 310B and 310C (common or overall conductive lines 310).

[0050] In layer 311, the width of the conductive lines 310 and the distance (i.e., pitch) between the conductive lines 310 vary. Therefore, conductive lines 310A and 310B are separated by a distance h1, while conductive lines 310B and 310C are separated by a different distance h2. Additionally, conductive line 310B has a width w1, while conductive line 310C has a different width w2. The geometry of the memristor interlayer connector 340 also varies. Therefore, various distances l1, l2, l3, and l4 separate the memristor interlayer connector 340. In some embodiments, the distances along other directions may vary. Layer 311 is also sparsely connected. In other embodiments, layer 311 may be densely connected. Despite the variation in distances, the memristor device 300 is still photolithographically formed and is therefore deterministic and repeatable in its fabrication. However, variations in layer 311 and other layers (not shown) can allow for greater irregularities in the memristor device 300.

[0051] Figure 4 A top view depicting layer 411 in an embodiment of memristor device 400. For clarity, only a portion of memristor device 400 is shown. Figure 4 Not to scale. For simplicity, only some structures are labeled. Memristor device 400 is similar to memristor devices 100, 100', 200 and / or 300. Therefore, memristor device 400 includes memristor interlayer connectors such as the labeled memristor connectors 440A, 440B, 440C and 440D (common or overall memristor connector 440) and conductive lines 410A, 410B, 410C and 410D (common or overall conductive lines 410).

[0052] In layer 411, the width of the conductive lines 410 and the distance between them vary. Furthermore, the conductive lines 410 are not parallel and extend at different distances. For example, conductive line 410B terminates in the field of view shown. Additionally, conductive line 410B is shown as including a loop. Conductive line 410C not only has multiple segments that converge at corners and extend in different directions, but also has varying widths. The geometry of the memristor interlayer connector 440 also varies. The memristor interlayer connector 440 also has different diameters s1 and s2. Layer 411 is also sparsely connected. In other embodiments, layer 411 may be densely connected. Despite the geometric variations, the memristor device 400 is still provided by photolithography and is therefore deterministic and repeatable in its fabrication. Variations in layer 411 and other layers (not shown) can allow for greater irregularities in the memristor device 400.

[0053] Figure 5 A cross-sectional view depicting an embodiment of the memristor device 500. For clarity, only a portion of the memristor device 500 is shown. Figure 5 Not to scale. For simplicity, only some structures are labeled. Memristor device 500 is similar to memristor devices 100, 100', 200, 300, and / or 400. Therefore, memristor device 500 includes memristor interlayer connectors 540A and 540B (commonly or generally memristor interlayer connector 540) and conductive lines 510A and 520A, similar to memristor interlayer connector 140 and conductive lines 110 and / or 120. Insulators 502, 512, and 522, respectively, are shown, similar to insulators 102, 112, and 122.

[0054] Memrist interlayer connectors 540A and 540B have different depths. Therefore, memrist interlayer connector 540A extends through conductive line 510A. However, memrist interlayer connector 540B extends into substrate 501. Therefore, the penetration depth (e.g., number of layers) of memrist interlayer connector 110 can also be used to control connectivity. Furthermore, memrist interconnects can extend to multiple devices. For example, memrist interconnects 540A and / or 540B can be connected to another device via conductive (e.g., metal / solder) bumps fabricated on the top surface of memrist device 500. Another memrist or other semiconductor device can be electrically connected to memrist interconnects 540A and / or 540B at the conductive bumps. Therefore, not only can conductive lines in multiple layers be connected via memrist interconnects, but multiple devices can also be connected via memrist interconnects.

[0055] Memristor devices 200, 300, 400, and / or 500 are similar to memristor devices 100 and / or 100'. As a result, memristor devices 200, 300, 400, and / or 500 can share the benefits of memristor devices 100 and / or 100'. Memristor devices 200, 300, 400, and / or 500 can provide complex, randomized, irregular, and / or sparsely connected, but lithographically and deterministically formed networks. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device, as well as devices 200, 300, 400, and / or 500 as a whole, is simplified and reproducible. As a result, the performance of systems using memristor devices 200, 300, 400, and / or 500 can be improved.

[0056] Figure 6 This is a flowchart depicting an embodiment of method 580 for providing a memristor device. For clarity, only some steps are shown. In some embodiments, other and / or additional processes may be performed. Although described in the context of a flowchart, the processes in method 580 may be performed in parallel and / or interleaved.

[0057] At 582, the first set of conductive lines in the first layer of the memristor device is photolithographically defined. In other words, photolithography (e.g., photolithography, UV lithography, and / or DUV lithography) is used to fabricate the first set of conductive lines. Although referred to as the first layer of the memristor device, the layer fabricated at 582 can be formed on the underlying structure. For example, a substrate, neurons, insulating layers, conductive lines, other semiconductor devices, electrodes, and / or other structures may have been formed. Furthermore, other structures may also be formed in this layer of the memristor device. The first set of conductive lines can be formed using a damascus process (lines formed in trenches provided in the insulating layer), a process of depositing and patterning conductive (e.g., metal) layers, and / or by other techniques.

[0058] At 584, a second set of conductive lines is photolithographically defined for a second layer of the memristor device. Some or all of the second set of conductive lines are insulated from the first set of conductive lines. Therefore, as part of 582 or 584, an insulating layer may be deposited on the first set of conductive lines. As part of 584, the second set of conductive lines may also be insulated. In some embodiments, 584 is implemented in a manner similar to 582. At 586, subsequent layers of conductive lines are optionally fabricated. In some embodiments, 586 is implemented in a manner similar to 582 and / or 584. Thus, multiple layers of conductive lines can be formed.

[0059] At 588, a memristor interlayer connector is photolithographically provided. The memristor interlayer connector is coupled to a first portion of a first set of conductive lines in the first layer and to a second portion of a second set of conductive lines in the second layer. The memristor interlayer connector may be sparsely coupled to a first plurality of conductive lines and sparsely coupled to a second plurality of conductive lines. The memristor interlayer connector is also coupled to portions of conductive lines in subsequent layers. For example, 588 may include providing a mask with orifices at the location of the memristor interlayer connector, and removing (e.g., etching) exposed portions of the memristor device. Thus, a via is formed. Memristor material may then be deposited to cover the sides of the via. The via is then filled with a conductive (e.g., metallic) material. In other embodiments, the memristor interlayer connector may be formed in another manner. For example, the memristor layer may be deposited and optionally patterned prior to the formation of the via described above. The via may be filled with a conductive material such that the memristor layer is interposed between the conductive portions and conductive lines of the memristor interlayer connector. In some embodiments, portions of 588 may be interleaved with 582, 584, and / or 586. For example, conductive vias may be formed after a subset of the fabrication layers.

[0060] In some embodiments, additional conductive interlayer connectors are fabricated at 590. These conductive interlayer connectors may be formed by photolithography. For example, 590 may include a mask with orifices provided at the location of the conductive interlayer connectors, and the removal (e.g., etching) of exposed portions of the memristor device. Thus, vias are formed. The vias are then filled with a conductive (e.g., metallic) material to provide conductive interlayer connectors. Thus, memristor devices can be formed.

[0061] For example, Figures 7A-7G An embodiment of the memristor device 600 is depicted during the formation process using method 580. For clarity, only a portion of the memristor device 600 is shown. Figures 7A-7G Not to scale. For simplicity, only some structures are marked. Figures 7A-7BThe memristor device 600 is depicted prior to the commencement of method 580. Thus, an overlying insulating substrate and an embedded pad 641 are shown. Pad 641 may be a metal pad (e.g., metal O) formed on the insulating substrate. Pad 641 may be considered as part of a memristor interlayer connector being formed, or as a separate component to which the memristor interlayer connector can be electrically connected. In some embodiments, other devices (not shown) are also formed. For example, neurons or other devices may have been provided on or within the insulating substrate. Figure 7B The memristor device 600 is depicted after an insulating layer 602 (e.g., insulator 1) has been formed on an embedded pad 641.

[0062] Figure 7C A conductive line (e.g., metal 1) 610 for the first layer 611 is depicted on the insulating layer 102 in method 580, at step 582. In some embodiments, the conductive line 610 is formed on the insulating layer 102. In such embodiments, the conductive line 610 is formed by an insulating dielectric layer below ( Figure 7C (Not shown in the image) insulation. In some embodiments, a damascus process (e.g., forming trenches in the insulation layer and then forming metal wires in the trenches) may be used at 582. However, other techniques may be used. In some embodiments, the conductive wire 610 is electrically connected to the underlying embedded pad 641. The conductive wire 610, layer 611, and insulator 602 are similar to the conductive wire 110, layer 111, and insulator 102 or 112.

[0063] Figure 7D The memristor device 600 is depicted after the second set of conductive lines is formed in the second layer at position 584. Furthermore, 584 can be implemented in a manner similar to 582. Therefore, conductive lines 620 in the second layer 621 have been formed in the insulating layer 622. The insulating layer 622 can be a second insulating layer (insulator 2). The second set of conductive lines 620 can be a second metal layer (metal 2). The conductive lines 620 are formed at a non-zero acute angle with the conductive lines 610. Therefore, the conductive lines 620, layer 621, and insulator 622 are similar to the conductive lines 120, layer 121, and insulator 122.

[0064] Figure 7E The memristor device 600 is depicted after execution 586. Therefore, the memristor device 600 includes a third layer 631, which includes a third insulating layer 632 (e.g., insulator 3) and a third set of conductive lines 630 (e.g., metal 3). In the illustrated embodiment, the conductive lines 630 are perpendicular to the conductive lines 610. However, other angles are also possible. The conductive lines 630, layer 631, and insulator 632 are similar to the conductive lines 130, layer 131, and insulator 132.

[0065] Figure 7FA memristor device 600 is depicted forming a memristor portion of a memristor interlayer connector 640 within a portion of 588. In some embodiments, the memristor interlayer connector 640 is formed by providing a via at least to a conductive line 120 (e.g., metal 1) in layer 111, and in some embodiments, to an underlying embedded pad 641 (e.g., metal 0). Memristor material is deposited. Memristor material 642 covers at least a portion (or all) of the sidewalls of the via. However, as... Figure 7F As depicted, the central portion of each via can remain empty. In other embodiments, a portion of the memristor material can be removed.

[0066] Figure 7G The memristor device 600 is depicted after the conductive portion 642 (e.g., a metal pillar) of the memristor interlayer connector 640 is formed in a portion of 588. Thus, the conductive pillar 642 (e.g., a core) has been provided in each of the vias, and the memristor interlayer connector 640 has been formed. Figure 7F-7G The instructions specify the sequential formation of vias through multiple layers of metal, deposition of memristor material for the multiple metal layers, and formation of conductive pillars for the multiple metal layers. In other embodiments, vias may be formed through a single metal layer prior to the formation of subsequent metal layers, forming memristor material and conductive pillars (e.g., metal) for that metal layer. Such portions of the memristor interlayer connector may be aligned and stacked to form the memristor interlayer connector shown. In some embodiments, the memristor interlayer connector may be formed only through some metal layers (e.g., between metal 1 and metal 2 but not between metal 2 and metal 3; or only between metal 2 and metal 3).

[0067] Therefore, memristor devices such as memristor device 600 can be fabricated photolithographically. As a result, memristor device 600 can share the benefits of memristor devices 100, 100', 200, 300, 400, and / or 500. Memristor device 600 can provide complex, randomized, irregular, and / or sparsely connected networks that are photolithographically and deterministically formed. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device, as well as device 600 itself, is simplified and reproducible. As a result, the performance of systems using memristor device 600 can be improved.

[0068] Figure 8 A plan view depicting a portion of an embodiment of the memristor device 700. For clarity, only a portion of the memristor device 700 is shown. Figure 8Not to scale. For simplicity, only some structures are labeled. Memristor device 700 is similar to memristor devices 100, 100', 200, 300, 400, 500, and / or 600. Therefore, memristor device 700 includes memristor layer 711, memristor interlayer connectors 740A, 740B, 740C, and 740D (generally or commonly memristor interlayer connector 740), and conductive lines 710A, 710B, and 710C (generally or commonly conductive lines 710). Layer 711, memristor interlayer connector 740, and conductive lines 710 are similar to layers 111, 121, and / or 131, memristor interlayer connector 140, and conductive lines 110, 120, and / or 130, respectively.

[0069] The memristor device 700 also includes conductive branch structures (some of which are labeled) 714A, 714B, and 714C (conductive branch structure 714 commonly or generally). In some embodiments, the conductive branch structure 714 is a short metal wire segment. The conductive branch structure 714 extends between the corresponding memristor interlayer connector 740 and the conductive line 710. Although all memristor interlayer connectors 740 in the column are shown as memristorically connected to the nearby conductive line 710 via the conductive branch structure 714, in some embodiments, fewer (including zero) memristor interlayer connectors 740 in the column are connected to the nearby conductive line 710. For example, some of the conductive branch structures 714 in a particular layer may be omitted. The omitted conductive branch structures (if any) may vary between layers. The conductive branch structure 714 may be photolithographically fabricated in a manner similar to the conductive line 710.

[0070] Memristor device 700 can share the benefits of memristor devices 100, 100', 200, 300, 400, 500, and / or 600. Memristor device 700 can provide complex, randomized, irregular, and / or sparsely connected networks that are lithographically and deterministically formed. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device and of device 700 is simplified and reproducible. Consequently, the performance of systems using memristor device 700 can be improved.

[0071] Figure 9A-9G An embodiment depicting a portion of a memristor device 800 during its formation is shown. For clarity, only a portion of the memristor device 800 is shown. Figure 9A-9G Not to scale. For simplicity, only some structures are labeled. Memristor device 800 is similar to memristor device 700. Memristor device 800 can be formed using method 580 and is described in the context of method 580. However, other techniques can be used to form memristor device 800. Figures 9A-9BThe memristor device 800 is depicted prior to the commencement of method 580. Thus, an overlying insulating substrate and an embedded pad 841 are shown. Pad 841 may be a metal pad (e.g., metal O) formed on the insulating substrate. Pad 841 may be considered as part of a memristor interlayer connector being formed, or as a separate component to which the memristor interlayer connector can be electrically connected. In some embodiments, other devices (not shown) are also formed. For example, neurons or other devices may have been disposed on or within the insulating substrate. Figure 8 B depicts a memristor device 800 after an insulating layer 802 (e.g., insulator 1) has been formed on an embedded pad 841.

[0072] Figure 9C A conductive line (e.g., metal 1) 810 for the first layer 811 is depicted on the insulating layer 102 in method 580, at step 582. In some embodiments, the conductive line 810 is formed on the insulating layer 802. In such embodiments, the conductive line 810 is formed by an insulating dielectric layer ( Figure 9C (Not shown in the image) insulation. In some embodiments, a damascus process (e.g., forming trenches in insulation layer 802 and then forming metal wires in the trenches) may be used at 582. However, other techniques may be used. In some embodiments, conductive wire 810 is electrically connected to an overlying embedded pad 841. Conductive wire 810, layer 811, and insulator 802 are similar to conductive wire 110, layer 111, and insulator 102 or 112.

[0073] Figure 9D A layer of memristor material 844 is formed on conductive line 810 as part of method 580. Therefore, memristor material 844 can be used in memristor interlayer connectors. In the illustrated embodiment, a sheet of memristor material 844 has been deposited. In some embodiments, memristor material 844 is patterned such that memristor contacts are only located near conductive line 810 and the conductive branch structure to be formed (…). Figure 9D (Not shown in the image) in the region.

[0074] Figure 9E The formation of a conductive branch structure 814 for the conductive line 810 is depicted. Branch structure 814 is similar to branch structure 714. However, in the illustrated embodiment, branch structure 814 is separated from the corresponding main conductive line 810 by a memristor layer. Nevertheless, the branch structure can still be considered part of the conductive line 810 (and therefore the first metal layer). Therefore, a portion of 582 can be considered to have been implemented for the conductive branch structure 814.

[0075] Figure 9FThe memristor device 800 is depicted as part of method 580, following the formation of a conductive (e.g., metallic) connection 842. In some embodiments, the conductor 842 is electrically connected to an underlying metal pad. Thus, a via can be formed to the embedded pad 841 (metal 0) through a layer 811 (metal 1) and an insulating layer 802 (insulating layer 1). The via is filled with a conductive material 842 (e.g., metallic). Thus, a memristor interlayer connector 840 comprising a portion of memristor material 844 and conductor 842 is formed. In alternative embodiments, the via may comprise a memristor shell / layer similar to those depicted in FIG. 1. However, in the illustrated embodiment, no such additional memristor material is used.

[0076] This process is repeated for subsequent metal layers in 584, 586, and 588. The memristor device 800, including the second layer 821 formed at 584, is... Figure 9G As shown in the illustration, in the illustrated embodiment, metal wire 820 is formed at 84 in insulating layer 822. Another memristor layer 844' and another conductive portion 842' have been formed. The memristor interlayer connector includes memristor portions 844 and 844' and conductive portions 842 and 842'. Therefore, the formation of memristor interlayer connector 840 continues at 588 of method 580. Thus, memristor interconnect 840 is still memristively connected to conductive lines 810 and 820. However, memristor interconnect 840 is constructed with memristor layers 844 and 844' instead of a memristor shell. In the illustrated embodiment, conductive line 820 is perpendicular to conductive line 810. However, conductive lines in subsequent layers may extend in different directions. In some embodiments, layers 811 and / or 821 may include conductive lines of arbitrary shape. In some embodiments, each layer has a different (e.g., unique) wiring pattern.

[0077] Memristor device 800 can share the benefits of memristor devices 100, 100', 200, 300, 400, 500, 600, and / or 700. Memristor device 800 can provide complex, randomized, irregular, and / or sparsely connected networks that are lithographically and deterministically formed. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device and of device 800 is simplified and reproducible. As a result, the performance of systems using memristor device 800 can be improved.

[0078] Figure 10 A perspective view depicting a portion of an embodiment of the memristor device 900. For clarity, only a portion of the memristor device 900 is shown. Figure 10Not to scale. For simplicity, only some structures are labeled. Memristor device 900 is similar to memristor devices 100, 100', 200, 300, 400, 500, 600, 700, and / or 800. For simplicity, only one layer 911 is shown. However, memristor device 900 may include multiple layers. Memristor device 900 includes layer 911, memristor interlayer connectors 940 and conductive lines 910, which are respectively similar to memristor interlayer connectors 140 and 840 and conductive lines 110 and 810.

[0079] The memristor device 900 also includes a conductive branch structure 914 (only one of which is labeled). In some embodiments, the conductive branch structure 914 is a short metal line segment. The conductive branch structure 914 extends between the corresponding memristor interlayer connector 940 and the conductive line 910. The conductive branch structure 914 can be photolithographically fabricated in a manner similar to that of the conductive line 910.

[0080] In the illustrated embodiment, memristor device 900 includes a memristor layer patch 944 sandwiched between conductive branch structure 914 and conductive line 910. Thus, memristor device 900 is similar to memristor device 800, but wherein the memristor layer 844 is patterned.

[0081] Memristor device 900 can share the benefits of memristor devices 100, 100', 200, 300, 400, 500, 600, 700, and / or 800. Memristor device 900 can provide complex, randomized, irregular, and / or sparsely connected networks that are lithographically and deterministically formed. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device and of device 900 is simplified and reproducible. As a result, the performance of systems using memristor device 900 can be improved.

[0082] Figure 11 A plan view depicting a portion of an embodiment of the memristor device 1000. For clarity, only a portion of the memristor device 1000 is shown. Figure 11Not to scale. For simplicity, only some structures are labeled. Memristor device 1000 is similar to memristor devices 100, 100', 200, 300, 400, 500, 600, 700, 800, and / or 900. Only one layer is shown. However, memristor device 1000 may include multiple layers. Memristor device 1000 includes conductive lines 1010 (only one is labeled), conductive branch structures 1014 (only one is labeled), and memristor interlayer connectors 1040 (only one is labeled), which are respectively similar to conductive lines 110, 810, and / or 910, conductive branch structures 814 and / or 914, and memristor interlayer connectors 140, 840, and / or 940. Memristor material may be incorporated as a shell surrounding the conductive post of memristor interlayer connector 1040 or as a patch between conductive branch structure 1014 and conductive line 1010.

[0083] A conductive interlayer connector 1060 is also shown. Although only one conductive interlayer connector 100 is shown, more than one may be present in the device. The conductive interlayer connector 1060 can provide electrical connections to another layer, multiple other layers, and / or other devices (e.g., via a similar...). Figure 5 (The conductive bumps described in the context of the previous section). Alternatively, the conductive interlayer connector can simply be a metal pad. The conductive interlayer connector 1060 is coupled to a conductive line 1070 that provides an electrical connection to the memristor interlayer connector 1040. Figure 11 The diagram indicates that, despite the crossing, conductive lines 1010 and 1070 are not short-circuited. The conductive interlayer connector 1060 can be used as a short-circuit via. For example, the conductive interlayer connector 1060 can help repair "broken" wires and / or extend the effective length of metal wires. Therefore, higher density connectivity can be achieved.

[0084] Therefore, memristor devices such as memristor device 1000 can be fabricated photolithographically. As a result, memristor device 1000 can share the benefits of memristor devices 100, 100', 200, 300, 400, 500, 600, 700, 800, and / or 900. Memristor device 1000 can provide complex, randomized, irregular, and / or sparsely connected networks that are photolithographically and deterministically formed. As a result, the benefits of sparse networks can be obtained, such as improved modeling of biological systems in neural networks, improved performance, and / or improved scalability. Furthermore, the fabrication of each layer in each device, as well as device 1000 itself, is simplified and reproducible. As a result, the performance of systems using memristor device 1000 can be improved.

[0085] In some applications, conductive interlayer connectors can also be used for other and / or additional purposes. For example, Figure 12 This is a plan view of an embodiment of a device 1100 including a sparsely connected neural array. For clarity, only a portion of the memristor device 1100 is shown. Figure 12 Not to scale. For simplicity, only some structures are marked. Figure 12 The diagram shows a single layer 1111. Memristor device 1100 may include multiple layers. For example, additional layers similar to layer 1111 (and / or other layers described) may be included. However, the conductive paths (i.e., the geometry of the various components) of such layers may differ from those of layer 1111. Some or all of the components in memristor device 1100 may be photolithographically fabricated as discussed with respect to memristor devices 100, 100', 200, 300, 400, 500, 600, 700, 800, 900, and 1000.

[0086] In device 1100, connections are made to neurons (not shown) that may be located below or above the illustrated layer 1111. For example, the neurons may be located below a portion of the illustrated device 1100. Therefore, a cross-sectional view of the underlying layer may include something similar to... Figure 1C The devices 106 and 108.

[0087] Device 1100 includes an insulator 1101, a conductive interlayer connector 1160 (black circles, some only), a memristor interlayer connector 1140 (white circles, some only), and a conductive line 1110 (formed by black line segments, some only). The conductive interlayer connectors 1160 and 1140 can be viewed as forming a rectangular (e.g., square) lattice connecting to the overlying (or overlying) neurons. In other embodiments, different lattices may be used. The conductive interlayer connector 1160 is similar to the conductive interlayer connector 1060. Therefore, the conductive interlayer connector 1160 does not include a memristor shell or similar component. As a result, direct electrical contact can be made with the conductive interlayer connector 1160. Electrical contact between the conductive interlayer connector 1160 and the conductive line 1110 is made via conductive branch segments 1170 (white segments outlined in black, some only). Conduction branch segment 1170 is similar to conduction branch structure 1114, but connects conduction line 1110 to conduction interlayer connector 1160. In some embodiments, conduction interlayer connector 1160 is electrically connected to input neurons that may be located below layer 1111. Figure 12 (Not shown in the image).

[0088] Memristor interlayer connector 1140 is similar to one or more of memristor interlayer connectors 140, 240, 340, 440, 540, 640, 740, 840, 940, and / or 1040. Therefore, memristor interlayer connector 1140 is memristively coupled to conductive line 1110. In the illustrated embodiment, memristor interlayer connector 1140 is memristively coupled to conductive line 1110 by conductive branch structures 1114 (gray line segments, only some of which are labeled). Conductive branch structures 1114 are similar to conductive branch structures 714, 814, 914, and / or 1014. In other embodiments, the connection between memristor interlayer connector 1140 and conductive line 1110 can be performed in another manner. For example, as... Figure 1A-1D As shown, the conductive line 1110 and the memristor interlayer connector 1140 can be memristively connected via direct contact. In some embodiments, the memristor interlayer connector 1140 is coupled to an output neuron that may be located below layer 1111. Figure 12 (Not shown in the image).

[0089] The segments of conductive lines 1110 connect or terminate at nodes 1118 (gray circles, only some of which are marked). Nodes 1118 are formed of a conductor such as a metal (e.g., Cu). Conductive lines 1110 formed from such segments can have arbitrary shapes and can be considered as clusters. For example, a cluster 1180 including conductive lines 1110 (black line segments) is... Figure 11 The area is enclosed by a dashed line 1180. Other clusters are not labeled for clarity. Conductive lines 1110 are sparsely connected to (and via) memristor interlayer connectors 1140 and conduction interlayer connectors 1160. In the illustrated embodiment, each cluster 1180 is connected to one conduction interlayer connector 1160 and multiple memristor interlayer connectors 1140. Thus, each cluster 1180 is connected to one input neuron and memristively connected to multiple output neurons. In other embodiments, other connectivity is possible.

[0090] Interlayer conductive connectors 1160 extend to input neurons via insulator 1101 and any desired underlayer (or overlayer). In some embodiments, each interlayer conductive connector 1160 is electrically connected to one input neuron. Interlayer memristor connectors 1140 extend to output neurons via insulator 1101 and any desired underlayer (or overlayer). In some embodiments, each interlayer memristor connector 1140 is connected to one output neuron. Thus, the neurons electrically connected to connectors 1140 and 1160 can be viewed as being divided into input neurons (connected to interlayer conductive connector 1160) and output neurons (connected to interlayer memristor connector 1140). In some embodiments, the roles of interlayer conductive connectors 1160 and interlayer memristor connector 1140 are interchangeable. Thus, in such embodiments, interlayer memristor connector 1140 may be electrically connected to input neurons, while interlayer connector 1160 may be electrically connected to output neurons. Interlayer conductive connector 1160 may also correspond to interlayer memristor connector 1140. For example, in the illustrated embodiment, the conductive interlayer connector 1160 and the memristor interlayer connector 1140 appear in pairs. In some embodiments, a one-to-one correspondence between the conductive interlayer connector 1160 and the memristor interlayer connector 1140 is not required.

[0091] In memristor device 1100, individual memristors (i.e., weights for output neurons) are individually addressable. In other words, the resistance for an individual memristor (a portion of the memristor interconnect 1140 for a specific layer) can be individually programmed. For example, in labeled cluster 1180, the corresponding conduction line 1110, conduction branch structure 1114 (not labeled within labeled cluster 1180), and conduction interlayer connector 1160 can be considered nodes (all at the same potential / short circuit). Individual voltage differences can be established between the conduction interlayer connector 1160 within labeled cluster 1180 and the directly connected memristor interlayer connector 1140 (only one of these is labeled for labeled cluster 1180). For example, a zero-volt voltage can be connected to the input neuron (i.e., the conduction interlayer connector 1160 of labeled cluster 1180), and a four-volt voltage can be connected to the labeled memristor interlayer connector 1140 for cluster 1180 (and therefore the corresponding output neuron). Current flows through conduction line 1110, and the memristor portions of memristor interlayer connector 1140 are programmed with corresponding weights. A similar process can be performed to program weights for other memristor interlayer connectors 1140 in the labeled cluster 1180. Weights (resistance of the memristors) for other output neurons connected to other clusters 1180 can be programmed in a similar manner. Therefore, in memristor device 1100, the memristor device formed by memristor interlayer connectors 1140 can be programmed individually.

[0092] Furthermore, the memristor device 1100 can provide various types of sparse connectivity between input and output neurons (e.g., very sparse, denser sparse, local / short-range connectivity, long-range connectivity). Although only one layer 1111 is shown, some embodiments may include multiple layers with different configurations of lattices, conduction lines 1110, clusters 1180, and / or connections to connectors 1140 and / or 1160. Therefore, a high degree of flexibility in varying connectivity and connection patterns can be provided. This allows for a high degree of flexibility in the connection patterns that can be formed. A range from very sparse to very dense (though still sparse) connectivity can be provided between and within layers. Furthermore, the regularity (or irregularity and randomness) of layer 1111 can be controlled, and thus the memristor device 1100 can be controlled. Since the memristors are formed for the memristor interlayer connectors 1160, individual control of all memristors can be provided within the network of layer 1111. Furthermore, the formation of the conduction lattice clusters 1180 can be controlled, and thus the degree and type of connectivity can be controlled. Therefore, the reproducibility of fabrication and formation of device 1100 can be improved. In some embodiments, fully parallel convolutions may be possible. As a result, the performance of devices employing such sparsely connected neuron arrays can be improved.

[0093] Figures 13A-13E This is a diagram depicting an embodiment of a device 1200 including a sparse neural array during manufacturing. For clarity, only a portion (i.e., a single layer) of the memristor device 1200 is shown. Figures 13A-13E Not to scale. For simplicity, only some structures are labeled. Memristor device 1200 is similar to memristor device 1100. Memristor device 1200 can be formed using method 580 and is described in the context of method 580. However, other techniques can be used to form memristor device 1100.

[0094] Figure 13A The device 1200 is depicted after forming a conductive interlayer connector 1260 (black circle, only one is marked) through insulator 1201 at step 590 using method 580. Therefore, the conductive interlayer connector 1260 is photolithographically fabricated. The conductive interlayer connector 1260 is similar to the conductive interlayer connector 1160. In some embodiments, metal pillars grow vertically through all intermediate layers and connect to input neurons. For example, the conductive interlayer connector 1260 may connect to the axon of an input neuron in a CMOS below the illustrated layer.

[0095] Figure 13BThe device 1200 is depicted after forming a memristor interlayer connector 1240 (white circle, only one is marked) through insulator 1201 in method 588 of method 580. Therefore, the memristor interlayer connector is provided photolithographically. Memristor interlayer connector 1240 is similar to memristor interlayer connector 1140. In some embodiments, 588 includes etching vias through layers (including insulating layer 1201), vertically growing a memristor layer coating the vias through all intermediate layers, and providing conductive (e.g., metallic) posts for connection to output neurons. For example, memristor interlayer connector 1240 may be connected to the dendrites of an output neuron in a node CMOS below the illustrated layer. Thus, other components can be memristively connected to the output neuron via memristor interlayer connector 1240.

[0096] Figure 13C The apparatus 1200 is depicted after forming a lattice of conduction lines 1210 providing interneuronal connectivity at 582 of method 580. The conduction lines 1210 may be photolithographically formed and resemble conduction lines 1110. The lattice includes segments (black lines) of conduction lines 1210 formed on a rectangular lattice and forming conduction lattice clusters 1280 (of which only three are marked and surrounded by dashed lines). In the illustrated embodiment, the segments terminate in and / or are connected by nodes 1218. In some embodiments, the conduction lines 1210 including nodes 1218 are metallic. Embodiments / regions with low segment density can create numerous clusters that can be used to form local connections. Embodiments / regions with high segment density can create fewer clusters that can be used to form long-range connections. Although the segments of conduction lines 1210 are shown formed as a square lattice, other lattices are possible. For example, segments of conduction lines 1210 may be formed diagonally and connected by nodes 1218.

[0097] Figure 13D The device 1200 is depicted after the formation of conduction branch segments 1270 (white rectangles, only one of which is marked). The conduction branch segment 1270 is similar to conduction branch segment 1170, may be a metallic wire, and connects to an input neuron. The conduction branch segment 1270 can therefore be considered an input line. In some embodiments, the fabrication of the conduction branch segment 1270 can be considered as part of forming conduction lines 1210 using method 580, step 582. In other embodiments, the fabrication of the conduction branch segment 1270 can be considered as part of forming conduction interlayer connectors 1260 using method 580, step 590. Therefore, in some embodiments, the conduction branch segment 1270 is formed photolithographically. Conduction lattice clusters 1280 are connected to the conduction interlayer connectors 120 via the input conduction branch segments 1270. In the illustrated embodiment, only one conduction interlayer connector 1260, and therefore only one input neuron, is connected to each conduction lattice cluster 1280.

[0098] Figure 13E The device 1200 is depicted after the formation of conduction branch structures 1214 (gray lines, only some of which are marked). The conduction branch structures 1214 are similar to conduction branch structures 1114, may be metallic wires, and are connected to output neurons. Therefore, the conduction branch structures can be considered as output lines. In some embodiments, the fabrication of the conduction branch structures 1214 can be considered as part of forming conduction lines 1210 using method 580, step 582. In other embodiments, the fabrication of the branch structures 1214 can be considered as part of forming memristor interlayer connectors 1240 using method 580, step 588. Therefore, in some embodiments, the branch structures 1214 are formed photolithographically. Conduction lattice clusters 1280 are connected to the memristor interlayer connectors 1240 via the conduction branch structures 1214. In the illustrated embodiments, a plurality of memristor interlayer connectors 1240, and thus a plurality of output neurons, are connected to each conduction lattice cluster 1280. In some embodiments, up to four connections are allowed per output neuron per layer. Therefore, in such embodiments, a particular memristor interlayer connector 1240 may be connected to no more than four (i.e., 1, 2, 3 or 4) conductive lattice clusters 1280.

[0099] Similar processes can be repeated for additional layers using methods 584 and 586 of method 580. Different conduction lattice clusters (e.g., different segments and / or different segment configurations) can be formed for each additional layer being connected. There may be no overlap between layers. Variations in the density of connections / lattice clusters between layers can be used to create both short-range and long-range connections.

[0100] Memristor device 1200 is similar to and shares the benefits of memristor device 1100. Therefore, memristor device 1200 allows individual memristors (i.e., weights for output neurons) to be addressed individually. Thus, the resistors for individual memristors (parts of the memristor interconnects 1240 in a specific layer) can be programmed individually. Furthermore, memristor device 1200 can provide various types of sparse connectivity between input and output neurons (e.g., very sparse, denser sparse, local / short-range connectivity, long-range connectivity). The memristor device can comprise multiple layers with different configurations of lattices, conduction lines 1210, clusters 1280, and / or connections to connectors 1240 and / or 1260. Therefore, varied connectivity and a high degree of flexibility in connection patterns can be provided. Moreover, the individual layers of memristor device 1200 are deterministically and reproducibly fabricated via photolithography. The regularity (or irregularity and randomness) of memristor device 1200 can be controlled. Therefore, the repeatability of manufacturing and forming of device 1200 can be improved. As a result, the performance of devices employing memristor device 1200 can be improved.

[0101] Figure 14This is a flowchart depicting an embodiment of method 1400 for using a sparsely connected neural array. For clarity, only some steps are shown. Other and / or additional processes may be performed in some embodiments. Although described in the context of the flowchart, the processes in method 1400 may be performed in parallel and / or interleaved.

[0102] At 1402, the memristors are programmed individually. For example, at 1402, the conductors in the memristor device are accessed by applying a voltage to the conductive portion of the memristor interlayer connector. Additionally, also at 1402, a voltage is applied to the node connected to the conductor. This may include applying a voltage to the conductive interlayer connector connected to the conductor. This process is repeated until all desired memristors are programmed with appropriate weights. Then, at 1404, a neural network or other devices incorporated into the memristors can be used. Based on the obtained output, new weights may be desired for some or all of the memristors in the device. As a result, at 1406, some or all of the memristors can be reprogrammed. The process performed for 1406 is similar to those performed for 1402. 1404 and 1406 can be repeated until the desired output is achieved.

[0103] For example, in device 1100, at 1402, different voltages can be applied to the conductive interlayer connector 1160 of the marked cluster 1180 and the marked memristor interlayer connector 1140 of the marked cluster 1180. Current flows through the conductive line 1110, and the memristor portion of the memristor interlayer connector 1140 is programmed with corresponding weights. Also at 1402, a similar process can be performed to program weights for the other memristor interlayer connectors 1140 in the marked cluster 1180 and the remainder of the memristor device 1100. Thus, the desired weights (resistance of the memristor) can be programmed individually for the memristor device 1100. The memristor device 1100 is then used at 1404. At 1406, based on the output, the memristors for one or more of the memristor interlayer connectors 1140 can be reprogrammed. Thus, the desired weights for the memristor device 1100 can be determined and provided individually. Using method 1400, the advantages of memristor device 1100 can be realized and the performance of devices employing memristor device 1100 can be improved.

[0104] Although the foregoing embodiments have been described in considerable detail for the purpose of clarity, the invention is not limited to the details provided. Many alternative ways of carrying out the invention exist. The disclosed embodiments are exemplary and not limiting.

Claims

1. A memristor device, comprising: The first layer includes a first plurality of conductive lines, which are photolithographically defined; The second layer includes a second plurality of conductive lines, the second layer being different from the first layer, the second plurality of conductive lines being insulated from the first plurality of conductive lines, and the second plurality of conductive lines being photolithographically defined; A plurality of memristor interlayer connectors are memristively connected to a first portion of a first plurality of conductive lines and a second portion of a second plurality of conductive lines, such that the plurality of memristor interlayer connectors are sparsely connected to the first plurality of conductive lines and sparsely connected to the second plurality of conductive lines. Each of the plurality of memristor interlayer connectors includes a conductive portion and a memristor portion, the memristor portion being located between the conductive portion and at least one corresponding line of at least one of the first plurality of conductive lines or the second plurality of conductive lines. The first plurality of conductive lines have a first connectivity, the second plurality of conductive lines have a second connectivity, and a third connectivity is less than both the first and second connectivity. The first connectivity is associated with a first fraction of conductive lines in the first layer connected to the plurality of memristor interlayer connectors. The second connectivity is associated with a second fraction of conductive lines in the second layer connected to the plurality of memristor interlayer connectors. The third connectivity is associated with a third fraction of the first plurality of conductive lines and the second plurality of conductive lines connected to the plurality of memristor interlayer connectors. Corresponding to the plurality of memristor interlayer connectors, the plurality of conductive interlayer connectors are electrically connected to the third portion of the first plurality of conductive lines and electrically connected to the fourth portion of the second plurality of conductive lines.

2. The memristor device according to claim 1, wherein, The first plurality of conductive lines have a first major axis oriented along a first direction, and the second plurality of conductive lines have a second major axis oriented along a second direction, wherein the first direction and the second direction form a non-zero acute angle.

3. The memristor device according to claim 1, wherein, Each of the first plurality of conductive lines and at least one of the second plurality of conductive lines includes a plurality of line segments having a plurality of long axes oriented in a plurality of directions.

4. The memristor device according to claim 1, further comprising: Multiple input neurons connected to at least a portion of the multiple interlayer conductive connectors; as well as Multiple output neurons connected to at least a portion of the multiple memristor interlayer connectors.

5. The memristor device according to claim 1, wherein, At least one of the third portion of the first plurality of conduction lines and the fourth portion of the second plurality of conduction lines comprises a plurality of clusters.

6. The memristor device according to claim 1, wherein, At least one of the first plurality of conductive lines and the second plurality of conductive lines is electrically floating.

7. The memristor device according to claim 1, wherein, The conductive part is a conductive column with sidewalls; and The memristor portion surrounds at least a portion of the sidewall.

8. The memristor device according to claim 1, wherein, Each of at least one of the first portion of the first plurality of conductive lines and the second portion of the second plurality of conductive lines is connected to the plurality of memristor interlayer connectors by a conductive branch structure.

9. The memristor device according to claim 8, wherein, Each of the plurality of memristor interlayer connectors includes a memristor layer adjacent to the conductive branch structure.

10. A method for manufacturing a memristor device, comprising: The first plurality of conductive lines are photolithographically defined in the first layer; A second plurality of conductive lines are photolithographically defined in a second layer, which differs from the first layer, and the second plurality of conductive lines are insulated from the first plurality of conductive lines; and A plurality of memristor interlayer connectors are provided, each connected to a first portion of a first plurality of conductive lines and a second portion of a second plurality of conductive lines, such that the plurality of memristor interlayer connectors are sparsely connected to both the first plurality of conductive lines and the second plurality of conductive lines. Each of the plurality of memristor interlayer connectors includes a conductive portion and a memristor portion, the memristor portion being located between the conductive portion and at least one corresponding line of either the first plurality of conductive lines or the second plurality of conductive lines. The first plurality of conductive lines have a first connectivity, the second plurality of conductive lines have a second connectivity, and a third connectivity is less than both the first and second connectivity. The first connectivity is associated with a first fraction of conductive lines in the first layer connected to the plurality of memristor interlayer connectors. The second connectivity is associated with a second fraction of conductive lines in the second layer connected to the plurality of memristor interlayer connectors. The third connectivity is associated with a third fraction of the first and second plurality of conductive lines connected to the plurality of memristor interlayer connectors. A plurality of conductive interlayer connectors corresponding to the plurality of memristor interlayer connectors are provided, the plurality of conductive interlayer connectors being electrically connected to a third portion of the first plurality of conductive lines and electrically connected to a fourth portion of the second plurality of conductive lines.

11. The method according to claim 10, wherein, Photolithographically defining the first plurality of conductive lines further includes: The first plurality of conductive lines define a first major axis oriented along a first direction; and The photolithographically defined second plurality of conductive lines further include defining a second long axis oriented along a second direction, wherein the first direction forms a non-zero acute angle with the second direction.

12. The method according to claim 10, wherein, Each of the first plurality of conductive lines and at least one of the second plurality of conductive lines includes a plurality of line segments having a plurality of long axes oriented in a plurality of directions.

13. The method of claim 10, further comprising: Provides a plurality of input neurons that are connected to at least a portion of the plurality of interlayer conductive connectors; as well as Provides a plurality of output neurons connected to at least a portion of the plurality of memristor interlayer connectors.

14. The method of claim 10, wherein, At least one of the third portion of the first plurality of conduction lines and the fourth portion of the second plurality of conduction lines comprises a plurality of clusters.

15. The method according to claim 10, wherein, At least one of the first plurality of conductive lines and the second plurality of conductive lines is electrically floating.

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