Storage device and method of manufacturing the same

Abstract

A storage device and a manufacturing method thereof. The storage device comprises a substrate structure, a first metal structure, a second metal structure and a dielectric layer. The resistive random access memory comprises a first electrode, a resistive switching layer and a second electrode which are stacked along a first direction. The dielectric layer comprises an electrode hole, a sidewall of the electrode hole surrounds a first opening and a second opening which are opposite in the first direction, the first opening exposes the first metal structure, and the second opening is located on a side surface of the dielectric layer away from the first metal structure; in a second direction intersecting the first direction, the size of the second opening is greater than that of the first opening; the first electrode is completely located in the electrode hole, the first electrode comprises a first electrode part and a second electrode part, the first electrode part is located on a side surface of the first metal structure away from the substrate structure, and the second electrode part is located on the sidewall; at least part of the resistive switching layer extends beyond the edge of the first electrode in the second direction. Thus, the reliability of the storage device is improved.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a storage device and a method for manufacturing the same. Background Technology

[0002] Resistive random access memory (RRAM), also known as memristor, is a new type of non-volatile memory. RRAM offers advantages such as process compatibility, low manufacturing cost, low power consumption, and good scalability, making it a promising candidate for various applications. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a storage device and a method for manufacturing the same.

[0004] At least one embodiment of this disclosure provides a storage device, comprising: a substrate structure; a first metal structure located on the substrate structure; a second metal structure located on a side of the first metal structure away from the substrate structure; a dielectric layer at least partially located between the first metal structure and the second metal structure; a resistive switching memory (RSM) including a first electrode, a resistive switching reaction layer, and a second electrode stacked along a first direction, the resistive switching reaction layer located between the first electrode and the second electrode; wherein the dielectric layer includes an electrode aperture, the sidewalls of the electrode aperture surrounding a first opening and a second opening formed opposite to each other in the first direction, the first opening exposing the first metal structure, and the second opening located on a surface of the dielectric layer away from the first metal structure; in a second direction intersecting the first direction, the size of the second opening is larger than the size of the first opening; the first electrode is completely located within the electrode aperture, the first electrode including a first electrode portion and a second electrode portion connected to each other, the first electrode portion located on a surface of the first metal structure away from the substrate structure, and the second electrode portion located on the sidewall; at least a portion of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction.

[0005] For example, according to at least one embodiment of the present disclosure, the orthographic projection of the first electrode lies within the orthographic projection of the sidewall on a plane perpendicular to the second direction.

[0006] For example, according to at least one embodiment of the present disclosure, the ratio of the thickness of the first electrode portion to the thickness of the second electrode portion is 0.9-1.1.

[0007] For example, according to at least one embodiment of the present disclosure, on the substrate structure, the orthographic projection of the first electrode is completely located within the orthographic projection of the resistive switching reaction layer, and there is a gap between the edge of the orthographic projection of the first electrode and the edge of the orthographic projection of the resistive switching reaction layer.

[0008] For example, according to at least one embodiment of the present disclosure, the sidewall includes a main body portion and a first arcuate portion, the first arcuate portion being connected between the main body portion and a side surface of the first metal structure away from the substrate structure; the side edge of the first arcuate portion away from the main body portion surrounds and forms the first opening.

[0009] For example, according to at least one embodiment of the present disclosure, the sidewall includes a main body portion and a second arcuate portion, the second arcuate portion being connected between the main body portion and a portion of the dielectric layer other than the electrode hole on a side surface away from the substrate structure; the edge of the second arcuate portion away from the main body portion forms the second opening.

[0010] For example, according to at least one embodiment of this disclosure, the maximum size of the first opening in the second direction is 5 nanometers to 100 nanometers.

[0011] For example, according to at least one embodiment of the present disclosure, the orthographic projection of the resistive switching layer overlaps with the orthographic projection of the sidewall on a plane perpendicular to the second direction.

[0012] For example, according to at least one embodiment of this disclosure, the orthographic projection of the second electrode overlaps with the orthographic projection of the sidewall on a plane perpendicular to the second direction.

[0013] For example, according to at least one embodiment of this disclosure, the orthographic projection of the second electrode coincides with the orthographic projection of the resistive switching layer on a plane perpendicular to the first direction.

[0014] For example, according to at least one embodiment of the present disclosure, the second electrode has a recess on the side surface away from the substrate structure, and a portion of the second metal structure is located within the recess.

[0015] For example, according to at least one embodiment of the present disclosure, the storage device further includes a first insulating layer and a second insulating layer; the first insulating layer surrounds a portion of the first metal structure, and the second insulating layer surrounds a portion of the resistive switching memory and a portion of the second metal structure.

[0016] For example, according to at least one embodiment of the present disclosure, the dielectric layer includes a first region overlapping the resistive switching reaction layer in the first direction and a second region other than the first region; the maximum thickness of the first region in the first direction is greater than the maximum thickness of the second region in the first direction.

[0017] At least one embodiment of this disclosure provides a method for fabricating a memory device, comprising: sequentially forming a first metal structure and a first dielectric material layer on a substrate structure; forming an electrode hole in the first dielectric material layer by a first photolithography process to obtain a second dielectric material layer; wherein the electrode hole includes a sidewall surrounding a first opening and a second opening formed opposite to each other in a first direction, the first opening exposing the first metal structure, and the second opening located on a side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, the size of the second opening is larger than the size of the first opening; forming a first electrode within the electrode hole; wherein the first electrode is completely located within the electrode hole, the first electrode including a first electrode portion and a second electrode portion connected to each other, the first electrode portion located on a side surface of the first metal structure away from the substrate structure, and the second electrode portion located on the sidewall; forming a resistive switching reaction layer and a second electrode stacked on the side of the first electrode away from the substrate structure to form a resistive switching memory; wherein at least a portion of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction; forming a second metal structure on the side of the resistive switching memory away from the substrate structure to form the memory device.

[0018] For example, according to at least one embodiment of the present disclosure, forming the first electrode in the electrode hole includes: forming a first electrode material layer on the side of the second dielectric material layer away from the substrate structure and in the electrode hole; forming a sacrificial layer on the side of the first electrode material layer away from the substrate structure; performing a planarization process to remove the portion of the sacrificial layer other than the portion located in the electrode hole, and removing the portion of the first electrode material layer other than the portion located in the electrode hole; removing the portion of the sacrificial layer in the electrode hole to obtain the first electrode.

[0019] For example, according to at least one embodiment of this disclosure, the material of the sacrificial layer includes spin-coated carbon.

[0020] For example, according to at least one embodiment of the present disclosure, on the substrate structure, the orthographic projection of the first electrode is completely located within the orthographic projection of the resistive switching reaction layer, and there is a gap between the edge of the orthographic projection of the first electrode and the edge of the orthographic projection of the resistive switching reaction layer.

[0021] For example, according to at least one embodiment of the present disclosure, forming the second metal structure on the side of the resistive switching memory away from the substrate structure includes: forming an insulating material layer on the side of the resistive switching memory and the second dielectric material layer away from the substrate structure; and forming the insulating layer and the second metal structure located within the insulating layer by an inlay process.

[0022] For example, according to at least one embodiment of the present disclosure, forming the resistive switching reaction layer and the second electrode stacked on the side of the first electrode away from the substrate structure includes: forming a resistive switching reaction material layer and a second electrode material layer stacked on the side of the first electrode away from the substrate structure and the side of the second dielectric material layer away from the substrate structure; removing a portion of the resistive switching reaction material layer and a portion of the second electrode material layer by a second photolithography process to form the resistive switching reaction layer and the second electrode to form the resistive switching memory.

[0023] For example, according to at least one embodiment of the present disclosure, before forming the second metal structure on the side of the resistive switching memory away from the substrate structure, the method further includes: removing a portion of the second dielectric material layer by the second photolithography process to form a dielectric layer; wherein, the portion is the part of the second dielectric material layer excluding the portion that overlaps with the resistive switching reaction layer in the first direction. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 This is a schematic diagram of a storage device.

[0026] Figure 2A and Figure 2B This is a schematic diagram of some film layers of different RRAMs.

[0027] Figure 3 This is a schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure.

[0028] Figure 4 This is a partial structural schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure.

[0029] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a storage device provided in at least one embodiment of the present disclosure.

[0030] Figures 6A to 6H for Figure 3 The diagram shows the manufacturing process of the storage device. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0033] The terms "parallel," "perpendicular," and "identical" as used in this disclosure include the strictly defined meanings of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include some degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. In embodiments of this disclosure, "center" can include a strictly geometrically centered location and an approximate center location within a small area surrounding the geometrically centered location. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0034] RRAM has many advantages over other types of memory, such as embedded flash memory (eFlash) and other new types of memory, such as magnetic random access memory (MRAM) and phase-change random access memory (PCRAM).

[0035] For example, because RRAM is fabricated using a back-end process located within the metal interconnect layer, it is compatible with unconventional processes such as High Voltage (HV) CMOS and Bipolar-CMOS-DMOS (BCD) processes, which is beneficial for large-scale integration. For example, fabricating RRAM only requires approximately 2-3 additional mask layers on top of the logic process, making its fabrication cost significantly lower than that of eFlash. For example, RRAM does not require the high voltages needed for eFlash internally, resulting in lower operating voltages and programming currents, making it ideal for low-power applications. For example, RRAM can be shrunk to below 10 nanometers, breaking the miniaturization limits of eFlash devices, and still maintains good applicability in advanced processes such as FinFET and Fully Depleted Silicon-On-Insulator (FD-SOI).

[0036] With the advancement of process nodes, embedded resistive random access memory (eRRAM) is regarded as the ideal choice for next-generation embedded storage IP and in-memory computing applications. At the same time, emerging application scenarios also place higher demands on the integration density, consistency and reliability of RRAM.

[0037] Figure 1 This is a schematic diagram of a storage device. Figure 2A and Figure 2B This is a schematic diagram of some film layers of different RRAMs.

[0038] refer to Figure 1The memory device can be embedded between metal layers 21 and 22 in a back-end of line (BEOL) interconnect structure. For example, metal layer 22 is located on the side of metal layer 21 away from the substrate structure 10. For example, short vias can be formed in the metal diffusion barrier layer 30 between metal layers 21 and 22 using photolithography, and a material with good conductivity and via-filling ability can be deposited in the short vias to form a conductive material layer 14, thereby realizing the electrical interconnection of the device. Subsequently, a lower electrode material layer, a resistive switching material layer, and a top electrode material layer can be formed on the conductive material layer 14, and then a sandwich structure of lower electrode (BE, Bottom Electronic) 11-resistive switching reactive layer (RCL, Resistive Core Layer) 12-top electrode (TE, Top Electronic) 13 can be formed through an etching process, thus forming an RRAM device. Subsequently, dielectric material layer deposition and metal interconnection can be performed to form dielectric layer 40 and metal layer 22, etc. For example, the resistive switching layer 12 may include a resistive switching layer (RSL) 12a and a metal capping layer (MCL) 12b.

[0039] The inventors of this application discovered in their research that the aforementioned RRAM device is fabricated using a single etching method. However, because this process utilizes high-energy plasma to physically bombard and chemically react with the RRAM film, plasma-induced damage (PID) during the etching process is difficult to avoid. (Reference) Figure 2A As shown at point a, the etching process may damage the surface surrounding the resistive switching reaction layer 12 of the RRAM device and the interface between film layers, leading to electric field concentration. Simultaneously, the aforementioned film surface may generate unnecessary dangling bonds during the etching process between the resistive switching reaction layer 12 and the lower electrode 11, thereby causing short-circuit breakdown of the RRAM device by adsorbing charged ions.

[0040] Furthermore, due to the stacking properties of the RRAM device films, the area surrounding the resistive switching layer 12a is exposed to the environment during the etching of the lower electrode 11. (Reference) Figure 2A As shown at point b, after being bombarded by plasma, the conductive metal of the lower electrode 11 may undergo re-deposition on the resistive switching layer 12a. Since the resistive switching layer 12a of the RRAM device is relatively thin, conductive paths can easily form on the sidewalls of the resistive switching layer 12a, leading to short-circuit breakdown.

[0041] Therefore, Figure 2AThe two failure mechanisms shown at points a and b are likely to cause initial low resistance in some devices, leading to fluctuation problems in RRAM array devices, which in turn reflects the reliability degradation of RRAM chips.

[0042] To improve the above problems, refer to Figure 2B Passivation processes, such as thermal oxidation, can be used to form a passivated portion 12c on a part of the sidewall, thereby reducing the negative impact of etching damage and improving the consistency between RRAM devices. However, Figure 2B The process shown consumes an additional 12b of metal overlay, reducing the effective size of the RRAM device and increasing the forming voltage. In other words, Figure 2B This approach requires sacrificing operating voltage in exchange for high device reliability and array consistency. This reduces the scalability of RRAM devices and hinders further miniaturization and high-density integration.

[0043] At least one embodiment of this disclosure provides a storage device, comprising: a substrate structure; a first metal structure located on the substrate structure; a second metal structure located on a side of the first metal structure away from the substrate structure; a dielectric layer at least partially located between the first metal structure and the second metal structure; a resistive switching memory (RSM) including a first electrode, a resistive switching reaction layer, and a second electrode stacked along a first direction, the resistive switching reaction layer located between the first electrode and the second electrode; wherein the dielectric layer includes an electrode aperture, the sidewalls of the electrode aperture surrounding a first opening and a second opening formed opposite to each other in the first direction, the first opening exposing the first metal structure, and the second opening located on a surface of the dielectric layer away from the first metal structure; in a second direction intersecting the first direction, the size of the second opening is larger than the size of the first opening; the first electrode is completely located within the electrode aperture, the first electrode including a first electrode portion and a second electrode portion connected to each other, the first electrode portion located on a surface of the first metal structure away from the substrate structure, and the second electrode portion located on the sidewall; at least a portion of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction.

[0044] At least one embodiment of this disclosure provides a method for fabricating a memory device, comprising: sequentially forming a first metal structure and a first dielectric material layer on a substrate structure; forming an electrode hole in the first dielectric material layer by a first photolithography process to obtain a second dielectric material layer; wherein the electrode hole includes a sidewall surrounding a first opening and a second opening formed opposite to each other in a first direction, the first opening exposing the first metal structure, and the second opening located on a side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, the size of the second opening is larger than the size of the first opening; forming a first electrode within the electrode hole; wherein the first electrode is completely located within the electrode hole, the first electrode including a first electrode portion and a second electrode portion connected to each other, the first electrode portion located on a side surface of the first metal structure away from the substrate structure, and the second electrode portion located on the sidewall; forming a resistive switching reaction layer and a second electrode stacked on the side of the first electrode away from the substrate structure to form a resistive switching memory; wherein at least a portion of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction; forming a second metal structure on the side of the resistive switching memory away from the substrate structure to form the memory device.

[0045] The storage device and its fabrication method provided in at least one embodiment of this disclosure feature a sloped sidewall of the electrode aperture due to the different sizes of the first and second openings of the electrode aperture in the dielectric layer. This facilitates the formation of the first electrode within the electrode aperture. Furthermore, the region where the resistive switching layer contacts the first electrode includes an electric field resistive switching region. Since the resistive switching layer extends beyond the edge of the first electrode, it helps to limit the range of the electric field resistive switching region, preventing short circuits in other undesirable areas. Consequently, the reliability and inter-device consistency of the resistive switching memory are improved, and the overall size of the storage device can be reduced. Simultaneously, under the same design and process conditions, it is possible to increase the size of the resistive switching memory cell and reduce the operating voltage, which is beneficial for improving the consistency and reliability of the storage device.

[0046] The storage device and its manufacturing method are described below with reference to the accompanying drawings and through some embodiments.

[0047] Figure 3 This is a schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure.

[0048] refer to Figure 3The storage device includes a substrate structure 500, a first metal structure 300, a second metal structure 400, a dielectric layer 200, and a resistive switching memory 100. The first metal structure 300 is located on the substrate structure 500, and the second metal structure 400 is located on the side of the first metal structure 300 away from the substrate structure 500. At least a portion of the dielectric layer 200 is located between the first metal structure 300 and the second metal structure 400. The resistive switching memory 100 includes a first electrode 110, a resistive switching reaction layer 130, and a second electrode 120 stacked along a first direction, with the resistive switching reaction layer 130 located between the first electrode 110 and the second electrode 120. Thus, the resistive switching memory 100 can form a stacked sandwich structure of the first electrode 110-resistive switching reaction layer 130-second electrode 120.

[0049] refer to Figure 3 The dielectric layer 200 includes an electrode hole 201. The sidewall 210 of the electrode hole 201 surrounds a first opening 201A and a second opening 201B formed opposite to each other in a first direction. The first opening 201A exposes the first metal structure 300, and the second opening 201B is located on the surface of the dielectric layer 200 away from the first metal structure 300. In a second direction intersecting the first direction, the size of the second opening 201B is larger than the size of the first opening 201A. For example, by providing first openings 201A and second openings 201B with different sizes, at least a portion of the sidewall 210 of the electrode hole 201 can be tilted relative to the surface of the dielectric layer 200 away from the first metal structure 300.

[0050] refer to Figure 3 The first electrode 110 is completely located within the electrode hole 201. The first electrode 110 includes a first electrode portion 111 and a second electrode portion 112 connected to each other. The first electrode portion 111 is located on the surface of the first metal structure 300 away from the substrate structure 500, and the second electrode portion 112 is located on the sidewall 210. At least a portion of the resistive switching layer 130 extends beyond the edge of the first electrode 110 in a second direction.

[0051] refer to Figure 3 The storage device provided in this embodiment has a first opening 201A and a second opening 201B in the electrode hole 201 of the dielectric layer 200 with different sizes, resulting in an inclined sidewall 210 of the electrode hole 201, which facilitates the formation of the first electrode 110 within the electrode hole 201. Furthermore, the region where the resistive switching layer 130 contacts the first electrode 110 includes an electric field resistive switching region. Since the resistive switching layer 130 extends beyond the edge of the first electrode 110, it helps to limit the range of the electric field resistive switching region and prevent short circuits from occurring in other undesirable areas.

[0052] and Figures 1 to 2B Compared to the RRAM devices shown in the diagram, in Figure 3 In the storage device shown, the first electrode 110 of the resistive random access memory 100 is disposed within the electrode hole 201, eliminating the need for additional electrodes as described above. Figure 1 The conductive material layer 14 shown helps to reduce the size of the storage device in the first direction. Furthermore, the resistive switching layer 130 is configured to extend beyond the edge of the first electrode 110. The resistive switching layer 130 and the first electrode 110 can be formed separately in two processes, thereby reducing the risk of short circuits caused by etching damage to the resistive switching layer 130. Moreover, there is no need to introduce a sidewall passivation process. As a result, the reliability and inter-device consistency of the resistive switching memory 100 are improved, and the overall size of the storage device can be reduced. Simultaneously, under the same design and process conditions, it is possible to increase the size of the resistive switching memory cells and reduce the operating voltage, which is beneficial to improving the consistency and reliability of the storage device.

[0053] refer to Figure 3 For example, the resistive switching memory 100 can be considered as a resistive via located between the first metal structure 300 and the second metal structure 400. For example, the first metal structure 300 and the second metal structure 400 can be two adjacent metal structures in a back-end interconnect structure.

[0054] refer to Figure 3 For example, the resistive switching memory 100 can store data by changing the state of conductive fibers or oxygen vacancies in the resistive switching reaction layer 130. For instance, the resistive switching memory 100 is initially in a high-resistivity state. By applying a large forward operating voltage to the resistive switching memory 100, conductive filaments are formed in the resistive switching reaction layer 130 between the first electrode 110 and the second electrode 120 due to soft dielectric breakdown, and the resistive switching memory 100 switches from a high-resistivity state to a low-resistivity state. This process is called the forming process. The setting process is similar, but requires a relatively smaller forward operating voltage. Applying a reverse operating voltage to the resistive switching memory 100 prevents the conductive filaments from connecting to the electrodes, thereby switching from a low-resistivity state to a high-resistivity state; this process is called the reset process.

[0055] For example, a memory device may include one or more transistors (not shown in the figure) and one or more resistive random-access memory elements (such as resistive random-access memory 100). For example, transistors may be represented by T, and resistive random-access memory elements by R, including but not limited to 1T1R, 2T1R, 2T2R, etc. For example, a transistor has a gate, a source, and a drain, and the resistive random-access memory element may be connected to the source or drain of the transistor. For example, the gate of the transistor is connected to the word line (WL), the source is connected to the source line (SL), and the drain is connected to the resistive random-access memory element and, through the resistive random-access memory element, to the bit line (BL). It should be understood that the positions and connections of the source and drain of the transistor can be interchanged.

[0056] For example, the substrate structure may include a substrate and a device layer formed on the substrate. For example, the substrate may be or include a semiconductor substrate, such as a bulk silicon substrate, silicon-on-insulator (SOI) substrate, etc. For example, the device layer may include active devices such as transistors, passive devices such as capacitors, or combinations thereof. For example, transistors may be formed using a front-end of line (FEOL) process. For example, the substrate structure may include a transistor (not shown) electrically connected to a resistive random access memory; for example, the source or drain of the transistor may be electrically connected to a first electrode.

[0057] refer to Figure 3 For example, dielectric layer 200 can be an inter-layer dielectric (ILD). For example, dielectric layer 200 can serve as a metal diffusion barrier layer to block metal diffusion. For example, the material of dielectric layer 200 can include silicon carbon nitride (SiCN), silicon nitride (SiN), aluminum nitride (AlN), etc.

[0058] refer to Figure 3 For example, the sidewall 210 of the electrode hole 201 has a certain slope angle to facilitate the formation of the first electrode 110. For example, the first opening 201A is directly opposite the second direction in the first direction, such that the orthographic projection of the first opening 201A on the substrate structure 500 is completely within the range surrounded by the orthographic projection of the second opening 201B on the substrate structure 500.

[0059] refer to Figure 3 For example, the first opening 201A exposes the first metal structure 300, so that the first electrode 110 located in the electrode hole 201 can be electrically connected to the first metal structure 300 through the first electrode portion 111.

[0060] refer to Figure 3 For example, the first direction can be Figure 3 The direction indicated by the Y-direction arrow, or the direction opposite to the direction indicated by the arrow. For example, the second direction could be... Figure 3 The direction indicated by the X-direction arrow, or the direction opposite to the direction indicated by the arrow. For example, the first direction and the second direction can be perpendicular. It is understood that the second direction can also be a direction perpendicular to the Y-direction and intersecting the X-direction; this disclosure does not impose any restrictions on this.

[0061] refer to Figure 3 For example, the dimension of the first opening 201A in the second direction can be the maximum dimension of the first opening 201A. For example, the outer contour shape of the first opening 201A can be approximately circular, and the maximum dimension of the first opening 201A can be the diameter of the first opening 201A. Of course, this disclosure is not limited to this; for example, the outer contour shape of the first opening can be approximately rectangular. For example, when the outer contour shape of the first opening is rectangular, the maximum dimension of the first opening can be the dimension of the longer side of the first opening.

[0062] refer to Figure 3 For example, the dimension of the second opening 201B in the second direction can be the maximum dimension of the second opening 201B. For example, the outer contour shape of the second opening 201B can be approximately circular, and the maximum dimension of the second opening 201B can be the diameter of the second opening 201B. Of course, this disclosure is not limited to this; for example, the outer contour shape of the second opening can be approximately rectangular. For example, when the outer contour shape of the second opening is rectangular, the maximum dimension of the second opening can be the dimension of the longer side of the second opening.

[0063] refer to Figure 3 It is understood that the dimensions of the first opening 201A and the second opening 201B in the X direction can be measured in a cross-section taken from the storage device by a reference plane. The reference plane can be a plane parallel to the XY plane. It is understood that dimensions such as thickness, mentioned later, can be measured in this cross-section, and will not be elaborated further.

[0064] refer to Figure 3 In some examples, on the substrate structure 500, the orthographic projection of the first electrode 110 may lie entirely within the orthographic projection of the resistive switching layer 130, and there is a gap between the edge of the orthographic projection of the first electrode 110 and the edge of the orthographic projection of the resistive switching layer 130. For example, the periphery of the resistive switching layer 130 may extend completely beyond the first electrode 110. This better prevents short circuits at the edges of the resistive switching layer 130. For example, a portion of the resistive switching layer 130 may be located on the first electrode 110, and another portion may be located on the surface of the dielectric layer 200 away from the substrate structure 500.

[0065] However, this disclosure is not limited to this. For example, in the second direction, only a portion of the resistive switching layer may extend beyond the edge of the first electrode, while another portion may overlap with the edge of the first electrode, thereby preventing short circuits at the edge of the resistive switching layer to some extent.

[0066] refer to Figure 3 For example, metal diffusion barrier layers may be provided on the periphery of the first metal structure 300 and the periphery of the second metal structure 400 to prevent metal diffusion into the insulating layer. For example, the first metal structure 300 and the second metal structure 400 may be metal conductive lines. For example, this disclosure schematically illustrates an interconnect structure including a first metal structure 300 and a second metal structure 400, but this disclosure is not limited thereto. For example, the interconnect structure may include multiple layers of conductive lines and conductive vias. Multiple components in a component layer can be connected through the interconnect structure to form a functional circuit. For example, the resistive switching memory 100 may be located between any two conductive layers.

[0067] refer to Figure 3 For example, the resistive switching reaction layer 130 may include a resistive switching layer 131 and a metal capping layer 132. The metal capping layer 132 may be electrically connected to the second electrode 120. The resistive switching reaction layer 130 is configured to achieve a high-resistivity state and a low-resistivity state transition under the influence of an electric field between the first electrode 110 and the second electrode 120. For example, the erase and write characteristics of the RRAM can be achieved through oxygen exchange between the resistive switching layer 131 and the metal capping layer 132 in the resistive switching reaction layer 130. By providing the metal capping layer 132, it is beneficial to improve the stability of the resistive switching memory 100.

[0068] However, this disclosure is not limited to this. For example, the metal capping layer may be omitted, and the RRAM can be erased and written by oxygen exchange between the resistive switching layer and the second electrode.

[0069] refer to Figure 3 In some examples, the orthographic projection of the first electrode 110 lies within the orthographic projection of the sidewall 210 on a plane perpendicular to the second direction. Thus, the dielectric layer 200 can completely confine the first electrode 110 within the electrode hole 201. (See reference...) Figure 3 For example, on a plane perpendicular to the second direction, the edge of the orthographic projection of the first electrode 110 may coincide with the edge of the orthographic projection of the sidewall 210. It is understood that the first electrode 110 will not extend beyond the electrode hole 201, that is, it will not extend to the surface of the dielectric layer 200 away from the substrate structure 500 except for the portion of the electrode hole 201.

[0070] refer to Figure 3In some examples, the ratio of the thickness of the first electrode portion 111 to the thickness of the second electrode portion 112 is 0.9-1.1. For example, the film thickness of the first electrode 110 is substantially uniform, such that the thickness of the first electrode portion 111 is substantially the same as the thickness of the second electrode portion 112.

[0071] refer to Figure 3 For example, the first electrode 110, which is substantially of uniform thickness, can circumferentially surround a portion of the resistive switching reaction layer 130. For instance, the resistive switching memory 100 including this surrounding structure of the first electrode 110 can be referred to as a fin-type RRAM (Fin RRAM) device. Thus, with the same layout design area, using the surrounding structure of the first electrode 110 can increase the area of ​​the electric field resistive switching region, i.e., increase the effective area of ​​the resistive switching memory 100. This facilitates the miniaturization of the resistive switching memory 100 and the memory device including it.

[0072] refer to Figure 3 In some examples, the orthographic projection of the resistive switching layer 130 overlaps with the orthographic projection of the sidewall 210 on a plane perpendicular to the second direction. For example, a portion of the resistive switching layer 130 may be located within the space surrounded by the sidewall 210 of the electrode aperture 201. Thus, with the same layout design area, the area of ​​the electric field resistive switching region can be increased, i.e., the effective area of ​​the resistive switching memory 100 can be increased.

[0073] refer to Figure 3 For example, the film thickness of the first electrode 110 is substantially uniform, so that the first electrode 110 formed within the electrode hole 201 can conform to the electrode hole 201. Thus, the first electrode portion 111 and the second electrode portion 112 can substantially form a groove structure. The film thickness of the resistive switching reaction layer 130 formed on the first electrode 110 is substantially uniform, so that a portion of the resistive switching reaction layer 130 can be located within the groove structure formed by the first electrode 110.

[0074] For example, conformal means that the thickness of each part of the film is approximately equal in the direction perpendicular to its extension direction, which will not be elaborated further below.

[0075] Refer to the examples described later. Figure 3 and Figure 4For example, on a plane perpendicular to the second direction, the orthographic projection of the resistive switching layer 130 can overlap with the orthographic projection of the second arcuate portion 212 of the sidewall 210. Thus, the thinner resistive switching layer 130 can be better formed on the first electrode 110 and the dielectric layer 200. For example, the orthographic projection of the resistive switching layer 130 can also overlap with the orthographic projection of the first arcuate portion 211 of the sidewall 210. For example, the shape and size of the resistive switching layer 130 can be determined by designing parameters such as the size of the electrode hole 201 and the thickness of the first electrode 110; this disclosure does not impose any limitations on this.

[0076] refer to Figure 3 In some examples, the orthographic projection of the second electrode 120 overlaps with the orthographic projection of the sidewall 210 on a plane perpendicular to the second direction. For example, a portion of the structure of the second electrode 120 may be located within the space surrounded by the sidewall 210 of the electrode hole 201. Thus, with the same layout design area, the area of ​​the electric field resistive switching region can be increased, i.e., the effective area of ​​the resistive switching memory 100 can be increased.

[0077] refer to Figure 3 For example, the film thickness of the first electrode 110 is substantially uniform, so that the first electrode 110 formed within the electrode hole 201 can conform to the electrode hole 201. Simultaneously, the film thickness of the resistive switching layer 130 is substantially uniform, so that the resistive switching layer 130 can conform to the first electrode 110, such as forming a groove structure. Therefore, a portion of the second electrode 120 formed on the resistive switching layer 130 can be located within the groove structure formed by the resistive switching layer 130.

[0078] Refer to the examples described later. Figure 3 and Figure 4 For example, on a plane perpendicular to the second direction, the orthographic projection of the second electrode 120 can overlap with the orthographic projection of the second arcuate portion 212 of the sidewall 210. Thus, the second electrode 120 can be better formed on the resistive switching layer 130. For example, the orthographic projection of the second electrode 120 can also overlap with the orthographic projection of the first arcuate portion 211 of the sidewall 210. For example, the shape and size of the second electrode 120 can be determined by designing parameters such as the size of the electrode hole 201, the thickness of the first electrode 110, and the thickness of the resistive switching layer 130; this disclosure does not impose any limitations on this.

[0079] refer to Figure 3 In some examples, the orthographic projection of the second electrode 120 coincides with the orthographic projection of the resistive switching layer 130 on a plane perpendicular to the first direction. For example, the edge of the second electrode 120 is flush with the edge of the resistive switching layer 130. Thus, the electric field resistive switching region formed between the first electrode 110, the resistive switching layer 130, and the second electrode 120 can be maximized.

[0080] refer to Figure 3 In some examples, the surface of the second electrode 120 away from the substrate structure 500 has a recess 121, and a portion of the second metal structure 400 is located within the recess 121. For example, the first electrode 110 conforms to the electrode via 201, the resistive switching layer 130 conforms to the first electrode 110, and the second electrode 120 conforms to the resistive switching layer 130. Thus, the recess 121 is formed on the side of the second electrode 120 away from the substrate structure 500. By configuring the second metal structure 400 to have a portion located within the recess 121, the reliability of the electrical connection between the second metal structure 400 and the second electrode 120 can be improved.

[0081] Figure 4 This is a partial structural schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure. Figure 4 The storage device shown is Figure 3 The difference in the storage devices shown is that, Figure 4 The electrode holes of the storage device shown are different Figure 3 The electrode holes of the storage device shown.

[0082] Understandably, in settings such as Figure 4 In the case of the electrode hole shown, the first electrode formed in the electrode hole, the resistive switching reactive layer stacked on the first electrode, and the second electrode may also be different. Figure 3 The first electrode, resistive switching reactive layer, and second electrode are shown. For example, formed on... Figure 4 The first electrode within the electrode hole shown can conform to Figure 4 The electrode aperture and the resistive switching reaction layer may be conformally formed with the first electrode, and the second electrode may be conformally formed with the first electrode, etc. This disclosure does not limit this.

[0083] refer to Figure 3 and Figure 4 In some examples, the sidewall 210 includes a main body 213 and a first arcuate portion 211, the first arcuate portion 211 connecting the main body 213 and the side surface of the first metal structure 300 away from the substrate structure 500. The edge of the first arcuate portion 211 away from the main body 213 forms a first opening 201A. By providing the first arcuate portion 211, it is beneficial to improve the deposition effect of the first electrode 110 in the electrode hole 201, and also to ensure a uniform distribution of electric field and stress. At the same time, it is also beneficial to the formation of the resistive switching reaction layer 130 and the second electrode 120.

[0084] refer to Figure 3 and Figure 4For example, the main body 213 and the surface of the first metal structure 300 away from the substrate structure 500 can be smoothly transitioned by the first arcuate portion 211. For example, in a cross-section taken from the storage device by a reference plane parallel to the XY plane, the surfaces of the main body 213, the first arcuate portion 211 and the first metal structure 300 are connected to form a generally U-shaped shape.

[0085] refer to Figure 3 and Figure 4 For example, the slope angle between the sidewall 210 of the aforementioned electrode hole 201 and the surface of the first metal structure 300 can be regarded as the angle between the main body 213 in the sidewall 210 and the surface of the first metal structure 300.

[0086] refer to Figure 3 and Figure 4 In some examples, the maximum dimension D of the first opening 201A in the second direction is 5 nanometers to 100 nanometers. By setting the size range of the first opening 201A, the deposition effect of the first electrode portion 111 and the second electrode portion 112 in the electrode hole 201 can be improved while ensuring good contact between the first electrode 110 and the first metal structure 300.

[0087] refer to Figure 3 and Figure 4 In some examples, the sidewall 210 includes a main body 213 and a second arcuate portion 212. The second arcuate portion 212 connects the main body 213 and the surface of the dielectric layer 200 away from the substrate structure 500, excluding the electrode hole 201. The edge of the second arcuate portion 212 away from the main body 213 forms a second opening 201B. By providing the second arcuate portion 212, it is beneficial to improve the deposition effect of the first electrode 110 and the resistive switching reaction layer 130, and also to ensure a uniform distribution of electric field and stress. At the same time, it is also beneficial to the formation of the second electrode 120.

[0088] refer to Figure 3 and Figure 4 For example, the main body 213 and the side surface of the dielectric layer 200 away from the substrate structure 500, excluding the electrode hole 201, can be smoothly transitioned by the second arc-shaped portion 212.

[0089] refer to Figure 3In some examples, the storage device further includes a first insulating layer 610 and a second insulating layer 620. The first insulating layer 610 surrounds a portion of the first metal structure 300, and the second insulating layer 620 surrounds a portion of the resistive switching memory 100 and a portion of the second metal structure 400. For example, the resistive switching memory 100 and the second metal structure 400 may be surrounded by the same insulating layer. It is understood that the resistive switching memory 100 has a smaller size in the first direction, such as not occupying an entire layer of the metal structure.

[0090] refer to Figure 3 For example, the first insulating layer 610 and the second insulating layer 620 can be inter-metal dielectric (IMD) layers.

[0091] refer to Figure 3 In some examples, the dielectric layer 200 includes a first region overlapping the resistive switching layer 130 in a first direction and a second region Z2 other than the first region Z1. The maximum thickness of the first region Z1 in the first direction is greater than the maximum thickness of the second region Z2 in the first direction. For example, during the formation of the resistive switching layer 130 and the second electrode 120, the dielectric layer 200 may have a smaller thickness in the second region Z2 due to over-etching. By appropriately over-etching the second region Z2, it can be ensured that the resistive switching layer 130 can be completely removed; at the same time, since the first electrode 110 is located inside the edge of the resistive switching layer 130 in the planar direction (such as the second direction), over-etching can ensure that the first electrode 110 is not prone to forming a short circuit structure with the second electrode 120.

[0092] refer to Figure 3 For example, in a plane perpendicular to the second direction, the orthographic projection of the first electrode 110 overlaps with the second insulating layer 620. For example, in the second direction, a portion of the dielectric layer 200 may be located between the second electrode portion 112 and the second insulating layer 620. For example, the dielectric layer 200 may have a stepped structure formed at a position flush with the edge of the resistive switching layer 130.

[0093] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a storage device provided in at least one embodiment of the present disclosure. Figures 6A to 6H for Figure 3 The diagram shows the manufacturing process of the storage device.

[0094] refer to Figures 5 to 6H This disclosure provides a method for manufacturing a storage device, including the following steps S10 to S50.

[0095] Step S10: A first metal structure 300 and a first dielectric material layer 2001 are sequentially formed on the substrate structure 500.

[0096] Step S20: An electrode hole 201 is formed in the first dielectric material layer 2001 by a first photolithography process to obtain a second dielectric material layer 2002; the electrode hole 201 includes a sidewall 210, which surrounds a first opening 201A and a second opening 201B formed opposite to each other in a first direction. The first opening 201A exposes the first metal structure 300, and the second opening 201B is located on the side surface of the second dielectric material layer 2002 away from the first metal structure 300; in a second direction perpendicular to the first direction, the size of the second opening 201B is larger than the size of the first opening 201A.

[0097] Step S30: A first electrode 110 is formed in the electrode hole 201; the first electrode 110 is completely located in the electrode hole 201, and the first electrode 110 includes a first electrode portion 111 and a second electrode portion 112 connected to each other. The first electrode portion 111 is located on the side surface of the first metal structure 300 away from the substrate structure 500, and the second electrode portion 112 is located on the side wall 210.

[0098] Step S40: A resistive switching reaction layer 130 and a second electrode 120 are formed on the side of the first electrode 110 away from the substrate structure 500 to form a resistive switching memory 100; in a second direction, at least a portion of the resistive switching reaction layer 130 extends beyond the edge of the first electrode 110 in the second direction.

[0099] Step S50: A second metal structure 400 is formed on the side of the resistive switching memory 100 away from the substrate structure 500 to form a memory device.

[0100] Since the method for manufacturing the storage device according to the embodiments of this disclosure is used to manufacture the aforementioned storage device, it also has corresponding beneficial technical effects, which will not be elaborated here. It should also be noted that the method for manufacturing the storage device provided in the embodiments of this disclosure basically does not require the introduction of additional processes or special materials, making it process-friendly and material-friendly.

[0101] Understandable, Figures 6A to 6H This merely illustrates the formation as shown in the diagram. Figure 3 The diagram illustrates the manufacturing process of the storage device. However, this disclosure is not limited to this. For example, it may also employ a method similar to... Figures 5 to 6H The methods shown are basically the same, and the production includes, for example, Figure 4 The storage device shown includes an electrode hole with an arcuate portion, but this disclosure does not limit it.

[0102] refer to Figure 3 , Figure 5 and Figure 6AFor example, in step S10, a first dielectric material layer 2001 may be deposited on the side of the first metal structure 300 away from the substrate structure 500. The material of the first dielectric material layer 2001 may include silicon carbon nitride (SiCN), silicon nitride (SiN), aluminum nitride (AlN), etc.

[0103] refer to Figure 3 , Figure 5 , Figure 6A and Figure 6B For example, in step S20, a photoresist layer can be formed on the first dielectric material layer 2001, and the photoresist layer can be patterned using a first photomask through a photolithography process to define a mask pattern. Then, using the mask pattern as an etching mask, an etching process is performed on the first dielectric material layer 2001 to form a second dielectric material layer 2002 including electrode holes 201. Afterwards, the mask pattern can be removed, for example, using a lift-off process.

[0104] refer to Figure 3 , Figure 5 , Figure 6C In some examples, step S30 includes the following steps: forming a first electrode material layer 1101 on the side of the second dielectric material layer 2002 away from the substrate structure 500 and within the electrode hole 201. (See reference) Figure 6D A sacrificial layer 7001 is formed on the side of the first electrode material layer 1101 away from the substrate structure 500. (Reference) Figure 6E A planarization process is performed to remove the portion of the sacrificial layer 7001 except for the portion located within the electrode hole 201, and to remove the portion of the first electrode material layer 1101 except for the portion located within the electrode hole 201. (Reference) Figure 6F Remove a portion of the sacrificial layer 7001 within the electrode hole 201 to obtain the first electrode 110.

[0105] refer to Figure 6C For example, the first electrode material layer 1101 can be deposited using a physical vapor deposition (PVD) process. For example, the thickness of the first electrode material layer 1101 can be from 10 angstroms to 1000 angstroms.

[0106] refer to Figure 6C For example, the material of the first electrode material layer 1101 may include at least one of tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), gold (Au), tungsten (W), tungsten nitride (WN), aluminum-copper alloy (AlCu), tantalum (Ta), molybdenum (Mo), palladium (Pd), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), zirconium (Zr), aluminum (Al), and titanium (Ti). However, this disclosure does not impose any limitations on this.

[0107] refer to Figure 6D and Figure 6E For example, planarization processes may include chemical mechanical polishing (CMP) or etch-back processes. For instance, after planarization, the remaining portion of the sacrificial layer 7001, the remaining portion of the electrode material layer 1101, and the second dielectric material layer 2002, all located away from the substrate structure 500, can be approximately flush in a direction parallel to the main surface of the substrate structure 500.

[0108] refer to Figure 6D and Figure 6E In some examples, the material of the sacrificial layer 7001 includes spin-on carbon (SOC). Therefore, in the subsequent removal step of the sacrificial layer 7001, it can be removed by an ashing process, i.e., by a controlled reaction with oxygen in an oxygen-containing environment. Setting the material of the sacrificial layer 7001 to spin-on carbon reduces the risk of sacrificial layer 7001 residue. In the first electrode 110, as shown... Figure 3 The special structure shown (or formed in) Figure 4 In the case of the special structure within the electrode hole 201 shown, since the sacrificial layer 7001 is essentially not left behind, the first electrode 110 can have good surface characteristics, such as a smooth surface and generally no surface impurities. Of course, the sacrificial layer 7001 can also be removed by other cleaning processes, and this disclosure does not limit this.

[0109] refer to Figure 6D and Figure 6E For example, the deposition thickness of the sacrificial layer 7001 can be 1,000 to 2,000 angstroms.

[0110] refer to Figure 3 , Figure 5 and Figure 6G In some examples, step S40 includes forming a stacked resistive switching material layer 1301 and a second electrode material layer 1201 on the side of the first electrode 110 away from the substrate structure 500 and on the side of the second dielectric material layer 2002 away from the substrate structure 500. (See reference) Figure 6H A portion of the resistive switching reaction material layer 1301 and a portion of the second electrode material layer 1201 are removed by a second photolithography process to form the resistive switching reaction layer 130 and the second electrode 120, thereby forming the resistive switching memory 100.

[0111] refer to Figure 6G and Figure 6HFor example, the resistive switching reactive material layer 1301 may include a resistive switching material layer 1311 and a metal overlay material layer 1321. For example, the resistive switching material layer 1311 may be deposited using an atomic layer deposition (ALD) process. Of course, this disclosure is not limited to this, and PVD or pulsed laser deposition (PLD) processes may also be used.

[0112] refer to Figure 6G For example, the material of the resistive switching material layer 1311 may include hafnium oxide (HfO). x ), tantalum oxide (TaO) x ), aluminum oxide (AlO) x ), silicon dioxide (SiO) x At least one of the following. However, this disclosure does not impose any limitation on this.

[0113] refer to Figure 6G For example, the thickness of the resistive switching material layer 1311 can be from 5 angstroms to 50 angstroms.

[0114] refer to Figure 6G For example, the material of the metal overlay layer 1321 may include tantalum (Ta), titanium (Ti), hafnium (Hf), aluminum (Al), platinum (Pt), and titanium oxide (TiO). x germanium oxide (GeO) x ), hafnium oxide (HfO) x Zirconia (ZrO) x ), tantalum oxide (TaO) x At least one of the following. However, this disclosure does not impose any limitation on this.

[0115] refer to Figure 6G For example, the material of the second electrode material layer 1201 may include at least one of titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), aluminum (Al), tungsten (W), ruthenium (Ru), vanadium (V), copper (Cu), beryllium (Be), cobalt (Co), and osmium (Os). However, this disclosure does not limit it.

[0116] refer to Figure 6G and Figure 6H For example, the removal of the resistive switching material layer 1301 mentioned above refers to the removal of the resistive switching material layer 1311 and the metal capping material layer 1321. As a result, a resistive switching material layer 130 including the resistive switching layer 131 and the metal capping layer 132 can be formed.

[0117] refer to Figure 6G and Figure 6HFor example, a photoresist layer can be formed on the second electrode material layer 1201, and the photoresist layer can be patterned using a second photomask through a photolithography process to define a mask pattern. Then, using the mask pattern as an etching mask, an etching process is performed on the second electrode material layer 1201 and the resistive switching reactive material layer 1301, including the resistive switching material layer 1311 and the metal capping material layer 1321, to remove the portions of these material layers not covered by the mask pattern. The remaining portions, together with the first electrode 110, form a stacked resistive switching memory 100. Afterwards, for example, a stripping process can be used to remove the mask pattern.

[0118] refer to Figure 3 , Figure 5 and Figures 6A to 6H As can be seen from steps S10 to S40 above, the formation of the first electrode 110 and the resistive switching reaction layer 130 and the second electrode 120 are formed by two separate processes, but no additional photomask is required. Therefore, the method for fabricating the memory device provided in this disclosure requires no additional cost and has good compatibility with some mass production platforms. Furthermore, because the first electrode 110 and the resistive switching reaction layer 130 are fabricated separately, device reliability issues introduced by continuous etching processes can be effectively prevented.

[0119] refer to Figure 6G and Figure 6H In some examples, before step S50, the process further includes: removing a portion of the second dielectric material layer 2002 by a second photolithography process to form the dielectric layer 200; the aforementioned portion is the part of the second dielectric material layer 2002 excluding the portion that overlaps with the resistive switching reaction layer 130 in the first direction. For example, during the etching process of the second electrode material layer 1201 and the resistive switching reaction material layer 1301, a portion of the second dielectric material layer 2002 can be removed due to over-etching.

[0120] refer to Figure 6H and Figure 3 In some examples, step S50 includes forming an insulating material layer on the side of the resistive switching memory 100 and the second dielectric material layer 2002 away from the substrate structure 500, forming the insulating layer and the second metal structure 400 located within the insulating layer by an inlay process.

[0121] refer to Figure 6H and Figure 3 For example, insulating material layers with low dielectric constants can be grown on the side of dielectric layer 200 away from substrate structure 500 and the side of resistive switching memory 100 away from substrate structure 500 by chemical vapor deposition (CVD).

[0122] refer to Figure 6H and Figure 3For example, the material of the insulating layer may include at least one of silicon dioxide (SiO2), carbon-doped silicon oxide (SiOCH), silicon phosphosilicate glass (PSG), and borosilicate glass (BPSG). However, this disclosure is not limiting in this regard. For example, the insulating layer formed in step S50 above may be... Figure 3 The second insulating layer 620 in the storage device shown. For example... Figure 3 The materials of the first insulating layer 610 and the second insulating layer 620 in the storage device shown may be the same or different, and this disclosure does not impose any restrictions.

[0123] For example, the inlay technique can be Damascus (Damascene) technique.

[0124] refer to Figure 6H and Figure 3 For example, a metal material can be deposited within the vias of the second insulating layer 620 using a PVD process to fill the vias and simultaneously form the metal lines in the upper layer. For instance, the metal material may include at least one of titanium (Ti), aluminum (Al), tungsten (W), copper (Cu), and titanium nitride (TiN). However, this disclosure does not impose any limitations on this.

[0125] refer to Figure 6H and Figure 3 For example, the first metal structure 300 can also be formed within the first insulating layer 610 by the above-described inlay process, which will not be described in detail here. For example, the material of the first metal structure 300 can be the same as or different from the material of the second metal structure 400, and this disclosure does not impose any restrictions.

[0126] The storage device and its fabrication method provided in this disclosure can meet the hardware applications of high-density storage or in-memory computing, and also meet the thermal budget of subsequent processes, with virtually no additional size overhead, and have the advantage of being process-friendly. Through flexible configuration of the film layers in the storage device, device systems can be realized to meet the needs of different application scenarios, making the storage device highly versatile.

[0127] The following points need to be explained:

[0128] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0129] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0130] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A storage device, comprising: Substrate structure; A first metallic structure is located on the substrate structure; The second metal structure is located on the side of the first metal structure away from the substrate structure; A dielectric layer, at least partially located between the first metal structure and the second metal structure; A resistive switching memory includes a first electrode, a resistive switching reaction layer, and a second electrode stacked along a first direction, wherein the resistive switching reaction layer is located between the first electrode and the second electrode. The dielectric layer includes an electrode hole, the sidewalls of which surround a first opening and a second opening formed opposite to each other in the first direction. The first opening exposes the first metal structure, and the second opening is located on the side surface of the dielectric layer away from the first metal structure. In a second direction intersecting the first direction, the size of the second opening is larger than the size of the first opening; The first electrode is completely located within the electrode hole. The first electrode includes a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located on the side surface of the first metal structure away from the substrate structure, and the second electrode portion is located on the sidewall. At least a portion of the resistive switching layer extends beyond the edge of the first electrode in the second direction.

2. The storage device according to claim 1, wherein, On a plane perpendicular to the second direction, the orthographic projection of the first electrode lies within the orthographic projection of the sidewall.

3. The storage device according to claim 2, wherein, The ratio of the thickness of the first electrode portion to the thickness of the second electrode portion is 0.9-1.

1.

4. The storage device according to claim 1, wherein, On the substrate structure, the orthographic projection of the first electrode is completely located within the orthographic projection of the resistive switching reaction layer, and there is a gap between the edge of the orthographic projection of the first electrode and the edge of the orthographic projection of the resistive switching reaction layer.

5. The storage device according to any one of claims 1-4, wherein, The sidewall includes a main body and a first arcuate portion, the first arcuate portion being connected between the main body and the surface of the first metal structure away from the substrate structure; The first arcuate portion forms the first opening around one edge away from the main body portion.

6. The storage device according to any one of claims 1-4, wherein, The sidewall includes a main body and a second arc-shaped portion, the second arc-shaped portion being connected between the main body and the surface of the dielectric layer other than the electrode hole on the side away from the substrate structure; The second arcuate portion forms the second opening around the edge of the side away from the main body portion.

7. The storage device according to any one of claims 1-4, wherein, The maximum size of the first opening in the second direction is 5 nanometers to 100 nanometers.

8. The storage device according to any one of claims 1-4, wherein, On a plane perpendicular to the second direction, the orthographic projection of the resistive switching layer overlaps with the orthographic projection of the sidewall.

9. The storage device according to any one of claims 1-4, wherein, On a plane perpendicular to the second direction, the orthographic projection of the second electrode overlaps with the orthographic projection of the sidewall.

10. The storage device according to claim 9, wherein, On a plane perpendicular to the first direction, the orthographic projection of the second electrode coincides with the orthographic projection of the resistive switching layer.

11. The storage device according to claim 9, wherein, The second electrode has a recess on the side of its surface away from the substrate structure, and a portion of the second metal structure is located within the recess.

12. The storage device according to any one of claims 1-4, further comprising a first insulating layer and a second insulating layer; The first insulating layer surrounds a portion of the first metal structure, and the second insulating layer surrounds a portion of the resistive switching memory and a portion of the second metal structure.

13. The storage device according to claim 12, wherein, The dielectric layer includes a first region that overlaps with the resistive switching layer in the first direction and a second region other than the first region; The maximum thickness of the first region in the first direction is greater than the maximum thickness of the second region in the first direction.

14. A method for manufacturing a storage device, comprising: A first metal structure and a first dielectric material layer are sequentially formed on the substrate structure; Electrode holes are formed in the first dielectric material layer using a first photolithography process to obtain a second dielectric material layer; wherein, the electrode holes include sidewalls surrounding a first opening and a second opening formed opposite to each other in a first direction, the first opening exposing the first metal structure, and the second opening located on the side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, the size of the second opening is larger than the size of the first opening; A first electrode is formed within the electrode hole; wherein the first electrode is completely located within the electrode hole, and the first electrode includes a first electrode portion and a second electrode portion connected to each other, the first electrode portion being located on the side surface of the first metal structure away from the substrate structure, and the second electrode portion being located on the sidewall; A resistive switching reaction layer and a second electrode are formed on the side of the first electrode away from the substrate structure to form a resistive switching memory; wherein at least a portion of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction; A second metal structure is formed on the side of the resistive switching memory away from the substrate structure to form a storage device.

15. The method according to claim 14, wherein, Forming the first electrode within the electrode hole includes: A first electrode material layer is formed on the side of the second dielectric material layer away from the substrate structure and within the electrode hole; A sacrificial layer is formed on the side of the first electrode material layer away from the substrate structure; A planarization process is performed to remove the portion of the sacrificial layer except for the portion located within the electrode hole, and to remove the portion of the first electrode material layer except for the portion located within the electrode hole. Remove a portion of the sacrificial layer within the electrode hole to obtain the first electrode.

16. The method according to claim 15, wherein, The material of the sacrificial layer includes spin-coated carbon.

17. The method of claim 14, wherein, On the substrate structure, the orthographic projection of the first electrode is completely located within the orthographic projection of the resistive switching reaction layer, and there is a gap between the edge of the orthographic projection of the first electrode and the edge of the orthographic projection of the resistive switching reaction layer.

18. The method according to claim 14, wherein, Forming the second metal structure on the side of the resistive switching memory away from the substrate structure includes: An insulating material layer is formed on the side of the resistive switching memory and the second dielectric material layer away from the substrate structure; An insulating layer and a second metal structure located within the insulating layer are formed through an inlay process.

19. The method of claim 14, wherein, The resistive switching reaction layer and the second electrode are formed in a stacked manner on the side of the first electrode away from the substrate structure, including: A resistive switching material layer and a second electrode material layer are formed on the side of the first electrode away from the substrate structure and on the side of the second dielectric material layer away from the substrate structure. The resistive switching memory is formed by removing a portion of the resistive switching reactive material layer and a portion of the second electrode material layer through a second photolithography process to form the resistive switching reactive layer and the second electrode.

20. The method according to claim 19, wherein, Before forming the second metal structure on the side of the resistive switching memory away from the substrate structure, the method further includes: A portion of the second dielectric material layer is removed by the second photolithography process to form a dielectric layer; wherein, the portion is the part of the second dielectric material layer excluding the portion that overlaps with the resistive switching reaction layer in the first direction.

Images