Microstrip transmission line with inductive and capacitive segments

Abstract

The present invention relates to a microstrip transmission line having inductive and capacitive segments, and discloses a structure of the microstrip transmission line and a method for forming the microstrip transmission line. The microstrip transmission line includes a signal line, a shielding cover, and a plurality of wiring structures connected to the signal line. Each wiring structure extends from a portion of the signal line toward the shielding cover and includes a metal component disposed adjacent to the shielding cover.

Description

Technical Field

[0001] The present invention relates to semiconductor devices and integrated circuit manufacturing, and more particularly to the structure of a microstrip transmission line and a method for forming the microstrip transmission line. Background Art

[0002] Microstrip is perhaps the most commonly used planar structure for transmission lines used as delay lines, phase shifters, microwave filters, and quarter-wavelength-based devices such as branch-line couplers, Wilkinson power dividers, and hybrid rings. Slow-wave designs can be implemented to shorten the physical length of microstrip transmission lines. In traditional slow-wave designs, microstrip transmission lines can include narrow inductive segments alternating with wider capacitive segments to define a periodic narrow-wide line structure. This periodic narrow-wide line structure can result in a simultaneous increase in both the line's equivalent inductance and capacitance, which can significantly reduce the propagation velocity, also known as the slow-wave effect.

[0003] There is a need for improved microstrip transmission line structures and methods of forming microstrip transmission lines. Summary of the Invention

[0004] In one embodiment of the present invention, a microstrip transmission line structure includes a signal line, a shielding cover, and a plurality of circuit structures connected to the signal line. Each circuit structure extends from a portion of the signal line toward the shielding cover, and each circuit structure includes a metal component disposed adjacent to the shielding cover.

[0005] In one embodiment of the present invention, a method for forming a microstrip transmission line includes forming a signal line in a back-end process stack, forming a shielding cover in the back-end process stack, and forming a plurality of wiring structures in the back-end process stack connected to the signal line. Each wiring structure extends from a portion of the signal line toward the shielding cover, and each wiring structure includes a metal component disposed adjacent to the shielding cover. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the invention given above and the detailed description of these embodiments given below, serve to explain these embodiments of the present invention. In the drawings, like reference numerals represent similar features in different views.

[0007] Figure 1 A top view of a structure according to an embodiment of the present invention is shown.

[0008] Figure 2 Show approximate edge Figure 1 A cross-sectional view taken along line 2-2.

[0009] Figure 2A Show approximate edge Figure 1 A cross-sectional view taken along line 2A-2A.

[0010] Figure 3 show Figure 1 、 2 , a schematic three-dimensional view of a unit segment of the structure of 2A.

[0011] Figure 4 A flow chart showing a sequence of operations that may be performed by a computer system to determine optimized segment properties of the structure.

[0012] Figure 5 A flow chart showing an alternative sequence of operations that may be performed by a computer system to determine optimized segment properties of the structure.

[0013] Figure 6 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0014] Figure 7 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0015] Figure 8 It is shown that the embodiment according to the present invention can be used to perform Figure 4 Operation or Figure 5 Schematic diagram of an example computer system for the operation of FIG. DETAILED DESCRIPTION

[0016] Please refer to Figure 1 、 2 , 2A and according to an embodiment of the present invention, the structure 10 of the microstrip transmission line includes a shield 26 and a signal line 28 arranged in a back-end process stack 14. The back-end process stack 14 is disposed on and above a semiconductor substrate 12. The semiconductor substrate 12 can be a bulk substrate comprising a semiconductor material (e.g., silicon). Alternatively, the semiconductor substrate 12 can be a silicon-on-insulator (SOI) substrate, which includes a device layer composed of a semiconductor material (e.g., silicon), a buried oxide layer composed of silicon dioxide, and a handle substrate also composed of a semiconductor material (e.g., silicon). Device structures, such as field-effect transistors, can be formed during the front-end process of the semiconductor substrate 12.

[0017] The back-end process stack 14 may include multiple circuit layers, which may be formed during the back-end process by deposition, polishing, photolithography, and etching techniques characteristic of a damascene process. Specifically, for each circuit layer of the back-end process stack 14, an interlayer dielectric layer may be deposited and patterned to define trenches and via openings, lined with a barrier layer (e.g., a double layer of tantalum and tantalum nitride), and filled with a planarized conductor (e.g., copper) to define lines and vias connecting lines in different circuit layers. The interlayer dielectric layers of the back-end process stack 14 may be composed of an inorganic dielectric material, such as silicon dioxide or a low-k dielectric material, deposited by, for example, chemical vapor deposition. In this representative embodiment, the back-end process stack 14 includes interlayer dielectric layers 16, 18, 20, 22, and 24 arranged in multiple circuit layers.

[0018] The shield 26 may be formed in one of the wiring layers of the back-end process stack 14, and the signal line 28 may be formed in another of the wiring layers of the back-end process stack 14 that is different from the wiring layer including the shield 26. The shield 26 is vertically disposed within the wiring layers of the back-end process stack 14 between the signal line 28 and the semiconductor substrate 12. In one embodiment, the shield 26 may be formed in the lowest wiring layer (i.e., the first metal layer (M1)) of the back-end process stack 14 and associated with the interlayer dielectric layer 16. In one embodiment, the signal line 28 may be formed in an upper wiring layer (e.g., the fifth metal layer (M5)) of the back-end process stack 14 and associated with the interlayer dielectric layer 24.

[0019] The signal line 28 can be coupled to a signal source, such as a driver 25. The driver 25 can include components, such as a driver amplifier, configured to provide data in the form of a radio frequency signal to the signal line 28. The shield 26 can be physically coupled electrically to a ground through the back-end process stack 14 and can be grounded, thereby defining a ground plane.

[0020] Back-end stack 14 includes wiring structures 42 that are physically and electrically connected to different portions of signal line 28 and extend downward from signal line 28 through interlayer dielectric layers 20, 22, and 24 toward shield 26. Each wiring structure 42 is terminated by a metal feature 40 that is disposed in a non-contacting relationship adjacent shield 26. Wiring structures 42 are disconnected from one another except for spaced apart connections to different portions of signal line 28 at longitudinally distributed locations.

[0021] Each wiring structure 42 includes a via 30 that physically connects signal line 28 to a metal component 32 in an underlying wiring layer (e.g., metal layer 4 (M4)). Each wiring structure 42 also includes a via 34 that physically connects metal component 32 to a metal component 36 in an underlying wiring layer (e.g., metal layer 3 (M3)). Each wiring structure 42 also includes a via 38 that physically connects metal component 36 to one of metal components 40 in an underlying wiring layer (e.g., metal layer 2 (M2)). However, metal component 40 is not connected to shield 26 through a via. Instead, a portion of interlayer dielectric layer 18 is disposed between metal component 40 and shield 26, and the dielectric material contained in this portion of interlayer dielectric layer 18 electrically isolates metal component 40 from shield 26.

[0022] The portion of interlayer dielectric layer 18 separating each metal component 40 from shield 26 has a dielectric material thickness T1, which can be less than the full thickness of interlayer dielectric layer 18. Signal line 28 is separated from shield 26 by interlayer dielectric layers 18, 20, 22, and 24, which have a dielectric material thickness T2 that is greater than thickness T1. The coupling between metal component 40 and shield 26 can be primarily capacitive and provide capacitive loading, while the coupling between shield 26 and the segments of signal line 28 not connected to metal component 40 can be primarily inductive and provide inductive loading due to the physical isolation of the larger dielectric fill. The individual capacitance values ​​attributed to the different metal components 40 result in a distributed equivalent capacitance value that is equal to the sum of the individual capacitance values.

[0023] In an embodiment, the metal component (e.g., metal component 40) that terminates the wiring structure 42 may be located in any wiring layer of the back-end processing stack 14 disposed between the shield 26 and the signal line 28. In this representative embodiment, the metal component 40 is located in a wiring layer that provides the second metal layer of the back-end processing stack 14, the shield 26 is located in a wiring layer that provides the first metal layer of the back-end processing stack 14, and the signal line 28 is located in a wiring layer that provides the fifth metal layer of the back-end processing stack 14. In one embodiment, the wiring layer of the back-end processing stack 14 that includes the metal component 40 may be immediately adjacent to or directly adjacent to the wiring layer of the back-end processing stack 14 that includes the shield 26.

[0024] The shield 26 and the signal line 28 may extend longitudinally along the longitudinal axis 27, and the line structure 42 may extend perpendicular to the longitudinal axis 27 in a vertical direction. The signal line 28 may be characterized by a width W1 in a direction perpendicular to the longitudinal axis 27 and a length L1 in a direction parallel to the longitudinal axis 27. The width W1 of the signal line 28 may be less than the width of the shield 26. In one embodiment, the signal line 28 may be centrally located above the shield 26. In one embodiment, the width W1 of the signal line 28 may be uniform or constant along its entire length L1, or at least along the portion of the length L1 located above the shield 26. In one embodiment, the width W1 of the signal line 28 may be substantially constant along its entire length L1, or at least along the portion of the length L1 located above the shield 26. The uniform or constant width W1 of the signal line 28 differs from conventional microstrip transmission lines having a periodic narrow-wide line structure in which narrow inductive segments of the signal line alternate longitudinally with wider capacitive segments of the signal line.

[0025] The metal features 40 and associated wiring structures 42 may have a periodic arrangement along the longitudinal axis 27 of the signal line 28. In one embodiment, the metal features 40 and associated wiring structures 42 may be arranged at uniform spacing along the longitudinal axis 27 of the signal line 28. In one embodiment, the width W1 of the signal line 28 may be uniform or constant along the entire length L1 of the signal line 28, and the metal features 40 and associated wiring structures 42 may be arranged at uniform spacing along the length of the signal line 28.

[0026] The metal components 40 can be characterized by a width W2 along a direction perpendicular to the longitudinal axis 27 of the signal line 28 and a length L2 along a direction parallel to the longitudinal axis 27 of the signal line 28. The width W2 of each metal component 40 can be less than the width of the shield 26, and the length L2 of each metal component 40 can be less than the length L1 of the signal line 28. In one embodiment, the width W2 of each metal component 40 can be equal to the width W1 of the signal line 28. In one embodiment, the width W2 of each metal component 40 can be substantially equal to the width W1 of the signal line 28.

[0027] Structure 10 can have a reduced length and reduced width, thereby facilitating a smaller device area and footprint compared to those exhibited by conventional microstrip transmission lines. The constant or substantially constant width of signal line 28 along its length can facilitate simplified layout, which can facilitate directional changes in signal line 28 and simplify the design and optimization of structure 10.

[0028] Please refer to Figure 3According to an embodiment of the present invention, signal line 28 may be formed from a plurality of unit segments 44, which may be considered to be arranged end-to-end in an overall chain or string to define an assembly. Each unit segment 44 of signal line 28 may include a capacitor segment 46, an inductor segment 48, and an inductor segment 50, each coupled to one of metal components 40 via one of the wiring structures 42. The capacitor segment 46 of each unit segment 44 is arranged longitudinally along the length of signal line 28, between the inductor segment 48 and the inductor segment 50.

[0029] Please refer to Figure 4 According to an embodiment of the present invention, the computer system 68 ( Figure 8 ) performs a series of operations to determine optimized properties of the cell segment 44 of the structure 10, for example, maximizing the cutoff frequency while minimizing the segment length to provide the greatest size reduction for the structure 10. In block 100, the length of the capacitor segment 46 (Lcap) is determined from a layout ground rule for the metal layer including the signal line 28 or from a layout ground rule for the metal layer including the metal feature 40. The ground rule is a geometric constraint imposed on the design data in the layout of the metal layer of the back-end process stack 14. The length of the capacitor segment 46 may be equal to the length of the metal feature 40 included in the cell segment 44. In block 102, the line width W is set to the ground rule minimum width for the metal layer including the signal line 28.

[0030] In block 104, the total length (Lsec) of the cell segments 44 is tuned until a target line characteristic impedance (e.g., 50 ohms) is achieved. In block 106, the integer number of cell segments 44 required for a given length L of signal line 28 is determined by: N = int(L / Lsec). In block 108, the new length (Lsec_new) of the cell segments 44 is determined by dividing the length L by the integer number of cell segments 44. In block 110, the new length (Lcap_new) of the capacitor segments 46 is determined by the ratio: Lcap_new = Lcap * Lsec_new / Lsec. In block 112, the line characteristic impedance of this new segment length is checked for acceptability relative to the target line characteristic impedance. If the line characteristic impedance is unacceptable, the length of the capacitor segments 46 is fine-tuned in block 114. Fine line width adjustments can be used as a secondary tuning factor to adjust the line characteristic impedance and can also be used for cell loss adjustment. If the line characteristic impedance is acceptable, multiple instances of the unit segment 44 (each having the final lengths of the unit segment 44 and the capacitor segment 46) may be used to form the signal line 28 in block 116. Generally, the line characteristic impedance is acceptable if it is within a few ohms of the target line characteristic impedance.

[0031] Please refer to Figure 5 According to an embodiment of the present invention, the computer system 68 ( Figure 8 ) performs a series of operations to determine optimized properties of the unit segment 44 of the structure 10, such as providing maximum size reduction and optimized insertion loss for the structure 10. In block 200, the length (Lcap) of the capacitor segment 46 is determined from the layout basis rules of the metal layer including the signal line 28 or from the layout basis rules of the metal layer including the metal component 40. In block 202, the maximum length (maxLsec) of the unit segment 44 is determined. The maximum length of the unit segment 44 can be set to be equal to a fraction of the wavelength of the maximum signal frequency of interest (e.g., 1 / 20 or 1 / 10). In block 204, a loss benchmark for the insertion loss is determined. The loss benchmark can be determined by a given number established by the design application or by using a standard on-chip microstrip transmission line unit loss.

[0032] In block 206, the line width W is incrementally scanned from a ground-rule minimum width to approximately half the width of a standard on-chip microstrip transmission line using the same signal line and ground shield metal layers. In block 208, the length (Lsec) of the unit segment 44 is incrementally scanned from twice the length of the capacitor segment 46 (i.e., 2*Lcap) to the maximum length (maxLsec) of the unit segment 44. In block 210, a determination is made as to whether the scan limits for the line width and segment length have been reached. If the scan limits have been reached, control transfers to block 212, and different parameters must be selected in one or more of blocks 200, 202, or 204. If the scan limits have not been reached, control transfers to block 214, where the line characteristic impedance (Z0) and line insertion loss are checked for acceptability. If the line characteristic impedance and insertion loss are unacceptable, control transfers to block 208. If the line characteristic impedance and insertion loss are unacceptable, control transfers to block 216, where the integer number of unit segments 44 required (N) for a given total length L of signal line 28 is determined by: N = int(L / Lsec). In block 218, a new segment length (Lsec_new) is determined by dividing the given total length L by the integer number of unit segments 44. In block 220, the new length of capacitor segment 46 (Lcap_new) is determined by the ratio: Lcap_new = Lcap * Lsec_new / Lsec. In block 222, the line characteristic impedance is checked for acceptability relative to the target line characteristic impedance. If the line characteristic impedance is unacceptable, the length of capacitor segment 46 is fine-tuned in block 224. If the line characteristic impedance is acceptable, multiple instances of unit segment 44 (each having the final lengths of unit segment 44 and capacitor segment 46) can be used to form signal line 28 in block 226.

[0033] Please refer to Figure 6According to an alternative embodiment of the present invention, via 38 and metal feature 40 may be omitted from structure 10, and metal feature 36 in the third metal layer of back-end stack 14 may be located in a circuit layer adjacent to and closest to shield 26 in the first metal layer of back-end stack 14. In this case, metal feature 36 terminates and is capacitively coupled to shield 26. Multiple circuit layers (including interlayer dielectric layers 18 and 20) of back-end stack 14 are disposed between the circuit layer including shield 26 and the circuit layer including metal feature 36.

[0034] Please refer to Figure 7 According to an alternative embodiment of the present invention, vias 34, 38 and metal features 36, 40 may be omitted from structure 10, and metal feature 32 in the fourth metal layer of back-end processing stack 14 may be adjacent to and closest to shield 26 in the first metal layer of back-end processing stack 14. In this case, metal feature 32 is capacitively coupled to shield 26. Multiple circuit layers and multiple interlayer dielectric layers 18, 20, 22 are disposed between shield 26 and metal feature 32.

[0035] Please refer to Figure 8 , the example computer system 68 may be configured to perform Figure 4 The sequence of operations in Figure 5 , to determine optimized segment properties for structure 10. Computer system 68 may include a processor 70, a memory 72, a mass storage memory device 74, an input / output (I / O) interface 76, and a human machine interface (HMI) 78. Computer system 68 may also be operatively coupled to one or more external resources 80 via I / O interface 76. External resources 80 may include, but are not limited to, servers, databases, mass storage devices, peripheral devices, cloud-based network services, or any other suitable computer resources that may be used by computer system 68.

[0036] The processor 70 may include one or more devices selected from a microprocessor, a microcontroller, a digital signal processor, a microcomputer, a central processing unit, a field programmable gate array, a programmable logic device, a state machine, a logic circuit, an analog circuit, a digital circuit, or any other device that manipulates signals (analog or digital) based on operating instructions stored in the memory 72. The memory 72 may include a single memory device or multiple memory devices, including but not limited to read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache, or any other device capable of storing information. The mass storage memory device 74 may include a data storage device, such as a hard drive, an optical drive, a tape drive, a non-volatile solid-state device, or any other device capable of storing information.

[0037] The processor 70 may operate under the control of an operating system 82 residing in the memory 72. The operating system 82 may manage computer resources so that computer program code, embodied as one or more computer software applications (e.g., application 84 residing in the memory 72), may have instructions for execution by the processor 70. In an alternative embodiment, the processor 70 may directly execute the application 84, in which case the operating system 82 may be omitted. One or more data structures 86 may also reside in the memory 72 and may be used by the processor 70, the operating system 82, or the application 84 to store or manipulate data. The application 84 may include a module having instructions for determining optimized segment properties of the structure 10 as described herein. In particular, the application 84 may be an electromagnetic simulation tool configured to solve Maxwell's equations for each point on a mesh using the finite element method.

[0038] The I / O interface 76 may provide a machine interface that operably couples the processor 70 to other devices and systems, such as one or more external resources 80. Thus, the applications 84 may work in conjunction with the external resources 80 by communicating via the I / O interface 76 to provide the various features, functions, applications, processes, or modules that comprise embodiments of the present invention. The applications 84 may also have program code that is executed by one or more external resources 80, or otherwise rely on functions or signals provided by other systems or network components external to the computer system 68. Indeed, given the nearly endless number of possible hardware and software configurations, those skilled in the art will appreciate that embodiments of the present invention may include applications that are external to the computer system 68, distributed among multiple computers or other external resources 80, or provided by computing resources (hardware and software) provided as a service (e.g., cloud computing services) over the communication network 90.

[0039] The HMI 78 can be operatively coupled to the processor 70 of the computer system 68 in a known manner to allow a user to directly interact with the computer system 68. The HMI 78 can include a video or alphanumeric display, a touch screen, speakers, and any other suitable audio and visual indicators capable of providing data to the user. The HMI 78 can also include input devices and control devices, such as an alphanumeric keyboard, a pointing device, a keypad, buttons, control knobs, a microphone, etc., which can receive commands or input from the user and transmit the typed input to the processor 70.

[0040] A database 88, which may reside on the mass storage memory device 74, may be used to collect and organize data used by the various systems and modules described herein. The database 88 may include data and supporting data structures that store and organize the data. In particular, the database 88 may be arranged in any database organization or structure, including, but not limited to, a relational database, a hierarchical database, a network database, or a combination thereof. A database management system in the form of a computer software application executed as instructions on the processor 70 may be used to access information or data stored in records of the database 88 in response to queries, where the queries may be dynamically determined and executed by the operating system 82, other applications 84, or one or more modules.

[0041] In general, routines executed to implement embodiments of the present invention, whether implemented as part of an operating system or as a specific application, component, program, object, module, or sequence of instructions, or even a subset thereof, may be referred to herein as "computer program code," or simply "program code." Program code typically includes computer-readable instructions that reside at various times in various memories and storage devices within a computer and, when read and executed by one or more processors within a computer, cause the computer to perform the operations necessary to implement the various aspects of the operations and / or elements of the embodiments of the present invention. The computer-readable program instructions for performing the operations of embodiments of the present invention may be, for example, source code or object code written in assembly language, or in any combination of one or more programming languages.

[0042] The program code implemented in any application / module described herein can be distributed individually or together as a program product in various forms. In particular, the program code can be distributed by using a computer-readable storage medium having computer-readable program instructions thereon to enable a processor to execute the aspects of the embodiments of the present invention.

[0043] Computer-readable storage media (which are non-transitory in nature) may include volatile and non-volatile, removable and non-removable tangible media implemented in any method or technology to store information, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media may also include random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid-state memory technology, portable compact disc read-only memory (CD-ROM) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be read by a computer. Computer-readable storage media should not be construed as inherently transient signals (e.g., radio waves or other propagating electromagnetic waves, electromagnetic waves propagating through a transmission medium such as a waveguide, or electrical signals transmitted through wires). Computer-readable program instructions can be downloaded from the computer-readable storage medium to a computer, another type of programmable data processing apparatus, or another device, or downloaded to an external computer or external storage device through a communication network.

[0044] Computer-readable program instructions stored in a computer-readable medium can be used to direct a computer, other type of programmable data processing device, or other apparatus to operate in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture, which includes instructions for implementing the functions / actions specified in the flowcharts, sequence diagrams, and / or block diagrams. The computer program instructions can be provided to one or more processors of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions, when executed by one or more processors, cause a series of calculations to be performed to implement the functions and / or actions specified in the flowcharts, sequence diagrams, and / or block diagrams.

[0045] In certain alternative embodiments, the functions and / or actions specified in the flowcharts, sequence diagrams, and / or block diagrams may be reordered, processed sequentially, and / or processed simultaneously without departing from the scope of the present invention. Furthermore, any flowchart, sequence diagram, and / or block diagram may include more or fewer blocks than the schematic blocks consistent with embodiments of the present invention.

[0046] The method described above is used to manufacture integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer containing multiple unpackaged chips), as bare chips, or in a packaged form. The chips can be integrated with other chips, discrete circuit components, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0047] Terms modified by approximating language such as "about," "approximately," and "substantially" as used herein are not limited to the precise values ​​specified. The approximate language may correspond to the precision of the instrument used to measure the value and may represent + / - 10% of the stated value unless otherwise dependent on the precision of the instrument.

[0048] Terms such as "vertical" and "horizontal" are used herein as examples to establish a frame of reference and are not limiting. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0049] A feature that is “connected” or “coupled” to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to another feature if no intervening features are present. A feature may be “not directly connected” or “not directly coupled” to another feature if at least one intervening feature is present. A feature that is “on” or “in contact with” another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly “on” or “in direct contact with” another feature if no intervening features are present. A feature may not be “directly” “on” or “not directly in contact with” another feature if at least one intervening feature is present. Different features overlap if one feature extends over and covers a portion of another feature.

[0050] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A microstrip transmission line structure, characterized in that: The structure includes: a signal line comprising a capacitor segment, a first inductor segment, and a second inductor segment, wherein the capacitor segment is longitudinally arranged between the first inductor segment and the second inductor segment along the length of the signal line; Shielding cover; a plurality of circuit structures connected to the capacitor section of the signal line, each circuit structure extending from a portion of the signal line toward the shielding cover, and each circuit structure including a metal component disposed adjacent to the shielding cover; and Back-end process stacking, including multiple interlayer dielectric layers, The signal line, the shielding cover, and the plurality of circuit structures are located in the back-end process stack.

2. The structure according to claim 1, characterized in that A portion of one of the plurality of interlayer dielectric layers is disposed between the metal component of each circuit structure and the shielding cover.

3. The structure according to claim 2, characterized in that The metal component of each circuit structure is located in the plurality of interlayer dielectric layers.

4. The structure according to claim 1, wherein The signal line includes a longitudinal axis and a width along a first direction perpendicular to the longitudinal axis, and the width of the signal line is uniform along the longitudinal axis.

5. The structure according to claim 4, characterized in that The signal line has a length along a second direction parallel to the longitudinal axis, and the metal component of each circuit structure has a length smaller than the length of the signal line.

6. The structure according to claim 5, characterized in that The metal component of each circuit structure has a width equal to the width of the signal line.

7. The structure according to claim 1, wherein: The back-end process stack includes a first circuit layer and a second circuit layer. The shielding cover is located in the first circuit layer, and the metal components of each circuit structure are located in the second circuit layer.

8. The structure according to claim 7, characterized in that The second circuit layer is adjacent to the first circuit layer and is located in the back-end process stack.

9. The structure according to claim 8, characterized in that The second circuit layer includes one of the plurality of interlayer dielectric layers, and a portion of one of the plurality of interlayer dielectric layers is disposed between the metal component of each circuit structure and the shielding cover.

10. The structure according to claim 7, wherein: The back-end process stack includes a third circuit layer. The second circuit layer is located between the first circuit layer and the third circuit layer. The signal line is located in the third circuit layer.

11. The structure according to claim 1, wherein The back-end process stack includes a first circuit layer and a second circuit layer. The metal component of each circuit layer is located in the first circuit layer, and the signal line is located in the second circuit layer.

12. The structure according to claim 11, wherein The second circuit layer is adjacent to the first circuit layer and is located in the back-end process stack.

13. The structure according to claim 11, wherein Each circuit structure extends from the signal line through the plurality of interlayer dielectric layers to the metal component.

14. The structure according to claim 1, wherein The plurality of circuit structures are disconnected from each other and spaced apart along the length of the signal line.

15. A method for forming a microstrip transmission line structure, characterized in that: The method includes: forming shields in the back-end process stack; forming a signal line in the back-end process stack, the signal line comprising a capacitor segment, a first inductor segment, and a second inductor segment, wherein the capacitor segment is longitudinally arranged along the length of the signal line between the first inductor segment and the second inductor segment; forming a plurality of circuit structures connected to the capacitor segment of the signal line; and A plurality of interlayer dielectric layers are formed in the back-end process stack, Each circuit structure extends from the portion of the signal line toward the shielding cover, and each circuit structure includes a metal component disposed adjacent to the shielding cover.

16. The method according to claim 15, wherein The back-end process stack includes a first circuit layer and a second circuit layer. The shielding cover is formed in the first circuit layer, and the metal components of each circuit structure are formed in the second circuit layer.

17. The method according to claim 16, wherein The second circuit layer is formed adjacent to the first circuit layer in the back-end process stack.

18. The method according to claim 17, wherein The second circuit layer includes one of the plurality of interlayer dielectric layers, and a portion of one of the plurality of interlayer dielectric layers is disposed between the metal component of each circuit structure and the shielding cover.

19. The method according to claim 15, wherein The back-end process stack includes a first circuit layer and a second circuit layer, the metal components of each circuit layer are formed in the first circuit layer, the signal line is formed in the second circuit layer, and the second circuit layer is formed adjacent to the first circuit layer in the back-end process stack.

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