BD-Type Pulse Width Modulation Circuit for Class-D Amplifier and Modulation Method Therein

Abstract

A BD-type pulse-width modulation circuit for a class-D amplifier and a modulation method therein. The BD-type pulse-width modulation (PWM) circuit for a class-D amplifier is used to convert a pair of complementary input signals into a corresponding pair of output PWM signals. The BD-type pulse-width modulation circuit modulates a basic modulation signal with the pair of input signals to generate a basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common-mode level. The BD-type pulse-width modulation circuit modulates an offset modulation signal with the pair of input signals to generate an offset PWM signal, wherein the offset modulation signal and the basic modulation signal have a non-zero offset. The BD-type pulse-width modulation circuit selects the offset PWM signal or the reload PWM signal as the pair of output PWM signals according to the levels of the pair of input signals, and the reload PWM signal is related to the basic PWM signal.

Description

Technical Field

[0001] The present invention relates to a BD type pulse width modulation circuit for a class D amplifier, and particularly to a BD type pulse width modulation circuit having a common mode transition function to reduce power consumption. The present invention also relates to a modulation method for a class D amplifier. Background Art

[0002] Figure 1 The figure shows a schematic diagram of the operating waveforms of a typical class D amplifier using BD type modulation. In this known technology, a pair of complementary input signals Vep and Ven modulate a basic modulation signal (triangular wave VTRI) to generate basic pulse width modulation signals PS1p and PS1n, and accordingly drive a load. PS1d is the differential mode signal of the pulse width modulation signals PS1p and PS1n, and PS1c is the common mode signal of the pulse width modulation signals PS1p and PS1n. The advantage of BD type modulation is that it can reduce the requirements for the output filter. However, in the case of light load, the duty cycle of its common mode signal PSOc will be as high as 50%, resulting in the ripple current and idle current being at their maximum values, thus causing additional power consumption and reducing the conversion efficiency.

[0003] Figure 2 The figure shows a schematic diagram of the operating waveforms of another prior art class D amplifier using BD type modulation. This prior art uses an asymmetric driving method, and the adjusted output PWM signals (PSOp and PSOn) are asymmetric with each other, thereby reducing the ripple current of the common mode signal PSOc. However, this prior art is likely to cause distortion of the duty cycle of the differential mode signal PSOd, and further cause distortion of the output signal.

[0004] Figure 3 The figure shows a schematic diagram of the operating waveforms of another prior art class D amplifier using BD type modulation. This prior art performs non-linear level adjustment on the paired input signals Vep and Ven according to their levels, thereby reducing the duty cycle of the common mode signal PSOc during light load. However, due to the non-linear adjustment, this prior art is likely to cause distortion of the differential mode signal PSOd.

[0005] In view of this, the present invention aims at the deficiencies of the above prior art, and proposes a class D amplifier using BD type modulation with adaptable transition of the common mode voltage, which can effectively reduce the ripple current and idle current simultaneously, and maintain low distortion of the output signal. Summary of the Invention

[0006] In one aspect, the present invention provides a BD type pulse width modulation circuit for a class D amplifier, which is used to convert a pair of complementary input signals into a corresponding pair of output PWM signals based on an operation period. The BD type pulse width modulation circuit includes: a duty cycle adjustment circuit for generating a plurality of relay PWM signals, the plurality of relay PWM signals including a basic PWM signal, an offset PWM signal, and an overload PWM signal. Each relay PWM signal has a corresponding in-phase sub-signal, an anti-phase sub-signal, and a differential mode signal, where the differential mode signal is the difference between the in-phase sub-signal and the anti-phase sub-signal. The duty cycle adjustment circuit includes:

[0007] A basic comparison circuit for generating the basic PWM signal by modulating a basic modulation signal with the pair of input signals, where the pair of input signals and the basic modulation signal have the same common mode level; and an offset comparison circuit for generating the offset PWM signal by modulating an offset modulation signal with the pair of input signals, where the offset modulation signal has a non-zero offset from the basic modulation signal; a load detection circuit for determining whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal, and enabling a light load signal when the level of the pair of input signals is lower than the light load threshold; and an output selection circuit for selecting the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light load threshold, and selecting the overload PWM signal as the pair of output PWM signals when the level of the pair of input signals is not lower than the light load threshold, so that when the level of the pair of input signals is lower than the light load threshold, the root mean square power of the pair of output PWM signals is less than the root mean square power of the basic PWM signal; where the overload PWM signal is related to the basic PWM signal.

[0008] In one embodiment, the load detection circuit periodically determines, according to the operation period, whether both the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal had a pulse in the previous operation period, and enables the light load signal to indicate that the level of the pair of input signals is lower than the light load threshold.

[0009] In one embodiment, the overload PWM signal corresponds to the basic PWM signal; or the plurality of relay PWM signals further includes a single-sided PWM signal, and the overload PWM signal corresponds to the single-sided PWM signal; where the duty cycle adjustment circuit further includes a single-sided selection circuit for generating the in-phase sub-signal corresponding to the single-sided PWM signal according to the positive part of the differential mode signal corresponding to the basic PWM signal, and generating the anti-phase sub-signal corresponding to the single-sided PWM signal according to the negative part of the differential mode signal corresponding to the basic PWM signal.

[0010] In one embodiment, the overloaded PWM signal is optionally the single-sided PWM signal or the basic PWM signal.

[0011] In one embodiment, the pair of output PWM signals are used to control a drive stage circuit to drive both ends of a load in a pulse width modulation manner. The overloaded PWM signal is determined and configured to be the single-sided PWM signal or the basic PWM signal according to the power supply of the drive stage circuit, the level of the load, a temperature related to the class D amplifier, or an operating frequency, where the operating frequency corresponds to the operating cycle.

[0012] In one embodiment, the offset is related to the light load threshold.

[0013] In one embodiment, the basic modulation signal and the offset modulation signal are each configured as a triangular wave or a sawtooth wave, where the basic modulation signal and the offset modulation signal are synchronized with the operating cycle.

[0014] In one embodiment, the absolute value of the offset is less than 1 / 2 of the peak-to-peak value of the basic modulation signal.

[0015] In one embodiment, the basic comparison circuit includes: a first comparator for comparing a common-phase input signal of the pair of input signals with the basic modulation signal to generate the common-phase sub-signal of the basic PWM signal; and a second comparator for comparing the basic modulation signal with an inverting input signal of the pair of input signals to generate the inverting sub-signal of the basic PWM signal. The offset comparison circuit includes: a third comparator for comparing the common-phase input signal of the pair of input signals with the offset modulation signal to generate the common-phase sub-signal of the offset PWM signal; and a fourth comparator for comparing the offset modulation signal with the inverting input signal of the pair of input signals to generate the inverting sub-signal of the offset PWM signal.

[0016] In one embodiment, the load detection circuit includes: a first state circuit for triggering a common-phase pulse indication signal according to the pulse of the common-phase sub-signal of the offset PWM signal; a second state circuit for triggering an inverting pulse indication signal according to the pulse of the inverting sub-signal of the offset PWM signal; and a third state circuit for determining whether both the common-phase pulse indication signal and the inverting pulse indication signal are enabled according to a frequency signal switched at the operating cycle to trigger enabling the light load signal, thereby indicating that the level of the pair of input signals is lower than the light load threshold.

[0017] In one embodiment, the single-sided selection circuit includes: a first logic gate for performing an AND logic operation on the inverted signal of the inverted sub-signal of the basic PWM signal and the non-inverted sub-signal of the basic PWM signal to generate the non-inverted sub-signal of the single-sided PWM signal; and a second logic gate for performing an AND logic operation on the inverted signal of the non-inverted sub-signal of the basic PWM signal and the inverted sub-signal of the basic PWM signal to generate the inverted sub-signal of the single-sided PWM signal.

[0018] In another aspect, the present invention provides a BD-type pulse width modulation method for a class D amplifier, which is used to convert a pair of complementary input signals into a corresponding pair of output PWM signals based on an operation period. The BD-type pulse width modulation method includes: S1: generating a plurality of relay PWM signals, the plurality of relay PWM signals including a basic PWM signal, an offset PWM signal, and an overload PWM signal, wherein each relay PWM signal has a corresponding non-inverted sub-signal, an inverted sub-signal, and a differential mode signal, wherein the differential mode signal is the difference between the non-inverted sub-signal and the inverted sub-signal, and the step of generating the plurality of relay PWM signals includes: S11: modulating a basic modulation signal with the pair of input signals to generate the basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common mode level; and S12: modulating an offset modulation signal with the pair of input signals to generate the offset PWM signal, wherein the offset modulation signal and the basic modulation signal have a non-zero offset; S2: judging whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal; and S3: when the level of the pair of input signals is lower than the light load threshold, selecting the offset PWM signal as the pair of output PWM signals, and when the level of the pair of input signals is not lower than the light load threshold, selecting the overload PWM signal as the pair of output PWM signals, so that when the level of the pair of input signals is lower than the light load threshold, the root mean square power of the pair of output PWM signals is less than the root mean square power of the basic PWM signal; wherein the overload PWM signal is related to the basic PWM signal.

[0019] In one embodiment, the step of judging whether the level of the pair of input signals is lower than the light load threshold includes: judging periodically according to an operation period whether both the non-inverted sub-signal and the inverted sub-signal corresponding to the offset PWM signal have a pulse in the previous operation period to judge whether the level of the pair of input signals is lower than the light load threshold.

[0020] In one embodiment, the overloaded PWM signal corresponds to the basic PWM signal; or the plurality of relay PWM signals further includes a single-sided PWM signal, and the overloaded PWM signal corresponds to the single-sided PWM signal; wherein the step of generating the plurality of relay PWM signals further includes: generating the in-phase sub-signal corresponding to the single-sided PWM signal according to the positive value portion of the differential-mode signal corresponding to the basic PWM signal, and generating the anti-phase sub-signal corresponding to the single-sided PWM signal according to the negative value portion of the differential-mode signal corresponding to the basic PWM signal.

[0021] In one embodiment, the pair of output PWM signals is used to control a drive stage circuit to drive both ends of a load in a pulse width modulation manner, and the overloaded PWM signal is determined and configured to be the single-sided PWM signal or the basic PWM signal according to the power supply of the drive stage circuit, the level of the load, a temperature related to the class D amplifier, or an operating frequency, wherein the operating frequency corresponds to the operating cycle.

[0022] In one embodiment, the step of generating the basic PWM signal includes: comparing a in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and comparing the basic modulation signal with an anti-phase input signal of the pair of input signals to generate the anti-phase sub-signal of the basic PWM signal; the step of generating the offset PWM signal includes: comparing the in-phase input signal of the pair of input signals with the offset modulation signal to generate the in-phase sub-signal of the offset PWM signal; and comparing the offset modulation signal with the anti-phase input signal of the pair of input signals to generate the anti-phase sub-signal of the offset PWM signal.

[0023] The following will be described in detail through specific embodiments, and it will be easier to understand the purpose, technical content, features and achieved effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Showing an operational waveform schematic diagram of a typical class D amplifier using BD modulation.

[0025] Figure 2 Showing an operational waveform schematic diagram of a prior art class D amplifier using BD modulation.

[0026] Figure 3 Showing an operational waveform schematic diagram of a prior art class D amplifier using BD modulation.

[0027] Figure 4 Showing a signal waveform schematic diagram of an embodiment of a class D amplifier according to the present invention.

[0028] Figure 5Shows a schematic circuit diagram of an embodiment of a BD-type pulse width modulation circuit for a class D amplifier according to the present invention.

[0029] Figure 6 Shows a schematic diagram of signal waveforms of an embodiment of a class D amplifier according to the present invention.

[0030] Figure 7 Shows a schematic circuit diagram of another embodiment of a BD-type pulse width modulation circuit for a class D amplifier according to the present invention.

[0031] Figure 8 Shows a schematic circuit diagram of yet another embodiment of a BD-type pulse width modulation circuit for a class D amplifier according to the present invention.

[0032] Description of symbols in the figure

[0033] 100: Duty cycle adjustment circuit

[0034] 1005: Class D amplifier

[0035] 110: Basic comparison circuit

[0036] 111, 112: Comparators

[0037] 120: Offset comparison circuit

[0038] 121, 122: Comparators

[0039] 20: Driver circuit

[0040] 200: Load detection circuit

[0041] 30: Load

[0042] 305, 307, 308: Output selection circuit

[0043] 315, 317, 318, 325, 327, 328, 338, 348: Multiplexers

[0044] 50: BD-type pulse width modulation circuit

[0045] CKs: Frequency signal

[0046] Fs: Operating frequency

[0047] ILD: Current level

[0048] PS1, PS1p, PS1n: Basic PWM signals

[0049] PS2, PS2p, PS2n: Offset PWM signals

[0050] PS3, PS3p, PS3n: Overload PWM signals

[0051] PS1d, PS2d, PS4d, PSOd: Differential-mode signals

[0052] PS1c, PS2c, PS4c, PSOc: Common-mode signals

[0053] PS1p and PS1n: Basic PWM signals

[0054] PSO, PSOp, PSOn: Output PWM signals

[0055] PVDD: Power supply

[0056] SEL: Selection signal

[0057] Sinp: In-phase pulse indication signal

[0058] Sinv: Anti-phase pulse indication signal

[0059] SLL: Light load signal

[0060] Temp: Temperature

[0061] Ts, T1 to T7: Operating periods

[0062] Vcm1, Vcm2: Common-mode levels

[0063] Vep, Ven: Input signals

[0064] Vos: Offset

[0065] VTR1: Basic modulation signal

[0066] VTR2: Offset modulation signal

[0067] VTRI: Basic modulation signal Detailed implementation manners

[0068] The drawings in the present invention are all schematic, mainly intended to show the coupling relationships between various circuits and the relationships between various signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn according to scale.

[0069] Please refer to Figure 4 and Figure 5 , Figure 4 showing a schematic diagram of signal waveforms of an embodiment of a class D amplifier according to the present invention, Figure 5 showing a schematic circuit diagram of an embodiment of a BD-type pulse width modulation circuit for a class D amplifier according to the present invention.

[0070] Such as Figure 4 and Figure 5As shown, the BD type pulse width modulation circuit 50 is used in the class D amplifier 1005. The BD type pulse width modulation circuit 50 is configured to convert a pair of complementary input signals Vep and Ven into a corresponding pair of output pulse width modulation (PWM) signals PSOp and PSOn, and is used to control the driving circuit 20 to drive both ends of the load 30 (such as a speaker) in a pulse width modulation manner. The BD type pulse width modulation circuit 50 includes a duty cycle adjustment circuit 100, a load detection circuit 200, and an output selection circuit 305.

[0071] The duty cycle adjustment circuit 100 is configured to generate a plurality of intermediate PWM signals, which include a basic PWM signal PS1, an offset PWM signal PS2, and a heavy load PWM signal PS3. Each intermediate PWM signal has a corresponding in-phase sub-signal, an anti-phase sub-signal, a differential mode signal, and a common mode signal. The differential mode signal is the difference between the in-phase sub-signal and the anti-phase sub-signal, and the common mode signal is the average value of the in-phase sub-signal and the anti-phase sub-signal.

[0072] According to an embodiment of the present invention, as Figure 5 shown, the duty cycle adjustment circuit 100 includes a basic comparison circuit 110 and an offset comparison circuit 120.

[0073] The basic comparison circuit 110 is configured to generate a basic PWM signal PS1 by modulating a basic modulation signal VTR1 with the input signals Vep and Ven. As Figure 4 shown, the input signals Vep and Ven and the basic modulation signal VTR1 have the same common mode level Vcm1, which particularly refers to the common mode voltage here. The offset comparison circuit 120 is configured to generate an offset PWM signal PS2 by modulating an offset modulation signal VTR2 with the input signals Vep and Ven. The offset modulation signal VTR2 has a non-zero offset Vos from the basic modulation signal VTR1. In other words, the common mode level Vcm2 of the offset modulation signal VTR2 also has an offset Vos from the common mode level Vcm1 of the input signals Vep and Ven. In Figure 4 the embodiment, the offset Vos is greater than 0. That is, the level of the offset modulation signal VTR2 is higher than the level of the basic modulation signal VTR1. However, this is not intended to limit the present invention. In other embodiments, the offset Vos can also be less than 0. In one embodiment, the absolute value of the offset Vos is less than 1 / 2 of the peak-to-peak value Vp-p of the basic modulation signal VTR1.

[0074] The load detection circuit 200 is configured to periodically determine, according to the operation period Ts of the frequency signal CKs, whether the in-phase sub-signal PS2p and the anti-phase sub-signal PS2n corresponding to the offset PWM signal PS2 both have a pulse within the previous operation period Ts, so as to enable the light load signal SLL, indicating that the levels of the input signals Vep and Ven are lower than a light load threshold. In an embodiment, the light load threshold is related to the offset Vos. Specifically, as Figure 4 shown, the in-phase sub-signal PS2p and the anti-phase sub-signal PS2n corresponding to the offset PWM signal PS2 both have a pulse within the operation periods T3 to T5. Therefore, the light load signal SLL is enabled within the operation periods T4 to T6.

[0075] It should be noted that the levels of the input signals Vep and Ven being lower than a light load threshold herein particularly refer to the absolute values of the AC levels of the input signals Vep and Ven. In addition, it should be noted that the aforementioned light load may refer to a lower level of the input signal or may also mean a lower power of the input signal or the output signal.

[0076] The output selection circuit 305 is configured to select the offset PWM signal PS2 as the output PWM signals PSOp and PSON when the light load signal SLL is enabled (i.e., during light load), and select the heavy load PWM signal PS3 as the output PWM signals PSOp and PSON when the light load signal SLL is disabled (i.e., during heavy load), such that when the levels of the input signals Vep and Ven are lower than the light load threshold, the root mean square power of the output PWM signal is less than the root mean square power corresponding to the basic PWM signal PS1. The heavy load PWM signal PS3 is related to the basic PWM signal PS1 and has various implementation manners, which are described in detail below.

[0077] Please continue to refer to Figure 4 and Figure 5 , in an embodiment, the heavy load PWM signal PS3 corresponds to the basic PWM signal PS1. When the light load signal SLL is disabled (indicating heavy load, that is, when the levels of the input signals Vep and Ven are higher than the light load threshold), the output selection circuit 305 selects the basic PWM signal PS1 as the output PWM signal PSO (PSOp, PSON).

[0078] Specifically, in this embodiment, the output selection circuit 305 includes multiplexers 315 and 325, which are configured to select the basic PWM signal PS1 during heavy load and select the offset PWM signal PS2 as the output PWM signal PSO during light load according to the light load signal SLL.

[0079] Please continue to refer to Figure 5, the basic comparison circuit 110 includes a first comparator 111 and a second comparator 112. The first comparator 111 is used to compare the in-phase input signal Vep with the basic modulation signal VTR1 to generate an in-phase sub-signal PS1p of the basic PWM signal PS1. The second comparator 112 is used to compare the basic modulation signal VTR1 with the anti-phase input signal Ven to generate an anti-phase sub-signal PS1n of the basic PWM signal PS1.

[0080] The offset comparison circuit 120 includes a third comparator 121 and a fourth comparator 122. The third comparator 121 is used to compare the in-phase input signal Vep with the offset modulation signal VTR2 to generate an in-phase sub-signal PS2p of the offset PWM signal PS2. The fourth comparator 122 is used to compare the offset modulation signal VTR2 with the anti-phase input signal Ven to generate an anti-phase sub-signal PS2n of the offset PWM signal PS2. It should be noted that in the above embodiments, the basic modulation signal VTR1 and the offset modulation signal VTR2 are compared with the input signal using their inverted signals.

[0081] The load detection circuit 200 includes a first state circuit (such as but not limited to a flip-flop) 210, a second flip-flop 220, and a third flip-flop 230. The first flip-flop 210 is used to trigger an in-phase pulse indication signal Sinp according to the pulse of the in-phase sub-signal PS2p of the offset PWM signal PS2. The second flip-flop 220 is used to trigger an anti-phase pulse indication signal Sinv according to the pulse of the anti-phase sub-signal PS2n of the offset PWM signal PS2. The third flip-flop 230 is used to determine whether both the in-phase pulse indication signal Sinp and the anti-phase pulse indication signal Sinv are enabled according to a frequency signal CKs switched with an operation period Ts, so as to trigger an enabled light load signal SLL, thereby indicating whether the levels of the input signals Vep and Ven are lower than the light load threshold.

[0082] It should be noted that the basic modulation signal VTR1 and the offset modulation signal VTR2 in the foregoing embodiments are both configured as triangular waves. However, this is not intended to limit the present invention. In other embodiments, the basic modulation signal VTR1 and the offset modulation signal VTR2 may also be configured as sawtooth waves, for example. In addition, as Figure 4 shown, the period of the triangular wave (or sawtooth wave) is synchronized with the operation period Ts.

[0083] Please also refer to Figure 6 and Figure 7 , Figure 6 show a signal waveform schematic diagram of an embodiment of a class D amplifier according to the present invention, Figure 7 show a circuit schematic diagram of an embodiment of a BD type pulse width modulation circuit (BD type pulse width modulation circuit 70) for a class D amplifier according to the present invention.

[0084] In this embodiment, the multiple relay PWM signals further include a single-sided PWM signal PS4, and the duty cycle adjustment circuit 100 further includes a single-sided selection circuit 400, which is used to generate the in-phase sub-signal PS4p corresponding to the single-sided PWM signal PS4 according to the positive part of the differential-mode signal PS1d corresponding to the basic PWM signal PS1, and generate the anti-phase sub-signal PS4n corresponding to the single-sided PWM signal PS4 according to the negative part (the absolute value in this embodiment) of the differential-mode signal PS1d corresponding to the basic PWM signal PS1.

[0085] As Figure 6 shown in Figure 7 In this embodiment, the heavy-load PWM signal PS3 corresponds to the single-sided PWM signal PS4 (PS4p, PS4n). When the light-load signal SLL is disabled (indicating heavy load, that is, when the levels of the input signals Vep and Ven are higher than the light-load threshold), the output selection circuit 305 selects the single-sided PWM signal PS4 (PS4p, PS4n) as the output PWM signal PSO (PSOp, PSOn).

[0086] Specifically, the output selection circuit 307 includes multiplexers 317 and 327, which are used to select the single-sided PWM signal PS4 during heavy load according to the light-load signal SLL, and select the offset PWM signal PS2 as the output PWM signal PSO during light load.

[0087] In one embodiment, the single-sided selection circuit 400 includes a first AND gate 410 and a second AND gate 420. The first AND gate 410 is used to perform an AND logic operation on the anti-phase signal of the anti-phase sub-signal PS1n of the basic PWM signal PS1 and the in-phase sub-signal PS1p of the basic PWM signal PS1 to generate the in-phase sub-signal PS4p of the single-sided PWM signal PS4. The second AND gate 420 is used to perform an AND logic operation on the anti-phase signal of the in-phase sub-signal PS1p of the basic PWM signal PS1 and the anti-phase sub-signal PS1n of the basic PWM signal PS1 to generate the anti-phase sub-signal PS4n of the single-sided PWM signal PS4.

[0088] Please refer to Figure 4 、 Figure 6 and Figure 8 simultaneously. Figure 8Show a schematic circuit diagram of another embodiment of the BD type pulse width modulation circuit for a class D amplifier according to the present invention. The BD type pulse width modulation circuit 80 is similar to the aforementioned BD type pulse width modulation circuits 50 and 70, the difference being that the output selection circuit 308 in the BD type pulse width modulation circuit 80 can select the single-sided PWM signal PS4 or the basic PWM signal PS1 as the heavy load PWM signal PS3 according to the selection signal SEL. Specifically, the output selection circuit 308 includes multiplexers 318, 328, 338 and 348. The multiplexers 318 and 328 are used to select the heavy load PWM signal PS3 or the offset PWM signal PS2 as the output PWM signal PSO according to the light load signal SLL. The multiplexers 338 and 348 are used to select the single-sided PWM signal PS4 or the basic PWM signal PS1 as the heavy load PWM signal PS3 according to the selection signal SEL.

[0089] In one embodiment, the output selection circuit 308 may further include a selection control circuit 358 for determining the selection signal SEL according to the power supply PVDD of the driving circuit 20, the level of the current or power of the load 30 (ILD), a temperature Temp related to the class D amplifier, or the operating frequency Fs (for example, by receiving a frequency signal CKs), where the operating frequency Fs = 1 / Ts.

[0090] In summary, the BD type pulse width modulation circuits (such as 50, 60, 70) of the present invention can adaptively hop according to the level of the input signal to switch or select the PWM signal (heavy load PWM signal PS3 or offset PWM signal PS2) modulated by the modulation signal (such as VTR1, VTR2) with different common mode voltages. Thus, when in light load, the duty cycle of the common mode signal PSOc of the output PWM signal PSO can be kept away from 50%, thereby effectively reducing the ripple current and the idle current, and maintaining low output signal distortion.

[0091] In addition, from Figure 4 and Figure 6 it can be known that according to the present invention, the average voltage and the switching frequency of the differential mode signal PSOd of the output PWM signal PSO can be kept unchanged.

[0092] In the foregoing embodiments, the description of the embodiments is made with the offset Vos greater than 0 (such as Figure 4 , Figure 6) Its common-mode voltage can quickly transition and shift, enabling the duty cycle of the common-mode signal PSOc during light load to be less than 50%. On the other hand, in other embodiments, when the offset Vos is less than 0 for modulation, the common-mode voltage transition is performed according to the aforementioned principle, enabling the duty cycle of the common-mode signal PSOc during light load to be higher than 50%. During light load, regardless of whether the duty cycle of the common-mode signal PSOc is higher or lower than 50%, as long as it is far from 50%, the ripple current and idle current can be reduced.

[0093] In addition, according to the present invention, the number of offset PWM signals is not limited. In other embodiments, multiple offset PWM signals can also be configured, which can further reduce distortion.

[0094] The present invention has been described above with respect to the preferred embodiments. However, the above description is only for making those skilled in the art easily understand the content of the present invention and is not used to limit the broadest scope of rights of the present invention. Each of the described embodiments is not limited to being applied alone and can also be applied in combination. For example, two or more embodiments can be combined, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or calculating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, but also includes, when necessary, converting the signal between voltage and current, current and voltage, and / or ratio conversion, etc., and then processing or calculating according to the converted signal to generate a certain output result. It can be seen that in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A BD-type pulse width modulation circuit for a class D amplifier, which is used to convert a pair of complementary input signals into a corresponding pair of output PWM signals based on an operating cycle. The BD-type pulse width modulation circuit includes: A duty cycle adjustment circuit is used to generate a plurality of relay PWM signals, and the plurality of relay PWM signals include a basic PWM signal, an offset PWM signal, and an overload PWM signal, wherein, Each relay PWM signal has a corresponding in-phase sub-signal, an anti-phase sub-signal, and a differential-mode signal. Among them, the differential-mode signal is the difference between the in-phase sub-signal and the anti-phase sub-signal. The duty cycle adjustment circuit includes: A basic comparison circuit, which is used to modulate a basic modulation signal through the pair of input signals to generate the basic PWM signal. Among them, the pair of input signals and the basic modulation signal have the same common-mode level; and An offset comparison circuit, which is used to modulate an offset modulation signal through the pair of input signals to generate the offset PWM signal. Among them, the offset modulation signal and the basic modulation signal have a non-zero offset; A load detection circuit, which is used to judge whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal. Among them, when the level of the pair of input signals is lower than the light load threshold, a light load signal is enabled; and An output selection circuit, which is used to select the offset PWM signal as the pair of output PWM signals when the level of the pair of input signals is lower than the light load threshold, and select the heavy load PWM signal as the pair of output PWM signals when the level of the pair of input signals is not lower than the light load threshold, so that when the level of the pair of input signals is lower than the light load threshold, the root mean square power of the pair of output PWM signals is less than the root mean square power of the basic PWM signal; Among them, the heavy load PWM signal is related to the basic PWM signal.

2. The BD type pulse width modulation circuit according to claim 1, wherein The load detection circuit periodically judges according to the operating cycle whether both the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal have a pulse in the previous operating cycle, and enables the light load signal to indicate that the level of the pair of input signals is lower than the light load threshold.

3. The BD-type pulse width modulation circuit according to claim 1, wherein The heavy load PWM signal corresponds to the basic PWM signal; or The plurality of relay PWM signals further include a single-sided PWM signal, and the heavy load PWM signal corresponds to the single-sided PWM signal; Among them, the duty cycle adjustment circuit further includes a single-sided selection circuit, which is used to generate the in-phase sub-signal corresponding to the single-sided PWM signal according to the positive part of the differential-mode signal corresponding to the basic PWM signal, and generate the anti-phase sub-signal corresponding to the single-sided PWM signal according to the negative part of the differential-mode signal corresponding to the basic PWM signal.

4. The BD type pulse width modulation circuit according to claim 3, wherein, The heavy load PWM signal can be optionally the single-sided PWM signal or the basic PWM signal.

5. The BD type pulse width modulation circuit according to claim 4, wherein, The pair of output PWM signals are used to control a driving stage circuit to drive both ends of a load in a pulse width modulation manner. The heavy load PWM signal is judged and selected to be configured as the single-sided PWM signal or the basic PWM signal according to the power supply of the driving stage circuit, the level of the load, a temperature related to the class D amplifier, or an operating frequency. Among them, the operating frequency corresponds to the operating cycle.

6. The BD type pulse width modulation circuit according to claim 1, wherein, The offset is related to the light load threshold.

7. The BD type pulse width modulation circuit according to claim 1, wherein, The basic modulation signal and the offset modulation signal are each configured as a triangular wave or a sawtooth wave, wherein the basic modulation signal and the offset modulation signal are synchronized with the operation period.

8. The BD type pulse width modulation circuit according to claim 7, wherein, The absolute value of the offset is less than 1 / 2 of the peak-to-peak value of the basic modulation signal.

9. The BD type pulse width modulation circuit according to claim 1, wherein The basic comparison circuit includes: A first comparator for comparing a common-phase input signal of the pair of input signals with the basic modulation signal to generate the common-phase sub-signal of the basic PWM signal; and A second comparator for comparing the basic modulation signal with an inverting input signal of the pair of input signals to generate the inverting sub-signal of the basic PWM signal; The offset comparison circuit includes: A third comparator for comparing the common-phase input signal of the pair of input signals with the offset modulation signal to generate the common-phase sub-signal of the offset PWM signal; and A fourth comparator for comparing the offset modulation signal with the inverting input signal of the pair of input signals to generate the inverting sub-signal of the offset PWM signal.

10. The BD type pulse width modulation circuit according to claim 2, wherein, The load detection circuit includes: A first state circuit for triggering a common-phase pulse indication signal according to the pulse of the common-phase sub-signal of the offset PWM signal; A second state circuit for triggering an inverting pulse indication signal according to the pulse of the inverting sub-signal of the offset PWM signal; and A third state circuit for judging whether both the common-phase pulse indication signal and the inverting pulse indication signal are enabled according to a frequency signal switched with the operation period to trigger enabling the light load signal, thereby indicating that the level of the pair of input signals is lower than the light load threshold.

11. The BD type pulse width modulation circuit according to claim 3, wherein, The single-sided selection circuit includes: A first logic gate for performing an AND logic operation on the inverted signal of the inverting sub-signal of the basic PWM signal and the common-phase sub-signal of the basic PWM signal to generate the common-phase sub-signal of the single-sided PWM signal; and A second logic gate for performing an AND logic operation on the inverted signal of the common-phase sub-signal of the basic PWM signal and the inverting sub-signal of the basic PWM signal to generate the inverting sub-signal of the single-sided PWM signal.

12. A BD type pulse width modulation method for a class D amplifier, used to convert a pair of complementary input signals into a corresponding pair of output PWM signals based on an operation period, the BD type pulse width modulation method includes: S1: Generate a plurality of relay PWM signals, the plurality of relay PWM signals including a basic PWM signal, an offset PWM signal, and an overload PWM signal, wherein, Each intermediate PWM signal has a corresponding common-phase sub-signal, an inverting sub-signal and a differential mode signal, wherein the differential mode signal is the difference between the common-phase sub-signal and the inverting sub-signal, and the step of generating the plurality of intermediate PWM signals includes: S11: Modulating a basic modulation signal with the pair of input signals to generate the basic PWM signal, wherein the pair of input signals and the basic modulation signal have the same common-mode level; and S12: Modulating an offset modulation signal with the pair of input signals to generate the offset PWM signal, wherein the offset modulation signal and the basic modulation signal have a non-zero offset; S2: Judging whether the level of the pair of input signals is lower than a light load threshold according to the offset PWM signal; and S3: When the levels of the pair of input signals are lower than the light load threshold, select the offset PWM signal as the pair of output PWM signals; and when the levels of the pair of input signals are not lower than the light load threshold, select the heavy load PWM signal as the pair of output PWM signals, so that when the levels of the pair of input signals are lower than the light load threshold, the root mean square power of the pair of output PWM signals is less than the root mean square power of the basic PWM signal; Wherein, the heavy load PWM signal is related to the basic PWM signal.

13. The BD type pulse width modulation method according to claim 12, wherein, The step of determining whether the levels of the pair of input signals are lower than the light load threshold includes: periodically determining according to the operation period whether the in-phase sub-signal and the anti-phase sub-signal corresponding to the offset PWM signal both have a pulse in the previous operation period to determine whether the levels of the pair of input signals are lower than the light load threshold.

14. The BD type pulse width modulation method according to claim 12, wherein, the heavy load PWM signal corresponds to the basic PWM signal; or the plurality of relay PWM signals further includes a single-sided PWM signal, and the heavy load PWM signal corresponds to the single-sided PWM signal; Wherein, the step of generating the plurality of relay PWM signals further includes: generating the in-phase sub-signal corresponding to the single-sided PWM signal according to the positive value part of the differential mode signal corresponding to the basic PWM signal, and generating the anti-phase sub-signal corresponding to the single-sided PWM signal according to the negative value part of the differential mode signal corresponding to the basic PWM signal.

15. The BD type pulse width modulation method according to claim 14, wherein, The heavy load PWM signal is optionally the single-sided PWM signal or the basic PWM signal.

16. The BD type pulse width modulation method according to claim 15, wherein, The pair of output PWM signals is used to control a driving stage circuit to drive both ends of a load in a pulse width modulation manner. The heavy load PWM signal is judged and selected to be configured as the single-sided PWM signal or the basic PWM signal according to the power supply of the driving stage circuit, the level of the load, a temperature related to the class D amplifier, or an operation frequency, wherein the operation frequency corresponds to the operation period.

17. The BD type pulse width modulation method according to claim 12, wherein, The offset is related to the light load threshold.

18. The BD type pulse width modulation method according to claim 12, wherein, The basic modulation signal and the offset modulation signal are each configured as a triangular wave or a sawtooth wave, wherein the basic modulation signal and the offset modulation signal are synchronized with the operation period.

19. The BD type pulse width modulation method according to claim 18, wherein, The absolute value of the offset is less than 1 / 2 of the peak-to-peak value of the basic modulation signal.

20. The BD type pulse width modulation method according to claim 12, wherein, The step of generating the basic PWM signal includes: comparing an in-phase input signal of the pair of input signals with the basic modulation signal to generate the in-phase sub-signal of the basic PWM signal; and comparing the basic modulation signal with an anti-phase input signal of the pair of input signals to generate the anti-phase sub-signal of the basic PWM signal; The step of generating the offset PWM signal includes: comparing the in-phase input signal of the pair of input signals with the offset modulation signal to generate the in-phase sub-signal of the offset PWM signal; and comparing the offset modulation signal with the anti-phase input signal of the pair of input signals to generate the anti-phase sub-signal of the offset PWM signal.

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