Isolation amplifier and abnormal state detection device

Abstract

The present application relates to an isolated amplifier and an abnormal state detection device. The isolated amplifier is provided with: a primary circuit provided with an analog-digital conversion circuit that converts an input signal imparted from a device of a detection object into a digital signal and an encoder that encodes the output of the analog-digital conversion circuit and outputs it; an abnormality detection circuit provided in the primary circuit, which detects an abnormality in the input signal and generates a detection signal; an isolation section that transmits the output of the encoder and the detection signal to a secondary circuit in a state in which the primary circuit and the secondary circuit are insulated; an output circuit provided in the secondary circuit, which receives the output of the encoder and the detection signal transmitted by the isolation section, includes a decoder that performs decoding processing corresponding to the encoding processing, and generates an output signal corresponding to the input signal; and an abnormal input detection output circuit provided in the secondary circuit, which causes the output signal of the output circuit to change in a prescribed rule as an output signal of the secondary circuit based on the detection signal.

Description

[0001] This application has priority to Japanese Patent Application No. 2021-50691 (Filing date: March 24, 2021). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to an isolation amplifier and an abnormal state detection device. BACKGROUND

[0003] Conventionally, an isolation amplifier is used as a device that takes into account both electrical insulation and signal transmission. Isolation amplifiers are widely used in various applications in the fields of industry, communication, household, and vehicle-mounted, and are used, for example, for data transmission between a motor driven with a large power supply voltage and a large current and an MPU (microprocessor unit) that controls the motor. For example, isolation amplifiers are used for current sensors, voltage sensors, and the like that detect a high voltage and a large current of a circuit of a detection object.

[0004] However, sometimes a circuit of a detection object generates an abnormality and an excessively large input is applied to the isolation amplifier. In this case, from the viewpoint of protecting the entire system, the isolation amplifier needs to transmit the generation of the abnormality in a short time. However, the transmission speed of the data transmission path of the isolation amplifier is relatively low, and there is a disadvantage that transmission of an abnormal state such as an excessively large input takes a relatively long time.

[0005] Therefore, a method of providing a transmission path different from the usual data transmission path of the isolation amplifier to transmit an abnormal state can be considered. However, in this case, a dedicated pin for the new transmission path is required. SUMMARY

[0006] Embodiments provide an isolation amplifier and an abnormal state detection device that can transmit the generation of an abnormal state at high speed.

[0007] The isolated amplifier of the embodiment includes: a primary circuit including an analog-digital conversion circuit that converts an input signal given from a device to be detected into a digital signal, and an encoder that encodes the output of the analog-digital conversion circuit and outputs the encoded signal; an abnormality detection circuit provided in the primary circuit, which detects an abnormality in the input signal and generates a detection signal; an isolation section that transmits the output of the encoder and the detection signal to a secondary circuit while insulating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, which receives the output of the encoder and the detection signal transmitted by the isolation section, includes a decoder that performs decoding corresponding to the encoding, and generates an output signal corresponding to the input signal; and an abnormality input detection output circuit provided in the secondary circuit, which causes the output signal of the output circuit to change as a predetermined rule based on the detection signal, and outputs the changed signal as an output signal of the secondary circuit. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram showing a semiconductor integrated circuit according to the first embodiment of the present application.

[0009] Figure 2 is a block diagram showing a specific configuration example of the isolation section 30.

[0010] Figure 3 is a block diagram showing a specific configuration example of the isolation section 30.

[0011] Figure 4 is a block diagram showing a specific configuration example of the isolation section 30.

[0012] Figure 5 is a circuit diagram showing a specific configuration example of the differential single-phase conversion circuit 50 in Figure 1 .

[0013] Figure 6 is a circuit diagram showing a specific configuration example of the LPF 23 and the abnormality input detection output circuit 26.

[0014] Figure 7 is a graph showing waveforms of input and output and the like, in which the horizontal axis represents time and the vertical axis represents voltage.

[0015] Figure 8 is a circuit diagram showing a modification example.

[0016] Figure 9 is a block diagram showing a semiconductor integrated circuit according to the second embodiment of the present application.

[0017] Figure 10 is a circuit diagram showing a specific configuration example of the abnormality input detection output circuit 27 of Figure 9 .

[0018] Figure 11 is a waveform chart showing input and output, etc. with time as the horizontal axis and voltage as the vertical axis.

[0019] Figure 12 is a block diagram showing the third embodiment of the present application.

[0020] Figure 13 is a circuit diagram showing a specific configuration of the mixer 62 and the external circuit 80 in Figure 12

[0021] Figure 14 is a timing chart for explaining the operation of the second embodiment.

[0022] Figure 15 is a block diagram showing a specific configuration of the mixer employed in the fourth embodiment of the present application.

[0023] Figure 16 is a timing chart for explaining the operation of the fourth embodiment.

[0024] Figure 17 is a block diagram showing a specific configuration of the mixer employed in the fifth embodiment of the present application.

[0025] Figure 18 is a timing chart for explaining the operation of the fifth embodiment.

[0026] Figure 19 is a block diagram showing a specific configuration of the mixer employed in the sixth embodiment of the present application.

[0027] Figure 20 is a timing chart for explaining the operation of the sixth embodiment.

[0028] Figure 21 is a block diagram showing a specific configuration of the mixer employed in the seventh embodiment of the present application.

[0029] Figure 22 is a timing chart for explaining the operation of the seventh embodiment.

[0030] Figure 23 is a block diagram showing a specific configuration of the mixer employed in the eighth embodiment of the present application.

[0031] Figure 24 is a circuit diagram showing a specific configuration of the pulse detector 87 in Figure 23

[0032] Figure 25 is a timing chart for explaining the generation of the clock MCLK and the output data MDAT in the isolation amplifier 8. ​​

[0033] Figure 26 is a timing chart for explaining the operation of the pulse detector 87.

[0034] Figure 27 is a diagram corresponding to the isolation amplifier of the analog output.

[0035] Figure 28 is a block diagram showing the 9th embodiment.

[0036] Figure 29 is a block diagram showing the 10th embodiment.

[0037] Figure 30 is a block diagram showing a modification. DETAILED DESCRIPTION

[0038] Hereinafter, an embodiment of the present application will be described in detail with reference to the accompanying drawings.

[0039] (1st Embodiment)

[0040] Figure 1 is a block diagram showing a semiconductor integrated circuit of the 1st embodiment of the present application. Figure 1 The semiconductor integrated circuit of the 1st embodiment is configured as an isolation amplifier. In the 1st embodiment, the output data is caused to change in accordance with the generation of an anomaly by a normal data transmission path of the isolation amplifier, whereby the generation of an anomaly can be transmitted at high speed.

[0041] In addition, in the 1st embodiment, as a detection object, the motor 55 or the motor drive circuit 56 that drives the motor 55 is assumed, and an example in which the voltage, the current, and the like generated in them are detected is described, but the detection object is not limited thereto. For example, in a case where a generator is assumed as a detection object, and a power anomaly of a sensor against vibration, heat, and the like generated in the generator is detected, or the like, the 1st embodiment can also be applied. Figure 1

[0042] In the 1st embodiment, the isolation amplifier 1 is provided with a primary circuit 10, a secondary circuit 20, and an isolation section 30. The primary circuit 10 outputs a digital value corresponding to the voltage, the current, and the like generated in a detection object such as a motor to the isolation section 30. The isolation section 30 transmits the output of the primary circuit 10 to the secondary circuit 20 while electrically insulating the primary circuit 10 from the secondary circuit 20. The secondary circuit 20 receives the digital value transmitted via the isolation section 30, and restores the value of the voltage, the current, and the like generated in the detection object. In addition, the output of the isolation amplifier 1 is supplied to a control circuit 52 configured of an MCU (Micro Controller Unit) or the like via a differential single-phase conversion circuit 50 and an anomaly detection circuit 51, whereby the state of the detection object can be grasped in the control circuit 52. Figure 1

[0043] ​​The primary circuit 10 includes, for example, a ΔΣ ADC 11, an encoder 12, a clock generator 13, a reference voltage generator 14, and a comparator 15. The primary circuit 10 and the secondary circuit 20 are supplied with independent power supplies. In Figure 1 In the present embodiment, a power supply voltage VDD1 and a ground voltage GND1 are supplied to the primary circuit 10, and a power supply voltage VDD2 and a ground voltage GND2 are supplied to the secondary circuit 20.

[0044] A signal corresponding to a voltage value, a current value, or the like generated in a detection object is input to the primary circuit 10 as a differential input VIN+. In the differential input VIN, a same-phase component of a prescribed same-phase level is included. These differential inputs VIN are input to the ΔΣ ADC 11. The clock generator 13 generates a clock and inputs the clock to the ΔΣ ADC 11. Further, the reference voltage generator 14 generates a reference voltage and inputs the reference voltage to the ΔΣ ADC 11. The ΔΣ ADC 11 converts the differential input VIN into a digital signal in synchronization with a clock signal generated by the clock generator 13 using the reference voltage from the reference voltage generator 14, and outputs the digital signal to the encoder 12. The encoder 12 encodes the digital signal converted by the ΔΣ ADC 11, and outputs the encoded digital signal to the isolation section 30.

[0045] Further, resistors R1 and R2 are connected in series between a power supply line to which the power supply voltage VDD1 is supplied and a ground line to which the ground voltage GND2 is supplied. A voltage appearing at a connection point of the resistors R1 and R2 is supplied to a negative polarity input terminal of the comparator 15 as a detection voltage VREF. The differential input VIN+ is supplied to a positive polarity input terminal of the comparator 15. The comparator 15 outputs a detection signal of a high level (H level) when the differential input VIN+ exceeds the detection voltage VREF. By appropriately setting resistance values of the resistors R1 and R2, it is possible to configure such that the detection signal of the H level is output from the comparator 15 in a case where the differential input VIN+ is an excessive input. That is, the detection signal from the comparator 15 indicates whether an abnormality such as an excessive input of the differential input occurs. The comparator 15 outputs the detection signal to the isolation section 30.

[0046] In the following description, a case where the detection signal of the H level is generated when an abnormality is detected to occur and a case where the detection signal is a low level (L level) when an abnormality is not detected to occur are described, but it is also possible to indicate detection of an abnormality by the L level and normal (normal) by the H level.

[0047] Figures 2 to 4 is a block diagram showing a specific configuration example of the isolation section 30. Figure 2 represents an optical coupling method, Figure 3 represents a magnetic coupling method, Figure 4indicates a capacitive coupling method.

[0048] In Figure 2 the driver 31 is given a digital signal from the encoder 12. The light emitting element 32a and the current source 33 are connected in series between a power supply line and a ground line. The driver 31 drives the light emitting element 32a in accordance with the input digital signal. Thereby, the light emitting element 32a is driven by the driver 31 to flow a current, and light of a luminous quantity corresponding to the flowing current is generated.

[0049] Further, the current source 33 is also given a detection signal from the comparator 15. The current source 33 causes a current of a prescribed amount to flow through the light emitting element 32a in accordance with the detection signal of the H level. The current of the current source 33 is set to a current larger than the amount of the current generated in the light emitting element 32a by the driving of the driver 31.

[0050] The light from the light emitting element 32a is received by the light detecting element 32b. The light emitting element 32a and the light detecting element 32b are electrically insulated. The light detecting element 32b generates a current corresponding to the luminous quantity of the light emitting element 32a. A trans-impedance amplifier (TIA) 34 converts the current generated by the light detecting element 32b into a voltage. The output voltage of the trans-impedance amplifier 34 is supplied to the positive polarity input terminal of the comparators 35, 36.

[0051] The comparator 35 compares the reference voltage VREF1 supplied to the negative polarity input terminal with the output voltage of the trans-impedance amplifier 34, and outputs a digital signal of the H level in a case where the output voltage of the trans-impedance amplifier 34 is larger, and outputs a digital signal of the low level (L level) in a case where the output voltage of the trans-impedance amplifier 34 is smaller. That is, the output of the comparator 35 becomes a digital signal corresponding to the digital signal from the encoder 12.

[0052] The comparator 36 compares the reference voltage VREF2 supplied to the negative polarity input terminal with the output voltage of the trans-impedance amplifier 34. The reference voltage VREF2 is set to a voltage larger than the reference voltage VREF1 and higher than the voltage generated by the driving of the driver 31. The comparator 36 outputs a digital signal of the H level in a case where the output voltage of the trans-impedance amplifier 34 is larger than the reference voltage VREF2, and outputs a digital signal of the L level in a case where it is smaller. That is, the output of the comparator 36 becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0053] Figure 3An isolation section 40 capable of utilizing the isolation section 30 is shown. The isolation section 40 includes drivers 41a, 41b, primary and secondary coils 42a, 42b, and receivers 43a, 43b. The driver 41a and the receiver 43a are electrically insulated by the primary and secondary coils 42a, and the driver 41b and the receiver 43b are electrically insulated by the primary and secondary coils 42b. Although not shown, two pairs of coil pairs can exist, and double insulation is possible.

[0054] The driver 41a drives the primary and secondary coils 42a in accordance with the digital signal from the encoder 12. The receiver 43a takes out a voltage generated by mutual induction of the primary and secondary coils 42a. In this way, the output of the receiver 43a becomes a digital signal corresponding to the digital signal from the encoder 12.

[0055] Further, the driver 41b drives the primary and secondary coils 42b in accordance with the detection signal from the comparator 15. The receiver 43b takes out a voltage generated by mutual induction of the primary and secondary coils 42b. In this way, the output of the receiver 43b becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0056] Figure 4 An isolation section 45 capable of utilizing the isolation section 30 is shown. The isolation section 45 includes drivers 46a, 46b, coupling capacitors 47a, 47b, and receivers 48a, 48b. The driver 46a and the receiver 48a are electrically insulated by the coupling capacitor 47a, and the driver 46b and the receiver 48b are electrically insulated by the coupling capacitor 47b. Although not shown, two pairs of coupling capacitors can exist, and double insulation is possible.

[0057] The driver 46a applies the digital signal from the encoder 12 to the coupling capacitor 47a. The receiver 48a takes out the output of the driver 46a via the coupling capacitor 47a. In this way, the output of the receiver 48a becomes a digital signal corresponding to the digital signal from the encoder 12.

[0058] Further, the driver 46b applies the detection signal from the comparator 15 to the coupling capacitor 47b. The receiver 48b takes out the output of the driver 46b via the coupling capacitor 47b. In this way, the output of the receiver 48b becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0059] In Figure 1 , the output of the isolation section 30 is supplied to the secondary circuit 20. The secondary circuit 20 includes a decoder 21, a 1-bit DAC 22, an LPF (low pass filter) 23, a clock regeneration circuit 24, a reference voltage generator 25, and an abnormal input detection output circuit 26.

[0060] The output (digital signal) of the isolation unit 30 based on the output of encoder 12 is supplied to decoder 21 and clock regeneration circuit 24. Clock regeneration circuit 24 regenerates a clock based on the input digital signal and outputs it to decoder 21. In addition, reference voltage generator 25 generates a reference voltage and outputs it to decoder 21. Decoder 21 uses the clock from clock regeneration circuit 24 and reference voltage to perform decoding processing to restore the signal encoded by encoder 12 to the signal before encoding. Decoder 21 outputs the decoded digital signal to 1-bit DAC 22.

[0061] The 1-bit DAC 22 converts the digital signal decoded by the decoder 21 into an analog signal and outputs it to the LPF 23. The LPF 23 removes unwanted frequency components from the analog signal output by the 1-bit DAC 22 and outputs differential outputs VOUT+ and VOUT- (hereinafter referred to as differential output VOUT unless otherwise distinguished). Additionally, the differential output VOUT contains a specified in-phase component. The differential outputs VOUT+ and VOUT- are input to the differential single-phase conversion circuit 50 as differential inputs AIN+ and AIN- (hereinafter referred to as differential input AIN unless otherwise distinguished). Furthermore, the decoder 21, the 1-bit DAC 22, and the LPF 23 constitute the output circuit.

[0062] The differential single-phase conversion circuit 50 converts the differential input AIN into a single-phase output. For example, the differential single-phase conversion circuit 50 calculates the difference between the differential inputs AIN+ and AIN-, thereby converting the differential input AIN into a single-phase output AOUT and outputting it to the ADC1 terminal of the control circuit 52. Furthermore, the differential single-phase conversion circuit 50 adds the differential inputs AIN+ and AIN- together and outputs the voltage of half of the sum to the fault detection circuit 51.

[0063] Figure 5 It means Figure 1 The circuit diagram shows an example of the specific configuration of the differential single-phase conversion circuit 50.

[0064] A differential input AIN+ is supplied to the non-inverting input terminal of operational amplifier OP1a. The inverting input terminal of operational amplifier OP1a is connected to the output terminal via resistor R22a, and to node r via resistor R21a. Operational amplifier OP1a, along with resistors R21a and R22a, constitute a non-inverting amplifier.

[0065] A differential input AIN- is supplied to the non-inverting input terminal of operational amplifier OP1b. The inverting input terminal of operational amplifier OP1b is connected to the output terminal via resistor R22b, and to node r via resistor R21b. The operational amplifier OP1b and resistors R21b and R22b constitute a non-inverting amplifier.

[0066] The output terminal of the operational amplifier OP1a is connected to the inverting input terminal of the operational amplifier OP2 via the resistor R23a, and the output terminal of the operational amplifier OP1b is connected to the non-inverting input terminal of the operational amplifier OP2 via the resistor R23b. The inverting input terminal of the operational amplifier OP2 is connected to the output terminal via the resistor R24a, and the non-inverting input terminal of the operational amplifier OP2 is connected to the reference potential point via the resistor R24b. A differential amplifier is constituted by the operational amplifier OP2 and the resistors R23a, R23b, R24a, R24b.

[0067] The differential input AIN+ is amplified by the non-inverting amplifier constituted by the operational amplifier OP1a, and is applied to the inverting input terminal of the operational amplifier OP2 which constitutes a differential amplifier. Further, the differential input AIN- is amplified by the non-inverting amplifier constituted by the operational amplifier OP1b, and is applied to the non-inverting input terminal of the operational amplifier OP2. The differential inputs AIN+, AIN- are differentially amplified by the operational amplifier OP2, and the single-phase output AOUT corresponding to the difference between the differential inputs AIN+, AIN- is obtained from the output terminal of the operational amplifier OP2. This single-phase output AOUT is supplied to the ADC1 terminal of the control circuit 52.

[0068] The voltages of the differential input AIN+ appearing at the inverting input terminal of the operational amplifier OP1a and the differential input AIN- appearing at the inverting input terminal of the operational amplifier OP1b are divided by the resistors R21a, R21b. By making the resistance values of the resistors R21a, R21b the same, a voltage of 1 / 2 of the sum of the differential inputs AIN+, AIN- appears at the node r. This voltage is supplied to the abnormality detection circuit 51.

[0069] In the Figure 1 abnormality detection circuit 51 can be constituted by a comparator, for example. The abnormality detection circuit 51 is also applied with the determination reference voltage Vref. The abnormality detection circuit 51 outputs an abnormality detection result indicating whether an excessive input or the like has occurred to the ADC2 terminal of the control circuit 52 by comparing the determination reference voltage Vref with the voltage based on the sum from the differential single-phase conversion circuit 50.

[0070] The control circuit 52 is constituted by an MCU, for example. The control circuit 52 obtains the value of the voltage, current or the like generated in the detection object from the single-phase output AOUT input to the ADC1 terminal. Further, the control circuit 52 grasps the excessive input or the like generated in the detection object from the abnormality detection result input to the ADC2 terminal.

[0071] However, the isolation amplifier 1 performs a process of converting a signal to be transmitted in the primary circuit 10 into a digital signal and restoring a digital signal to be transmitted in the secondary circuit 20 into an analog signal, and a filtering process based on the LPF 23 is required after D / A conversion. However, in the filtering process of the LPF 23, a prescribed delay time of a relatively large amount is inherently generated. Since the signal is delayed based on the LPF 23, a relatively long time is required until the control circuit 52 recognizes an abnormal state such as an over input.

[0072] Therefore, in the present embodiment, the abnormal input detection output circuit 26 is provided. The abnormal input detection output circuit 26 is such that, when a detection signal of an H level indicating generation of an abnormal state such as an over input is imparted, the output of the LPF 23 is changed at the timing of the detection signal, whereby generation of an abnormal state such as an over input can be transmitted to the control circuit 52 in a short time.

[0073] (Abnormal Input Detection Output Circuit)

[0074] Figure 6 is a circuit diagram indicating an example of a specific configuration of the LPF 23 and the abnormal input detection output circuit 26.

[0075] The LPF 23 has an LPF section 23b that performs a filtering process on a positive polarity input VINP from the 1-bit DAC 22, and an LPF section 23a that performs a filtering process on a negative polarity input VINN from the 1-bit DAC 22. The LPF section 23b is a secondary active filter constituted by resistors R1P, R2P, capacitors C1P, C2P, and an operational amplifier 23P. Further, the LPF section 23a is a secondary active filter constituted by resistors R1N, R2N, capacitors C1N, C2N, and an operational amplifier 23N.

[0076] The positive polarity input VINP is input to the non-inverting input terminal in+ of the operational amplifier 23P via the resistors R1P, R2P. The non-inverting input terminal in+ of the operational amplifier 23P is connected to a ground line (gnd) via the capacitor C1P, the output terminal is connected to the inverting input terminal in-, and is connected to the connection point of the resistors R1P, R2P via the capacitor C2P. The LPF section 23b outputs a differential output VOUT+ after band-limiting a high frequency of the positive polarity input VINP.

[0077] On the other hand, the negative polarity input VINN is input to the non-inverting input terminal in+ of the operational amplifier 23N via resistors R1N, R2N. The non-inverting input terminal in+ of the operational amplifier 23N is connected to a ground line (gnd) via a capacitor C1N, is connected to the output terminal and the inverting input terminal in-, and is connected to the connection point of the resistors R1N, R2N via a capacitor C2N. The LPF section 23a outputs the differential output VOUT- after band-limiting the high frequency of the positive polarity input VINP.

[0078] In the present embodiment, the non-inverting input terminal in+ of the operational amplifier 23P is connected to the node b of the abnormal input detection output circuit 26, and the non-inverting input terminal in+ of the operational amplifier 23N is connected to the node a of the abnormal input detection output circuit 26. The abnormal input detection output circuit 26 is constituted by a constant voltage generation circuit V0, current sources I0, I1, resistors R3, R4, and switches S0, S1.

[0079] The negative polarity terminal of the constant voltage generation circuit V0 is connected to the ground line (gnd), and the positive polarity terminal is connected to the node a via the current source I0 and the switch S0. The resistor R3 is connected in parallel to the current path of the current source I0. Further, the positive polarity terminal of the constant voltage generation circuit V0 is also connected to the node b via the current source I1 and the switch S1. The resistor R4 is connected in parallel to the current path of the current source I1.

[0080] The abnormal input detection output circuit 26 inputs a detection signal from the isolation section 30, and controls the on / off of the switches S0, S1 in accordance with the detection signal. That is, in the case where the detection signal is an L level which does not indicate detection of an excessive input or the like, both of the switches S0, S1 are off, and in the case where the detection signal is an H level which indicates detection of an excessive input or the like, both of the switches S0, S1 are on.

[0081] In the case where the switch S0 is on, a voltage Vcm1 determined by the voltage generated by the constant voltage generation circuit V0, the current generated by the current source I0, and the resistance value of the resistor R3 is applied to the node a. By this voltage Vcm1, the voltage of the non-inverting input terminal in+ of the operational amplifier 23N is set, and the same phase level of the differential output VOUT- becomes Vcm1.

[0082] Further, similarly, in the case where the switch S1 is on, a voltage Vcm2 determined by the voltage generated by the constant voltage generation circuit V0, the current generated by the current source I1, and the resistance value of the resistor R4 is applied to the node b. By this voltage Vcm2, the voltage of the non-inverting input terminal in+ of the operational amplifier 23P is set, and the same phase level of the differential output VOUT+ becomes Vcm2. Hereinafter, it is assumed that Vcm1 = Vcm2 = Vcm.

[0083] The detection signal from comparator 15 becomes a high level (H) after the differential input VIN+ becomes an excessive input. Nodes a and b of the abnormal input detection output circuit 26 change to a voltage Vcm after the differential input VIN+ becomes an excessive input. Therefore, before the differential output VOUT corresponding to the excessive input of the differential input VIN+ is output from LPF23, and after the differential input VIN+ becomes an excessive input, the in-phase level of the differential output VOUT from LPF23 shifts to Vcm. That is, the in-phase level, which is normally at a specified level (e.g., 0V), changes to Vcm.

[0084] Under normal conditions, where the differential output VOUT does not experience excessive input or other abnormal states, the sum of the differential outputs VOUT+ and VOUT- reaches a certain level. Conversely, under abnormal conditions such as excessive input to the differential output VOUT, the sum of the differential outputs VOUT+ and VOUT- reaches a level corresponding to the voltage Vcm. Therefore, based on the sum of the differential outputs VOUT+ and VOUT-, abnormal states such as excessive input can be determined.

[0085] (effect)

[0086] Next, refer to Figure 7 The waveform diagram illustrates the operation of this implementation method. Figure 7 It is a graph that represents waveforms such as input and output, with time on the horizontal axis and voltage on the vertical axis. Figure 7 In the upper section, the dashed line represents the differential voltage between the differential inputs VIN+ and VIN-, and the solid line represents the differential voltage between the differential outputs VOUT+ and VOUT-. Furthermore, in Figure 7 In the middle section, the solid line represents the differential output VOUT+, and the dashed line represents the differential output VOUT-. Furthermore, Figure 7 The lower section indicates the detection result of an anomaly in the control circuit.

[0087] Now, assuming the input Figure 7 The differential input VIN is shown by the dashed line in the upper section. Figure 7 The detection level in the upper section represents the judgment level for excessive input. If the voltage difference between the differential inputs VIN+ and VIN- is higher than the detection level, an excessive input is determined to exist. That is, the period during which the differential input VIN is higher than the detection level is the period during which an anomaly occurs. Additionally, with... Figure 7 The detection voltage VREF corresponding to the detection level is set according to the power supply voltage VDD1 and resistors R1 and R2.

[0088] The differential input VIN to the primary circuit 10 is converted into a digital signal by the ΔΣADC 11 and then encoded by the encoder 12 before being supplied to the isolation unit 30. The isolation unit 30 transmits the output of the encoder 12 to the secondary circuit 20. The decoder 21 of the secondary circuit 20 decodes the input signal and assigns it to the 1-bit DAC 22. The 1-bit DAC 22 returns the output of the decoder 21 to an analog signal and outputs it to the LPF 23. The LPF 23 filters the high frequency of the output of the 1-bit DAC 22, thereby outputting a differential output VOUT corresponding to the differential input VIN.

[0089] The filtering process of this LPF23 introduces a delay. The result is as follows: Figure 7 As shown in the upper section, the differential output VOUT is output with a relatively long delay relative to the differential input VIN.

[0090] Now, suppose the differential input VIN becomes more than Figure 7 The state of the upper segment's detection level being too high (during the abnormality generation period). Comparator 15 outputs a detection signal of level H for a relatively short time after the excessive input is generated. The H-level period of the detection signal is the abnormality detection period of the primary circuit 10. The detection signal is supplied to the abnormal input detection output circuit 26 via the isolation section 30, turning on switches S0 and S1. As a result, a voltage Vcm is applied to nodes a and b of the abnormal input detection output circuit 26, and the non-inverting outputs of the LPF sections 23a and 23b become voltage Vcm.

[0091] Figure 7 The middle section represents this state, where the average rising voltage Vcm of the differential outputs VOUT+ and VOUT- is [value missing]. When the excessive input of the differential input VIN is eliminated and VIN becomes lower than [value missing], [the condition changes]. Figure 7 When the detection level of the upper segment is reached, the detection signal from comparator 15 immediately afterwards becomes L level. This detection signal is supplied to the abnormal input detection output circuit 26 via isolation section 30, and switches S0 and S1 are opened. As a result, the in-phase outputs of LPF sections 23a and 23b return to the normal in-phase voltage.

[0092] The differential output VOUT from LPF23 is supplied to the subsequent differential single-phase conversion circuit 50. The differential single-phase conversion circuit 50 calculates the output corresponding to the differential input VIN based on the difference between the differential outputs VOUT+ and VOUT-, and outputs it to the control circuit 52. Thus, the control circuit 52 can determine the voltage, current, etc., of the detected object based on the differential output VOUT.

[0093] Further, the differential single-phase conversion circuit 50 obtains the sum of the differential output VOUT+ and the differential output VOUT- and outputs it to the abnormality detection circuit 51. The abnormality detection circuit 51 compares the determination reference voltage Vref with a voltage based on the sum obtained from the differential single-phase conversion circuit 50 and outputs the comparison result. As Figure 7 As shown in the lower stage, in the normal state, the sum voltage of the differential output VOUT+ and the differential output VOUT- is a certain voltage (a voltage equivalent to the in-phase voltage in the normal state). In the abnormal state, 1 / 2 of the sum voltage of the differential output VOUT+ and the differential output VOUT- becomes the voltage Vcm. That is, Figure 7 The pulse waveform of the lower stage shows the detection result of the abnormality detection circuit 51 indicating the period of the abnormal state such as an excessive input (abnormality detection period). The abnormality detection circuit 51 outputs the abnormality detection result to the ADC2 terminal of the control circuit 52. Figure 7 The pulse waveform of the lower stage indicates the abnormality detection period delayed from the abnormality generation period by several, and the isolation amplifier 1 can rapidly transfer the generation of the abnormality detected by the primary circuit 10.

[0094] Further, the differential output VOUT+ and the differential output VOUT- in the abnormality detection period are obtained by the abnormal input detection output circuit 26 adding the known voltages. Thus, even in the abnormality detection period, as Figure 7 As shown in the upper stage, the difference between the differential output VOUT+ and the differential output VOUT- corresponds to the differential input VIN. That is, in the present embodiment, based on the differential output VOUT from the LPF 23, it is possible to detect the abnormality period such as an excessive input and to grasp the voltage, current, and the like of the detection object throughout the entire period including the abnormality period.

[0095] Thus, in the present embodiment, the abnormality of the differential input VIN is detected on the primary side and the detection signal is transmitted to the secondary side. On the secondary side, based on the detection signal, the level of the differential output VOUT of the LPF is shifted in the abnormality detection period. Thereby, it is possible to rapidly transfer the generation of the abnormality to the control circuit 52 of the subsequent stage by the output of the LPF without being affected by the processing delay of the LPF.

[0096] (Modified Example)

[0097] Figure 8 is a circuit diagram showing a modified example. Figure 8 shows another configuration example of the LPF 23 and the abnormal input detection output circuit 26. The present modified example shows a configuration example in which a full differential circuit is used as the LPF 23.

[0098] In Figure 8In the present embodiment, the positive polarity input VINP from the 1-bit DAC 22 is applied to the non-inverting input of the full differential amplifier OPA1 via the resistor R5P. In addition, the negative polarity input VINN from the 1-bit DAC 22 is applied to the inverting input of the full differential amplifier OPA1 via the resistor R5N. The capacitor C3P is connected between the positive polarity output and the non-inverting input of the full differential amplifier OPA1, and the capacitor C3N is connected between the negative polarity output and the inverting input of the full differential amplifier OPA1. The LPF 23 is constituted by the full differential amplifier OPA1, the resistors R5P, R5N, and the capacitors C3P, C3N.

[0099] The positive polarity input VINP and the negative polarity input VINN are filtered by the full differential amplifier OPA1, and the differential output VOUT+ is output from the positive polarity output of the full differential amplifier OPA1, and the differential output VOUT- is output from the negative polarity output.

[0100] The resistor R6P and the resistor R6N are connected in series between the positive polarity output and the negative polarity output of the full differential amplifier OPA1, and the connection point of the resistors R6P, R6N is connected to the inverting input of the operational amplifier OPA2. The voltage generated by the voltage generating circuit 26a is supplied to the non-inverting input of the operational amplifier OPA2. The operational amplifier OPA2 supplies the voltage based on the difference voltage of the two inputs to the full differential amplifier OPA1. The full differential amplifier OPA1 operates in such a manner that the same phase voltage coincides with the output voltage of the operational amplifier OPA2.

[0101] The negative polarity terminal of the constant voltage generating circuit V0 is connected to the ground line (gnd), and the positive polarity terminal is connected to one terminal of the switch SW1. The negative polarity terminal of the constant voltage generating circuit V1 is connected to the positive polarity terminal of the constant voltage generating circuit V0, and the positive polarity terminal is connected to the other terminal of the switch SW1. The constant voltage generating circuits V0, V1 generate the voltages V0, V1, respectively.

[0102] The common terminal of the switch SW1 is connected to the non-inverting input of the operational amplifier OPA2. The switch SW1 is controlled by the detection signal from the isolation section 30. The switch SW1 applies the voltage V0 generated by the constant voltage generating circuit V0 to the non-inverting input of the operational amplifier OPA2 according to the detection signal indicating that no abnormality is generated, and applies the sum voltage (V0+V1) of the voltages generated by the constant voltage generating circuits V0, V1 to the non-inverting input of the operational amplifier OPA2 according to the detection signal indicating that an abnormality is generated.

[0103] Figure 8The circuit is a fully differential circuit. Therefore, in order to change the differential output VOUT of LPF23, the non-inverting voltage of the fully differential amplifier OPA1 is controlled according to the detection signal. Under normal conditions, the output of operational amplifier OPA2 is fed back to the fully differential amplifier OPA1 so that the voltage at the connection point of resistors R6P and R6N is consistent with the voltage V0.

[0104] Under normal conditions, switch SW1 applies the voltage V0 generated by the constant voltage generating circuit V0 to the non-inverting input of operational amplifier OPA2 based on the detection signal. Therefore, the non-inverting voltage of the fully differential amplifier OPA1 becomes V0. When an abnormality such as excessive input occurs and the detection signal becomes H level, switch SW1 applies the sum of the voltages generated by the constant voltage generating circuits V0 and V1 (V0 + V1) to the non-inverting input of operational amplifier OPA2. Therefore, the non-inverting voltage of the fully differential amplifier OPA1 becomes (V0 + V1), causing the differential output VOUT to increase by V1.

[0105] Thus, after adopting Figure 8 In the case of the circuit, the same effect as in the first embodiment can also be obtained.

[0106] (Second Implementation)

[0107] Figure 9 This is a block diagram illustrating the second embodiment of the present invention. Figure 9 China for Figure 1 Identical components are marked with the same symbols and their descriptions are omitted.

[0108] In this embodiment, the isolation amplifier 2, located after the LPF23, deforms the output of the LPF23 based on the detection signal transmitted from the primary circuit 10 to the secondary circuit 20, thereby rapidly transmitting the abnormality to the subsequent control circuit 52. Furthermore, in this embodiment, the differential single-phase conversion circuit 50 and the control circuit 52 are omitted from the illustration. Additionally, in this embodiment, as... Figure 10 As shown, an operational circuit 29 is used instead of the anomaly detection circuit 51.

[0109] The secondary circuit 28 in this embodiment and Figure 1 The difference in the secondary circuit 20 is that an abnormal input detection output circuit 27 is used instead of an abnormal input detection output circuit 26. The abnormal input detection output circuit 27 is supplied with the output of LPF 23 and outputs differential outputs VOUT+ and VOUT-. Furthermore, a detection signal indicating the detection result of an abnormality such as excessive input is input from the primary circuit 10 to the abnormal input detection output circuit 27 via the isolation unit 30. When an abnormality is indicated by the detection signal, the abnormal input detection output circuit 27 generates an output to notify of the occurrence of the abnormality, instead of the differential output VOUT.

[0110] Figure 10 is a circuit diagram showing a specific configuration of the abnormal input detection output circuit 27. Figure 9 Figure 10 only shows a configuration of a part of the secondary circuit 28 in Figure 9

[0111] In Figure 10 , the abnormal input detection output circuit 27 includes two switches S2, S3 controlled by the detection signal. The differential output VOUT+ is input from the LPF 23 to one input terminal of the switch S2, and the internal clock (internal CK) is input to the other input terminal. Further, the differential output VOUT- is input from the LPF 23 to one input terminal of the switch S3, and the internal clock (internal CK) is input to the other input terminal. In addition, the internal CK is a regenerated clock regenerated by the clock regenerating circuit 24.

[0112] The switches S2, S3 select the differential output VOUT+ or the differential output VOUT- of the LPF 23 and output it in a case where the detection signal is the L level not indicating generation of the abnormality. On the other hand, the switches S2, S3 select the internal CK and output it in a case where the detection signal is the H level indicating generation of the abnormality.

[0113] The differential outputs VOUT+, VOUT- input to the one input terminals of the switches S2, S3 are differential signals, and the internal CK input to the other input terminals of the switches S2, S3 is a common signal. Thus, in a circuit at a stage subsequent to the secondary circuit 28, the output of the abnormal input detection output circuit 27 is given to the operation circuit 29 such as an AND circuit, an EXOR circuit, and the like, whereby it is possible to determine which input terminal is selected in the switches S2, S3 and which signal is output.

[0114] Next, the operation of the embodiment thus configured will be described with reference to the waveform chart of Figure 11 . Figure 11 is a chart showing waveforms of input and output and the like with time as the horizontal axis and voltage as the vertical axis. Figure 11 As in Figure 7 , in the upper stage, the broken line shows the difference voltage of the differential inputs VIN+ and VIN-, and the solid line shows the difference voltage of the differential outputs VOUT+ and VOUT-, in the middle stage, the solid line shows the differential output VOUT+, and the broken line shows the differential output VOUT-, and in the lower stage, the abnormality detection result input to the control circuit 52 is shown.

[0115] ​​The operation from the input of the signals (VIN+, VIN-) corresponding to the differential inputs VIN+ and VIN- to the input of the 1-bit DAC22 and the output of the analog signal from the 1-bit DAC22 is the same as in the first embodiment. Furthermore, the operation of the comparator 15 from the output of a detection signal indicating the occurrence of an anomaly and its transmission to the secondary circuit 28 via the isolation unit 30 is also the same as in the first embodiment.

[0116] In this embodiment, the LPF23 performs high-frequency filtering on the input signal and outputs filtered differential outputs VOUT+ and VOUT-. Figure 11 The upper section uses a solid line to represent the difference between the differential output VOUT+ and the differential output VOUT- in this case, and a dashed line to represent the difference between the differential input VIN+ and the differential output VIN-. That is, Figure 11 The solid line waveform represents the difference between the differential output VOUT+ and the differential output VOUT- input to the abnormal input detection output circuit 27.

[0117] The differential input VIN did not exceed Figure 11 When the detection level of the upper segment is too high, the detection signal input to the abnormal input detection output circuit 27 is at level L. In this case, the switches S2 and S3 of the abnormal input detection output circuit 27 select the differential outputs VOUT+ and VOUT- from LPF23 and output them.

[0118] Here, it is assumed that the differential input VIN becomes more than Figure 11 The state of the upper segment's detection level being too high (during the abnormality generation period). Comparator 15 outputs a detection signal, represented by a level H, indicating the abnormality detection period within a relatively short time from the generation of this excessive input. The detection signal is supplied to the abnormal input detection output circuit 27 via isolation section 30, causing switches S2 and S3 to select the internal CK. As a result, as Figure 11 As shown during the abnormal detection period in the middle section, the output of the abnormal input detection output circuit 27 becomes the clock CK.

[0119] When the differential input VIN becomes lower than Figure 11 When the detection level is at the upper level, the detection signal becomes L level, and switches S2 and S3 directly output the differential output VOUT from LPF23 again. Figure 11 (Middle section).

[0120] like Figure 11 As shown in the previous section, the difference between the differential output VOUT+ and the differential output VOUT- becomes 0V during the anomaly detection period, but not 0V during other periods. Therefore, the arithmetic circuit 29 can determine the anomaly detection period through AND operations, XOR operations, etc. Figure 11The lower segment indicates 1 / 2 of the sum of the differential output VOUT+ and the differential output VOUT- from the abnormal input detection output circuit 27. As shown in Figure 11 the sum voltage of the differential output VOUT+ and the differential output VOUT- is a certain voltage (in-phase voltage at normal time). At abnormal time, 1 / 2 of the sum voltage of the differential output VOUT+ and the differential output VOUT- becomes a pulse waveform synchronized with the internal CK. The period of the pulse waveform indicates the period of the abnormal state such as an excessive input (abnormal detection period). Figure 11 The period of the pulse waveform of the lower segment indicates the abnormal detection period delayed from the abnormal generation period by several, and the isolation amplifier 2 can rapidly transfer the generation of the abnormality detected by the primary circuit 10.

[0121] Thus, in the present embodiment, as in the first embodiment, the abnormality of the differential input VIN is detected on the primary side and the detection signal is transmitted to the secondary side. On the secondary side, based on the detection signal, the differential output VOUT of the LPF is converted into an in-phase signal in the abnormal detection period. Thereby, the generation of the abnormality can be rapidly transferred to the control circuit of the subsequent stage by the output of the LPF without being affected by the processing delay of the LPF.

[0122] (Third Embodiment)

[0123] Figure 12 is a block diagram showing the third embodiment of the present application. In Figure 12 the same components as in the Figure 1 first and second embodiments are denoted by the same symbols and the description thereof is omitted.

[0124] In the above first and second embodiments, the example in which the isolation amplifier outputs an analog signal as the differential output VOUT is described. The present embodiment shows the example in which digital data is output from the isolation amplifier. In this case, low-pass filter processing is also required in the circuit of the subsequent stage of the isolation amplifier, and signal delay caused by the low-pass filter is generated in the usual signal transmission path.

[0125] In Figure 12 the primary circuit 10 of the isolation amplifier 3 and the isolation section 30 are configured the same as in the Figure 1 first and second embodiments. In the present embodiment, the decoder 61 of the secondary circuit 60 decodes the differential signal transmitted from the isolation section 30 to generate output data DTI corresponding to the differential input VIN, and generates the clock CKI reproduced in the clock reproducing circuit 24.

[0126] In addition, in the present embodiment, the example in which the clock CKI reproduced in the clock reproducing circuit 24 in the isolation amplifier 3 is used in data transmission is described, but as the clock CKI, a clock taken in from the outside can also be adopted.

[0127] In the present embodiment, the output data DTI and the clock CKI from the decoder 61 are not directly output as the output of the isolation amplifier 3, but are supplied to the mixer 62. The detection signal from the comparator 15 is supplied to the mixer 62 as the detection signal FLTN via the isolation section 30 as an abnormality input detection output circuit. Further, the output circuit is constituted by the decoder 61 and the mixer 62.

[0128] In the present embodiment, as described later, the mixer 62 forcibly changes the logic of the output data DTI according to the detection signal FLTN of the H level, thereby passing the abnormality generation period to the circuit in the subsequent stage. In the circuit in the subsequent stage, the generation period of the abnormality is grasped by detecting this forcible change. The mixer 62 outputs the output data DTO obtained by changing the output data DTI in correspondence with the detection signal FLTN, and directly outputs the clock CKI as the clock CKO. These clock CKO and output data DTO are output as the clock MCLK and the output data MDAT from the isolation amplifier 3 via the buffers 63, 64, respectively.

[0129] The clock MCLK and the output data MDAT from the isolation amplifier 3 are supplied to the FPGA 70. The FPGA 70 is constituted by a latch 71, an LPF 72, and an MCU interface (I / F) 73. Further, in the following description, the latch is sometimes referred to as a D-type flip-flop. The clock MCLK is supplied to the latch 71 and the LPF 72 via the clock terminal CLK of the FPGA 70. Further, the output data MDAT is input to the latch 71 via the data terminal DAT of the FPGA 70. The latch 71 takes in the data MDAT in synchronization with the rising edge of the clock MCLK and outputs to the LPF 72. The LPF 72 performs a filter process of limiting the high frequency of the data using the clock MCLK, and outputs the data after the filter process to the MCU I / F 73. The MCU I / F 73 outputs the data from the LPF 72 to the DIF terminal of the control circuit 90 via the output terminal DIF. The control circuit 90 is constituted by, for example, an MCU, takes in the output data from the LPF 72, and restores the data corresponding to the differential input VIN.

[0130] In the present embodiment, the clock MCLK and the output data MDAT from the isolation amplifier 3 are also supplied to the external circuit 80. The external circuit 80 obtains the detection result FAULTN indicating the abnormality detection period by using the clock MCLK and the output data MDAT. The external circuit 80 outputs the detection result FAULTN to the interrupt (INT) terminal of the control circuit 90. The control circuit 90 grasps the period in which the abnormality is generated on the basis of the detection result FAULTN input to the INT terminal.

[0131] Figure 13 is a detection resultFigure 12 a circuit diagram of an example of the specific configuration of the mixer 62 and the external circuit 80.

[0132] In Figure 13 The mixer 62 is configured of a rising detector DT1, an inverter IN1, latches L1, L2, and an AND circuit A1. Further, the external circuit 80 is configured of a latch 81. The clock CKI from the decoder 61 is supplied to the latches L1, the rising detector DT1, and the inverter IN1, and also to the buffer 63. The output data DTI from the decoder 61 is supplied to the latch L2. Further, the detection signal FLTN from the isolation section 30 is supplied to the latch L1.

[0133] The rising detector DT1 detects the rising of the clock CKI, and gives a rising edge detection pulse to one input terminal of the AND circuit A1. The inverter IN1 inverts the clock CKI and gives the clock terminal of the latch L2. The latch L1 takes in the detection signal FLTN according to the clock CKI and gives the other input terminal of the AND circuit A1. The AND circuit A1 gives the AND operation result of the two inputs to the S terminal of the latch L2. The latch L2 takes in the output data DTI at the timing of the falling edge of the clock CKI from the inverter IN1 during the period when the S terminal is supplied with the L level, and outputs it. Further, the latch L2 outputs the H level during the period when the S terminal is supplied with the H level. The output of the latch L2 becomes the output (output data MDAT) of the isolation amplifier 3 via the buffer 64.

[0134] The latch L2 takes in the output data DTI at the timing of the falling edge of the clock CKI and outputs it, so the output data MDAT becomes data whose logic changes within the L level period of the clock MCLK. Further, at the rising timing of the clock CKI immediately after the detection signal FLTN changes to the H level, the clock MCLK becomes the H level.

[0135] Further, the clock MCLK is supplied to the data terminal of the latch 81 of the external circuit 80, and the output data MDAT is supplied to the clock terminal. That is, the latch 81 takes in the clock MCLK at the rising edge of the output data MDAT and outputs it.

[0136] Next, the operation of the embodiment thus configured will be described with reference to Figure 14 to the timing chart for explaining the operation of the third embodiment. Figure 14

[0137] The decoder 61 of the secondary circuit 60 outputs the clock CKI, and outputs the output data DTI in synchronization with this clock CKI. Figure 14 ​CKI and DTI represent these clocks and data. These clocks CKI and output data DTI are output as clock MCLK and output data MDAT via mixer 62 and buffers 63 and 64.

[0138] Now, let's assume a normal operating condition without any abnormalities such as excessive input. In this case, the detection signal FLTN is at level L, and the outputs of latch L1 in mixer 62 and AND circuit A1 are also at level L. Therefore, latch L2 fetches and outputs output data DTI synchronously with the falling edge of clock CKI. Thus, output data MDAT, which is the same as output data DTI, is output synchronously with clock MCLK. Furthermore, the output data MDAT is toggled during the L level of clock MCLK.

[0139] Next, assume that an anomaly such as excessive input occurs, causing the detection signal FLTN to change to level H. Figure 14 The FLTN indicates this state. In this embodiment, in order to transmit the anomaly detection result to the control circuit 90 at high speed, the mixer 62 superimposes the anomaly detection result information into the output data MDAT. In this case, the anomaly detection result information is superimposed using a portion of a one-clock data period so that the logic for determining the output data MDAT can be performed in subsequent circuits.

[0140] That is, in order to determine the superposition timing, the rising edge detector DT1 detects the rising edge of the clock CKI and outputs a rising edge detection pulse. Figure 14 The DT1 output). Latch L1 latches and outputs the detection signal FLTN at the timing of clock CKI. Figure 14 (The output of L1). The AND circuit A1 performs an AND operation between the rising edge detection pulse and the output of latch L1. Figure 14 The A1 output represents the result of the AND operation. The pulse generated from the A1 output of the AND circuit is synchronized with the rising timing of the clock CKI during the H level of the detection signal FLTN.

[0141] The rising pulse of latch L2 synchronizes with the output pulse of AND circuit A1, forcibly changing the level of output data DTI to H level. The output of latch L2 becomes the output data DTO from mixer 62. Furthermore, clock CKI directly becomes clock CKO from mixer 62. These clocks CKO and output data DTO, after being delayed by buffers 63 and 64, are output to FPGA 70 as clock MCLK and output data MDAT. Figure 14 MCLK and MDAT represent these outputs.

[0142] Figure 14the output pulse of the AND circuit Al. Even if the output data DTI is an L level at the timing of the output pulse of the AND circuit Al, the output data MDAT changes to an H level at the timing of the output pulse of the AND circuit Al. In Figure 14 In the example of FIG. 8, the case where the data Dl, D2, D3 among the data D0, Dl,... is forcibly changed to an H level is indicated.

[0143] The clock MCLK and the output data MDAT from the isolation amplifier 3 are supplied to the latch 81 of the external circuit 80. The latch 81 takes in the clock MCLK at the rising timing of the output data MDAT and outputs the detection result FAULTN. In the case where no forcible level change is performed, the switching of the data value of the output data MDAT occurs during the L level period of the clock MCLK. In contrast, by forcibly changing the level to an H level in the middle of the data, the H level of the clock can be latched at the rising edge timing of the output data MDAT. Thus, the detection result FAULTN indicated by the FAULTN of FIG. 8 can be obtained. Figure 14

[0144] Figure 14 The broken line of FIG. 8 indicates the case where the detection result FAULTN depends on the output data MDAT. For example, in the case where the data Dl is originally an L level, the data Dl is forcibly changed to an H level at the timing of the output pulse of the AND circuit Al. In this case, the H level of the clock MCLK is taken in at the rising edge of the data Dl. That is, the detection result FAULTN changes to an H level at the timing when the data Dl is input to the external circuit 80.

[0145] However, in the case where the data Dl is originally an H level, the data Dl does not rise at the timing of the output pulse of the AND circuit Al, and thus the detection result FAULTN from the latch 81 remains unchanged at an L level. That is, the broken line of the FAULTN indicates that the detection result FAULTN is likely to change to an H level at any one of the timings of the data Dl, D2, D3. Also, when the detection signal FLTN becomes an L level, the detection result FAULTN takes in the L level of the clock MCLK at any one of the rising timings of the data D4, D5,... and is output. For example, when the original data Dl, D4 is an L level and the original data D3 is an H level, the detection result FAULTN becomes an H level at the timing when the data Dl is input to the latch 81 and becomes an L level at the timing when the data D4 is input to the latch 81.

[0146] ​The control circuit 90 determines the H level period of the detection result FAULTN as an abnormality detection result. Further, at the rising timing of the clock MCLK, the information of the data D0, Dl,... is maintained as the original information, and the data corresponding to the differential input VIN can be reliably acquired in the control circuit 90.

[0147] Thus, in the present embodiment, the detection signal indicating that an abnormality has occurred in the primary circuit 10 is acquired and transmitted to the secondary circuit 60. In the secondary circuit 60, using the transmitted detection signal, information indicating the detection period of the abnormality is superimposed in the digital data, and the superimposed information is extracted without performing the filtering process. Thus, the detection result of the abnormality can be rapidly transmitted to the circuit at the subsequent stage.

[0148] (4th Embodiment)

[0149] Figure 15 is a block diagram showing an example of a specific configuration of a mixer employed in the 4th embodiment of the present application. In Figure 15 the same configuration elements as in the Figure 13 are denoted by the same symbols and the explanation thereof is omitted. In addition, the isolation amplifier 4 of the present embodiment differs from the Figure 12 in that the mixer 100 is employed instead of the mixer 62, and the explanation of the configuration other than the mixer 100 is omitted.

[0150] In the above-described 3rd embodiment, the detection result FAULTN cannot be obtained in some cases depending on the logic level of the transmitted output data MDAT. Therefore, in the present embodiment, the data of the rising and falling timing of the detection signal FLTN is forcibly rewritten, whereby the detection result FAULTN can be reliably obtained.

[0151] In the Figure 15 , the clock CKI is supplied to the inverters IN2, IN3 and the rising detector DTl constituting the mixer 100, and is directly supplied to the buffer 63. The output data DTI is supplied to the selector SEl. The detection signal FLTN is supplied to the inverter IN4, the AND circuit A2 and the latch L3.

[0152] The inverter IN2 inverts the clock CKI and applies it to the latch L3. The latch L3 takes in the detection signal FLTN in synchronization with the falling edge of the clock CKI and outputs it to the latch L4 and the AND circuit A4, and inverts the taken-in detection signal FLTN and applies it to the AND circuit A2. The AND circuit A2 outputs the AND operation result of the two inputs to the OR circuit ORl. The latch L4 takes in the output of the latch L3 in synchronization with the falling edge of the clock CKI and outputs it to the AND circuit A3, and inverts the taken-in output of the latch L3 and outputs it to the AND circuit A4.

[0153] AND circuit A3 outputs the AND operation result of the two inputs to AND circuit A5 and OR circuit ORl. OR circuit ORl outputs the OR operation result of the two inputs as a selection signal to selector SEl. The detection signal FLTN is inverted by inverter IN4 and input to selector SEl, and selector SEl selects either the output data DTI or the inverted signal of the detection signal FLTN according to the selection signal from OR circuit ORl and outputs it to latch L5.

[0154] AND circuit A5 outputs the AND operation result of the output of the rising detector DTl and the output of AND circuit A3 to the R terminal of latch L5. Further, AND circuit A6 outputs the AND operation result of the output of the rising detector DTl and the output of AND circuit A4 to the S terminal of latch L5. Latch L5 takes in the output of selector SEl in synchronization with the falling edge of the clock CKI from inverter IN3 and outputs it, and outputs an H level according to the H level output of AND circuit A5 and an L level according to the H level output of AND circuit A6. The output of latch L5 becomes the output (output data MDAT) of isolation amplifier 4 via buffer 64.

[0155] Next, the operation of the embodiment thus configured will be described with reference to Figure 16 The operation of the embodiment thus configured will be described. Figure 16 is a timing chart for explaining the operation of the fourth embodiment.

[0156] The decoder 61 of the secondary circuit 60 outputs the clock CKI and outputs the output data DTI in synchronization with the clock CKI. Figure 16 CKI, DTI indicate the clock and the data. These clock CKI and output data DTI are output as the clock MCLK and the output data MDAT via the mixer 100 and the buffers 63, 64.

[0157] Now, it is assumed that this is a normal time when no abnormality such as an overlarge input has occurred. In this case, the detection signal FLTN is an L level. Thus, the outputs of the latches L3, L4, AND circuits A2 to A6, and OR circuit ORl within the mixer 100 are all L levels. As a result, selector SEl selects the output data DTI and outputs it to latch L5. Latch L5 outputs the output of selector SEl to buffer 64 in synchronization with the falling edge of the clock CKI. Thus, in this case, the clock MCLK and the output data MDAT correspond to the clock CKI and the output data DTI, respectively. In this embodiment, the data value of the output data MDAT also changes during the L level period of the clock MCLK.

[0158] Next, let's assume that an anomaly such as excessive input occurs, causing the detection signal FLTN to change to level H. Figure 16 The FLTN indicates this state. In this embodiment, similar to the first embodiment, when the detection signal FLTN changes to an H level, the mixer 100 forces the output data MDAT to become an H level during the H level period of the clock MCLK. Furthermore, in this embodiment, when the detection signal FLTN changes to an H level, the mixer 100 forces the output data to become an L level at a timing corresponding to the change timing, and when the detection signal FLTN changes to an L level, it forces the output data to become an H level at a timing corresponding to the change timing.

[0159] That is, latch L3 synchronously takes in the detection signal FLTN and outputs it on the falling edge of clock CKI. Figure 16 The output of L3). The AND circuit A2 performs an AND operation between the inverted signal of the output of latch L3 and the detection signal FLTN, resulting in a pulse of level H during the period from the rise of the detection signal FLTN to the fall of the clock CKI. Figure 16 The A2 output is output to the OR circuit OR1.

[0160] Latch L4 delays the output of latch L3 by one clock cycle, outputting the result to AND circuit A3, and inverts this output, outputting it to AND circuit A4. The output of AND circuit A4 becomes level H for one clock cycle from the time the detection signal FLTN becomes level H after the clock CKI falls. Figure 16 The output of A4). Furthermore, the output of AND circuit A3 becomes H level for one clock cycle starting from the drop in clock CKI after the detection signal FLTN becomes L level. Figure 16 (A3 output).

[0161] OR circuit OR1 performs an OR operation between the outputs of AND circuit A2 and AND circuit A3, and outputs a pulse that reaches the H level while both inputs are at the H level. Figure 16 (OR1 output). Selector SE1 selects and outputs the output data DTI during the L level of the selection signal from the OR circuit OR1, and selects and outputs the inverted signal of the detection signal FLTN during the H level of the selection signal. That is, the output of selector SE1 during the H level of the selection signal becomes L level immediately after the rising edge of the detection signal FLTN, and becomes H level immediately after the falling edge of the detection signal FLTN.

[0162] The rising edge detector DT1 detects the rising edge of the clock CKI and outputs a rising edge detection pulse. Figure 16The AND circuit A6 outputs the result of the AND operation between the rising edge detection pulse from the rising edge detector DT1 and the output of the AND circuit A4 to the S terminal of latch L5. Figure 16 The output of AND circuit A6 is the rising edge detection pulse generated during the period when the output of AND circuit A4 reaches the H level after the rise of the detection signal FLTN.

[0163] Furthermore, the AND operation result of the output of the rising detector DT1 and the output of the AND circuit A3 is ( ) Figure 16 The output of AND circuit A5 is a rising edge detection pulse generated during the H level period of the output of AND circuit A3, which becomes H level after the detection signal FLTN falls.

[0164] During the period when the outputs of AND circuits A5 and A6 are both at level L, latch L5 selects and outputs the output (output data DTI) of selector SE1. Furthermore, latch L5 outputs level H based on the rising edge detection pulse from AND circuit A5 supplied to the R terminal, and outputs level L based on the rising edge detection pulse from AND circuit A6 supplied to the S terminal.

[0165] The result, such as Figure 16 As shown, in the output data MDAT, data D2 is forcibly set to L level, and data D6 is forcibly set to H level. The clock MCLK and the output data MDAT are supplied to FPGA 70. Through the forced level changes performed by mixer 100, thus... Figure 16 As shown in the FPGA, the values ​​of data D2 and D6 of the output data MDAT processed within FPGA70 disappear.

[0166] The latch 81 of the external circuit 80 fetches the clock MCLK at the rising time of the output data MDAT and outputs it as the detection result FAULTN. Figure 16 As shown, the timing of the rising edge detection pulse of the detection result FAULTN after the detection signal FLTN becomes H level is H level, and the timing of the rising edge detection pulse after the detection signal FLTN becomes L level is L level.

[0167] Thus, based on the detection result FAULTN, the abnormal detection result can be transmitted to the control circuit 90 at high speed.

[0168] Thus, in this embodiment, the same effect as in the third embodiment can be obtained. In this embodiment, the data value is forcibly changed at the timing of the change in the detection signal FLTN, so the detection result FAULTN representing the anomaly detection result can be reliably obtained.

[0169] (5th Embodiment)

[0170] Figure 17 is a block diagram showing a specific configuration example of the mixer employed in the 5th embodiment of the present application. In Figure 17 , the same reference numerals are assigned to the same constituent elements as those of Figure 13 , and the description thereof is omitted. Further, the isolation amplifier 5 of the present embodiment differs from that of the 4th embodiment in that the mixer 110 is employed instead of the mixer 62, and the description of the other constituents other than the mixer 110 is omitted. Figure 12

[0171] In the 4th embodiment, the output data MDAT is forcibly changed to the L or H level, and thus the data disappearance occurs. The present embodiment prevents the data disappearance. To this end, the mixer 110 of the present embodiment sets the latter half of the data to the H level after setting it to the L level during the H level of the clock MCLK at the rise of the detection signal FLTN. Further, the mixer 110 sets the latter half of the data to the H level after setting it to the L level during the L level of the clock MCLK at the fall of the detection signal FLTN.

[0172] In Figure 17 , the clock CKI is supplied to the inverters IN5, IN6, IN7 constituting the mixer 110, and directly to the latch L6. The output data DTI is supplied to the latch L7. The detection signal FLTN is supplied to the latch L7.

[0173] The inverters IN5 to IN7 invert the clock CKI and apply it to the latches L8, L6, L9, respectively. The latch L6 takes in the output data DTI in synchronization with the falling edge of the clock CKI and outputs it to the selector SE2. The latch L7 takes in the detection signal FLTN in synchronization with the clock CKI and outputs it to the latch L8 and the AND circuit A7, and outputs the inverted signal of the detection signal FLTN to the AND circuit A8. The latch L8 takes in the output of the latch L7 in synchronization with the falling edge of the clock CKI and outputs it to the delay circuit DEl. The delay circuit DEl applies the delayed output obtained by delaying the output of the latch L8 to the AND circuit A8, and inverts and outputs the delayed output to the AND circuit A7.

[0174] The AND circuit A7 outputs the AND operation result of the 2 inputs as a selection signal to the selector SE2, and outputs the AND operation result to the delay circuit DE2. The delay circuit DE2 outputs to the selector SE2 after delaying the output of the AND circuit A7. The selector SE2 selects the output of the latch L6 or the output of the delay circuit DE2 based on the selection signal from the AND circuit A7 and outputs it to the selector SE3.​

[0175] AND circuit A8 outputs the AND operation result of the 2 inputs as a selection signal to selector SE3, and outputs the AND operation result to latch L9. Latch L9 takes in the output of AND circuit A8 in synchronization with the falling edge of clock CKI and outputs to selector SE3. Selector SE3 selects either the output of selector SE2 or the output of latch L9 based on the selection signal from AND circuit A8 and outputs to buffer 64.

[0176] Next, the operation of the embodiment thus configured will be described with reference to Figure 18 The operation of the embodiment thus configured will be described. Figure 18 is a timing chart for explaining the operation of the 5th embodiment.

[0177] The decoder 61 of the secondary circuit 60 outputs clock CKI, and outputs output data DTI in synchronization with this clock CKI. Figure 18 CKI, DTI of indicates these clocks and data. These clocks CKI and output data DTI are output as clock MCLK and output data MDAT via the mixer 110 and buffers 63, 64.

[0178] Now, assume a normal time when no abnormality such as an excessive input has occurred. In this case, the detection signal FLTN is at the L level. Thus, the outputs of latches L7, L8, L9, AND circuits A7, A8, and delay circuits DE1, DE2 within the mixer 110 are all at the L level. As a result, selector SE2 selects the output of latch L6, and selector SE3 selects the output of selector SE2. In this way, output data DTI is supplied to buffer 64 via latch L6, selectors SE2, SE3, and output data MDAT corresponding to output data DTI is output from buffer 64 in synchronization with clock MCLK.

[0179] Next, assume a case where an abnormality such as an excessive input has occurred and the detection signal FLTN changes to the H level. Figure 18 FLTN of indicates this state. In the present embodiment, as in the 1st embodiment, the mixer 110 forcibly sets output data MDAT to the H level during the H level of clock MCLK in the case where the detection signal FLTN changes to the H level. Further, in the present embodiment, the mixer 110 forcibly sets output data to the H level after forcibly setting it to the L level during the H level of clock MCLK in correspondence with the change timing in the case where the detection signal FLTN changes to the H level, and forcibly sets output data to the L level in correspondence with the change timing when the detection signal FLTN changes to the L level, and forcibly sets it to the H level during the L level of clock MCLK.

[0180] That is, latch L7 synchronously takes in the detection signal FLTN with the rising of clock CKI and outputs it to latch L8. Figure 18 L7 output). Latch L8 takes the detection signal FLTN from latch L7 at the falling time of clock CKI and outputs it to delay circuit DE1. Delay circuit DE1 delays the detection signal FLTN from latch L8 and outputs it ( Figure 18 (DE1 output). That is, the output of the delay circuit DE1 becomes level H after a specified period from the fall of the initial clock CKI after the rise of the detection signal FLTN.

[0181] The AND operation result of the inverted signal of the output of the delay circuit DE1 and the output of the latch L7 is obtained by ANDing the output of the AND circuit A7. Figure 18 As shown in the A7 output, the output of the AND circuit A7 becomes the width of the specified period from the fall of the initial clock CKI after the rise of the detection signal FLTN. Figure 18 A pulse with a width of more than half a clock cycle becomes an H-level pulse.

[0182] The delay circuit DE2 will delay the output of the AND circuit A7. Figure 18 The output of DE2 is assigned to selector SE2. The delay time of the delay circuit DE2 is set to be longer than the period required from the rise of clock CKI to the sampling of output data DTI, but shorter than half a clock period (the period during which clock CKI is at level H). Therefore, during the period when the output of AND circuit A7 is at level H, the output of selector SE2 is at level L immediately after the output of AND circuit A7 becomes level H, and becomes level H after the delay time of the delay circuit DE2, after the output of AND circuit A7 becomes level H.

[0183] The AND circuit A8 outputs the result of the AND operation between the inverted signal of latch L7 and the output of delay circuit DE1 to latch L9 and selector SE2. For example... Figure 18 As shown in the A8 output, the output of the AND circuit A8 becomes the width of the specified period starting from the initial clock CKI drop after the detection signal FLTN drops. Figure 18 A pulse with a width of more than half a clock cycle becomes an H-level pulse.

[0184] Latch L9 is fed into the output of AND circuit A8 synchronously with the falling edge of clock CKI and assigns it to selector SE3. Figure 18The selector SE3 selects the output of the selector SE2 during the L level of the output of the AND circuit A8 and selects the output of the latch L9 during the H level. Thus, when the output of the AND circuit A8 becomes the H level, the output of the selector SE3 becomes the L level immediately after the output of the AND circuit A8 becomes the H level and becomes the H level at the falling timing of the next clock CKI after the output of the AND circuit A8 becomes the H level. The output of the selector SE3 is output as the output data MDAT from the isolation amplifier 5 via the buffer 64.

[0185] As a result, as shown in FIG. 16, at the timing of the data D2 in the data D0, D1,... of the output data MDAT corresponding to the rising of the detection signal FLTN, the data D2 forcibly becomes the L level from the middle and returns to the H level during the H level of the clock MCLK. Further, at the timing of the data D5 in the data D0, D1,... of the output data MDAT corresponding to the falling of the detection signal FLTN, the data D5 forcibly becomes the L level from the middle and returns to the H level during the L level of the clock MCLK. Figure 18

[0186] The clock MCLK and the output data MDAT are supplied to the FPGA 70. The latch 81 of the external circuit 80 takes in the clock MCLK at the rising timing of the output data MDAT and outputs the detection result FAULTN. As shown in FIG. 17, the detection result FAULTN becomes the H level about one clock after the detection signal FLTN becomes the H level and becomes the L level about one and a half clocks after the detection signal FLTN becomes the L level. Figure 18

[0187] Thus, according to the detection result FAULTN, the abnormality detection result can be rapidly transmitted to the control circuit 90. Further, even if there is the forced level change based on the mixer 110, as shown in FIG. 18, the output data MDAT processed in the FPGA 70 does not generate the data loss. Figure 18

[0188] Thus, in the present embodiment, the same effect as the third embodiment can be obtained. In the present embodiment, the level of the data is forcibly changed at the change timing of the detection signal FLTN while the value of the data is maintained, so the detection result FAULTN indicating the abnormality detection result can be reliably obtained without the data loss.

[0189] (Sixth Embodiment)

[0190] Figure 19 is a block diagram showing an example of a specific configuration of a mixer employed in the sixth embodiment of the present application. In Figure 19 the same manner as in the​​​Figure 13 The same components are denoted by the same reference numerals and the description thereof is omitted. In addition, the isolation amplifier 6 of the present embodiment differs from the isolation amplifier 6 of the first embodiment only in that the mixer 120 is used instead of the mixer 62, and the description thereof is omitted for components other than the mixer 120. In addition, in the present embodiment, the FPGA 75 capable of processing at double data rate is used instead of the FPGA 70. Furthermore, in the present embodiment, the external circuit 82 is used instead of the external circuit 80 of the first embodiment. Figure 12 Figure 12

[0191] In the present embodiment, a double data rate system in which data is transferred at both edges of a clock is used, and in normal times, data is transferred at one clock and an L level, and in abnormal times such as an over input, data is transferred at one clock and an H level.

[0192] In the present embodiment, the clock CKI is supplied to the inverter IN8, the selector SE4, and the double edge detector DT2 that constitute the mixer 120, and is directly supplied to the buffer 63. The output data DTI is supplied to the selector SE4. The detection signal FLTN is supplied to the latch L10. The inverter IN8 inverts the clock CKI and supplies it to the latch L10. The latch L10 takes in the output data DTI in synchronization with the falling timing of the clock CKI and outputs it to the selector SE4. Figure 19 The selector SE4 selects and outputs the output data DTI in accordance with the H level of the clock CKI, and selects and outputs the detection signal FLTN from the latch L10 in accordance with the L level of the clock CKI. The double edge detector DT2 detects the rising edge and the falling edge of the clock CKI and outputs an edge detection pulse to the latch L11. The latch L11 takes in the output of the selector SE4 at the timing of the edge detection pulse and outputs it to the buffer 64.

[0193] Thus, the output data DTI is output in synchronization with the rising edge of the clock CKI from the latch L11, and the detection signal FLTN is output in synchronization with the falling edge of the clock CKI. In addition, the output of the latch L11 outputs an L level in synchronization with the falling edge of the clock CKI during the L level of the detection signal FLTN in which no abnormality such as an over input has occurred, and outputs an H level in synchronization with the falling edge of the clock CKI during the H level of the detection signal FLTN in which an abnormality such as an over input has occurred.

[0194] The clock MCLK and the output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 differs from the FPGA 70 of the first embodiment only in that it can process a double data rate signal, and the description thereof is omitted for components other than this.

[0195] Figure 12 ​​​The FPGA 70 is the same configuration. The FPGA 75 samples the output data MDAT in synchronization with the rising edge of the clock MCLK, thereby obtaining data corresponding to the differential input VIN. The FPGA 75 outputs to the control circuit 90 after performing low-pass filter processing or the like on the taken-in data.

[0196] In the present embodiment, the external circuit 82 is configured by inverters 83 to 85 and a latch 81. The inverter 83 inverts the output data MDAT and supplies it to the latch 81, and the inverter 84 inverts the clock MCLK and supplies it to the clock terminal of the latch 81. Thus, the latch 81 takes in the inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK and outputs it. The output of the latch 81 is supplied to the inverter 85. The inverter 85 inverts the output of the latch 81 and outputs it as the detection result ALM to the INT terminal of the control circuit 90.

[0197] Next, the operation of the embodiment thus configured will be described with reference to Figure 20 Figure 20 is a timing chart for explaining the operation of the 6th embodiment.

[0198] The decoder 61 of the secondary circuit 60 outputs the clock CKI and outputs the output data DTI in synchronization with this clock CKI. Figure 20 CKI, DTI indicate these clocks and data. These clocks CKI and output data DTI are output as the clock MCLK and the output data MDAT via the mixer 120 and the buffers 63, 64.

[0199] The double-edge detector DT2 detects the rising and falling of the clock CKI and outputs an edge detection pulse (DT2 output). Using the edge detection pulse generated at the rising and falling of the clock CKI, the latch L11 takes in the output of the selector SE4 and outputs it. Thus, the output from the latch L11 becomes double data rate. Figure 20 DT2 output). Using the edge detection pulse generated at the rising and falling of the clock CKI, the latch L11 takes in the output of the selector SE4 and outputs it. Thus, the output from the latch L11 becomes double data rate.

[0200] Now, assume that it is normal time when no abnormality such as an overdrive input has occurred. In this case, the detection signal FLTN is at the L level. Thus, the output of the latch L10 within the mixer 120 is at the L level. The selector SE4 takes in the output data DTI in accordance with the H level of the clock CKI and outputs it to L11, and takes in the detection signal FLTN in accordance with the L level of the clock CKI and outputs it to L11. Thus, in this case, the output of the latch L11 has the information of the output data DTI during the period in synchronization with the H level of the clock CKI, and becomes the L level during the period in synchronization with the L level of the clock CKI.

[0201] Next, assume a case where the detection signal FLTN changes to the H level due to an abnormality such as an overdrive input.​Figure 20 FLTN indicates the state. The output of the latch L10 becomes H level at the first clock CKI fall after the detection signal FLTN becomes H level (L10 output). The H level output of this latch L11 is output from the selector SE4 in synchronization with the fall of the clock CKI. Thus, when the detection signal FLTN becomes H level, the output of the latch L11 has the information of the output data DTI in the period in synchronization with the H level of the clock CKI, and becomes H level in the period in synchronization with the L level of the clock CKI (SE4 output). The output of the latch L11 is output as the output data MDAT from the isolation amplifier 6 via the buffer 64. Figure 20 Figure 20

[0202] The clock MCLK and the output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 samples the output data MDAT in synchronization with the rising edge of the clock MCLK, thereby obtaining data corresponding to the differential input VIN.

[0203] The inverter 83 of the external circuit 82 inverts the output data MDAT and applies it to the latch 81. Further, the inverter 84 inverts the clock MCLK and applies it to the clock terminal of the latch 81. Thus, the latch 81 takes in the inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK and outputs it. Thus, the latch 81 outputs H level in correspondence with the L level period of the detection signal FLTN, and outputs L level in correspondence with the H level period of the detection signal FLTN. The output of the latch 81 is inverted by the inverter 85 to become the detection result ALM. As shown by ALM, the detection result ALM is a signal corresponding to the detection signal FLTN. The detection result ALM from the inverter 85 is supplied to the control circuit 90. Figure 20

[0204] Thus, according to the detection result ALM, the abnormality detection result can be transmitted to the control circuit 90 at high speed. Further, as shown in the FPGA in Figure 20

[0205] Thus, in the present embodiment, the same effects as the 5th embodiment can be obtained.

[0206] (7th Embodiment)

[0207] Figure 21 is a block diagram showing a specific configuration of a mixer employed in the 7th embodiment of the present application. In Figure 21 Figure 13 ​​​​​​Identical components are labeled with the same symbols and their descriptions are omitted. Furthermore, the isolation amplifier 7 in this embodiment differs from the previous one only in that it uses a mixer 130 instead of a mixer 62. Figure 12 The configurations other than mixer 130 are omitted from the description. Furthermore, in this embodiment, instead of... Figure 12 The external circuit 80 is replaced by the external circuit 86.

[0208] Furthermore, in embodiments 3 to 6, it was explained that the clock CKI could be either a clock generated by the clock regeneration circuit 24 or a clock taken from outside the isolation amplifier. However, in this embodiment, the clock CKI uses the clock generated by the clock regeneration circuit 24.

[0209] The embodiments described above, 3 to 6, illustrate an example of transmitting information from the detection signal FLTN superimposed on the output data MDAT. This embodiment, however, is an example of transmitting information from the detection signal FLTN using a clock.

[0210] exist Figure 21 In this embodiment, the clock CKI is supplied to latches L12, L13, and L14, as well as the delay circuit DE3, which constitutes mixer 130. Mixer 130 supplies the input clock CKI to buffer 63 via latch L13. Output data DTI is supplied to latch L14. Latch L14 latches the output data DTI synchronously with the clock CKI and outputs it to buffer 64.

[0211] The detection signal FLTN is supplied to latch L12. Latch L12 synchronously receives the detection signal FLTN with the rising edge of clock CKI and supplies it as a selection signal to selector SE5. Delay circuit DE3 delays clock CKI by a specified delay time and outputs the delayed signal to rising detector DT1 and falling detector DT3. Rising detector DT1 detects the rising edge of clock CKI delayed in delay circuit DE3 and outputs the edge detection pulse to selector SE5. Falling detector DT3 detects the falling edge of clock CKI delayed in delay circuit DE3 and outputs the edge detection pulse to selector SE5.

[0212] Selector SE5 selects the edge detection pulse from the rising detector DT1 during the H level of the detection signal FLTN from latch L12 and assigns it to the R terminal of latch L13, and selects the edge detection pulse from the falling detector DT3 during the L level of the detection signal FLTN from latch L12 and assigns it to the R terminal of latch L13.

[0213] The latch L13 takes in the inputted H level (logic value "1") at the rising of the clock CKI and outputs, and returns to the L level when the edge detection pulse from the selector SE5 is inputted to the R terminal. That is, during the L level period of the detection signal FLTN from the latch L12, the output of the L13 becomes the H level due to the rising of the clock CKI, and becomes a pulse output of which the pulse width is short at the timing of the edge detection pulse from the rising detector DT1 becoming the L level. Further, during the H level period of the detection signal FLTN from the latch L12, the output of the L13 becomes the H level due to the rising of the clock CKI, and becomes a pulse output of which the pulse width is wide at the timing of the edge detection pulse from the falling detector DT3 becoming the L level. The output of the latch L13 becomes the output of the isolation amplifier 7 as the clock MCLK via the buffer 63.

[0214] The clock MCLK and the output data MDAT from the isolation amplifier 7 are also given to the external circuit 86. The external circuit 86 has a low pass filter constituted by a capacitor Cll and a resistor Rll. One end of the resistor Rll is connected to the output terminal of the clock MCLK of the isolation amplifier 7, and the other end is connected to a reference potential point via the capacitor Cll. The connection point of the capacitor Cll and the resistor Rll is connected to the ADC terminal of the control circuit 90.

[0215] The external circuit 86 obtains the average value of the voltage level of the clock MCLK, and supplies the obtained average value as the detection result ALM to the ADC terminal of the control circuit 90.

[0216] Next, the operation of the embodiment thus configured will be described with reference to Figure 22 The operation of the embodiment thus configured will be described. Figure 22 is a timing chart for explaining the operation of the 7th embodiment.

[0217] The decoder 61 of the secondary circuit 60 outputs the clock CKI, and outputs the output data DTI in synchronization with the clock CKI. Figure 22 CKI, DTI indicate these clocks and data. These clocks CKI and output data DTI are outputted as the clock MCLK and the output data MDAT via the mixer 130 and the buffers 63, 64.

[0218] The output data DTI is supplied to the latch L14, and the latch L14 outputs the output data DTI to the buffer 64 in synchronization with the rising edge of the clock CKI. Thus, the output data MDAT (MDAT of Figure 22 ) from the isolation amplifier 7 is information corresponding to the output data DTI, and is outputted in synchronization with the rising of the clock CKI.

[0219] The clock CKI is supplied to the latch L13. The latch L13 outputs an H level of the logical value "1" at the rising timing of the clock CKI. The output of the latch L13 is output as the clock MCLK via the buffer 63. Thus, the rising of the clock MCLK is synchronized with the rising of the clock CKI.

[0220] The clock CKI is also supplied to the delay circuit DE3. The delay circuit DE3 outputs a delayed signal to the rising detector DT1, DT3 after delaying the clock CKI. The rising detector DT1 detects the rising edge of the delayed signal and outputs an edge detection pulse to the selector SE5, and the falling detector DT3 detects the falling edge of the delayed signal and outputs an edge detection pulse to the selector SE5. The output of the selector SE5 is supplied to the R terminal of the latch L13, and the output of the latch L13 becomes an L level at the timing of the output pulse of the selector SE5.

[0221] Now, assume a normal time when no abnormality such as an excessive input has occurred. In this case, the detection signal FLTN is an L level. Thus, the selector SE5 selects the edge detection pulse from the rising detector DT1 and applies it to the latch L13. In this case, the output of the latch L13 becomes an H level at the rising of the clock CKI, and outputs a narrow pulse which becomes an L level due to the rising of the clock CKI.

[0222] Next, assume a case where the detection signal FLTN changes to an H level due to an abnormality such as an excessive input. Figure 22 The FLTN indicates this state. The output of the latch L12 becomes an H level at the rising of the clock CKI immediately after the detection signal FLTN becomes an H level (the L12 output). The edge detection pulse from the rising detector DT1 is a pulse which is generated after the delay time of the delay circuit DE3 from the rising of the clock CKI (the DT1 output). Further, the output of the falling detector DT3 is a pulse which is generated at the falling edge of the clock CKI after the delay time of the delay circuit DE3 from the rising of the clock CKI (the DT3 output). Figure 22 Figure 22 The output of the latch L13 becomes a narrow pulse which becomes an H level at the rising of the clock CKI in the period corresponding to the L level period of the detection signal FLTN, and becomes an L level at the timing of the edge detection pulse from the rising detector DT1. Further, the output of the latch L13 becomes a wide pulse which becomes an H level at the rising of the clock CKI in the period corresponding to the H level period of the detection signal FLTN, and becomes an L level at the timing of the edge detection pulse from the falling detector DT3 (the MCLK). Figure 22

[0223] The output of the latch L13 becomes a narrow pulse which becomes an H level at the rising of the clock CKI in the period corresponding to the L level period of the detection signal FLTN, and becomes an L level at the timing of the edge detection pulse from the rising detector DT1. Further, the output of the latch L13 becomes a wide pulse which becomes an H level at the rising of the clock CKI in the period corresponding to the H level period of the detection signal FLTN, and becomes an L level at the timing of the edge detection pulse from the falling detector DT3 (the MCLK). Figure 22

[0224] ​​​The clock MCLK and the output data MDAT are supplied to the FPGA 70. As shown in Figure 22 the output data MDAT is synchronized with the clock MCLK, and the output data MDAT can be processed in the FPGA 70.

[0225] The clock MCLK is also supplied to the external circuit 86. The clock MCLK is averaged by a low-pass filter based on the capacitor Cll and Rll of the external circuit 86. The external circuit 86 outputs the averaged clock MCLK as the detection result ALM to the control circuit 90.

[0226] As shown in Figure 22 the clock MCLK is averaged by the external circuit 86, and thus the level of the detection result ALM is lower in the period in which the clock MCLK is narrow, and the level of the detection result ALM is higher in the period in which the clock MCLK is wide. The control circuit 90 compares the level shown by the dotted line in Figure 22 with the level of the detection result ALM, and thus obtains an abnormality detection result.

[0227] Thus, in the present embodiment, the same effects as those of the fifth embodiment can be obtained.

[0228] (Eighth Embodiment)

[0229] Figure 23 is a block diagram showing an example of a specific configuration of a mixer employed in the eighth embodiment of the present application. In Figure 23 the same components as those of the Figure 13 are denoted by the same symbols and the description thereof is omitted. In addition, the isolation amplifier 8 of the present embodiment differs from the Figure 12 only in that the mixer 140 is employed instead of the mixer 62, and the description of the components other than the mixer 140 is omitted. In addition, in the present embodiment, the external circuit 80 of the Figure 12 is replaced by a pulse detector 87 as an external circuit.

[0230] The present embodiment is an example in which the information of the detection signal FLTN is superimposed on the invalid period of the output data MDAT for transmission. In the FPGA 70 at the rear stage of the isolation amplifier 8, the sampling of the output data MDAT is performed in the H level period of the clock MCLK. Therefore, in the present embodiment, the information of the detection signal FLTN is superimposed on the invalid period of the output data MDAT corresponding to the L level period of the clock MCLK.

[0231] In Figure 23In this case, the clock CKI is supplied to the inverter IN9, the latches L16, L17 that constitute the mixer 140, and directly to the buffer 63. The output data DTI is supplied to the selector SE6. The detection signal FLTN is supplied to the XOR circuit EX1. The inverter IN9 inverts the clock CKI and applies it to the latch L15. The latch L15 takes in the output of the XOR circuit EX1 at the timing of the inverted clock of the clock CKI and outputs it as a selection signal to the selector SE6, and also outputs it to the XOR circuit EX1 and the latch L16.

[0232] The XOR circuit EX1 performs an exclusive OR operation (hereinafter, referred to as XOR operation) of the detection signal FLTN and the output of the latch L15 and outputs the XOR operation result to L15. The output of the selector SE6 is applied to the latch L17, which takes in the output of the selector SE6 at the rising edge of the clock CKI and outputs it to the selector SE6 and the XOR circuit EX2. The selector SE6 outputs the output data DTI when the selection signal is the L level, and outputs the output of the latch L17 when it is the H level.

[0233] The latch L16 takes in the output of the latch L15 at the rising edge of the clock CKI and outputs it to the falling detector DT3. The falling detector DT3 detects the falling edge of the output of the latch L15 and outputs an edge detection pulse to the XOR circuit EX2. The XOR circuit EX2 outputs the XOR operation result of the output of the latch L17 and the output of the falling detector DT3 to the buffer 64.

[0234] According to this configuration, as described later, a pulse that inverts and restores the level of the output data MDAT is generated in the invalid period of the output data MDAT corresponding to the rising and falling of the detection signal FLTN.

[0235] The clock MCLK and the output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. The FPGA 70 samples the output data MDAT in synchronization with the rising edge of the clock MCLK, thereby obtaining data corresponding to the differential input VIN.

[0236] In the present embodiment, the pulse detector 87 is employed as an external circuit. The clock MCLK from the isolation amplifier 8 is supplied to the CLK terminal of the pulse detector 87, and the output data MDAT from the isolation amplifier 8 is supplied to the DAT terminal. The pulse detector 87 detects the pulse superimposed in the invalid period of the output data MDAT, thereby generating a detection result ALM indicating detection of an abnormality and outputting it to the control circuit 90.

[0237] Figure 24 is a circuit diagram of an example of a specific configuration of the pulse detector 87 in Figure 23 is a circuit diagram of an example of a specific configuration of the pulse detector 87 in

[0238] The clock MCLK and the output data MDAT from the isolation amplifier 8 are also supplied to the pulse detector 87. That is, the clock MCLK is supplied to the latches L18, L20, L21 and the delay circuit DE4. The output data MDAT is supplied to the latch L18 and the EXCLUSIVE OR circuit EX3. The latch L18 takes in the output data MDAT at the rising edge of the clock MCLK and outputs it to the EXCLUSIVE OR circuit EX3. The EXCLUSIVE OR circuit EX3 performs an EXCLUSIVE OR operation of outputting an H level when the two inputs are the same logic (identical) and outputting an L level when they are not identical, and outputs the EXCLUSIVE OR operation result to the AND circuit A9. Further, the EXCLUSIVE OR operation result of the EXCLUSIVE OR circuit EX3 is also inverted and supplied to the latch L19.

[0239] The delay circuit DE4 delays the output data MDAT by a prescribed period and outputs it to the latch L19. The latch L19 takes in the inverted signal of the output of the EXCLUSIVE OR circuit EX3 during the H level period of the output of the delay circuit DE4 and outputs it to the AND circuit A9, and outputs an L level (logic value "0") to the AND circuit A9 during the L level period of the output of the delay circuit DE4. The AND circuit A9 outputs the AND operation result of the two inputs to the OR circuit OR2 and the latch L20.

[0240] The latch L20 takes in the output of the AND circuit A9 at the rising edge of the clock MCLK and outputs it to the OR circuit OR2. The OR circuit OR2 outputs the OR operation result of the two inputs to the latch L21. The latch L21 takes in the output of the OR circuit OR2 at the rising edge of the clock MCLK and outputs it. The output of the latch L21 is supplied to the control circuit 90 as the detection result ALM. As will be described later, a pulse contained in the inactive period of the output data MDAT is detected by the pulse detector 87, and the detection result ALM is obtained based on the pulse.

[0241] Next, the operation of the embodiment thus configured will be described with reference to Figure 25 and Figure 26 Figure 25 is a timing chart for explaining the generation of the clock MCLK and the output data MDAT in the isolation amplifier 8, Figure 26 is a timing chart for explaining the operation of the pulse detector 87.

[0242] The decoder 61 of the secondary circuit 60 outputs the clock CKI, and outputs the output data DTI in synchronization with the clock CKI. Figure 25 CKI, DTI of FIG. 10 indicate the clocks and the data. These clocks CKI and the output data DTI are output as the clock MCLK and the output data MDAT via the mixer 140 and the buffers 63, 64. ​

[0243] Now, assume a normal time when no abnormality such as an excessive input is generated. In this case, the detection signal FLTN is at the L level. Thus, the outputs of the latches L15, L16 are also at the L level, and the output of the XOR circuit EXl remains at the L level. The selector SE6 selects the output data DTI and outputs it to the latch L17. The latch L17 outputs the output data DTI to the XOR circuit EX2 at the rising edge of the clock CKI.

[0244] The output of the latch L16 is at the L level, and thus the output of DT3 also becomes the L level, and the output data DTI is output from the XOR circuit EX2. The output of the XOR circuit EX2 is output as the output data MDAT via the buffer 64. Thus, in the normal time, the clock CKI and the output data DTI are directly output as the clock MCLK and the output data MDAT.

[0245] Next, assume a case where an abnormality such as an excessive input is generated, and the detection signal FLTN changes to the H level. Figure 25 The FLTN indicates this state. The output of the XOR circuit EXl is the output of the H level when the detection signal FLTN changes from the L level to the H level. The output of the XOR circuit EXl is taken in by the latch L15 at the falling edge of the clock CKI and returned to the input terminal. Thus, the output of the XOR circuit EXl changes every time the clock CKI falls during the H level period of the detection signal FLTN. Thus, the output of the latch L15 also inverts at the falling edge of the clock CKI during the H level period of the detection signal FLTN (L15 output). Figure 25

[0246] The latch L17 takes in the output of the selector SE6 at the rising edge of the clock CKI and returns it to the input terminal of the selector SE6. The output data DTI is directly output from the selector SE6 during the L level period of the detection signal FLTN, and the output data DTI one clock before output by the latch L17 is output from the selector SE6 during the H level period. Thus, as shown by the L17 output, the same data is output from the latch L17 for two clock periods during the detection signal FLTN. Figure 25

[0247] The latch L16 takes in the output of the latch L15 at the rising edge of the clock CKI and outputs it to the falling detector DT3. Thus, the output of the latch L16 is the output of the latch L15 delayed by half a clock period (L16 output). The falling detector DT3 detects the falling edge of the latch L16 and outputs an edge detection pulse (DT3 output). Figure 25 Figure 25 ​​​XOR circuit EX2 performs XOR operation of the output of the latch L17 and the falling detector DT3. During the period when the output of the latch L16 is L level, the data from the latch L17 is directly output from the XOR circuit EX2, and during the period when the edge detection pulse from the latch L16 is H level, the data from the latch L17 is inverted and output. Figure 25 The MDAT shows this case, and the level of the data Dl is inverted during the period corresponding to the H level period of the edge detection pulse.

[0248] The clock MCLK and the output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. As shown in the FPGA, the FPGA 70 takes the output data MDAT during the H level period of the clock MCLK. Figure 25

[0249] Further, the clock MCLK and the output data MDAT from the isolation amplifier 8 are also supplied to the pulse detector 87. Figure 26 The MCLK and the MDAT show an example of the clock MCLK and the output data MDAT supplied to the pulse detector 87. In the example of the MCLK and the MDAT, the output data MDAT indicates whether the data value is "0" or "1" by the L level or the H level, and the protrusion-like pulse in the MDAT indicates the pulse Pl added to the data by the mixer 140 corresponding to the change of the detection signal FLTN from the L level to the H level and the pulse P2 corresponding to the change of the detection signal FLTN from the H level to the L level. Figure 26

[0250] The latch L18 of the pulse detector 87 takes in the output data MDAT at the rising edge of the clock MCLK and outputs to the coincidence circuit EX3. As shown in the output of the L18, the latch L18 outputs the output data MDAT in synchronization with the rising edge of the clock MCLK. Figure 26

[0251] The output data MDAT from the isolation amplifier 8 is supplied to the coincidence circuit EX3, and the coincidence circuit EX3 outputs the coincidence operation result of the output of the latch L18 and the input output data MDAT to the AND circuit A9 as H level during the period when they coincide and as L level during the period when they do not coincide. Further, the coincidence operation result from the coincidence circuit EX3 is inverted and given to the latch L19.

[0252] The delay circuit DE4 gives the output obtained by delaying the clock MCLK by a prescribed period to the latch L19 Figure 26 ​​​the output of the latch L19 is taken in from the inverting signal of the output of the coincidence circuit EX3 during the period when the output of the delay circuit DE4 is at the H level and is output to the AND circuit A9, and an L level (logic value "0") is output to the AND circuit A9 during the period when the output of the delay circuit DE4 is at the L level.

[0253] As a result, the following output can be obtained from the latch L19: an output that is an output in which the output of the coincidence circuit EX3 is roughly inverted, but in which the rising timing of the output of the coincidence circuit EX3 is delayed by the amount of the delay of the delay circuit DE4 and the falling timing is advanced. Therefore, as shown in the L19 output, the output of the latch L19 becomes a waveform having an H level period that is slightly wider than the period when the output of the coincidence circuit EX3 is at the L level at the switching timing of the normal data. On the other hand, at the timings corresponding to the pulses P1 and P2 that are narrow-width pulses, the output of the delay circuit DE4 becomes the L level before rising in correspondence with the rising of the pulses P1 and P2, and therefore a change in the waveform due to the pulses P1 and P2 does not occur in the output of the L19. Figure 26

[0254] The AND circuit A9 performs an AND operation of the output of the coincidence circuit EX3 and the output of the latch L19. As shown in the A9 output, the output of the AND circuit A9 is a waveform corresponding to the period when the output of the latch L19 is at the H level, which is wider than the L level period of the coincidence circuit EX3, and becomes a narrow-width pulse waveform. Further, the output of the AND circuit A9 is a pulse waveform in which the H level is wide corresponding to the waveform of the output of the latch L19 during the period corresponding to the pulses P1 and P2. Figure 26

[0255] The latch L20 takes in the output of the AND circuit A9 at the rising edge of the clock MCLK and outputs to the OR circuit OR2. The narrow-width pulse of the output of the latch L19 is generated after the rising timing of the clock MCLK and does not occur in the output of the latch L20. On the other hand, the pulse waveform possessed by the output of the latch L20 has a width of one clock period corresponding to the wide-width pulse period of the output of the latch L19 (L20 output) in the H level period of the wide-width pulse of the output of the latch L19 generated at the rising timing of the clock MCLK. Figure 26

[0256] The OR circuit OR2 performs an OR operation of the output of the AND circuit A9 and the output of the latch L20 and obtains the output shown in the OR2 output. Figure 26 The output of the OR circuit OR2 is given to the latch L21, and the latch L21 takes in the output of the OR circuit OR2 at the rising edge of the clock MCLK and outputs. As shown in the L21 output, the output of the latch L21 is a waveform in which the H level period is wide corresponding to the period when the output of the AND circuit A9 is at the H level, and the L level period is narrow corresponding to the period when the output of the AND circuit A9 is at the L level. Figure 26 ​​​The output of the latch L21 becomes the detection result ALM corresponding to the period from the pulse P1 to the pulse P2 as shown in the ALM. The latch L21 outputs the detection result ALM to the control circuit 90.

[0257] Thus, in the present embodiment, the same effects as the third embodiment can be obtained.

[0258] (9th Embodiment)

[0259] Figure 27 and Figure 28 is a block diagram showing the 9th embodiment. Figure 27 an isolation amplifier corresponding to the analog output, Figure 28 an isolation amplifier corresponding to the digital output.

[0260] In each of the above embodiments, two terminals, a data input terminal for inputting data corresponding to the differential input VIN and an interrupt terminal for inputting the abnormality detection result, are required in the control circuit. The present embodiment can take in the data corresponding to the differential input VIN and the abnormality detection result into the control circuit via one terminal.

[0261] In Figure 27 , the isolation amplifier 53 is the isolation amplifier 1 or 2 of the 1st or 2nd embodiment. The differential single-phase conversion circuit 50 adds the differential outputs VOUT+, VOUT- of the isolation amplifier 53 and outputs the addition result to the A terminal of the abnormality detection circuit 51. The abnormality detection circuit 51 is composed of a comparator and compares the decision reference voltage Vref input to the B terminal with the addition result A. The abnormality detection circuit 51 outputs an H level in the case where the level at the A terminal is equal to or higher than the level at the B terminal, and outputs an L level in the case where the level at the A terminal is lower than the level at the B terminal. In the present embodiment, the abnormality detection circuit 51 outputs the comparison result to the selector 54 as a selection signal.

[0262] The selector 54 also inputs the single-phase output AOUT from the differential single-phase conversion circuit 50, selects the single-phase output AOUT according to the selection signal of the L level and outputs it, and selects the prescribed maximum value according to the selection signal of the H level and outputs it. The output of the selector 54 is output to the ADC1 terminal of the control circuit 91.

[0263] The control circuit 91, in the case where a signal of the normal level is input to the ADC1 terminal, judges the input signal as the single-phase output AOUT and processes it. On the other hand, the control circuit 91, in the case where a signal of the maximum value of the processed level is input to the ADC1 terminal, judges the input signal as the abnormality detection result indicating the occurrence of an abnormality and processes it.

[0264] Thus, by adopting Figure 27Its structure enables data and anomaly detection results to be transmitted to the control circuit via a single terminal.

[0265] exist Figure 28 In the diagram, isolation amplifier 57, FPGA 58, and external circuit 59 represent the isolation amplifiers 3-8, FPGAs 70 and 75, and external circuits 80, 82, and 86 of embodiments 3 to 8, respectively. The external circuit 59 receives the clock MCLK and output data MDAT from the isolation amplifier 57 as inputs. The external circuit 59 generates the detection result ALM based on the clock MCLK and the output data MDAT.

[0266] In this embodiment, the external circuit 59 outputs the detection result ALM as a selection signal to the selector 92. Filtered data is also input to the selector 92 from the output terminal DIF of the FPGA 58. The selector 92 selects and outputs data from the FPGA 58 based on the L-level selection signal, and selects and outputs a specified odd value based on the H-level selection signal. Furthermore, negative maximum values ​​can be considered as odd values. The selector 92 outputs the selected output to the DIF terminal of the control circuit 93.

[0267] Control circuit 93 processes the input signal as data from FPGA 58 when a normal level signal is input to the DIF terminal. On the other hand, control circuit 93 processes the input signal as an anomaly detection result indicating an anomaly when an odd value signal is input to the DIF terminal.

[0268] Thus, by adopting Figure 28 Its structure enables data and anomaly detection results to be transmitted to the control circuit via a single terminal.

[0269] (10th Embodiment)

[0270] Figure 29 This is a block diagram illustrating the tenth embodiment. Figure 29 China for and Figure 12 Identical components are marked with the same symbols and their descriptions are omitted. Figure 12 The implementation described is an example of using a built-in clock (clock MCLK) generated in the secondary circuit 60 of the isolation amplifier 3, but this implementation shows an example of using an externally generated clock as clock MCLK.

[0271] Figure 29The secondary circuit 151 of the isolation amplifier 150 differs from the secondary circuit 60 of the isolation amplifier 3 in that the clock regenerating circuit 24 and the buffer 63 are omitted. The clock MCLK is input from the outside to the isolation amplifier 150 via the clock input terminal as the clock MCLKIN. The decoder 61 of the secondary circuit 151 decodes the differential signal transmitted from the isolation section 30 using the clock MCLKIN, and generates the output data DTI corresponding to the differential input VIN. Further, the mixer 62 of the secondary circuit 151 outputs the output data DTO which changes in correspondence with the detection signal FLTN, as with the mixer 62 of the isolation amplifier 3. In addition, the mixer 62 of the secondary circuit 151 does not output the clock.

[0272] In Figure 29 the example, the clock MCLK is generated by a clock generating circuit 156 provided in the FPGA 155. The FPGA 155 differs from the FPGA 70 in that the clock generating circuit 156 is added thereto. The clock generating circuit 156 supplies the generated clock MCLK to the latch 71, and also to the clock input terminal of the isolation amplifier 150.

[0273] The present embodiment differs from the embodiment of the isolation amplifier 3 only in that an external clock is used instead of a built-in clock, and the other configurations and actions are the same as those of the embodiment of the isolation amplifier 3. Figure 12 Figure 12 The present embodiment differs from the embodiment of the isolation amplifier 3 only in that an external clock is used instead of a built-in clock, and the other configurations and actions are the same as those of the embodiment of the isolation amplifier 3.

[0274] Further, the present embodiment explains an example applied to the 3rd embodiment of the isolation amplifier 3, but can also be applied to the 3rd to 6th, 8th and 9th embodiments except for the 7th embodiment in which the clock is processed. Figure 12

[0275] (Variation)

[0276] Figure 30 is a block diagram showing a variation. In Figure 30 the same configuration elements as in the 3rd embodiment of the isolation amplifier 3 are denoted by the same symbols and the explanation thereof is omitted. Figure 1 In the embodiment of the isolation amplifier 3, an example in which the detection information is generated by the external resistor Rl, the resistor R2 and the comparator 15 is explained, but a circuit for generating the detection information can also be built in.

[0277] shows an example in this case. Figure 1 Figure 30

[0278] Figure 30 ​​​​The primary circuit 161 of the isolation amplifier 160 differs from the primary circuit 10 of the isolation amplifier 1 in that an abnormality detection circuit 162 is used instead of the comparator 15. Further, in this modification example, the resistors R1, R2 are omitted. The differential input VIN+, VIN- is given to the abnormality detection circuit 162. The abnormality detection circuit 162 detects generation of an abnormality based on the differential input VIN+, VIN-. For example, the abnormality detection circuit 162 can also divide the differential input VIN+ and compare it with a prescribed detection voltage VREF, thereby detecting generation of an abnormality. The abnormality detection circuit 162 outputs a detection signal indicating whether or not an abnormality is generated to the secondary circuit 20 via the isolation section 30.

[0279] The other configurations, effects, and advantages are the same as those of the first embodiment.

[0280] The several embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications are included in the scope and gist of the application, and are included in the scope of the application and the equivalent range described in the patent claim.

Claims

1. An isolated amplifier comprising: a primary circuit including an analog-digital conversion circuit that converts a plurality of input differential signals applied from a device to be detected into a plurality of digital signals, and an encoder that encodes and outputs an output of the analog-digital conversion circuit; an abnormality detection circuit provided in the primary circuit, detects a level abnormality generated in the plurality of input differential signals, and generates a detection signal; an isolation section that transmits an output of the encoder and the detection signal to a secondary circuit in a state of insulating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, receives the output of the encoder and the detection signal transmitted by the isolation section, includes a decoder that performs a decoding process corresponding to the encoding process, and generates a plurality of output differential signals corresponding to the plurality of input differential signals; and an abnormal input detection output circuit provided in the secondary circuit, directly outputs the plurality of output differential signals generated by the output circuit during a period in which the plurality of input differential signals indicate that no level abnormality is generated, and causes respective in-phase levels of the plurality of output differential signals generated by the output circuit to change and outputs the plurality of output differential signals after the in-phase levels have changed during a period in which the plurality of input differential signals indicate that a level abnormality has occurred.

2. The isolated amplifier according to claim 1, wherein the output circuit includes a digital-analog conversion circuit that converts an output of the decoder into an analog signal, and a low-pass filter that limits a high frequency of an output of the digital-analog conversion circuit to generate the plurality of output differential signals.

3. The isolated amplifier according to claim 2, wherein the abnormal input detection output circuit is configured to cause the in-phase levels of both of a pair of differential signals of the plurality of output differential signals to change by a predetermined level during a period in which the detection signal indicates that an abnormality has occurred.

4. The isolated amplifier according to claim 1, wherein the abnormal input detection output circuit is configured to output a plurality of signals of a predetermined level instead of the plurality of output differential signals, that is, a pair of differential signals, during a period in which the detection signal indicates that an abnormality has occurred.

5. An isolated amplifier comprising: a primary circuit including an analog-digital conversion circuit that converts a plurality of input differential signals applied from a device to be detected into a plurality of digital signals, and an encoder that encodes and outputs an output of the analog-digital conversion circuit; an abnormality detection circuit provided in the primary circuit, detects a level abnormality generated in the plurality of input differential signals, and generates a detection signal; an isolation section that transmits an output of the encoder and the detection signal to a secondary circuit in a state of insulating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, receives the output of the encoder and the detection signal transmitted by the isolation section, includes a decoder that performs a decoding process corresponding to the encoding process, and generates a plurality of output differential signals corresponding to the plurality of input differential signals; and an abnormal input detection output circuit provided in the secondary circuit, directly outputs the plurality of output differential signals generated by the output circuit during a period in which the plurality of input differential signals indicate that no level abnormality is generated, and causes respective in-phase levels of the plurality of output differential signals generated by the output circuit to change and outputs the plurality of output differential signals after the in-phase levels have changed during a period in which the plurality of input differential signals indicate that a level abnormality has occurred. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ An abnormal input detection output circuit is provided in the secondary circuit, and during a period in which the plurality of input differential signals do not indicate a level abnormality, directly outputs the plurality of output differential signals generated by decoding by the output circuit, and during a period in which the plurality of input differential signals indicate a level abnormality, changes the plurality of output differential signals generated by decoding by the output circuit and outputs the plurality of output differential signals after the change, The decoder outputs a plurality of digital output differential signals corresponding to the plurality of input differential signals, The output circuit outputs the plurality of digital output differential signals generated by the decoder as the plurality of output differential signals, The abnormal input detection output circuit changes the logic levels of the plurality of digital output differential signals from the decoder in correspondence with the period in which the abnormality is indicated by the detection signal.

6. The isolation amplifier according to claim 5, wherein The abnormal input detection output circuit outputs the logic levels of the plurality of digital output differential signals from the decoder in synchronization with one edge of a clock, and forcibly changes to one logic level in synchronization with the other edge of the clock during the period in which the abnormality is indicated by the detection signal.

7. The isolation amplifier according to claim 6, wherein The abnormal input detection output circuit forcibly changes the logic levels of the plurality of digital output differential signals from the decoder during the output period of 1 data at timings corresponding to the start timing of the abnormality indicated by the detection signal and the end timing of the abnormality.

8. The isolation amplifier according to claim 6, wherein The abnormal input detection output circuit forcibly changes the logic levels of the plurality of digital output differential signals from the decoder to one logic level and then to the other logic level during the output period of 1 data at timings corresponding to the start timing of the abnormality indicated by the detection signal and the end timing of the abnormality.

9. The isolation amplifier according to claim 5, wherein The abnormal input detection output circuit outputs the plurality of digital output differential signals in synchronization with one edge of a clock, and outputs logic levels different from those during the period other than the period in which the abnormality is indicated by the detection signal in synchronization with the other edge of the clock during the period in which the abnormality is indicated by the detection signal.

10. The isolation amplifier according to claim 5, wherein The decoder outputs not only the plurality of digital output differential signals but also a clock, The output circuit outputs not only the plurality of digital output differential signals but also the clock as the plurality of output differential signals, The abnormal input detection output circuit changes the duty ratio of the clock from the decoder in the period in which the abnormality is indicated by the detection signal and the period other than the same.

11. The isolation amplifier according to claim 5, wherein The abnormal input detection output circuit generates a narrow pulse by reverting immediately after changing to a logic level different from a logic level of the data, in an invalid period in a data period of the plurality of digital output differential signals from the decoder, corresponding to a start timing of generation of the abnormality indicated by the detection signal and an end timing of generation of the abnormality.

12. An abnormal state detection device, comprising: the isolation amplifier according to claim 1; and a detection circuit that detects presence or absence of a level abnormality of the plurality of input differential signals applied from the device to be detected, based on the plurality of output differential signals of the isolation amplifier, and outputs an abnormality detection result to a control circuit.

13. The abnormal state detection device according to claim 12, comprising: a processing circuit that outputs a signal corresponding to the plurality of input differential signals included in the plurality of output differential signals of the isolation amplifier; and a selector that switches the output of the processing circuit and a signal indicating that the plurality of input differential signals have generated an abnormality, based on the abnormality detection result from the detection circuit, and outputs to a common terminal of the control circuit.

14. An abnormal state detection device, comprising: the isolation amplifier according to claim 5; and a detection circuit that detects presence or absence of a level abnormality of the plurality of input differential signals applied from the device to be detected, based on the plurality of output differential signals of the isolation amplifier, and outputs an abnormality detection result to a control circuit.

15. The abnormal state detection device according to claim 14, comprising: a processing circuit that outputs a signal corresponding to the plurality of input differential signals included in the plurality of output differential signals of the isolation amplifier; and a selector that switches the output of the processing circuit and a signal indicating that the plurality of input differential signals have generated an abnormality, based on the abnormality detection result from the detection circuit, and outputs to a common terminal of the control circuit.

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