Anti-skew unit for delay and pulse width adjustment

Abstract

This disclosure relates to an anti-skew unit for delay and pulse width adjustment. The anti-skew system can be used to adjust signal characteristics such as pulse width and edge timing. In one example, the anti-skew system may include multiple timing control units, and each unit may operate in one of multiple different modes according to its respective mode control signal. These modes may include at least a signal delay mode and a signal pulse width adjustment mode. In one example, a first unit in the anti-skew system may be configured to receive a test input signal at a first input node and, in response, provide an anti-skew output signal at a first output node. The anti-skew output signal may be based on the test input signal, the pulse width adjustment provided by the first unit, and a delay signal corresponding to the input signal (provided by subsequent units in the sequence).

Description

Background Technology

[0001] A test system for testing electronic equipment may include a pin driver circuit that provides voltage or current test pulses to the device under test (DUT). In response, the test system may be configured to measure the response from the DUT, for example, to determine whether the DUT meets one or more specified operating criteria.

[0002] In one example, a test system may include dynamic control for transmitting timing signals, including controls for synchronizing or de-synchronizing multiple signals to be provided to or received from the DUT. Timing signals can be used to test various integrated circuit devices. In each test, timing signals can be applied to individual pins of the DUT, and the corresponding response signals can be analyzed. Timing signals can be transmitted to each DUT pin via different paths, and response signals from the DUT can similarly be transmitted to different paths in response analysis circuitry. This difference in propagation paths, or other effects on signal timing or propagation, can affect test results. Various techniques can be used to correct or more precisely control the timing of test signals expected to arrive at the DUT at precise times or synchronously.

[0003] Timing errors are commonly referred to as "skew" in this paper. In early deskew signal processing methods, numerous manually adjustable potentiometers were associated with each pin to ensure timely alignment of the input signal to each pin. The potentiometers could be adjusted whenever the system required recalibration. In another approach, the deskew system can comprise a series of stages for delaying the signal. Coarser stages can delay the signal by a predetermined multiple of the delay interval, while finer stages can provide more precise adjustment of the delay interval. Summary of the Invention

[0004] Among other things, the inventors have recognized that the problem to be solved includes providing a test system that can synchronize timing signals or adjust the edge position or pulse width characteristics of stimulus signals, thereby reducing or eliminating timing errors at the device under test (DUT).

[0005] In one example, a solution to the above problem may include or use an anti-skew system for providing programmable delays. The anti-skew system may be configured to change the edge timing or other characteristics of the test signal provided to the device under test. The anti-skew system may include multiple timing control units coupled in series. A specific unit among the multiple timing control units may include a first input node and a first output node, and the unit may be configured to delay and / or adjust the pulse width of the input signal received at the first input node. The specific unit may also include: an early signal input node coupled to the forward output node or first input node of the preceding unit in the sequence; and a late signal input node coupled to the inverse output node of a subsequent unit in the series. The specific unit may also include a summing circuit configured to provide an intermediate signal by combining a signal modulated by a delayed component based on the unit control code and corresponding data signals at the early and late signal input nodes. The specific unit may also include a pulse width adjustment circuit configured to provide a pulse width-adjusted output signal at the first output node based on the pulse width component of the unit control code and the intermediate signal from the summing circuit.

[0006] In one example, the solution to the above problem may additionally or alternatively include or use a method for providing a programmable delayed signal or a programmable pulse width adjustment signal. Among other things, the method may include using a plurality of series-coupled signal timing control units, wherein each control unit operates in a pulse width adjustment mode, a delay mode, or a pulse width adjustment and delay mode. The method may include: receiving an input test signal at an input node of a first unit of the timing control unit; receiving unit control code; providing a first delay signal to a subsequent unit of the series-coupled timing control unit based on the input test signal; receiving a second delay signal from the subsequent unit at the first unit; and providing a pulse width-adjusted output signal based on the second delay signal. In this example, the delay characteristics and pulse width characteristics of the output signal may be based on information in the unit control code.

[0007] This abstract aims to provide an overview of the subject matter of this patent application. This invention is not intended to provide an exclusive or exhaustive explanation of the invention. Detailed descriptions are included to provide further information regarding this patent application. Attached Figure Description

[0008] To facilitate identification of any particular element or behavior being discussed, one or more of the most significant digits in the reference number refer to the figure number in which the element was first introduced.

[0009] Figure 1A An example of an output signal that is a delayed version of the input signal is shown in general.

[0010] Figure 1BThis section generally illustrates an example of an output signal that is a pulse-width modulated version of the input signal.

[0011] Figure 2A This section generally explains the relationship between delay adjustment codes and signal delay amplitude.

[0012] Figure 2B This roughly illustrates the relationship between pulse width adjustment codes and pulse width duration variations.

[0013] Figure 3 The relationship between delay linearity error and delay adjustment code is explained in general terms.

[0014] Figure 4 An example of the first deskipation system is shown in general.

[0015] Figure 5A An example of a first delay cell array is shown in general.

[0016] Figure 5B An example of a second delay cell array is shown in general.

[0017] Figure 5C An example of a third delay unit array is shown in general.

[0018] Figure 6 An example of a first signal delay circuit is shown in general.

[0019] Figure 7 A diagram of the delayed output signal corresponding to the first signal delay circuit is shown in general.

[0020] Figure 8A An example of a first pulse width adjustment unit array is shown in general.

[0021] Figure 8B An example of a second pulse width adjustment unit array is shown in general.

[0022] Figure 8C An example of a third pulse width adjustment unit array is shown in general.

[0023] Figure 9 An example of a first pulse width adjustment circuit is generally shown.

[0024] Figure 10 The signal timing diagram corresponding to the first pulse width adjustment circuit is shown in general.

[0025] Figure 11 An example of a hybrid unit deskipation system is shown in general.

[0026] Figure 12 A block diagram of the hybrid anti-torsional skew element is shown in general.

[0027] Figure 13 A schematic example of a first hybrid battery is shown in general.

[0028] Figure 14 A schematic example of a second hybrid battery is shown in general.

[0029] Figure 15A An example of a hybrid unit deskipation system is shown in general.

[0030] Figure 15B An example of a hybrid unit deskipation system is shown in general.

[0031] Figure 16 An example of a method using a hybrid unit deskipation system is shown in general. Detailed Implementation

[0032] A test system (such as an automated test equipment (ATE) system) has pin driver circuitry that provides voltage pulse excitation to a device under test (DUT) at specified times, and optionally, comparator circuitry that measures the response from the DUT. The test system can be configured to provide high-fidelity output signal pulses over a relatively large range of output signal amplitudes to accommodate different types of DUTs. In one example, the ATE system may include multiple test channels that can operate substantially independently and in parallel, for example, providing multiple test signals to the same DUT or to different DUTs simultaneously.

[0033] Automated test equipment systems are typically configured to perform tests and determine whether a DUT meets one or more performance specifications. ATE systems can provide precise and reproducible test signals or vectors to determine whether a particular DUT conforms to specified timing or response specifications.

[0034] A key characteristic of ATE systems is their edge placement accuracy. Edge placement, which refers to the fidelity or accuracy of a signal, helps quantify the precision and repeatability of the test signals provided by the system to the DUT. As more channels are added to a single system or die, it may be necessary to compensate for differences in board traces, transmitted signal lengths, parasitic load effects, and other physical characteristics that can affect test signal behavior. These differences between channels can lead to timing errors, such as between signals supplied to different pins on the DUT. In one example, a programmable test signal de-skew unit, also known as a de-skew circuit or timing cursor, can be used to help synchronize vector timing, such as in terms of signal edge position, pulse width, or other signal shape characteristics, thereby reducing or eliminating timing errors on the DUT. In one example, one or more programmable test signal de-skew units may be provided for each of the multiple channels in the system.

[0035] Figure 1A An example of an output signal that is a delayed version of the input signal is shown in general. Figure 1A Includes a first delay example 100a, which illustrates the result of using a delay deskew circuit to delay an input signal in a timely manner. The first delay example 100a includes a first input signal vector 102a and a first output signal vector 104a. The delay deskew circuit can receive the first input signal vector 102a at the input node and provide a first output signal vector 104a as a delayed version of the first input signal vector 102a. Under ideal conditions, the delay deskew circuit delays the first input signal vector 102a by a precise, adjustable amount without altering signal fidelity, shape (e.g., corresponding waveform shape), or bandwidth, to provide the first output signal vector 104a as a copy of the first input signal vector 102a, except for the time offset.

[0036] Figure 1A The example demonstrates when the rise time TR of the input signal... input (For example, corresponding to the first input signal vector 102a) Match the rise time TR of the output signal output (For example, corresponding to the first output signal vector 104a) there is no bandwidth limitation. Delay duration ΔT D The size can be specified by delay adjustment codes, which may include, for example, digital or analog control signals input to the anti-torsion swashplate controller.

[0037] Figure 1B An example of an output signal that is a pulse-width-adjusted version of the input signal is shown in general. Figure 1B Includes a first pulse width example 100b, which illustrates the result of adjusting the pulse width characteristics of an input signal using a pulse width deskew circuit. The first pulse width example 100b includes a second input signal vector 102b and a second output signal vector 104b. For illustrative purposes, the second input signal vector 102b and the second output signal vector 104b are... Figure 1B The example is overlaid to more clearly show the pulse width difference between the input and output signals. The pulse width deskew circuit can receive the second input signal vector 102b at the input node and provide a second output signal vector 104b as a pulse width-adjusted version of the second input signal vector 102b. Ideally, the pulse width deskew circuit adjusts the pulse width of the second input signal vector 102b by a precise, adjustable amount without altering signal fidelity, shape, or amplitude, to provide the second output signal vector 104b as a replica of the pulse of the second input signal vector 102b, except for expansion or contraction in the pulse duration. In the example, the pulse width adjustment ΔT PWThe amplitude can be specified by pulse width adjustment codes, which may include, for example, digital or analog control signals input to the anti-torsion swashplate controller.

[0038] Figure 2A and Figure 2B Examples of different skew adjustment charts are shown in general. The charts illustrate the different skew control signals and the relationship between their respective signal changes. For example, Figure 2A Includes a first skew adjustment chart 202, which shows the relationship between the delay adjustment code and the signal delay amplitude (e.g., corresponding to the signal from...). Figure 1A Example of ΔT D The delay adjustment code can include analog or digital signals and can be provided to the anti-torsion skew circuit to indicate the amount or magnitude of the delay for application, for example... Figure 1A The first input signal vector is 102a. In this example, the delay adjustment code can be one of several different values ​​ranging from a minimum (e.g., zero delay) to a maximum (e.g., the maximum amount of delay that can be provided by the anti-torsion swashplate circuit). Figure 2A In the example, the line in the first skew adjustment chart 202 represents the ideal linear relationship between the delay adjustment code and the corresponding signal delay amplitude.

[0039] Figure 2B Examples include a second skew adjustment chart 204, which illustrates the relationship between the pulse width adjustment code and the magnitude of the pulse width duration variation (e.g., corresponding to the pulse width adjustment code from...). Figure 1B Example of ΔT PW The pulse width adjustment code may include analog or digital signals and may be provided to the anti-torsion skew circuit to indicate the amount or magnitude of the pulse width adjustment for application, for example... Figure 1B The second input signal vector 102b. In the example, the pulse width adjustment code can be one of several different values ​​ranging from a [minimum value] (e.g., representing a decrease in the maximum pulse width that the anti-skew circuit can provide) to a [maximum value] (e.g., indicating an increase in the maximum pulse width that the anti-skew circuit can provide). Figure 2B In the example, the line in the second skew adjustment chart 204 represents the ideal linear relationship between the pulse width adjustment code and the corresponding signal pulse width change amplitude.

[0040] Figure 3The third graph 300 is generally shown, illustrating the relationship between delay linearity error and delay adjustment code. Delay linearity error is sometimes referred to as delay bias. In this example, error bar 302 indicates that the first skew adjustment graph 202 has no linearity error in the ideal deskew relationship shown in Figure 2. In other examples, the relationship can be non-linear, and in this case, error bar 302 will deviate from the horizontal line. Generally, a predictable and repeatable relationship between delay adjustment code and output signal delay is preferable. Non-linearity or unpredictability is undesirable because it introduces edge placement uncertainty, leading to erroneous or inconsistent measurement results. The linearity and predictability of the relationship between pulse width adjustment code and the pulse width adjustment of the signal generated at the output may be equally important.

[0041] Various signal processing circuit topologies can be used to receive input signals and provide output signals that are de-skewed relative to the input signals, for example, in terms of delay or pulse width (e.g., pulse signal duration). Figure 4 An example of a first signal processing circuit or a first deskipation system 400 is generally shown. The example of the first deskipation system 400 includes a delay circuit 406 configured to receive an input signal D at a deskipation input node 402 and, in response, provide an intermediate delayed signal X. The first anti-skip system 400 includes a pulse width adjustment circuit 410 configured to receive the delayed signal X from the delay circuit 406 and, in response, provide an anti-skip signal Q at an output signal node 404.

[0042] In the example, delay circuit 406 includes a cell-based topology. Delay circuit 406 may include an array or series of delay cells, cells D1 to DN, and each cell may be configured to apply the same or different delay to the input signal. Delay circuit 406 may be configured to receive delay adjustment codes, such as from an anti-skew controller, and the delay adjustment codes may specify the delay magnitude to be applied to the input signal, for example, by using one or more delay cells.

[0043] In the example, as few as zero or one delay unit in delay circuit 406 may be used, for example, to provide the minimum signal delay, or all delay units in delay circuit 406 may be used to provide the maximum signal delay. In one example, fewer than all units in delay circuit 406 may be used to provide an intermediate signal delay. Figure 5A , Figure 5B , Figure 5C , Figure 6 and Figure 7 An example of delay circuit 406 is generally shown, as well as examples of delay circuits and signal timing delays.

[0044] exist Figure 4In the example, delay circuit 406 illustrates a parallel connection of multiple different delay units D1 to DN. As further explained in the following example, at least one unit in the delay unit group of delay circuit 406 can be configured to "loop back" or terminate the delay chain. When specifying a small or medium delay amount, one or more units in delay circuit 406 that follow the loop back unit may not be used.

[0045] In the example, the pulse width adjustment circuit 410 includes a cell-based topology. The pulse width adjustment circuit 410 may include an array or series of pulse width adjustment cells, cells PW1 to PWN, and each cell may be configured to apply the same or different pulse width adjustments to the input signal. The pulse width adjustment circuit 410 may be configured to receive pulse width adjustment codes, such as from a correction controller, and the pulse width adjustment codes may specify the amplitude or direction of the pulse width variation to be applied to the input signal, for example, using one or more pulse width adjustment cells.

[0046] In the example, as few as zero or one unit of the pulse width adjustment circuit 410 can be used to provide the minimum pulse width variation, or all units of the pulse width adjustment circuit 410 can be used to provide the maximum pulse width variation. In the example, fewer than all units of the pulse width adjustment circuit 410 can be used to provide an intermediate pulse width variation. Figure 8A , Figure 8B , Figure 8C , Figure 9 and Figure 10 An example of the pulse width adjustment circuit 410 and an example of signal pulse width change are shown in general.

[0047] The pulse width adjustment circuit 410 illustrates a series connection of multiple different pulse width adjustment units PW1 to PWN. Any one or more units can be configured in active pulse width adjustment mode or bypass mode. Units in active mode can affect the pulse width characteristics of the signal, while units in bypass mode can be substantially or completely unused, or can be removed from the signal chain to avoid signal degradation.

[0048] Figure 5A , Figure 5B and Figure 5C An example of a deskipation cell array for providing adjustable signal delay is shown in general. For example, Figure 5A Including the first delay unit array 500a, Figure 5B Including the second delay unit array 500b, while Figure 5C This includes the third delay cell array 500c. Various examples of deskew cell arrays can typically correspond to those from... Figure 4 Example delay circuit 406.

[0049] In each example of the delay cell array, the illustrated array or a portion of a larger array includes three discrete cells labeled "Cell 1", "Cell 2", and "Cell 3". Each cell is configured to pass through the positive input node D. F Receive the input signal, delay the input signal for a specified duration, and then output it through the inverting node Q. R Provides a delayed output signal. If a greater delay than that a specific unit can provide is needed, the specific unit can do so through the forward output node Q. F The signal is sent to the adjacent cell. The specific cell then transmits the signal through the reverse input node D. R The delayed signal is received from the adjacent cell, as explained further below. In each example, the program delay line is a graphical representation of the delay adjustment code relative to the minimum and maximum delays available in the example three-cell array.

[0050] In the example of the first delay unit array 500a, this array provides minimal delay, as shown on the program delay line. In this example, the first unit, Cell 1, is configured in a loopback configuration. The first delay unit array 500a can receive an input signal D, which is then delayed in cell 1 by a positive delay duration Δ. F and reverse delay Δ R It provides a delayed output signal Q. In the example of the first delay unit array 500a, the total delay from the input signal D to the delayed output signal Q is (Δ). F +Δ R ).

[0051] In the example of the second delay unit array 500b, this array provides a first intermediate delay greater than the minimum delay, such as Figure 5B The programming delay is shown on the line. The first intermediate delay is generated using a combination of Cell 1 and the adjacent Cell 2, where Cell 1 is configured in a pass-through configuration and Cell 2 is configured in a loop-back configuration. As shown, the input signal D enters the correction circuit, passes through Cell 1 to Cell 2, and then returns to Cell 1, exiting the correction circuit as the delayed output signal Q. The total delay in this example is (2Δ) F +2Δ R Because the signal is delayed Δ by the positive direction of Cell 1. R The forward delay Δ of Cell 2 F The reverse delay Δ of Cell 2 R and the inverse delay Δ of Cell 1 R Delay.

[0052] In the example of the third delay unit array 500c, the array provides a second intermediate delay that is greater than a minimum delay and less than a first intermediate delay. This delay is provided by interpolation between an early delay signal and a delayed delay signal, wherein unit 1 is configured for interpolation and unit 2 is configured for loopback. The early delay signal can be generated by delaying the input signal D by a first delay amount, such as the positive delay Δ of unit 1. F The total delay is Δ F The delayed signal can be delayed by a delay of Δ. F The early delay signal is generated, and the positive delay Δ of delay unit 2 is... F and the reverse delay Δ of unit 2 R The total delay is (2ΔF + ΔR). Interpolation between the early and late delayed signals will result in a total delay between ΔF and ΔR. F and (2Δ F +Δ R The interpolated delay signal is then delayed by unit 1 in the reverse direction by Δ. R It provides a delayed output signal Q, with a total delay of 1×(Δ). F +Δ R ) and 2×(Δ F +Δ R Between ), the anti-torsional skew can provide any delay between the minimum delay and the first intermediate delay.

[0053] The three-cell array example can be extended to understand how a deskew system with many cells can provide a delay between arbitrary minimum and maximum delays. By selecting the middle cell (e.g., cell n) in an interpolation configuration, placing all previous cells (e.g., cells 1 to (n-1)) in a pass-through configuration, and placing the adjacent cell after cell n (e.g., cell (n+1)) in a loop-back configuration, n×(Δ) can be provided. F +Δ R ) and (n+1)×(Δ F +Δ R The delay between the minimum and maximum delays can be adjusted by changing which cell is cell n, or by providing it in the interpolation configuration, for example, by keeping all previous cells in a pass-through configuration and keeping the next or subsequent cells in a loop-back configuration.

[0054] Figure 6An example of a first signal delay circuit 600 that can be used to generate a delayed signal is shown in general. In the example, the first signal delay circuit 600 includes an example of a delay circuit that can be used in one or more delay units, for example, to interpolate between two input signals and generate an output signal with a controllable delay (see example...). Figures 5A-5C (Discussion). The first signal delay circuit 600 includes a shunt 604 (e.g., a circuit configured to distribute or allocate a current signal), the shunt 604 being configured to receive a source current signal I from the current source 602. CTRL The source current signal is divided into early and late current I in each of the respective signal paths, including the first current signal path 606 and the second current signal path 608. EARLY and I LATE The current divider 604 divides or distributes the source current signal I based on a specified delay amount or delay duration. CTRL , making I EARLY and I LATE The sum equals I CTRL The first current signal path 606 includes the early switch SW. EARLY And the second current signal path 608 includes a late switch SW LATE The early and late switches are driven by the input signals at the early signal input node 610 and the late signal input node 612, respectively. After the early and late switches, the first and second current signal paths are coupled to the summing node 618, which is also coupled to the load resistor 616 and the capacitor 614.

[0055] In the example, Figures 5A to 5C The delay units in the example may each include or include one or more instances of the first signal delay circuit 600. In the first example, the early signal input node 610 may be configured to receive a positive input signal V. EARLY For example, this corresponds to the input signal D, while the late signal input node 612 may not be used. For example, V at the summation node 618... OUT The output can correspond to the positive output node Q. F In the second example, the early signal input node 610 can be configured to receive the positive input signal V. EARLY For example, corresponding to the positive output node Q F The signal at the location, and the late signal input node 612 can be configured to receive the inverted input signal V. LATE For example, corresponding to the reverse input node D R Signals at locations such as V at summation node 618. OUT The output can correspond to the inverted output node Q. R .

[0056] Figure 7 An example illustrating the relationship between the summing node signal and the source current signal is given in general. Examples with different delays are shown below. Figure 7 Examples include a delayed output signal diagram 700, which shows the voltage V at the summation node 618 of the first signal delay circuit 600. OUT The delayed output signal diagram 700 includes a first trace 702 and a second trace 704, respectively, corresponding to circuit configurations providing minimum and maximum delays. The first trace 702 corresponds to a circuit configuration in which current separator 604 provides a 1-ampere current signal to a first current signal path 606 and does not provide a current signal to a second current signal path 608. This causes the summing node 618 to charge to an intermediate scale voltage of 0.5V at time T1, because the signal V... EARLY At time T EARLY The signal transitions from low to high at early signal input node 610. The second trace 704 corresponds to a circuit configuration where current separator 604 provides a 1-ampere current signal to the second current signal path 608 and does not provide a current signal to the first current signal path 606. This causes summing node 618 to charge to 0.5V at time T4, due to the fact that at time T... LATE Signal V LATE The signal transitions from low to high at the late signal input node 612.

[0057] The delayed output signal diagram 700 includes a third trace 706 and a fourth trace 708, which show intermediate delays, such as when the current separator 604 divides the source current signal I between the first current signal path 606 and the second current signal path 608. CTRL For example, the third trace 706 corresponds to a circuit configuration in which the first current signal path 606 carries a larger current signal than the second current signal path 608, causing the summing node 618 to charge to 0.5V at time T2. The fourth trace 708 corresponds to a circuit configuration in which the second current signal path 608 carries a larger current than the first current signal path 606, causing the summing node 618 to charge to 0.5V at time T3.

[0058] therefore, Figure 7 The example generally illustrates that the first signal delay circuit 600 can generate a signal that is selectively and adjustablely delayed relative to the input signal based on the amount of current supplied to each of the first current signal path 606 and the second current signal path 608 by the current separator 604. In the third trace 706, where a relatively larger amount of current is allocated to the first current signal path 606, the voltage V... OUTAt the transition at time T2, compared to the maximum delayed transition at time T4, this is closer to the minimum delayed transition at time T1. As more current is delivered through the current shunt 604 to the second current signal path 608, the resulting signal transition shifts closer to the maximum delayed transition, for example, corresponding to the fourth trace 708. Thus, the source current signal I... CTRL It can be divided in any proportion or ratio to provide an intermediate amount of latency between the minimum and maximum latency.

[0059] Refer again Figure 7 The conversion rate of the first trace 702, corresponding to the minimum delay, can be substantially the same as the conversion rate of the second trace 704, corresponding to the maximum delay. Therefore, from T... EARLY The delay to T1 can be compared with the delay from T. LATE The latency to T4 is essentially the same. This also means that the latency from T1 to T4 is roughly the same as the latency from T2 to T4. EARLY To T LATE The delays are basically the same. Therefore, the resulting signal transformation can be signal V. EARLY and V LATE Interpolation between and a fixed delay (e.g., T1–T) EARLY Or T4–T LATE A function of ), for example, can be derived from the inverse delay Δ. R This interpolation can also be interpreted as 0 and (T). LATE –T EARLY The adjustable delay between I and I provided by the current separator 604 is... EARLY and I LATE The relationship or values ​​between them are determined.

[0060] Figure 8A , Figure 8B and Figure 8C Examples of different configurations of units in a pulse width adjustment unit array are shown in general, for example, for providing signals with adjustable pulse widths. For example, Figure 8A Including the first pulse width adjustment unit array 800a, Figure 8B Including the second pulse width adjustment unit array 800b, Figure 8C This includes the third pulse width adjustment unit array 800c. Various examples of pulse width adjustment unit arrays can typically correspond to those from... Figure 4 Example of a pulse width adjustment circuit 410.

[0061] Each of the pulse width adjustment (PWM) unit array examples shown includes N PWM units labeled “Cell PW1” to “Cell PWN”. Each unit can be configured in an active mode where the input signal receives PWM adjustment, or in a bypass mode where the input signal remains unchanged. In one example, each unit is configured to receive an input signal D through a positive input node, adjust the input signal by a specified PWM adjustment amount, and then provide a delayed output signal Q through an output node. If the required PWM adjustment amount exceeds what a single battery can provide, multiple batteries can be placed in active mode. The example includes a programmed PWM line, which is a graphical representation of the PWM adjustment code relative to the minimum (e.g., corresponding to the maximum decrease in PWM width) and maximum (e.g., corresponding to the maximum increase in PWM width) values ​​available using the array.

[0062] In the example of the first pulse width adjustment unit array 800a, the array can provide intermediate pulse width adjustment, as shown on the programmed pulse width adjustment line. In this example, not all N pulse width adjustment units are configured in active mode or pulse width adjustment mode, and other units in the array are configured in bypass mode. The first pulse width adjustment unit array 800a can receive an input signal D, for example, having a pulse width duration ΔT2 at the first unit Cell PW1, and in response can provide an output signal Q, for example, having a different pulse width duration ΔT1. In the example of the first pulse width adjustment unit array 800a, the first pulse width adjustment unit PW1 is configured to reduce the pulse width characteristic of the input signal such that ΔT2 > ΔT1. In other words, since the programmed pulse width adjustment indicates a value less than the intermediate value, the first pulse width adjustment unit PW1 can be configured to apply negative pulse width adjustment, such that the output signal has a smaller pulse width relative to the input signal.

[0063] In the example of the second pulse width adjustment unit array 800b, the array effectively provides zero pulse width adjustment, as shown on the programmed pulse width adjustment line at the middle scale. In this example, each of the N pulse width adjustment units is configured in bypass mode. The second pulse width adjustment unit array 800b can therefore receive an input signal D, for example, having a pulse width duration ΔT2 at the first unit Cell PW1, and in response can provide an output signal Q, for example, having a pulse width duration ΔT2 of essentially the same.

[0064] In the example of the third pulse width adjustment unit array 800c, this array can provide maximum pulse width adjustment, as shown by the programmed pulse width adjustment line. In this example, all N pulse width adjustment units are configured in active mode, or pulse width adjustment mode. The third pulse width adjustment unit array 800c can receive an input signal D, for example, having a pulse width duration ΔT2 at the first unit Cell PW1, and in response can provide an output signal Q, for example, having a different pulse width duration ΔT3. In the example of the third pulse width adjustment unit array 800c, each of the N pulse width adjustment units PW1 to PWN can be configured to extend or increase the pulse width characteristic of the input signal such that ΔT3 > ΔT2; however, units can be similarly configured to decrease the pulse width characteristic of the input signal such that ΔT3 < ΔT2.

[0065] exist Figures 8A to 8C In the example, each of the N units can introduce some negligible or non-negligible jitter that can affect the actual pulse width of the output signal. Each unit can introduce jitter in bypass mode or active or pulse width modulation mode. That is, because the signal flows serially through N different units, the output signal is affected by jitter or other signal coloring that may be introduced by any or all of the units. Figures 8A to 8C In the example, total jitter can be a function of the number of units N used in the system, where N is the number of units used to provide a specified maximum pulse width adjustment.

[0066] Figure 9 An example of a first pulse width adjustment circuit 900 that can be used to generate a pulse width adjustment signal is generally shown. In this example, the first pulse width adjustment circuit 900 includes an example of a pulse width adjustment circuit that can be used in one or more pulse width adjustment units, for example, to provide a controlled pulse width adjustment signal. The first pulse width adjustment circuit 900 can be configured to receive an input signal D (e.g., as a differential signal including components D and D-bar) at a pulse width circuit input 906, and in response, provide a corresponding output signal Q (e.g., as a differential signal) at a pulse width circuit output 908. The output signal Q may have a different pulse width characteristic than the input signal D.

[0067] The first pulse width modulation circuit 900 includes a first differential pair 910, such as first and second transistors N1 and N2, configured to receive an input signal. The first differential pair 910 is coupled to a common base 914, such as third and fourth transistors N3 and N4, and corresponding load resistors. The first differential pair 910 and the common base 914 provide a cascaded configuration. The cascode output can drive an emitter follower pair 912, such as fifth and sixth transistors N5 and N6. Figure 9 In the example, the emitters of the first and second transistors N1 and N2 of the first differential pair 910 are biased by a common current source I2, and the emitters of the fifth and sixth transistors N5 and N6 are biased by their respective current sources I4 and I5.

[0068] In one example, the output from the cascaded common gate may include a first pulse-width timing signal 902 and a second pulse-width timing signal 904. The amplitude characteristics of the timing signals are affected by the value of the load resistor and the current signals provided to the cascaded common gate, respectively. For example, the first current source I1 or the first adjustable current source 916 and the third current source I3 or the second adjustable current source 918 may include their respective hold-active current sources configured to provide a corresponding bias signal in each leg of the cascaded common gate, thereby ensuring a minimum voltage drop across the load resistor. The pulse-width timing signal or the output from the cascaded common gate may each include a corresponding combination or superposition of the voltage at the load resistor and the voltage switched through the corresponding branch of the first differential pair 910. The voltage across the load resistor, or the first pulse-width timing signal 902 and the second pulse-width timing signal 904, is therefore a function of the bias signals provided by the first adjustable current source 916 and the second adjustable current source 918. In other words, a variable current source, such as a first adjustable current source 916 and a second adjustable current source 918, can be used to adjust the common mode of the first pulse width timing signal 902 and the second pulse width timing signal 904 of the first pulse width adjustment circuit 900. By adjusting the common mode signal, the output signal pulse width can be provided as a result or a corresponding change.

[0069] Figure 10 Example 1000 is generally shown, illustrating the relationship between an example of a cascaded output from a first pulse width modulation circuit 900 and its differential output signal (e.g., from a pulse width modulation circuit output 908). In Example 1000, the output signal V OUT This represents the relationship between the intersection points of the output signal Q and the Q-bar. Output signal V OUT The pulse width characteristic depends on the relationship between the first pulse width timing signal 902 and the second pulse width timing signal 904.

[0070] exist Figure 10In the example, the crossover of the initial first pulse width timing signal 902a and the initial second pulse width timing signal 904a corresponds to a transition in the output signal, such as from low to high or from high to low. The common mode of the two signals can be adjusted independently, for example, by controlling the amplitude of the bias signal provided by the first adjustable current source 916 or the second adjustable current source 918. In one example, the adjusted first pulse width timing signal 902b may correspond to a decrease in the amount of bias current provided by the first adjustable current source 916, and the adjusted second pulse width timing signal 904b may correspond to an increase in the amount of bias current provided by the second adjustable current source 918. Due to the change in bias voltage, the crossover point of the adjusted first pulse width timing signal 902b and the adjusted second pulse width timing signal 904b can be shifted in time and represents the output signal V. OUT The pulse width can be changed accordingly.

[0071] Refer again Figure 4 The first anti-skew system 400 includes a delay circuit 406 and a pulse width adjustment circuit 410, which may include, for example, separate functional blocks or circuits. Each of the delay circuit 406 and the pulse width adjustment circuit 410 may have different requirements in terms of die size, cost, power consumption, control circuitry, and other characteristics. In an example of the pulse width adjustment circuit 410, the units constituting the pulse width adjustment circuit 410 are coupled in series, and in some examples, each unit is powered during operation. That is, the individual bias sources or current sources in the pulse width adjustment units may be active and may contribute to the overall power consumption of the system. In one example, the series-coupled units may each introduce jitter or edge placement deviation from the original input signal, including when the pulse width adjustment unit is in bypass mode or minimum adjustment mode. For example, jitter accumulates as the signal passes through each differential pair or cascaded amplifier in each pulse width adjustment unit.

[0072] In one example, solutions to these and other problems associated with the first anti-skew system 400 may include or utilize a cell-based anti-skew system topology with hybrid cells that include delay and pulse width modulation capabilities. Through the delay and pulse width modulation capabilities in each hybrid cell of the system, support or control circuitry can be integrated and infrastructure shared. This integrated architecture enables energy savings and reduces the die area of ​​the test system. In one example, the system may include cells that can be configured to impart signal delay or pulse width modulation characteristics, and fewer than all cells in the system can be used. Using fewer cells or a minimum number of cells helps reduce jitter and contributes to lower power consumption.

[0073] Figure 11An example of a hybrid unit deskipation system 1100 is shown in general. The hybrid unit deskipation system 1100 can be configured to receive an input signal D, process the signal using one or more hybrid units, and then provide an output signal Q deskipated relative to the input signal, for example, in terms of delay and / or pulse width. Examples of the hybrid unit deskipation system 1100 include a unit-based system having an array of N different hybrid units labeled H1 to HN. Although... Figure 11 The example shows the hybrid unit deskew system 1100 as including only a hybrid unit, but other systems may include combinations of hybrid units, delay units (e.g., one or more units from the example of delay circuit 406), or pulse width adjustment units (e.g., one or more units from the example of pulse width adjustment circuit 410).

[0074] The hybrid unit anti-skew system 1100 can be configured to receive hybrid unit control code, such as from an anti-skew controller. The hybrid unit control code may include one or more signals configured to specify configuration instructions for, for example, one or more hybrid units, such as information about the magnitude of a delay to be applied to an input signal (e.g., delay adjustment code), or information about the magnitude or direction of a pulse width variation applied to the input signal (e.g., pulse width adjustment code). In one example, the information in the hybrid unit control code can be used to configure each hybrid unit in the system as a delay unit or a pulse width adjustment unit.

[0075] In one example, one or more preamble units or first units receiving the input signal can be configured as pulse width adjustment units, and subsequent units can be configured as delay units. In another example, a mixing unit can be configured to delay and adjust the pulse width of the input signal. In one example, at least one unit in the mixing unit deskew system 1100 can be configured as a loopback unit, where the signal path direction returns and propagates through a return path in one or more previous units in the system. In other examples, one or more units may include a signal tap from which a delayed signal or a pulse width adjustment signal can be received or monitored.

[0076] In one example, a minimum number of units in the hybrid unit anti-skew system 1100 may be used, for example, to provide minimum signal delay or minimum pulse width adjustment. In another example, all units in the hybrid unit deskew system 1100 may be used to provide maximum signal delay or maximum pulse width adjustment. In one example, fewer than all units in the delay circuit 406 may be used to provide intermediate signal delay or intermediate pulse width adjustment, for example, based on information or instructions in the hybrid unit control code.

[0077] Figure 12 A block diagram example of the mixing unit 1202 is shown in general. The mixing unit 1202 may include components from... Figure 11 Examples of one of the mixing units H1 to HN. Mixing unit 1202 may include a configuration for receiving an input signal (e.g., V). IN The positive input node 1204 of the circuit provides a positive output signal to the subsequent unit at the positive output node 1206, or an output signal (e.g., V) at the negative output node 1210. OUT The mixing unit 1202 can be configured to receive control signals, such as those from... Figure 11 The example shows the control code for the mixing unit, and the information in the control signals can be used to configure the mixing unit 1202 to provide a delay, to provide pulse width adjustment, or both. The information in the control signals can define the magnitude of the delay or pulse width adjustment.

[0078] The mixing unit 1202 may include a positive signal delay circuit 1212 in the positive path between the positive input node 1204 and the positive output node 1206. The mixing unit 1202 may additionally or alternatively include a reverse signal delay circuit 1216 in the reverse path between the reverse input node 1208 and the reverse output node 1210. The positive signal delay circuit 1212 and the reverse signal delay circuit 1216 may be configured to provide a fixed or variable signal delay to the signal at their respective inputs, for example, using information from the unit control code.

[0079] The mixing unit 1202 includes a pulse width adjustment unit circuit 1218 configured to provide pulse width adjustment. Figure 12 In one example, the pulse width adjustment unit circuit 1218 is located in the reverse signal path between the inverted signal delay circuit 1216 and the inverted output node 1210. In other examples, the pulse width adjustment unit circuit 1218 may be located elsewhere in the mixing unit 1202, such as in the forward path between the forward signal delay circuit 1212 and the forward output node 1206, or between the forward input node 1204 and the forward signal delay circuit 1212, or elsewhere.

[0080] Examples of the hybrid unit 1202 can be configured to provide an adjustable delay, for example, using information about the Early, Mid, or Middle and Late data signal paths. U.S. Patent No. 10,547,294 to Mort et al., entitled “Anti-skew Circuit for Automated Test Systems,” the entire contents of which are incorporated herein by reference, illustrates various examples of delay circuits that can be configured using Early, Mid, or Middle and Late signal paths, such as in… Figure 12 See section 17 and its corresponding description. For the sake of clarity regarding the hybrid units presented herein, the discussion is generally limited to example circuits or units with two data signal paths, rather than those from [the original text]. Figure 12 All three Early, Mid, and Late data signal paths in the example of Mort et al.

[0081] exist Figure 12 In the example, the mixing unit 1202 includes a summing circuit 1214 that can receive information from the Early, Mid, and Late signal paths and can combine the information to provide a delayed or pulse width-adjusted signal at the inverted output node 1210, for example, through an inverted signal delay circuit 1216 or a pulse width adjustment unit circuit 1218.

[0082] Figure 13 An example of a first mixing unit 1300 is generally shown. The first mixing unit 1300 is configured to provide selectable delay and selectable pulse width adjustment to an input signal D. The first mixing unit 1300 includes a forward path circuit 1302 and a reverse path circuit 1304. In one example, the circuitry in the forward path circuit 1302 or the reverse path circuit 1304 can be used to adjust the pulse width or delay characteristics of the input signal, for example, according to instructions from mixing unit control code. In the example, current sources in one or more of the forward path circuit 1302 and the reverse path circuit 1304 can be adjusted to provide delay or pulse width adjustment.

[0083] In the example, the forward path circuit 1302 includes a first instance of the first pulse width adjustment circuit 900. For example, the input of the forward path circuit 1302 can be configured to receive a differential input signal D. This input may include signals from... Figure 9 The example pulse width circuit input 906. The output of the forward path circuit 1302 can be configured to provide a positive signal output, and may include, for example, a signal from... Figure 9 The example pulse width circuit outputs 908.

[0084] In the forward path circuit 1302, the first to fifth current sources I1 to I5 can be configured to provide their respective fixed bias currents. Each signal can have the same or different current amplitudes and can be the minimum current amplitude that allows the forward path circuit 1302 to essentially function as a through circuit without applying pulse width modulation to the input signal.

[0085] In the example, the reverse path circuit 1304 includes a second instance of a first pulse width adjustment circuit 900 coupled to the late path differential pair 1306 and the early path differential pair 1308 of the delay circuit. The late path differential pair 1306 can receive a bias current signal from the seventh current source I7 and can receive an inverted signal D. R For example, from adjacent cells (e.g., subsequent cells) in a hybrid cell array. The early path differential pair 1308 of the delay circuit can receive a bias current signal from the sixth current source I6 and can provide a delayed signal to a second instance of the first pulse width adjustment circuit 900. The delayed signal can be relative to the input signal D and / or relative to the received inverted signal D. R Delay. The delay characteristics of the reverse path circuit 1304 can be set or adjusted by the magnitude of the current signal used to bias the differential pair of the delay circuit board strip path 1306 or the differential pair of the early path path 1308 of the delay circuit. That is, the applied delay amplitude can be based on the amplitude of the current provided by the sixth current source or the seventh current source or both. In one example, the magnitude of the current signal provided by the sixth and seventh current sources can be set by the mixing unit control code.

[0086] In the example, a second instance of the first pulse width adjustment circuit 900, within the reverse path circuit 1304, can be used to adjust the reverse signal D. R The pulse width adjustment circuit 900 may be a delayed version of the inverted signal provided by the later path differential pair 1306 and the earlier path differential pair 1308 of the delay circuit. A second instance of the first pulse width adjustment circuit 900 may include corresponding current sources, such as an eighth current source I8 and a ninth current source I9. The amplitude of the pulse width adjustment imparted by the inverted path circuit 1304 can be set by adjusting the amplitude of the current signals provided by the eighth and ninth current sources, for example, based on information from the mixing unit control code. The output stage of the second instance of the first pulse width adjustment circuit 900 may be biased by the tenth and eleventh current sources I10 and I11, respectively, and may provide the output signal Q from the inverted path circuit 1304 of the first mixing unit 1300.

[0087] Figure 14An example of the second mixing unit 1400 is shown in general. Similar to the first mixing unit 1300, the second mixing unit 1400 is configured to provide selectable delay and selectable pulse width adjustment to the input signal D. The second mixing unit 1400 includes a forward path circuit 1302 and a reverse path circuit 1304.

[0088] In an example of the second mixing unit 1400, a first instance of the forward path circuit 1302 includes first and third current sources I1 and I3, which are configured to provide adjustable current, for example, based on mixing unit control code. The first and third current sources can be used to introduce pulse width modulation into the signal processed by the forward path circuit 1302. That is, the forward path circuit 1302 can be used to provide pulse width modulation to the input signal D, such that the forward path output signal Q... F It is a pulse width modulation version of the input signal.

[0089] In the example of the second hybrid battery 1400, the eighth current source I8 and the ninth current source I9 in the reverse path circuit 1304 can be configured to provide a fixed bias current. The corresponding current signals can have the same or different current amplitudes, and can be the minimum current amplitude that allows the reverse path circuit 1304 to essentially act as a pass-through circuit without imposing pulse width modulation on the input signal. In one example, the sixth current source I6 and the seventh current source I7 can be used to set the delay characteristics of the signal processed by the reverse path circuit 1304. That is, similar to the above... Figure 13 In the example described in the discussion, the reverse path circuit 1304 can use the delayed later path differential pair 1306 to receive the reverse signal D. R For example, from adjacent cells in a hybrid cell array, and the early path differential pair 1308 of the delay circuit can provide a delayed signal to a second instance of the first pulse width adjustment circuit 900. The delayed signal can be relative to the input signal D and / or relative to the received inverse signal D. R Delay. Figure 14 In the example, a second instance of the first pulse width adjustment circuit 900 can be configured to provide minimum pulse width adjustment or not provide pulse width adjustment.

[0090] In one example, further pulse width adjustment or control can be provided by adjusting the first current source I1, the third current source I3, the eighth current source I8, and the ninth current source I9 together. That is, pulse width adjustment circuitry can be provided in each of the forward path circuit 1302 and the reverse path circuit 1304, and can be used together to provide further pulse width adjustment or control. Control circuitry can be provided to generate hybrid unit control code, which can be used, for example, to control the amplitude of the current signals provided by any one or more of the first to eleventh current sources I1 to I11.

[0091] Pulse width modulation (PWM) and delay circuitry can therefore be combined or integrated on or within a common unit, for example, in unit-based anti-skew systems, such as the hybrid unit anti-skew system 1100. Combining PWM and delay circuitry can facilitate resource and signal path sharing, resulting in a reduction in overall system or device size, for example, relative to [other components]. Figure 4 The example is the first deskipation system 400. Furthermore, a hybrid unit deskipation system 1100 can be used to achieve power savings relative to the first deskipation system 400, since unused units can be de-energized and therefore may not contribute to the overall system current consumption. Additionally, the hybrid unit deskipation system 1100 can be used to improve signal jitter, as fewer than all units in the system can be used to provide the test signal.

[0092] In one example, the mixing unit control code may include a delay code and a pulse width code. The delay code may include an analog or digital signal configured to specify the amount of delay that a particular mixing unit is configured to impart or apply to an input signal. The delay code may include, for example, a 64-bit digital word. The pulse width code may include an analog or digital signal configured to specify the amount of pulse width adjustment that a particular mixing unit is configured to impart or apply to an input signal. In one example, the pulse width code may include 33 codes per unit, such as neutral, negative, and positive codes. A negative code may indicate a decrease in the desired pulse width, while a positive code may indicate an increase in the desired pulse width. Zero, intermediate, or neutral codes may indicate no change in pulse width. In this example, the mixing unit control code may also include a unit address code associated with the delay code and pulse width code, which may be configured to indicate a specific unit in the unit array.

[0093] In one example, each unit in a hybrid unit deskew system can be configured to receive a minimum pulse width adjustment (e.g., zero seconds), a maximum pulse width adjustment (e.g., ±75 picoseconds), or an intermediate pulse width adjustment (e.g., between zero and ±75 picoseconds). For discussion purposes only, 75 picoseconds is used as an example of the maximum pulse width adjustment magnitude for each unit. Other maximum pulse width adjustment values ​​can be used similarly.

[0094] In one example, each unit in a hybrid unit deskew system can be configured to have a minimum delay (e.g., zero seconds), a maximum delay (e.g., 150 picoseconds), or an intermediate delay (e.g., between zero and 150 picoseconds). For discussion purposes only, 150 picoseconds is used as an example of the maximum delay adjustment magnitude for each unit. Other maximum delay adjustment values ​​can be used similarly.

[0095] In one example, the preceding cell in an anti-skew system can be configured for maximum delay before subsequent cells can be used for delay, or the preceding cell in an anti-skew system can be configured for maximum pulse width adjustment before subsequent cells can be used for pulse width adjustment. In some examples, a hybrid cell can be configured for maximum delay so that the same cell can be configured for pulse width adjustment.

[0096] Figure 15A A first example 1500a of an anti-skew system is generally shown. In the first example 1500a, a first unit is configured as a pulse width adjustment unit, second to seventh subsequent units are configured as delay units, and a ninth unit is configured as a termination unit or loopback unit. In this example, the pulse width adjustment unit is configured to provide a delay of 150 picoseconds. In the configuration of the first example 1500a, the anti-skew system can be configured to delay the input signal by at least 150 picoseconds and at most 1.2 nanoseconds (e.g., corresponding to a maximum delay of 150 picoseconds at each of the eight different units). In the first example 1500a, only one unit is configured as a pulse width adjustment unit, so the anti-skew system can be configured to provide a pulse width adjustment of 75 picoseconds or less, for example, depending on the value of the delay code.

[0097] In one example, fewer than all the units in the first example 1500a may be used. For example, a first unit (e.g., configured as a pulse width adjustment unit) and a second unit (e.g., configured as a delay unit) may be used. The third cell may be unused or configured as a termination cell or a loopback cell. In this example, units three through nine may be partially or completely unused and may be unpowered or minimally powered. In this example, the system may provide pulse width adjustments of 75 picoseconds or less (e.g., using the first unit) and may provide delay adjustments between 150 picoseconds and 300 picoseconds (e.g., using the first and second units).

[0098] Figure 15B A second example 1500b of the anti-skew system is generally shown. In the second example 1500b, the first and second units are configured as pulse width adjustment units, the third through seventh subsequent units are configured as delay units, and the ninth unit is configured as a termination unit or loopback unit. In this example, the pulse width adjustment unit is configured to provide a delay of 300 picoseconds. In the configuration of the second example 1500b, the correction system can be configured to delay the input signal by at least 300 picoseconds and at most 1.2 nanoseconds (e.g., a maximum delay of 150 picoseconds corresponding to each of the eight different units). In the second example 1500b, since two units are configured to provide pulse width adjustment, the total pulse width adjustment can be 150 picoseconds or less (e.g., each of the first and second units is 75 picoseconds or less).

[0099] Figure 16 Generally, a method 1600 for adjusting the timing of test signals supplied to a device under test using multiple series-coupled signal timing control units is shown. In an example, method 1600 may include or use an anti-skew system comprising one or more hybrid units, such as those from... Figure 11 Example of a hybrid unit anti-torsional skew system 1100. In the example, each timing control unit or hybrid unit can be configured to operate in a pulse width adjustment mode, a delay mode, or a mode in which the pulse width and delay can be adjusted.

[0100] Method 1600 may include, in block 1602, receiving an input test signal at the input of a first unit in the anti-skew system. For example, block 1602 may include receiving a differential input signal (e.g., Q and Q-bar, or differential voltage signal V) at the input of a first hybrid unit in the hybrid unit anti-skew system 1100. IN In block 1604, method 1600 may include receiving first and second mode control codes in the first and subsequent second units of the anti-torsional skew system. The mode control codes may include, for example, corresponding hybrid unit control codes or portions of hybrid unit control codes. Figure 16In the example, block 1604 follows block 1602; however, these blocks can be executed in a different order or can be executed substantially simultaneously.

[0101] In one example, at block 1606, method 1600 may include providing a first delayed signal from a first unit to a subsequent second unit based on an input test signal. In one example, the first delayed signal may be a delayed version of the input signal. The first delayed signal may optionally be delayed by zero seconds, corresponding to minimum delay or edge-free timing adjustment. In response to receiving the first delayed signal, the subsequent second unit may process the signal and provide a second delayed signal. The subsequent second unit may process the signal to provide the second delayed signal by changing the signal's delay, pulse width, or other characteristics.

[0102] In block 1608, method 1600 may include a first unit in the anti-skew system receiving a second delayed signal from a subsequent second unit. In response to receiving the second delayed signal, the first unit may process the signal and provide a deskew signal. The first unit may process the signal by changing at least one pulse width characteristic of the signal and optionally a delay or other characteristic to provide the deskew signal. In block 1610, method 1600 may include providing the deskew signal as an output from the first unit (e.g., as a differential output signal). The deskew output signal may therefore include a signal corresponding to the input test signal but may have different signal delay characteristics, and may have a pulse width characteristic different from the input test signal.

[0103] Various aspects of this disclosure can help provide solutions to problems related to test systems identified herein. For example, delay and pulse width adjustment circuitry, which may include portions of the same unit in a cell-based anti-skew system, can be used to help compensate for mismatches in high-speed data signal paths. In some examples, the solutions described herein may include or use a combination of delay and pulse width adjustment circuitry to control pulse duration and signal edge position, and can help reduce or eliminate timing errors, such as timing errors between multiple different signals or channels in a test system.

[0104] In one example, aspect 1 may include or use a subject matter (e.g., apparatus, system, device, method, means for performing an action, or a device-readable medium or article of manufacture that includes instructions which, when performed by the device, may cause the device to perform an action), for example, it may include an anti-skew system for providing a test signal to a device under test. In aspect 1, the system may include a plurality of timing control units coupled in series, wherein each unit is operable in one of a plurality of different operating modes according to its respective mode control signal, the different modes including a signal delay mode and a signal pulse width adjustment mode. In one example, in aspect 1, a first unit of the plurality of timing control units includes a first input node configured to receive a test input signal, an inverting input node configured to receive a delayed signal from a subsequent unit in the sequence based on the test input signal, a first output node configured to provide an anti-skew output signal, and a timing adjustment circuit configured to adjust the pulse width of at least one of the test input signal or the delayed signal to provide the anti-skew output signal.

[0105] Aspect 2 may include or use, or optionally combine with the subject matter of aspect 1, to optionally include: in the signal pulse width adjustment mode, the first unit is configured to provide the anti-skew output signal having pulse width and delay characteristics different from the test input signal.

[0106] Aspect 3 may include or use, or optionally combine with the subject matter of aspect 2, to optionally include: the first unit includes a positive output node coupled to the subsequent unit and a negative input node coupled to the subsequent unit, and the anti-skew output signal may be based on a delayed signal received from the subsequent unit at the negative input node.

[0107] Aspect 4 may include or use, or optionally combine with the subject matter of one or any combination of aspects 1 to 3, to optionally include: control circuitry configured to provide corresponding first and second mode control signals to the first unit and the subsequent unit. In aspect 4, the first unit may be configured to operate in the signal pulse width adjustment mode in response to the first mode control signal, and the subsequent unit may be configured to operate in the signal delay mode in response to the second mode control signal.

[0108] Aspect 5 may include or use, or optionally combine with the subject of aspect 4, to optionally include or use control circuitry configured to provide a pulse width control signal to the timing adjustment circuitry in the first unit to control the amplitude of the pulse width of the anti-skew output signal.

[0109] Aspect 6 may include or use, or optionally combine with the subject of aspect 4, to optionally include or use control circuitry configured to provide a delay control signal to the subsequent unit to control the edge timing of the delay signal relative to the test input signal.

[0110] Aspect 7 may include or use, or may optionally combine with the subject matter of one or any combination of aspects 1 to 6, to optionally include: at a first unit, an early signal input node coupled to a forward output node or a first input node of the preceding unit in the sequence; a delayed signal input node coupled to a reverse output node of a subsequent unit in the sequence; a summing circuit configured to provide an intermediate signal by combining signals modulated based on a delay control signal and corresponding signals at the early and late signal input nodes, respectively; and a pulse width adjustment circuit configured to provide the anti-skew output signal based on a pulse width control signal and the intermediate signal from the summing circuit.

[0111] Aspect 8 may include or use, or may optionally combine with the subject matter of one or any combination of aspects 1 to 7, to optionally include: at a first unit, a pulse width adjustment circuit configured to receive the test input signal and, in response, provide an intermediate pulse width adjustment signal to the subsequent unit; and a delay signal input node coupled to the inverted output node of the subsequent unit in the series; and a summing circuit configured to provide the anti-skew output signal by combining the signal received at the delay signal input node and the intermediate pulse width adjustment signal.

[0112] Aspect 9 may include or use, or optionally combine with the subject matter of one or any combination of aspects 1 to 8, to optionally include a common-source cascode stage with an adjustable bias current source in a timing adjustment circuit, wherein the amplitude of the current signal provided by the bias current source corresponds to the amplitude of the pulse width adjustment.

[0113] Aspect 10 may include or use, or optionally combine with the subject matter of one or any combination of aspects 1 to 9, to optionally include a method for adjusting the timing of a test signal provided to a device under test using a plurality of series-coupled signal timing control units, wherein each control unit operates in one of a pulse width adjustment mode or a delay mode. In one example, aspect 10 may include: at a first unit of the timing control unit; receiving an input test signal at an input node of the first unit, receiving a first mode control signal; providing a first delay signal to a subsequent unit of the series-coupled timing control unit based on the input test signal; receiving a second delay signal from the subsequent unit; and providing a pulse width-adjusted output signal based on the second delay signal, wherein the delay characteristics and pulse width characteristics of the output signal are based on the first mode control signal.

[0114] Aspect 11 may include or use, or optionally combine with the subject matter of aspect 10, to optionally include: receiving a first delay signal from the first unit in a subsequent unit of the timing control unit, receiving a second mode control signal, and providing the second delay signal to the first unit, wherein the second delay signal is based on the first delay signal, and wherein the delay characteristics of the second delay signal are based on the second mode control signal.

[0115] Aspect 12 may include or use, or optionally combine with the subject matter of aspect 10 or 11, to optionally include: receiving discrete delay control and pulse width control codes, and the delay and pulse width characteristics of the output signal being based on the delay and pulse width control codes, respectively.

[0116] Aspect 13 may include or use, or optionally combine with the subject matter of aspect 12, to optionally include: receiving a second mode control code at the subsequent unit; and the second mode control code indicating the configuration of delay and / or pulse width adjustment circuitry in the subsequent unit.

[0117] Aspect 14 may include or use, or optionally combine with the subject matter of one or any combination of aspects 10 to 13, to optionally include: changing the amplitude of the current signal provided by the bias current source in the subsequent unit. The delay or pulse width characteristics of the second delayed signal may depend at least in part on the amplitude of the current signal provided by the bias current source.

[0118] Aspect 15 may include or use, or optionally combine with the subject matter of one or any combination of aspects 10 to 14, to optionally include: updating the first bias current amplitude of the first differential pair in the reverse signal path extending from the subsequent unit to the output node of the first unit based on a delay instruction in the first mode control signal.

[0119] Aspect 16 may include or use, or optionally combine with the subject matter of aspect 15, to optionally include: updating the bias current amplitude of a cascode circuit in the forward signal path of the first cell based on a pulse width instruction in the first mode control signal, the forward signal path extending between the input node of the first cell and the input node of the subsequent cell.

[0120] Aspect 17 may include or use, or optionally combine with the subject matter of aspect 15, to optionally include: updating the bias current amplitude of the second differential switch pair in the reverse signal path based on the pulse width instruction in the first mode control signal.

[0121] Aspect 18 may include or use, or optionally combine with the subject matter of one or any combination of aspects 1 to 17, to optionally include a system for altering the signal delay or pulse width characteristics of a test signal provided to the device under test. In aspect 18, the system may include: a plurality of timing control units coupled in series, wherein a first unit of the plurality of timing control units includes a first input node and a first output node; and the first unit is configured to delay and adjust the pulse width of an input signal received at the first input node. In aspect 18, the first unit may include: an early signal input node coupled to a forward output node or a first input node of a preceding unit in the sequence; and a late signal input node coupled to a reverse output node of a subsequent unit in the sequence; a summing circuit configured to provide an intermediate signal by combining a signal modulated based on a delay adjustment command and corresponding data signals at the early and late signal input nodes; and a pulse width adjustment circuit configured to provide a pulse width-adjusted output signal at the first output node based on a pulse width adjustment command and the intermediate signal from the summing circuit.

[0122] Aspect 19 may include or use, or optionally combine with the subject matter of aspect 18, to optionally include: the delay adjustment instruction indicating an amount of delay applied using the first unit relative to the input signal, and the pulse width adjustment instruction indicating the magnitude of a pulse width variation applied using the first unit relative to the pulse width of the input signal.

[0123] Aspect 20 may include or use, or optionally combine with the subject matter of aspect 18 or 19, to optionally include: the subsequent unit being configured to provide a late data signal at the late signal input node of the first unit, the late data signal corresponding to a time-delayed version of the input signal, and the first unit being configured to provide a pulse-width-adjusted output signal as a pulse-width-adjusted and further time-delayed version of the input signal.

[0124] Each of these non-restrictive aspects may exist independently or may be combined in various permutations or combinations with one or more of other aspects, examples, or features discussed elsewhere in this document.

[0125] This detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors have also contemplated examples in which only those elements shown or described are provided. The inventors have contemplated examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described, or with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0126] In this document, as is common in patent documents, the terms “a” or “one” are used to include one or more, regardless of any other instances or uses of “at least one” or “one or more.” In this document, the term “or” is used to indicate a non-exclusive “or,” so “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise stated. In this document, the terms “comprising” and “wherein” are used as simple equivalents to the corresponding terms “comprising” and “wherein.”

[0127] In the following claims, the terms "comprising" and "including" are open-ended, meaning that a system, device, article, composition, formulation, or process, including elements other than those listed after the term in the claim, is still considered to be within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labelling and are not intended to impose numerical requirements on their objects.

[0128] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods or circuit operations or circuit configuration instructions described in the examples above. Implementations of this method may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. This code may form part of a computer program product. Furthermore, in the examples, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical discs and digital video disks), magnetic tapes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0129] The above description is intended to be illustrative and not restrictive. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used, for example, by those skilled in the art after reading the above description. The abstract is provided to enable the reader to quickly determine the nature of the technical disclosure. It is understood that this summary is not intended to be construed as limiting the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be combined to simplify this disclosure. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may not be limited to all features of a particular disclosed embodiment. Therefore, the following claims are incorporated herein by way of example or embodiment, each claim existing independently as a separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An anti-torsional skew system for providing test signals to a device under test, the system comprising: A plurality of timing control units coupled in series, wherein each unit is capable of operating in one of a plurality of different operating modes according to its respective mode control signal, the plurality of different operating modes including a signal delay mode and a signal pulse width adjustment mode, wherein the first unit of the plurality of timing control units includes: It is configured as the first input node to receive test input signals; The reverse input node is configured to receive a delayed signal based on the test input signal from a subsequent unit among the plurality of timing control units; The first output node is configured to provide an anti-skew output signal; and A timing adjustment circuit is configured to adjust the pulse width of at least one of a test input signal or a delay signal to provide an anti-skew output signal; and A control circuit is configured to provide corresponding first mode control signals and second mode control signals to the first unit and the subsequent unit, wherein the first unit is configured to operate in the signal pulse width adjustment mode in response to the first mode control signal, and wherein the subsequent unit is configured to operate in the signal delay mode in response to the second mode control signal.

2. The system of claim 1, wherein in the signal pulse width adjustment mode, the first unit is configured to provide the anti-skew output signal, the anti-skew output signal having pulse width and delay characteristics different from the test input signal.

3. The system of claim 2, wherein the first unit includes a forward output node coupled to the subsequent unit and a reverse input node coupled to the subsequent unit, and wherein the anti-skew output signal is based on a delayed signal received from the subsequent unit at the reverse input node.

4. The system of claim 1, wherein the control circuit is configured to provide a pulse width control signal to the timing adjustment circuit in the first unit to control the amplitude of the pulse width of the anti-skew output signal.

5. The system of claim 1, wherein the control circuitry is configured to provide a delay control signal to the subsequent unit to control the edge timing of the delay signal relative to the test input signal.

6. The system of claim 1, wherein the first unit comprises: An early signal input node is coupled to the first input node or the forward output node of the preceding unit in the plurality of timing control units; The late signal input node is coupled to the inverse output node of the subsequent unit in the plurality of timing control units; The summing circuit is configured to provide an intermediate signal by combining signals based on a delay control signal and signals modulated at the early signal input node and the late signal input node, respectively. and The pulse width adjustment circuit is configured to provide the anti-skew output signal based on the pulse width control signal and an intermediate signal from the summing circuit.

7. The system of claim 1, wherein the first unit comprises: A pulse width adjustment circuit is configured to receive the test input signal and, in response, provide an intermediate pulse width adjustment signal to the subsequent unit. The late signal input node is coupled to the inverse output node of the subsequent unit in the plurality of timing control units; and The summing circuit is configured to provide the anti-skew output signal by combining the signal received at the late signal input node with the intermediate pulse width adjustment signal.

8. The system of claim 1, wherein the timing adjustment circuit includes a common-source cascode stage with an adjustable bias current source, wherein the amplitude of the current signal provided by the bias current source corresponds to the amplitude of the pulse width adjustment.

9. A method for adjusting the timing of a test signal provided to a device under test using a plurality of series-coupled signal timing control units, wherein each of the control units operates in one of a pulse width adjustment mode or a delay mode, the method comprising: At the first unit of the timing control unit: The input test signal is received at the input node of the first unit; Receive the first mode control signal; Provide a first delayed signal based on the input test signal to subsequent units in the series-coupled timing control unit; Receive a second delayed signal from the subsequent unit; and A pulse-width-adjusted output signal is provided based on the second delay signal, wherein the delay characteristics and pulse-width characteristics of the output signal are based on the first mode control signal; At the subsequent unit in the timing control unit: Receive a first delayed signal from the first unit; Receive the second mode control signal; and The second delay signal is provided to the first unit, wherein the second delay signal is based on the first delay signal, and wherein the delay characteristic of the second delay signal is based on the second mode control signal.

10. The method of claim 9, wherein receiving the first mode control signal includes receiving discrete delay control code and pulse width control code, and wherein the delay characteristic and pulse width characteristic of the output signal are based on the delay control code and the pulse width control code, respectively.

11. The method of claim 10, further comprising receiving a second mode control code at the subsequent unit, wherein the second mode control code indicates the configuration of delay and / or pulse width adjustment circuitry in the subsequent unit.

12. The method of claim 9, further comprising changing the amplitude of a current signal provided by a bias current source in the subsequent unit, wherein the delay or pulse width characteristic of the second delayed signal depends at least in part on the amplitude of the current signal provided by the bias current source.

13. The method of claim 9, further comprising: Based on the delay instruction in the first mode control signal, the first bias current amplitude of the first differential pair in the reverse signal path extending from the subsequent unit to the output node of the first unit is updated.

14. The method of claim 13, further comprising: Based on the pulse width instruction in the first mode control signal, the bias current amplitude of the cascode circuit in the forward signal path of the first unit is updated, the forward signal path extending between the input node of the first unit and the input node of the subsequent unit.

15. The method of claim 13, further comprising: Based on the pulse width instruction in the first mode control signal, the bias current amplitude for the second differential switch pair in the reverse signal path is updated.

16. A system for changing the signal delay or pulse width characteristics of a test signal provided to a device under test, the system comprising: A plurality of timing control units coupled in series, wherein a first unit of the plurality of timing control units includes a first input node and a first output node, and the first unit is configured to delay and adjust the pulse width of an input signal received at the first input node, and wherein the first unit includes: An early signal input node is coupled to the first input node or the forward output node of the preceding unit in the plurality of timing control units; The late signal input node is coupled to the inverse output node of the subsequent unit in the plurality of timing control units; The summing circuit is configured to provide an intermediate signal by combining signals modulated based on delay adjustment instructions and corresponding data signals at the early and late signal input nodes; A pulse width adjustment circuit is configured to provide a pulse width-adjusted output signal at the first output node based on a pulse width adjustment command and an intermediate signal from the summing circuit.

17. The system of claim 16, wherein the delay adjustment instruction indicates an amount of delay applied by the first unit relative to the input signal, and wherein the pulse width adjustment instruction indicates the magnitude of a pulse width variation applied by the first unit relative to the pulse width of the input signal.

18. The system of claim 16, wherein the subsequent unit is configured to provide a late data signal at a late signal input node of the first unit, the late data signal corresponding to a time-delayed version of the input signal, and wherein the first unit is configured to provide a pulse-width-adjusted output signal as a pulse-width-adjusted and further time-delayed version of the input signal.

Images