Segmented dual-switching SAR ADC with residue amplification

Abstract

A kind of segmented double-switching mode successive approximation type analog-digital converter based on residual error amplification, including capacitor array, comparator and logic control unit;Capacitor array includes first capacitor array MSBs array, bridging capacitor Ca, second capacitor array SSBs array, bridging capacitor Cb and third capacitor array LSBs array, three capacitor arrays are connected by bridging capacitor;The positive input end and the negative input end of comparator are connected with first capacitor array MSBs array, the output of comparator is connected with logic control unit, residual error voltage is sampled and amplified by comparator, then compared with minimum resolution LSB, the present application adopts segmented capacitor method, by introducing bridging capacitor, the number of capacitors of traditional high-precision successive approximation type digital-to-analog converter is reduced.Precision is improved without increasing the area of capacitor array by using residual error amplification technology.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of analog integrated circuit design, and particularly relates to a segmented double-switching successive approximation analog-to-digital converter based on residual amplification. BACKGROUND

[0002] With the rapid development of wireless communication technology, the great demand of society for digital signal processing system is getting higher and higher. Among the components of the digital signal processing system, the analog-to-digital converter (ADC) plays an important role that cannot be ignored. As a tool for converting analog signals in the real world into digital signals for processing, the performance parameters of the ADC will greatly affect the performance of the digital signal processing system. With the progress of process size, digital circuits can achieve lower energy consumption and faster speed, while the performance and design environment of analog circuits are deteriorating. The successive approximation analog-to-digital converter (SAR ADC) is mainly composed of digital modules due to its structure, and does not require energy-consuming analog modules such as operational amplifiers, so it can fully inherit the advantages of energy consumption and speed brought by process progress, and design an analog-to-digital converter with excellent performance.

[0003] Due to the working principle and process, the precision of the successive approximation analog-to-digital converter is generally not more than 16 bits, the main reason being that the increase in precision will cause an exponential increase in the number of capacitors, which will not only increase the area overhead, but also bring corresponding difficulties to capacitor matching. On the other hand, since SAR ADC mostly uses a capacitive digital-to-analog converter (CDAC), and its power consumption accounts for a major part of the total power consumption, as the number of capacitors increases, the switching energy consumed by the CDAC during conversion will also greatly increase, thereby increasing the overall power consumption. In view of the high precision, the currently widely used methods include adding redundant bits to the CDAC to increase robustness, using segmented capacitors to reduce the total number of capacitors, and using digital calibration to reduce capacitor mismatch error. In view of the low power consumption, researchers generally reduce power consumption by changing the structure of the CDAC and the capacitor switching method, such as changing the traditional bottom plate sampling to top plate sampling, which can save the highest bit (MSB) capacitor and reduce the overall number of capacitors by half; for example, capacitor switching based on Vcm reduces switching power consumption by introducing an additional voltage. SUMMARY

[0004] The present application aims to solve the problems in the prior art, and provides a segmented double-switching successive approximation analog-to-digital converter based on residual amplification, which reduces the area of the CDAC while achieving high precision and low power consumption.

[0005] In order to achieve the above-mentioned purpose, the present application has the following technical solutions:

[0006] The application discloses a kind of based on residual amplification segmented double switching mode successive approximation analog-digital converter, including capacitor array, comparator and logic control unit;The capacitor array includes first capacitor array MSBs array, bridging capacitor Ca, second capacitor array SSBs array, bridging capacitor Cb and third capacitor array LSBs array, first capacitor array MSBs array, second capacitor array SSBs array and third capacitor array LSBs array are connected by bridging capacitor Ca, bridging capacitor Cb;The positive input end and the negative input end of the comparator are connected with first capacitor array MSBs array, and the output end of the comparator is connected with logic control unit, residual voltage is sampled and amplified by comparator, then compared with minimum resolution LSB, higher precision bit is outputted without increasing the area of capacitor array.

[0007] As a preferred scheme, the first capacitor array MSBs array includes binary split capacitor array, redundant capacitor array Crdt1 and weight capacitor Cdmy1, the lower plate of bridging capacitor Ca is connected with the upper plate of first capacitor array MSBs array, and the upper plate of bridging capacitor Ca is connected with the upper plate of second capacitor array SSBs array, the binary split capacitor array, the lower plate of redundant capacitor array Crdt1 is connected with reference voltage Vref or ground GND, and the lower plate of weight capacitor Cdmy1 is connected with ground GND.

[0008] The second capacitor array SSBs array includes binary capacitor array, redundant capacitor array Crdt2 and weight capacitor Cdmy2, the lower plate of bridging capacitor Cb is connected with the upper plate of second capacitor array SSBs array, and the upper plate of bridging capacitor Cb is connected with the upper plate of third capacitor array LSBs array, the binary capacitor array of second capacitor array SSBs array, the lower plate of redundant capacitor Crdt2 is connected with reference voltage Vref or ground GND, and the lower plate of weight capacitor Cdmy2 is connected with ground GND.

[0009] The third capacitor array LSBs array includes binary capacitor array, redundant capacitor array Crdt3 and weight capacitor Cdmy3, the binary capacitor array of third capacitor array LSBs array, the lower plate of redundant capacitor array Crdt3 is connected with reference voltage Vref or ground GND, and the lower plate of weight capacitor Cdmy3 is connected with ground GND.

[0010] Further, as a preferred scheme, the binary split capacitor array in the first capacitor array MSBs array is [2 M-2 C 2 M-2 C 2 M-3C 2 M-3 C …C C C], wherein C is a unit capacitance, and M is the number of switchings of the first capacitance array MSBs array completed in the whole ADC conversion process.

[0011] Further, as a preferred solution, the binary capacitance array in the second capacitance array SSBs array is [2 N-1 C 2 N-2 C …2C C], wherein C is a unit capacitance, and N is the number of switchings of the second capacitance array SSBs array completed in the whole ADC conversion process.

[0012] Further, as a preferred solution, the binary capacitance array in the third capacitance array LSBs array is [2 L-1 C 2 L-2 C …2C C], wherein C is a unit capacitance, and L is the number of switchings of the third capacitance array LSBs array completed in the whole ADC conversion process.

[0013] As a preferred solution, the logic control unit is connected with the first capacitance array MSBs array, the second capacitance array SSBs array and the third capacitance array LSBs array, and according to the output result of the comparator, the logic control unit controls the binary split capacitance array, the redundant capacitance array Crdt1 in the first capacitance array MSBs array, and the binary capacitance array, the redundant capacitance array Crdt2 and the redundant capacitance array Crdt3 in the second capacitance array SSBs array and the third capacitance array LSBs array to switch the reference voltage Vref or the ground GND.

[0014] As a preferred solution, the comparator comprises a preamplifier A1, a preamplifier A2, a preamplifier A3, a latch L, a coupling capacitor C1, a coupling capacitor C2 and a coupling capacitor C3, the output end of the preamplifier A1 is connected with the upper plate of the coupling capacitor C1, the input end of the preamplifier A2 is connected with the lower plate of the coupling capacitor C1, the output end of the preamplifier A2 is connected with the upper plate of the coupling capacitor C2, the input end of the preamplifier A3 is connected with the lower plate of the coupling capacitor C2, the output end of the preamplifier A3 is connected with the upper plate of the coupling capacitor C3, the input end of the latch L is connected with the lower plate of the coupling capacitor C3, and the output end of the latch L is connected with the logic control unit; the input end of the preamplifier A1 is short-circuited through a switch Sc0, the input end of the preamplifier A2 is short-circuited through a switch Sc1, the input end of the preamplifier A3 is short-circuited through a switch Sc2, and the input end of the latch L is short-circuited through a switch Sc3.

[0015] Further, as a preferred solution, the residual voltage is sampled and amplified by the coupling capacitors at the output end of the multi-stage pre-amplifier in the comparator.

[0016] Compared with the prior art, the application has at least the following beneficial effects:

[0017] The application adopts the segmented capacitor method, effectively reduces the number of capacitors of the traditional high-precision SARADC digital-analog converter by introducing the bridge capacitor, and adopts the residual amplification technology to connect the positive input end and the negative input end of the comparator with the first capacitor array MSBs array, sample and amplify the residual voltage through the comparator, compare with the minimum resolution LSB, output higher precision bits, and realize the improvement of the precision without increasing the area of the capacitor array.

[0018] Further, the first capacitor array MSBs array, the second capacitor array SSBs array and the third capacitor array LSBs array are connected through the bridge capacitor Ca and the bridge capacitor Cb, the first capacitor array MSBs array, the second capacitor array SSBs array and the third capacitor array LSBs array are realized by the addition of the weight capacitor, the integer design of the bridge capacitor is realized, and the difficulty of layout matching is reduced.

[0019] Further, the first capacitor array MSBs array includes a binary split capacitor array, adopts a double switching mode technology, splits the binary capacitor array of the first capacitor array MSBs array, introduces another capacitor switching mode, reduces the switching power consumption without additional common-mode voltage Vcm, and in the case that the second capacitor array SSBs array and the third capacitor array LSBs array are switched to the single switching mode, since the first capacitor array MSBs array has the switching mode, the common-mode level offset can be ignored. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The circuit structure schematic diagram of the segmented double switching mode successive approximation type analog-digital converter of the application;

[0021] Figure 2 The switching waveform schematic diagram of the segmented double switching mode successive approximation type analog-digital converter of the application;

[0022] Figure 3 The split capacitor switching mode schematic diagram of the first capacitor array MSBs array of the application;

[0023] Figure 4The schematic diagram of the monotonic capacitance switching mode adopted by the second capacitance array SSBs array and the third capacitance array LSBs array;

[0024] Figure 5 The residual amplification flowchart of the segmented double-switching mode successive approximation type analog-digital converter. DETAILED DESCRIPTION

[0025] The application will be further described in detail below with reference to the accompanying drawings.

[0026] Referring to Figure 1 The embodiment of the application is a segmented double-switching mode successive approximation type analog-digital converter based on residual amplification, comprising a capacitance array, a comparator and a logic control unit. The capacitance array comprises a first capacitance array MSBs array, a bridge capacitance Ca, a second capacitance array SSBs array, a bridge capacitance Cb and a third capacitance array LSBs array.

[0027] The first capacitance array MSBs array comprises a binary split capacitance array, a redundant capacitance array Crdt1 and a weight capacitance Cdmy1. The lower plate of the bridge capacitance Ca is connected to the upper plate of the first capacitance array MSBs array, and the upper plate of the bridge capacitance Ca is connected to the upper plate of the second capacitance array SSBs array. The binary split capacitance array and the redundant capacitance array Crdt1 of the first capacitance array MSBs array are connected to a reference voltage Vref or ground GND at the lower plate, and the weight capacitance Cdmy1 is connected to ground GND at the lower plate. The binary split capacitance array in the first capacitance array MSBs array is [2 M-2 C 2 M-2 C 2 M-3 C 2 M-3 C …C C C], wherein C is a unit capacitance, and M is the number of switchings of the first capacitance array MSBs array in the entire ADC conversion process.

[0028] The second capacitance array SSBs array comprises a binary capacitance array, a redundant capacitance array Crdt2 and a weight capacitance Cdmy2. The lower plate of the bridge capacitance Cb is connected to the upper plate of the second capacitance array SSBs array, and the upper plate of the bridge capacitance Cb is connected to the upper plate of the third capacitance array LSBs array. The binary capacitance array and the redundant capacitance Crdt2 of the second capacitance array SSBs array are connected to a reference voltage Vref or ground GND at the lower plate, and the weight capacitance Cdmy2 is connected to ground GND at the lower plate. The binary capacitance array in the second capacitance array SSBs array is [2 N-1 C 2 N-2C …2C C], wherein C is a unit capacitance, and N is the number of switchings of the second capacitance array SSBs array during the entire ADC conversion process.

[0029] The third capacitance array LSBs array includes a binary capacitance array, a redundant capacitance array Crdt3, and a weight capacitance Cdmy3. The binary capacitance array and the redundant capacitance array Crdt3 of the third capacitance array LSBs array have their lower plates connected to a reference voltage Vref or ground GND, and the weight capacitance Cdmy3 has its lower plate connected to ground GND. The binary capacitance array in the third capacitance array LSBs array is [2 L-1 C 2 L-2 C …2C C], wherein C is a unit capacitance, and N is the number of switchings of the second capacitance array SSBs array during the entire ADC conversion process.

[0030] Referring to Figure 5 The comparator includes a preamplifier A1, a preamplifier A2, a preamplifier A3, a latch L, a coupling capacitor C1, a coupling capacitor C2, and a coupling capacitor C3. The output terminal of the preamplifier A1 is connected to the upper plate of the coupling capacitor C1, the input terminal of the preamplifier A2 is connected to the lower plate of the coupling capacitor C1, the output terminal of the preamplifier A2 is connected to the upper plate of the coupling capacitor C2, the input terminal of the preamplifier A3 is connected to the lower plate of the coupling capacitor C2, the output terminal of the preamplifier A3 is connected to the upper plate of the coupling capacitor C3, the input terminal of the latch L is connected to the lower plate of the coupling capacitor C3, and the output terminal of the latch L is connected to a logic control unit. The input terminal of the preamplifier A1 is shorted by a switch Sc0, the input terminal of the preamplifier A2 is shorted by a switch Sc1, the input terminal of the preamplifier A3 is shorted by a switch Sc2, and the input terminal of the latch L is shorted by a switch Sc3.

[0031] The positive input terminal and the negative input terminal of the comparator are connected to the first capacitance array MSBs array, the output terminal of the comparator is connected to the logic control unit, and the logic control unit is connected to the first capacitance array MSBs array, the second capacitance array SSBs array, and the third capacitance array LSBs array. According to the output result of the comparator, the reference voltage Vref or ground GND is switched for the binary split capacitance array and the redundant capacitance array Crdt1 in the first capacitance array MSBs array, and for the binary capacitance array, the redundant capacitance array Crdt2, and the redundant capacitance array Crdt3 in the second capacitance array SSBs array and the third capacitance array LSBs array. The residual voltage is sampled and amplified by the coupling capacitors of the output terminals of the multiple-stage preamplifiers in the comparator, and then compared with the minimum resolution LSB, so that higher precision bits are output without increasing the area of the capacitance array.

[0032] The segmented capacitor array significantly reduces the total number of capacitors, saves a large number of unit capacitors, the weight capacitors Cdmy1, Cdmy2 and Cdmy3 can design the bridge capacitors Ca and Cb as an integer multiple of the unit capacitor, reduce the difficulty of layout matching, the redundant capacitors Crdt1, Crdt2 and Crdt3 provide additional robustness for high-precision SAR ADC, and improve the output accuracy.

[0033] Referring to Figure 2 The double switching mode proposed by the application includes a split capacitor switching mode adopted by the first capacitor array MSBs array, the level change is consistent with the switching mode based on Vcm, and since the redundant capacitor array Crdt1 sets a redundant bit, there is an additional comparison stage. The double switching mode proposed by the application also includes a monotonic switching mode adopted by the second capacitor array SSBs array and the third capacitor array LSBs array, and the level change is monotonically decreasing.

[0034] Referring to Figure 3 The split capacitor switching mode adopted by the first capacitor array MSBs array of the application splits the capacitors greater than or equal to 2C in the binary capacitor array [2C 1C 1C] into two equal capacitors. After sampling the upper plate of the capacitor array, the lower plate of the capacitor array is set to [Vref GND Vref …Vref]. Since the input voltages Vip and Vin are directly connected to the comparator input, the first comparison does not require additional switching power consumption. If Vip>Vin, the lower plate of the capacitor array at the Vip end becomes [GND GND …], and if Vip<Vin, the lower plate of the capacitor array at the Vin end becomes [Vref Vref …]. The switching power consumption is (1 / 2)CV ref 2 Much smaller than the traditional method.

[0035] Referring to Figure 4 The monotonic capacitor switching mode adopted by the second capacitor array SSBs array and the third capacitor array LSBs array is that when the comparator output is "1", i.e. Vip>Vin, the lower plate of the bit capacitor at the Vip end is connected to GND, and when the comparator output is "0", i.e. Vip<Vin, the lower plate of the bit capacitor at the Vin end is connected to GND. The switching power consumption is CV ref 2 Greater than the split capacitor switching mode, and less than the traditional lower plate sampling mode.

[0036] Referring to Figure 5 The residual amplification flow of the successive approximation type analog-to-digital converter of the segmented double switching mode of the application is as follows:

[0037] The comparator acquires input voltages Vin1+, Vin1-, while V DAC1+ , V DAC1- The comparator performs the first conversion under the control of the logic unit, and obtains digital code D1 after the conversion. The voltage Vres1 less than 1 LSB remains at the input terminal of the comparator, the switch Sc1 is closed, the preamplifier A1 enters the additional self-zero stage, the coupling capacitor C1 acquires voltage -A1×Vres1, and the switch Sc1 is opened after the end. The comparator enters the second sampling stage, the input terminal of the preamplifier A1 is connected to the capacitor array, the switch Sc0 is closed, and the voltages Vin2+, Vin2- are sampled.

[0038] The switch Sc0 is opened after the second sampling, the comparator completes the second conversion, and obtains digital code D2 after the conversion. The voltage Vres2 less than 1 LSB remains at the input terminal of the comparator, the switch Sc3 is closed, the preamplifier A3 enters the additional self-zero stage, and the coupling capacitor C3 acquires voltage A1×A2×A3×(Vres1+Vres2). The switch Sc3 is opened after the end.

[0039] The switch Sc2 is closed, the preamplifier A2 enters the additional self-zero stage, and the coupling capacitor C2 acquires voltage A1×A2×(Vres1+Vres2). The switch Sc2 is opened after the end.

[0040] The switch Sc1 is closed, the preamplifier A1 enters the additional self-zero stage, and the coupling capacitor C1 acquires voltage A1×Vres2. The switch Sc1 is opened after the end, and the comparator enters the third comparison stage to obtain digital code D3.

[0041] The final output is Dout=2D1+2D2+D3, where D1, D2 and D3 are binary codes. The precision of the result is improved by two bits compared with the traditional successive approximation type analog-to-digital converter, and the area of the capacitor array is not increased.

[0042] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the same. Although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones. The modification or replacement does not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A successive approximation register analog-to-digital converter based on a segmented dual- switching mode with residue amplification, characterized by: The application relates to a high-precision capacitance-to-digital converter, which comprises a capacitance array, a comparator and a logic control unit; the capacitance array comprises a first capacitance array MSBs array, a bridging capacitance Ca, a second capacitance array SSBs array, a bridging capacitance Cb and a third capacitance array LSBs array; the first capacitance array MSBs array, the second capacitance array SSBs array and the third capacitance array LSBs array are connected through the bridging capacitance Ca and the bridging capacitance Cb; the positive input end and the negative input end of the comparator are connected with the first capacitance array MSBs array; the output end of the comparator is connected with the logic control unit; the residual voltage is sampled and amplified through the comparator, and then compared with the minimum resolution LSB; higher precision bits are outputted without increasing the area of the capacitance array. The first capacitance array MSBs array comprises a binary split capacitance array, a redundant capacitance array Crdt1 and a weight capacitance Cdmy1; the lower plate of the bridging capacitance Ca is connected with the upper plate of the first capacitance array MSBs array; the upper plate of the bridging capacitance Ca is connected with the upper plate of the second capacitance array SSBs array; the binary split capacitance array and the redundant capacitance array Crdt1 are connected with a reference voltage Vref or the ground GND through the lower plates; and the weight capacitance Cdmy1 is connected with the ground GND through the lower plate. The second capacitance array SSBs array comprises a binary capacitance array, a redundant capacitance array Crdt2 and a weight capacitance Cdmy2; the lower plate of the bridging capacitance Cb is connected with the upper plate of the second capacitance array SSBs array; the upper plate of the bridging capacitance Cb is connected with the upper plate of the third capacitance array LSBs array; the binary capacitance array and the redundant capacitance Crdt2 of the second capacitance array SSBs array are connected with the reference voltage Vref or the ground GND through the lower plates; and the weight capacitance Cdmy2 is connected with the ground GND through the lower plate. The third capacitance array LSBs array comprises a binary capacitance array, a redundant capacitance array Crdt3 and a weight capacitance Cdmy3; the binary capacitance array and the redundant capacitance array Crdt3 of the third capacitance array LSBs array are connected with the reference voltage Vref or the ground GND through the lower plates; and the weight capacitance Cdmy3 is connected with the ground GND through the lower plate. The comparator comprises preamplifiers A1, A2, A3, a latch L, coupling capacitors C1, C2 and C3, wherein the output terminal of the preamplifier A1 is connected to the upper plate of the coupling capacitor C1, the input terminal of the preamplifier A2 is connected to the lower plate of the coupling capacitor C1, the output terminal of the preamplifier A2 is connected to the upper plate of the coupling capacitor C2, the input terminal of the preamplifier A3 is connected to the lower plate of the coupling capacitor C2, the output terminal of the preamplifier A3 is connected to the upper plate of the coupling capacitor C3, the input terminal of the latch L is connected to the lower plate of the coupling capacitor C3, and the output terminal of the latch L is connected to a logic control unit; the input terminal of the preamplifier A1 is short-circuited by a switch Sc0, the input terminal of the preamplifier A2 is short-circuited by a switch Sc1, the input terminal of the preamplifier A3 is short-circuited by a switch Sc2, and the input terminal of the latch L is short-circuited by a switch Sc3; The binary split capacitor array in the first capacitor array MSBs array is [2 M-2 C 2 M-2 C 2 M-3 C 2 M-3 C …C C C], wherein C is a unit capacitance, and M is the number of switchings completed by the first capacitor array MSBs array during the entire ADC conversion process. The binary capacitance array in the second capacitance array SSBs array is [2 N-1 C 2 N-2 C …2C C], wherein C is a unit capacitance, and N is the number of switchings completed by the second capacitance array SSBs array during the entire ADC conversion process. The binary capacitor array in the third capacitor array LSBs array is [2 L-1 C 2 L-2 C …2C C], wherein C is a unit capacitance, and L is the number of switch switching times completed by the third capacitor array LSBs array during the entire ADC conversion process.

2. The SAR ADC with segmented dual switching based on residue amplification according to claim 1, wherein: The logic control unit is connected to a first capacitor array MSBs array, a second capacitor array SSBs array and a third capacitor array LSBs array, and according to the output result of the comparator, the logic control unit controls the binary split capacitor array, the redundant capacitor array Crdt1 in the first capacitor array MSBs array, and the binary capacitor array, the redundant capacitor array Crdt2 and the redundant capacitor array Crdt3 in the second capacitor array SSBs array and the third capacitor array LSBs array to switch the reference voltage Vref or the ground GND.

3. The SAR ADC with segmented dual switching based on residue amplification of claim 1, wherein: The residual voltage is sampled and amplified by the coupling capacitors at the output terminals of the multiple-stage preamplifiers in the comparator.

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