Semiconductor assembly and method of dicing same, filter, and electronic device

Abstract

The application relates to a cutting method of a semiconductor assembly, comprising: step 1: providing a first substrate, a second substrate, a sealing layer and MEMS devices, the sealing layer is arranged between the lower side of the first substrate and the upper side of the second substrate, the first substrate, the second substrate and the sealing layer define or enclose accommodating spaces, and the MEMS devices are arranged in the corresponding accommodating spaces, wherein: the sealing layer comprises a first sealing layer arranged on the first substrate and a second sealing layer arranged on the second substrate, and the first sealing layer is adapted to be sealingly connected with the second sealing layer; step 2: removing a predetermined part of the peripheral area of the first substrate to expose the second sealing layer corresponding to the predetermined part; and step 3: performing cutting with the second sealing layer corresponding to the predetermined part as an alignment mark.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular to a semiconductor assembly, a cutting method of a semiconductor assembly, a filter having the semiconductor assembly, and an electronic device having the filter. BACKGROUND

[0002] Electronic devices have been widely used as basic elements of electronic devices, and their application ranges include mobile phones, automobiles, home appliances, etc. In addition, future technologies such as artificial intelligence, Internet of Things, 5G communication, etc. that will change the world still need to rely on electronic devices as the foundation.

[0003] Electronic devices can exhibit different characteristics and advantages according to different working principles. Among all electronic devices, devices working by using piezoelectric effect (or inverse piezoelectric effect) are very important, and piezoelectric devices have very wide application scenarios. Film bulk acoustic resonator (FBAR, also known as bulk acoustic resonator, BAW) as an important member of piezoelectric devices is playing an important role in the field of communication, especially FBAR filter is occupying an increasingly large share in the market of radio frequency filter field. FBAR has excellent characteristics such as small size, high resonance frequency, high quality factor, large power capacity, good roll-off effect, etc. Its filter is gradually replacing traditional surface acoustic wave (SAW) filter and ceramic filter, and plays a huge role in the field of wireless communication radio frequency. Its high sensitivity advantage can also be applied to the fields of biology, physics, medicine, etc.

[0004] For MEMS devices such as film bulk acoustic resonator, they are usually arranged between two substrates, and the two substrates are bonded by a sealing bonding layer. One substrate can be a functional substrate on which the MEMS device is arranged, and the other substrate can be a packaging substrate, but the MEMS device can also be arranged. For a separated MEMS device and its packaging structure, it can be referred to as a die.

[0005] In the process of manufacturing the MEMS device, two wafers are arranged opposite to each other, and the wafers are connected by a sealing bonding layer. The two wafers are separated based on the sealing bonding layer, so that a plurality of dies are formed between the two wafers.

[0006] Figure 1 A structure diagram for cutting a die from two dies in the prior art. Figure 1In the diagram, 201 and 202 represent wafers or substrates, 101 is a dicing alignment mark, b is the horizontal distance between alignment marks 101, 102 is a lower sealing structure or lower sealing bonding layer, 104 is a conductive via, 105 is a pad, and 109 is an upper sealing structure or upper sealing bonding layer. Bonding layer 109 and bonding layer 102 are bonded together to form a sealing structure. For example... Figure 1 As shown, the horizontal distance between the bonding layers 102 is a.

[0007] Due to the misalignment during the bonding of the two wafers, the alignment mark 101 cannot be perfectly aligned with the sealing structure. To ensure that the sealing structure is not damaged during dicing, the distance 'a' between the lower sealing ring or the lower sealing bonding layer 102 must be greater than the distance 'b' between the dicing marks 101. Typically, the difference between 'a' and 'b' is around 20µm.

[0008] Because dicing is a physical cutting process, the trajectory of the dicing blade cannot be guaranteed to be without deviation. Therefore, the distance b between the dicing marks must be greater than the thickness of the dicing blade (or the width of the laser), usually about 20um larger.

[0009] Therefore, in adopting Figure 1 The cutting scheme shown requires setting redundant width, which wastes wafer area.

[0010] Figure 2 This is a schematic diagram of a structure in existing technology that uses etching methods to cut between two dies. Figure 2 As shown, if the separation channel 106 is etched by etching, the distance a between the lower sealing structures 102 can be greatly reduced while ensuring accuracy. However, if the die is separated before the pad forming process, subsequent electroplating cannot be carried out, or the bonding will fail when the wafer thinning process is carried out because the single die cannot withstand the external force.

[0011] Therefore, there is a need in the existing technology to improve the cutting method between dies. Summary of the Invention

[0012] The present invention is proposed to overcome at least one aspect of the problems in the prior art.

[0013] According to one aspect of an embodiment of the present invention, a semiconductor component is provided, comprising:

[0014] First substrate and second substrate;

[0015] A sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate;

[0016] At least one MEMS device,

[0017] in:

[0018] The first substrate, the second substrate, and the sealing layer define or enclose at least one receiving space, and the MEMS device is disposed within the corresponding receiving space;

[0019] No scribing alignment marks are provided on the upper side of the first substrate.

[0020] Embodiments of the present invention also relate to a method for cutting a semiconductor component, comprising:

[0021] Step 1: Provide a first substrate, a second substrate, a sealing layer, and a MEMS device. The sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate. The first substrate, the second substrate, and the sealing layer define or enclose a receiving space. The MEMS device is disposed in the corresponding receiving space. The sealing layer includes a first sealing layer disposed on the first substrate and a second sealing layer disposed on the second substrate. The first sealing layer is adapted to be sealed to the second sealing layer.

[0022] Step 2: Remove a predetermined portion of the peripheral area of ​​the first substrate to expose the second sealing layer corresponding to the predetermined portion;

[0023] Step 3: Perform cutting with the second sealing layer corresponding to the predetermined portion as the alignment mark.

[0024] Embodiments of the present invention also relate to a filter comprising the semiconductor components described above.

[0025] Embodiments of the present invention also relate to an electronic device, including the filter described above or the semiconductor component described above. Attached Figure Description

[0026] The following description and accompanying drawings will better aid in understanding these and other features and advantages of the various embodiments disclosed herein, wherein the same reference numerals in the drawings always denote the same parts, wherein:

[0027] Figure 1 This is a schematic diagram of a prior art structure that involves dicing between two dies to separate them.

[0028] Figure 2 This is a schematic diagram of a structure in the prior art that uses etching methods to cut between two dies;

[0029] Figure 3A and Figure 3B This is a schematic diagram illustrating a method for cutting between two dies according to an exemplary embodiment of the present invention, wherein... Figure 3A In the middle, the upper substrate has not yet been cut. Figure 3B In the middle, the predetermined portion around the upper base has been cut;

[0030] Figure 3C for Figure 3B A schematic top view of the wafer structure, where the circled part in the middle represents the wafer on the top side;

[0031] Figure 3D for Figure 3C A magnified view of the edge portion of the wafer structure in the diagram;

[0032] Figure 3E This is a partially enlarged schematic diagram of the edge portion of a wafer structure according to another exemplary embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure of two wafers before dicing, according to an exemplary embodiment of the present invention. The ellipsis indicates that more dies are not shown.

[0034] Figures 5A-5F Manufacturing a display according to an exemplary embodiment of the present invention Figure 3B A schematic structural diagram illustrating the steps of the structure shown;

[0035] Figure 6 This is a solid image of the etched surface;

[0036] Figure 7 for Figure 6 A magnified view of the etched surface. Detailed Implementation

[0037] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0038] Figure 3A and Figure 3B This is a schematic diagram illustrating a method for cutting between two dies according to an exemplary embodiment of the present invention, wherein... Figure 3A In the middle, the upper substrate has not yet been cut. Figure 3B In the middle, the predetermined portion of the upper base has been cut. Figure 3C for Figure 3B A schematic top view of the wafer structure, where the circled portion in the middle represents the wafer on the top side.

[0039] Figure 3A and Figure 3BIn the diagram, 201 and 202 are wafers or substrates, 102 is a lower sealing structure or lower sealing bonding layer, 104 is a conductive via, 105 is a pad, and 109 is an upper sealing structure or upper sealing bonding layer. The bonding layer 109 and the bonding layer 102 are bonded to each other to form a sealing structure.

[0040] In map design, such as Figure 3A As shown, the sealing bonding layer 109 on the substrate 202 is removed within a peripheral width b (typically 1mm-10mm, further, 1mm-3.5mm) of the substrate 202, thereby enabling... Figure 3A The two substrates in region b are in a non-bonded state.

[0041] Next, as Figure 3B As shown, the region corresponding to b on the substrate 202 is removed using a cutting method, thereby exposing the sealing bonding layer 102 on the upper side of the substrate 201. Thus, as... Figure 3C As shown, the sealing bonding layer 102 can be exposed in the peripheral area of ​​the outer edge of the substrate 201.

[0042] Figure 3D for Figure 3C A magnified view of a portion of the edge of the wafer structure. From Figure 3D As can be seen, the sealing bonding layers 102 (thin solid lines) crisscross, defining a rectangular area enclosing the MEMS device 103. Cut channels are formed between the thin solid lines or the sealing bonding layers 102. Figure 3D The middle section is divided into horizontally zoned streets and vertically zoned streets.

[0043] exist Figure 3C Based on the structure shown, a cutting tool is used along... Figure 3D The street slabs shown can be divided to form individual individual die.

[0044] The advantage of this dicing method is that it avoids the alignment problem between the post-set dicing mark 101 and the sealing bonding layer 102, so that there is no need to increase the sealing ring distance (usually 20um) for this alignment, thereby increasing the die yield per wafer.

[0045] Figure 3E This is a partially enlarged schematic diagram of the edge portion of a wafer structure according to another exemplary embodiment of the present invention. Figure 3E and Figure 3D The difference is that, in Figure 3E In the middle, the edge portion of the first base 202 (in Figure 3EThe portion corresponding to part 107) was not removed, but a portion of the first substrate 202 was removed at a predetermined distance from the edge of the first substrate 202 (e.g., no more than 3 mm, which is sufficient to ensure that the sealing bonding layer 102 exposed during the cutting can be aligned), thereby exposing the sealing bonding layer 102.

[0046] Figure 4 This is a schematic diagram of the structure of two wafers before dicing, according to an exemplary embodiment of the present invention. The ellipsis indicates that more dies are not shown. Figure 4 The structure shown is similar to Figure 3B The structures shown are similar.

[0047] In addition to reference Figure 3A and Figure 3B The cutting method described above can also employ other methods to expose the sealing bonding layer 102. See below for reference. Figures 5A-5F An example is provided. Figures 5A-5F Manufacturing a display according to an exemplary embodiment of the present invention Figure 3B A schematic structural diagram illustrating the steps of the structure shown.

[0048] like Figure 5A As shown, a substrate 202 is provided.

[0049] like Figure 5B As shown, a via 104 is etched on one side of the substrate 202 to form a sealing bonding layer 109, and a notch 110 is formed in the edge region of the substrate 202. To save costs, the via 104 may not penetrate the substrate 202, and the via 104 and the notch 110 are formed simultaneously.

[0050] like Figure 5C As shown, a substrate 201 is provided, on one side of which a MEMS device 103 and a sealing bonding layer 102 are disposed.

[0051] like Figure 5D As shown, Figure 5C The base 201 and Figure 5B The substrates 202 in the middle are bonded to each other, and at this time, the sealing bonding layer 102 and the sealing bonding layer 109 are bonded to each other.

[0052] like Figure 5E As shown, it can be achieved through grinding processes, etc. Figure 5E A predetermined thickness of substrate material is removed from the upper side of the intermediate substrate 202 to allow for the removal of substrate material of a predetermined thickness. Figure 5D The portion corresponding to the notch 110 is removed, thereby exposing the sealing bonding layer 102 on the substrate 201.

[0053] like Figure 5F As shown, metal pad 105 is fabricated.

[0054] Subsequent cutting operations and Figure 3B The structures shown are the same.

[0055] Based on the above, the method of the present invention can eliminate the [impact / effects]. Figure 1 Therefore, the present invention proposes a semiconductor component in which the substrate side where the scribe alignment mark 101 is provided does not have a scribe alignment mark.

[0056] Given that in the prior art, the dicing alignment mark 101 is often arranged on the same layer as the metal pad 105 and spaced apart, in the semiconductor component proposed in this invention, no dicing alignment mark arranged on the same layer as the conductive pad and spaced apart is provided between the outer edge of the conductive pad and the end face of the substrate on which it is located.

[0057] In this invention, for example, can be used Figure 3A and Figure 3B The cutting scheme shown is used instead of the existing technology. Figure 2 The etching scheme shown is therefore based on, for example Figure 3A and Figure 3B The end face of the semiconductor component substrate obtained by the dicing scheme shown is formed by dicing rather than etching. That is, in this invention, the end face of the substrate 202 does not have textures formed by etching. Figure 6 This is a solid image of the etched surface. Figure 7 for Figure 6 A magnified view of the etched surface. (See image below.) Figure 7 As shown, the etched surface has a porous texture. The fact that the end face of the substrate 202 does not have a texture formed by etching indicates that the end face does not have a porous texture.

[0058] In the above example of the present invention, it is illustrated that both sealing bonding layers 102 and 109 are metal bonding layers. However, the bonding layer used to form the seal may not be a metal bonding layer. Furthermore, in the MEMS device packaging structure, a dedicated sealing layer is provided outside the metal bonding layer used for metal bonding to perform a sealing function. In this case, the cutting method of the present invention uses this dedicated sealing layer, which is substantially exposed elsewhere, as the cutting guide reference.

[0059] In the claims of this invention, the positional relationship between the first substrate and the second substrate is not explicitly stated; the first substrate may be above the second substrate, or the second substrate may be above the first substrate. For substrates that are provided with scribe alignment marks in the prior art, the upper side of the substrate is one side of the substrate where the scribe alignment marks are provided. Correspondingly, in the claims of this invention, the side of the first substrate that requires scribe alignment marks in the prior art but does not require them using the cutting scheme of this invention is the upper side of the first substrate, and the upper side of the second substrate is the side opposite the lower side of the first substrate.

[0060] As those skilled in the art will understand, the semiconductor components according to the present invention can be used to form filters or electronic devices. These electronic devices include, but are not limited to, intermediate products such as radio frequency front-ends and filtering / amplifying modules, as well as terminal products such as mobile phones, Wi-Fi devices, and drones.

[0061] It should be noted that, in this invention, each numerical range, except where explicitly stated not to include endpoint values, can be either an endpoint value or the median of each numerical range, and all of these are within the protection scope of this invention.

[0062] Based on the above, the present invention proposes the following technical solution:

[0063] 1. A semiconductor component, comprising:

[0064] First substrate and second substrate;

[0065] A sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate;

[0066] At least one MEMS device,

[0067] in:

[0068] The first substrate, the second substrate, and the sealing layer define or enclose at least one receiving space, and the MEMS device is disposed within the corresponding receiving space;

[0069] No scribing alignment marks are provided on the upper side of the first substrate.

[0070] 2. The component according to 1, wherein:

[0071] The component includes a conductive via through the first substrate;

[0072] A conductive pad is provided on the upper side of the first substrate, and the conductive pad is connected to the conductive via.

[0073] On the upper side of the first substrate, no alignment mark is provided between the outer edge of the conductive pad and the end face of the first substrate.

[0074] 3. The component according to 2, wherein:

[0075] The sealing layer is a metal bonding layer, and the conductive via is aligned with and electrically connected to the bonding layer in the thickness direction of the first substrate.

[0076] 4. The component according to 2, wherein:

[0077] On the upper side of the first substrate, there are no scribe alignment marks arranged in the same layer as the conductive pad and spaced apart from it between the outer edge of the conductive pad and the end face of the first substrate.

[0078] 5. The component according to any one of 1-4, wherein:

[0079] The end face of the first substrate does not have textures formed by etching.

[0080] 6. A method for cutting a semiconductor component, comprising:

[0081] Step 1: Provide a first substrate, a second substrate, a sealing layer, and a MEMS device. The sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate. The first substrate, the second substrate, and the sealing layer define or enclose a receiving space. The MEMS device is disposed in the corresponding receiving space. The sealing layer includes a first sealing layer disposed on the first substrate and a second sealing layer disposed on the second substrate. The first sealing layer is adapted to be sealed to the second sealing layer.

[0082] Step 2: Remove a predetermined portion of the peripheral area of ​​the first substrate to expose the second sealing layer corresponding to the predetermined portion;

[0083] Step 3: Perform cutting with the second sealing layer corresponding to the predetermined portion as the alignment mark.

[0084] 7. According to the method described in 6, wherein:

[0085] Removing a predetermined portion of the peripheral region of the first substrate includes removing the portion containing the outer edge of the first substrate.

[0086] 8. According to the method described in 7, wherein:

[0087] The predetermined portion is removed by cutting or etching the first substrate in a direction parallel to the thickness direction of the first substrate.

[0088] 9. According to the method described in 8, wherein:

[0089] In step 1, in the region corresponding to the predetermined portion, the first sealing layer is not provided on the underside of the first substrate.

[0090] 10. According to the method described in 7, wherein:

[0091] In step 1, the lower side of the first substrate is a recessed portion in the predetermined portion, and the first substrate has a first thickness in the portion corresponding to the recessed portion;

[0092] In step 2, a base material of a predetermined thickness is removed from the upper side of the first substrate to expose a second sealing layer corresponding to the predetermined portion, wherein the predetermined thickness is not less than the first thickness.

[0093] 11. According to the method described in 6, wherein:

[0094] A predetermined portion of the peripheral region of the first substrate is horizontally spaced from the outer edge of the first substrate by a distance.

[0095] 12. According to the method described in 11, wherein:

[0096] The distance is no greater than 3mm.

[0097] 13. According to the method described in 6, wherein:

[0098] The width of the predetermined portion is in the range of 1mm-10mm.

[0099] 14. According to the method described in 13, wherein:

[0100] The width of the predetermined portion is in the range of 1mm-3.5mm.

[0101] 15. A filter comprising a semiconductor component according to any one of 1-5, wherein the MEMS device includes a resonator.

[0102] 16. An electronic device comprising the filter according to claim 15 or the semiconductor component according to any one of claims 1-5.

[0103] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that variations may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for cutting a semiconductor component, comprising: Step 1: Provide a first substrate, a second substrate, a sealing layer, and a MEMS device. The sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate. The first substrate, the second substrate, and the sealing layer define or enclose a receiving space. The MEMS device is disposed in the corresponding receiving space. The sealing layer includes a first sealing layer disposed on the first substrate and a second sealing layer disposed on the second substrate. The first sealing layer is adapted to be sealed to the second sealing layer. Step 2: Remove a predetermined portion of the peripheral area of ​​the first substrate to expose the second sealing layer corresponding to the predetermined portion; Step 3: Perform cutting with the second sealing layer corresponding to the predetermined portion as the alignment mark.

2. The method according to claim 1, wherein: Removing a predetermined portion of the peripheral region of the first substrate includes removing the portion containing the outer edge of the first substrate.

3. The method according to claim 2, wherein: The predetermined portion is removed by cutting or etching the first substrate in a direction parallel to the thickness direction of the first substrate.

4. The method according to claim 3, wherein: In step 1, in the region corresponding to the predetermined portion, the first sealing layer is not provided on the underside of the first substrate.

5. The method according to claim 2, wherein: In step 1, the lower side of the first substrate is a recessed portion in the predetermined portion, and the first substrate has a first thickness in the portion corresponding to the recessed portion; In step 2, a base material of a predetermined thickness is removed from the upper side of the first substrate to expose a second sealing layer corresponding to the predetermined portion, wherein the predetermined thickness is not less than the first thickness.

6. The method according to claim 1, wherein: A predetermined portion of the peripheral region of the first substrate is horizontally spaced from the outer edge of the first substrate by a distance.

7. The method according to claim 6, wherein: The distance is no greater than 3mm.

8. The method according to claim 1, wherein: The width of the predetermined portion is in the range of 1mm-10mm.

9. The method according to claim 8, wherein: The width of the predetermined portion is in the range of 1mm-3.5mm.

10. A semiconductor component, diced according to the method of any one of claims 1-9, and comprising: First substrate and second substrate; A sealing layer is disposed between the lower side of the first substrate and the upper side of the second substrate; At least one MEMS device, in: The first substrate, the second substrate, and the sealing layer define or enclose at least one receiving space, and the MEMS device is disposed within the corresponding receiving space; No scribing alignment marks are provided on the upper side of the first substrate.

11. The component of claim 10, wherein: The component includes a conductive via through the first substrate; A conductive pad is provided on the upper side of the first substrate, and the conductive pad is connected to the conductive via. On the upper side of the first substrate, no alignment mark is provided between the outer edge of the conductive pad and the end face of the first substrate.

12. The component of claim 11, wherein: The sealing layer is a metal bonding layer, and the conductive via is aligned with and electrically connected to the bonding layer in the thickness direction of the first substrate.

13. The component of claim 11, wherein: On the upper side of the first substrate, there are no scribe alignment marks arranged in the same layer as the conductive pad and spaced apart from it between the outer edge of the conductive pad and the end face of the first substrate.

14. The component according to any one of claims 10-13, wherein: The end face of the first substrate does not have textures formed by etching.

15. A filter comprising a semiconductor component according to any one of claims 10-14, wherein the MEMS device includes a resonator.

16. An electronic device comprising the filter of claim 15 or the semiconductor component of any one of claims 10-14.

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