High frequency resolution digital sine wave generator

Abstract

A high frequency resolution digital sine wave generator is disclosed. A delay circuit applies a sample delay to a first digital sine signal and outputs a delayed digital sine signal. The first digital sine signal and the delayed digital sine signal are then added by an adder circuit to produce a summed digital sine signal. A gain scaling circuit applies a scaling factor to the summed digital sine signal to produce a second digital sine signal. A multiplexing circuit alternately selects samples of the first digital sine signal and the second digital sine signal to produce a third digital sine signal having twice the samples of the first digital sine signal within the same sine period.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 167,858, filed March 30, 2021, the disclosure of which is incorporated by reference. TECHNICAL FIELD

[0003] Embodiments herein relate generally to the generation of sinusoidal signals, and in particular, to a digital sinusoidal wave generator with high frequency resolution. BACKGROUND

[0004] Reference is made to Figure 1 which shows a block diagram of a conventional digital sinusoidal (sine or cosine) generator 10. A sine / cosine look-up table (LUT) 12 stores a plurality of digital values representing the amplitude of a sinusoidal curve having a particular fundamental frequency fb and sampled at a particular sampling frequency fs. This is represented in the illustration of Figure 2 is shown for a sinusoidal wave 15 sampled over one period T = 1 / fb to produce N discrete samples 13, where fs = N*fb. The discrete digital values of those samples stored in the sin / cos LUT 12 are accessed in response to a multi-bit (e.g., a-bit) tuning signal 14 and a multi-bit (e.g., b-bit) amplitude signal 16, one at a time at a rate set by a clock signal CLK at frequency fclk to produce a digital sinusoidal signal 18. In an example implementation, the frequency fclk can be equal to the sampling frequency fs. In the discrete domain, the digital sinusoidal signal 16 output from the sin / cos LUT 12 is a multi-bit (e.g., c-bit) digital signal of the form x(n) = Asin(2πnk / N), where A is the amplitude of the sinusoid selected by the amplitude signal 16, n is the digital signal index used to access the look-up table, and k is the frequency tuning value provided by the tuning signal 14. In the time domain, this digital sinusoidal signal ideally corresponds to x(t) = Asin(ωt). sin

[0005] As a representative, but not limiting, example, for a tunable sinusoidal wave generator with 256 stored samples, the number of bits in the multi-bit digital signals can be: a = 7 bits, b = 8 bits, and c = 16 bits, which outputs a 16-bit word with 127 tunable sinusoidal frequencies.

[0006] The frequency fsin of the output digital sinusoidal signal 16 is equal to the frequency of the clock signal (fclk) divided by the number of samples in one period accessed from the sin / cos LUT 12. The tuning signal 14 is used to set the frequency of the digital sinusoidal signal x sin ​(n). The tuning value k of the signal 14 is set by the tuner circuit 20. By increasing the value of k, fewer of the N samples in the sin / cos LUT 12 are accessed and the frequency fsin(increases (given a fixed frequency fclkof the clock signal CLK). For example, with k = 1, all N samples from 0 to N-1 stored in the sin / cos LUT 12 are sequentially accessed at the frequency of the clock signal CLK and output to produce a digital sine signal x sin (n). However, for k = 2, only half (i.e., N / 2) of the N samples from the sin / cos LUT 12 are sequentially accessed at the same frequency of the clock signal CLK (e.g., by taking only even samples as dictated by the term "nk") and output to produce a digital sine signal x sin (n).

[0007] In tuning the frequency of the generated digital sine wave, the allowable range of values for k is limited by the Nyquist criterion to the range 0 to (N-1) / 2. This places a significant limitation on the ability of the circuit 10 to produce digital sine waves of different frequencies. In practice, the frequency resolution of the circuit 10 is limited by the number of available samples N stored in the sin / cos LUT 12. This problem can be addressed by increasing the size of the sin / cos LUT 12 and correspondingly increasing the number of stored samples N. However, this requires the use of larger memory, and in many circuit applications, it is not possible to use such a large memory for the sin / cos LUT 12 due to one or more considerations such as circuit area occupied, power, temperature, etc. Thus, there is a need in the art to improve the frequency resolution of a sin / cos LUT-based digital sine wave generator without necessarily increasing the memory size (i.e., the number of samples stored in the LUT). SUMMARY

[0008] In one embodiment, a digital circuit includes an input configured to receive a first digital sine signal, a first delay circuit configured to impose a delay on the first digital sine signal to produce a first delayed digital sine signal, a first adder circuit configured to add the first digital sine signal and the first delayed digital sine signal to produce a first added digital sine signal, a first gain scaling circuit configured to apply a first scaling factor to the first added digital sine signal to produce a second digital sine signal, and a selection circuit configured to repeatedly select samples from the first digital sine signal and the second digital sine signal and produce an output digital sine signal.

[0009] In one embodiment, a sine wave generator circuit includes: an input configured to receive a first digital sine signal having a time domain representation corresponding to Asin(ωt); processing circuitry coupled to the input and configured to produce from the first digital sine signal a second digital sine having a time domain representation corresponding to Asin(ωt + a / 2); where a is a phase shift equal to one sample of the first digital sine signal; and a selection circuit having a first input and a second input configured to receive the first digital sine signal and the second digital sine signal, respectively, the multiplexing circuitry configured to repeatedly and sequentially select samples of the first digital sine signal and the second digital sine signal to produce a third digital sine signal.

[0010] In one embodiment, a sine wave generator circuit includes: an input configured to receive a first digital sine signal having a discrete domain representation of Asin(2πn / N), where n is an index of a sample, and N is a total number of samples in one sine period; processing circuitry coupled to the input and configured to produce from the first digital sine signal a second digital sine having a discrete domain representation corresponding to Asin(2π(n-(1 / 2)) / N); and a selection circuit having a first input and a second input configured to receive the first digital sine signal and the second digital sine signal, respectively, the multiplexing circuitry configured to repeatedly and sequentially select samples of the first digital sine signal and the second digital sine signal to produce a third digital sine signal.

[0011] In one embodiment, a method includes: receiving a first digital sine signal; delaying the first digital sine signal to produce a delayed digital sine signal; adding the first digital sine signal and the delayed digital sine signal to produce an added digital sine signal; applying a scaling factor to the added digital sine signal to produce a second digital sine signal; and repeatedly and sequentially selecting samples from the first digital sine signal and the second digital sine signal to produce a third digital sine signal. BRIEF DESCRIPTION OF DRAWINGS

[0012] For a better understanding of the embodiments, reference will now be made, purely by way of example, to the accompanying drawings in which:

[0013] Figure 1 is a block diagram of a conventional digital sine (sine or cosine) generator;

[0014] Figure 2 shows sine samples to produce discrete digital values for a Figure 1 sine look-up table (LUT) in the circuit of

[0015] Figure 3 is a block diagram of a digital sine (sine or cosine) generator according to an embodiment;

[0016] Figure 4A 、 Figure 4C and Figure 4D is a sine sample plot of the signal present in the generator of Figure 3

[0017] Figure 4B is a vector phase plot;

[0018] Figure 5 is a block diagram of a digital sine (sine or cosine) generator according to another embodiment; and

[0019] Figure 6 is a block diagram of a digital sine (sine or cosine) generator according to another embodiment. DETAILED DESCRIPTION

[0020] The solution to the above problem provides for increasing the frequency resolution of a digital sine wave generator based on a sine look-up table (LUT) without having to increase the size of the memory of the LUT or the number of stored samples. The solution makes use of the following mathematical relationship:

[0021] Asin(ωt) + Asin(ωt + α) = 2Acos(α / 2)sin(ωt + α / 2) (Equation 1)

[0022] where α is the phase shift.

[0023] The term 2cos(α / 2) is a constant that depends only on the size of the phase shift α. This constant can be eliminated by a proper mathematical scaling operation:

[0024] 2Acos(α / 2)sin(ωt + α / 2)*1 / (2cos(α / 2)) = Asin(ωt + α / 2) (Equation 2)

[0025] where 1 / (2cos(α / 2)) is a scaling factor that is used to cancel out the phase dependent constant value.

[0026] Thus, by gain scaling of the sum of two phase shifted (α) sine waves, a sine wave Asin(ωt + α / 2) can be generated.

[0027] By a proper choice of the phase shift α in the digital domain, the digital sample of Asin(ωt + α / 2) can be placed between the consecutive digital samples of Asin(ωt). Then, an alternating selection between the digital sample of Asin(ωt) and the digital sample of Asin(ωt + α / 2) can be made in the digital domain to generate a digital sine wave with twice the number of samples and thus twice the frequency resolution in the same period.

[0028] Reference is now made to Figure 3 ​which shows a block diagram of a digital sine (sine or cosine) generator 110 for implementing this solution. A sin / cos look-up table (LUT) 112 stores a plurality of digital values that represent discrete samples of the amplitude of a sinusoidal curve having a particular fundamental frequency fband sampled at a particular sampling frequency fs(see Figure 2 ). The discrete digital values of those samples stored in the sin / cos LUT 112 are accessed to be output one at a time at a rate set by a clock signal CLK having a frequency fclk in response to a multi-bit (e.g., a-bit) tuning signal 114 and a multi-bit (e.g., b-bit) amplitude signal 116 to produce a first digital sine signal 118. In an example implementation, the frequency fclk can be equal to the sampling frequency fs. In the discrete domain, the first digital sine signal 118 output from the sin / cos LUT 112 is a multi-bit (e.g., c-bit) digital signal of the form x sin1 (n) = Asin(2πnk / N), where A is the amplitude of the sine selected by the amplitude signal 116 set by the tuner, n is the digital signal index used to access the look-up table, and k is the tuning value provided by the tuning signal 114. Figure 4A A visual representation of the first digital sine signal 116 is shown in FIG. 1B, where the samples of the sine are represented by "x" (note that Figure 4A only a quarter of the full sine waveform from 0 ® p / 2 is shown). In the time domain, this digital sine signal ideally corresponds to x(t) = Asin(ωt), which is equal to the first addend of the mathematical relationship equation 1 above.

[0029] The generator 110 also includes digital signal processing circuitry 111, including a delay circuit 120, a summer circuit 124, a gain scaling circuit 128, and a 2:1 multiplexing (MUX) circuit 132.

[0030] The first digital sine signal 118 is input to the delay circuit 120, which is clocked by the clock signal CLK. The delay circuit 120 imposes a sample delay (i.e., a delay equal to one period of the clock signal CLK) on the first digital sine signal 118 to produce a delayed digital sine signal 122. In the discrete domain, the delayed digital sine signal 122 output from the delay circuit 120 is a multi-bit (e.g., c-bit) digital signal of the form x dly (n) = Asin(2π(n-1)k / N). In the time domain, this delayed digital sine signal ideally corresponds to x(t) = Asin(ωt + a), which is equal to the second addend of the mathematical relationship equation 1 above. In this case, the phase delay a corresponds to the sample delay imposed by the delay circuit 120 based on the clock signal CLK.

[0031] Adder circuit 124 adds the first digital sine wave signal 118 and the delayed digital sine wave signal 122 to generate a summed digital sine wave signal 126. In the discrete domain, the summed digital sine wave signal 126 output from adder circuit 124 is of the form: x add (n) = Asin(2πnk / N) + Asin(2π(n-1)k / N) = 2Acos(π / N)sin(2π(n-(1 / 2))k / N) is a multi-bit (e.g., c-bit) digital signal. In the time domain, this delayed digital sine signal ideally corresponds to x(t) = 2Acos(α / 2)sin(ωt+α / 2), which is the sum of the above mathematical relation, Equation 1. Figure 4B This is a vector phase diagram illustrating this relationship, where vector V1 corresponds to signal 118 with phase 0, vector V2 corresponds to signal 122 with phase 2π / N, and vector V3 (which is the sum of V1 and V2) corresponds to signal 126 with phase π / N.

[0032] The term 2cos(π / N) = 2cos(α / 2) is a mathematical constant that depends entirely on the applied phase shift α set by a sampling delay. The gain scaling circuit 128 can then be used to mathematically apply a gain scaling value g to the summed digital sine signals 126, where g = 1 / (2cos(π / N)), to cancel out the constant and generate a second digital sine signal 130. In the discrete domain, the second digital sine signal 130 output from the gain scaling circuit 128 is of the form: x sin2 (n) = Asin(2π(n-(1 / 2))k / N) is a multi-bit (e.g., c-bit) digital signal. The visual representation of the second digital sine wave signal 130 is as follows: Figure 4C As shown, the samples of the sine wave are represented by "+" (where... Figure 4C Only a quarter sample of the complete sine wave waveform from 0 to π / 2 is shown. In the time domain, this second digital sine signal ideally corresponds to x(t) = Asin(ωt + α / 2), which is equal to the output term of equation 2 of the mathematical scaling operation mentioned above.

[0033] In this case, the phase shift α / 2 term of Asin(ωt+α / 2) corresponds to half of the sampling delay provided by the delay circuit 120 based on the clock signal CLK. This is important because it will affect the sampling delay of the second digital sine wave x. sin2 Each sample of (n) is placed in the first digital sine signal x sin1 Between consecutive samples of (n). Figure 4D A visual representation of this is shown, with the sample of the first digital sine wave represented by "x" (see also...). Figure 4A The second digital sine wave sample is indicated by a "+" sign (note again, Figure 4DThe sample shown is only one-quarter of the entire sine wave waveform from 0 to π / 2.

[0034] First digital sine signal x sin1 (n) and the second digital sine wave signal x sin2 (n) is provided as input to the 2:1 multiplexing (MUX) circuit 132. The selected input of the MUX circuit 132 receives the clock signal CLK. Therefore, when the clock signal has a first (e.g., low) logic state, the MUX circuit 132 operates accordingly to transmit the first digital sine wave signal x. sin1 The MUX circuit 132 further operates to transmit the second digital sine wave signal x when the clock signal has a second (e.g., high) logic state (n) of the sample (x) shown in Figure 4. sin2 (n) samples (e.g.) Figure 4B (The "+" sample is shown). An output digital sine wave signal 134 is generated at the output of the MUX circuit 132, and is formed from the repeated and alternating selection of samples of the first and second digital sine waves. In the discrete domain, the output digital sine wave signal 134 is of the form: x out (m) = Asin(2π(n-1)k / 2N) = Asin(π(n-1)k / N) is a multi-bit (e.g., c-bit) digital signal; where the "2N" term represents twice the number of samples N available for each cycle of the sine wave (e.g., ...). Figure 4D (As shown).

[0035] Circuit 110 only needs to include delay, addition, and multiplication (gain scaling) operations using digital signal processing circuit 111 to process the digital sine signal output from sin / cos LUT 112 and double the available frequency resolution by generating twice the number of samples. This is achieved without increasing the number of samples N stored in sin / cos LUT 112 itself or increasing the size of the memory used for sin / cos LUT 112.

[0036] The digital signal processing circuit 111 of circuit 110 can be cascaded to further double the frequency resolution. An example of such a cascaded circuit configuration is shown below. Figure 5The digital sinusoidal signal 134(1) output from the first stage digital signal processing circuit 111(1) is applied to the input of the second stage digital signal processing circuit 111(2) that produces the digital sinusoidal signal 134(2). Because the first stage digital signal processing circuit 111(1) produces twice as many samples in response to the positive and negative phases of the clock signal CLK, the second stage digital signal processing circuit 111(2) must operate with a clock signal CLK' that has a frequency that is twice the frequency of the clock signal CLK. Any suitable clock multiplication circuit can be used to produce the clock CLK'. Alternatively, an appropriate clock tree circuit can be used to produce two clock signals CLK and CLK' that have different frequencies. Furthermore, because of the increased frequency resolution from the first stage and the increased rate at which these samples are output from the first stage, the gain scaling circuit 128 in the second stage must apply a gain scaling value g' where g' = 1 / (2cos(π / 2N)). In the discrete domain, the output digital sinusoidal signal 134(2) from the second stage is of the form: x out (m) = Asin(2π(n-1)k / 4N) = Asin(π(n-1)k / 2N) is a multi-bit (e.g., c-bit) digital signal; where the "4N" term indicates that four times the number of samples N provided by the sin / cos LUT 112 is available.

[0037] Reference is now made to Figure 6 which shows a block diagram of a digital signal processing circuit 211 for a digital sinusoidal (sine or cosine) generator according to another embodiment. This embodiment is similar to the embodiment of Figure 5 which supports a further doubling of the frequency resolution compared to the embodiment of Figure 3 However, only a single frequency clock CLK is required.

[0038] The discrete digital values representing the amplitude of a sine with a particular fundamental frequency fb and sampled at a particular sampling frequency fs are received from the sin / cos LUT (see Figure 2 as a first digital sinusoidal signal 218 whose rate is set by the clock signal CLK having a frequency fclk. In the discrete domain, the first digital sinusoidal signal 218 is of the form: x sin1 (n) = Asin(2πnk / N) is a multi-bit (e.g., c-bit) digital signal. The first digital sinusoidal signal 218 is input to a delay circuit 220 that is clocked by the clock signal CLK. The delay circuit 220 applies a sample delay (i.e., a delay equal to one period of the clock signal CLK) to the first digital sinusoidal signal 218 to produce a delayed digital sinusoidal signal 222. In the discrete domain, the delayed digital sinusoidal signal 222 output from the delay circuit 220 is of the form: x dly (n) = Asin(2π(n-1)k / N) is a multi-bit (e.g., c-bit) digital signal.

[0039] A first summer circuit 224 sums the first digital sinusoid 218 and the delayed digital sinusoid 222 to produce a first summed digital sinusoid 226. In the discrete domain, the first summed digital sinusoid 226 output from the summer circuit 224 is of the form: x add1 (n) = Asin(2πnk / N) + Asin(2π(n - 1)k / N) = 2Acos(π / N)sin(2π(n - (1 / 2))k / N) a multi-bit (e.g., c-bit) digital signal.

[0040] The term 2cos(π / N) is a mathematical constant that depends only on the applied phase shift set by one sample delay. A first gain scaling circuit 228 can then be used to mathematically apply a gain scaling value g, where g = 1 / (2cos(π / N)), to the summed digital sinusoid 226 in order to cancel this constant and produce a second digital sinusoid 230. In the discrete domain, the second digital sinusoid 230 output from the gain scaling circuit 228 is of the form: x sin2 (n) = Asin(2π(n - (1 / 2))k / N) a multi-bit (e.g., c-bit) digital signal.

[0041] A second summer circuit 234 sums the first digital sinusoid 218 and the second sinusoid 230 to produce a second summed digital sinusoid 236. In the discrete domain, the second summed digital sinusoid 236 output from the second summer circuit 234 is of the form: x add2 (n) = Asin(2πnk / N) + Asin(2π(n - (1 / 2)k / N) = 2Acos(π / 2N)sin(2π(n - (1 / 4))k / N) a multi-bit (e.g., c-bit) digital signal.

[0042] The term 2cos(π / 2N) is a mathematical constant that depends only on the applied phase shift set by one sample delay. A second gain scaling circuit 238 can then be used to mathematically apply a gain scaling value g', where g' = 1 / (2cos(π / 2N)), to the second summed digital sinusoid 236 in order to cancel this constant and produce a third digital sinusoid 240. In the discrete domain, the third digital sinusoid 240 output from the gain scaling circuit 238 is of the form: x sin3 (n) = Asin(2π(n - (1 / 4))k / N) a multi-bit (e.g., c-bit) digital signal.

[0043] The third adder circuit 244 adds the delayed digital sinusoidal signal 222 and the second sinusoidal signal 230 to produce a third added digital sinusoidal signal 246. In the discrete domain, the third added digital sinusoidal signal 246 output from the third adder circuit 244 is of the form: x add3 (n) = Asin(2π(n - 1)k / N) + Asin(2π(n - (1 / 2)k / N) = 2Acos(π / 2N)sin(2π(n - (3 / 4))k / N) a multi-bit (e.g., c-bit) digital signal.

[0044] The term 2cos(π / 2N) is a mathematical constant that depends only on the applied phase shift set by one sample delay. A third gain scaling circuit 248 can then be used to mathematically apply a gain scaling value g' to the third added digital sinusoidal signal 246, where g' = 1 / (2cos(π / 2N)), in order to cancel out the constant and produce a fourth digital sinusoidal signal 250. In the discrete domain, the fourth digital sinusoidal signal 250 output from the gain scaling circuit 248 is of the form: x sin4 (n) = Asin(2π(n - (3 / 4))k / N) a multi-bit (e.g., c-bit) digital signal.

[0045] A selection circuit 252 clocked by the clock signal CLK is then used to repeatedly and sequentially select samples from the delayed digital sinusoidal signal 222 (x dly (n)) and the first, second, third, and fourth digital sinusoidal signals (x sin1 (n) to x sin4 (n)) to produce an output digital sinusoidal signal 254. In the discrete domain, the output digital sinusoidal signal 254 is of the form: x out (m) = Asin(2π(n - 1)k / 4N) a multi-bit (e.g., c-bit) digital signal; where the "4N" term indicates that four times the number N of samples available per period of the sinusoidal curve.

[0046] In an example embodiment, the selection circuit 252 can comprise a 4: 1 multiplexer circuit that receives the first, second, third, and fourth digital sinusoidal signals (x sin1 (n) to x sin4 (n)) as inputs. A select input of this 4: 1 multiplexer circuit receives the clock signal CLK and a ninety degree phase shifted clock signal CLK90. When the clock signal CLK has a first (e.g., low) logic state and the phase shifted clock signal CLK90 also has the first logic state, the multiplexing circuit operates to pass the fourth digital sinusoidal signal x sin4samples of the second digital sinusoid x sin2 (n) are passed by the multiplexer circuit. When the clock signal CLK has the second logic state and the phase-shifted clock signal CLK90 also has the second logic state, the third digital sinusoid x sin3 (n) is sampled by the multiplexer circuit. Finally, when the clock signal CLK has the first logic state and the phase-shifted clock signal CLK90 has the second logic state, the first digital sinusoid x sin1 (n) are passed by the multiplexer circuit.

[0047] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed application, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A digital circuit comprising: an input configured to receive a first digital sinusoidal signal; a first delay circuit configured to impose a delay on the first digital sinusoidal signal to produce a first delayed digital sinusoidal signal; a first summer circuit configured to add the first digital sinusoidal signal to the first delayed digital sinusoidal signal to produce a first added digital sinusoidal signal; a first gain scaling circuit configured to apply a first scaling factor to the first added digital sinusoidal signal to produce a second digital sinusoidal signal; and a selection circuit configured to repeatedly select samples from among the first digital sinusoidal signal and the second digital sinusoidal signal and produce an output digital sinusoidal signal.

2. The digital circuit of claim 1, wherein the selection circuit comprises a first multiplexing circuit configured to alternately select samples from among the first digital sinusoidal signal and the second digital sinusoidal signal to output as the output digital sinusoidal signal.

3. The digital circuit of claim 2, wherein the first multiplexing circuit alternately selects at a rate that is twice a rate at which the first digital sinusoidal signal is received.

4. The digital circuit of claim 1, wherein the first delay circuit imposes a one-sample delay on the first digital sinusoidal signal.

5. The digital circuit of claim 1, wherein the delay imposed by the first delay circuit provides a first phase shift between the first digital sinusoidal signal and the first delayed digital sinusoidal signal, and wherein there is a second phase shift between the first digital sinusoidal signal and the second digital sinusoidal signal, the second phase shift being equal to one-half of the first phase shift.

6. The digital circuit of claim 5, wherein the first digital sinusoidal signal has N samples over one sinusoidal period, and wherein the first phase shift is equal to 2π / N and the second phase shift is equal to π / N.

7. The digital circuit of claim 6, wherein the first gain is a function of the cosine of the first phase shift.

8. The digital circuit of claim 1, wherein the first gain is a function of the cosine of a phase angle of the delay imposed by the first delay circuit.

9. The digital circuit of claim 1, further comprising: a second delay circuit configured to impose a delay on the output digital sinusoidal signal to produce a second delayed digital sinusoidal signal; a second summer circuit configured to add the output digital sinusoidal signal to the second delayed digital sinusoidal signal to produce a second added digital sinusoidal signal; a second gain scaling circuit configured to apply a second scaling factor to the second added digital sinusoidal signal to produce a third digital sinusoidal signal; and another selection circuit configured to repeatedly select samples from among the output digital sinusoidal signal and the third digital sinusoidal signal and produce another output digital sinusoidal signal. ​ ​ 10. The digital circuit of claim 9, wherein the further selection circuit comprises a multiplexing circuit configured to alternately select samples from the output digital sinusoidal signal and the third digital sinusoidal signal for output as the further output digital sinusoidal signal.

11. The digital circuit of claim 9, wherein the second delay circuit imposes one sample delay on the output digital sinusoidal signal.

12. The digital circuit of claim 9, wherein the delay imposed by the second delay circuit provides a third phase shift between the output digital sinusoidal signal and the second delayed digital sinusoidal signal, and wherein there is a fourth phase shift between the output digital sinusoidal signal and the third digital sinusoidal signal, the fourth phase shift being equal to one-half of the third phase shift.

13. The digital circuit of claim 12, wherein the first digital sinusoidal signal has N samples over one sinusoidal period, wherein the output digital sinusoidal signal has 2N samples over the one sinusoidal period, and wherein the third phase shift is equal to 4π / N and the fourth phase shift is equal to 2π / N.

14. The digital circuit of claim 13, wherein the second gain is a function of the cosine of π / 2N.

15. The digital circuit of claim 9, wherein the second gain is a function of the cosine of the phase angle of the delay imposed by the second delay circuit.

16. The digital circuit of claim 1, further comprising: a second summer circuit configured to add the first digital sinusoidal signal to the second digital sinusoidal signal to produce a second added digital sinusoidal signal; a second gain scaling circuit configured to apply a second scaling factor to the second added digital sinusoidal signal to produce a third digital sinusoidal signal; a third summer circuit configured to add the second digital sinusoidal signal to the first delayed digital sinusoidal signal to produce a third added digital sinusoidal signal; and a third gain scaling circuit configured to apply a third scaling factor to the third added digital sinusoidal signal to produce a fourth digital sinusoidal signal; wherein the selection circuit is configured to repeatedly select samples from all of the first digital sinusoidal signal, the second digital sinusoidal signal, the third digital sinusoidal signal, and the fourth digital sinusoidal signal, and to produce the output digital sinusoidal signal.

17. The digital circuit of claim 16, wherein the second scaling factor and the third scaling factor are equal.

18. The digital circuit of claim 16, wherein the selection circuit comprises a first multiplexing circuit configured to sequentially select samples from the first digital sinusoidal signal through the fourth digital sinusoidal signal for output as the output digital sinusoidal signal.

19. The digital circuit of claim 18, wherein the first multiplexing circuit sequentially selects at a rate four times faster than the rate at which samples of the first digital sinusoidal signal are received. ​ 20. The digital circuit of claim 16, wherein the first digital sinusoidal signal is provided by a sinusoidal lookup table (LUT).

21. The digital circuit of claim 20, wherein the first digital sinusoidal signal has samples, and wherein the LUT outputs the samples at a rate set by a clock signal.

22. The digital circuit of claim 21, wherein the first delay circuit is clocked by the clock signal.

23. The digital circuit of claim 21, wherein the repeated selection of samples from the first digital sinusoidal signal, the second digital sinusoidal signal, the third digital sinusoidal signal, and the fourth digital sinusoidal signal is responsive to the clock signal.

24. The digital circuit of claim 21, wherein the first digital sinusoidal signal has N samples in one sinusoidal period, and further comprising a tuning circuit configured to generate a control signal for selecting the N samples from the LUT.

25. The digital circuit of claim 1, wherein the digital circuit is a digital sinusoidal wave generator.

26. A sinusoidal wave generator circuit, comprising: an input configured to receive a first digital sinusoidal signal, the first digital sinusoidal signal having a time domain representation corresponding to Asin(ωt); a processing circuit coupled to the input and configured to generate a second digital sinusoidal signal from the first digital sinusoidal signal, the second digital sinusoidal signal having a time domain representation corresponding to Asin(ωt+α / 2); wherein α is a phase shift equal to one sample of the first digital sinusoidal signal; and a selection circuit having a first input and a second input configured to receive the first digital sinusoidal signal and the second digital sinusoidal signal, respectively, the selection circuit configured to repeatedly and sequentially select samples of the first digital sinusoidal signal and the second digital sinusoidal signal to generate a third digital sinusoidal signal.

27. The sinusoidal wave generator circuit of claim 26, wherein the processing circuit is configured to process the first digital sinusoidal signal and the second digital sinusoidal signal to implement the following mathematical expression represented in the time domain:

28. The sinusoidal wave generator circuit of claim 26, wherein the processing circuit comprises: 。 a delay circuit to delay the first digital sinusoidal signal by one sample; an adder circuit configured to add the first digital sinusoidal signal to an output of the delay circuit; and a gain scaling circuit configured to scale an output of the adder circuit by a scaling factor that is a function of 2cos(α / 2).

29. A sinusoidal wave generator circuit, comprising: an input configured to receive a first digital sinusoidal signal, the first digital sinusoidal signal having a discrete domain representation of Asin(2πn / N), where n is an index of a sample, and N is a total number of samples in one sinusoidal period; ​ ​ processing circuitry coupled to the input and configured to generate a second digital sinusoidal signal from the first digital sinusoidal signal, the second digital sinusoidal signal having a discrete domain representation corresponding to Asin(2π(n-(1 / 2)) / N); and selection circuitry having a first input and a second input configured to receive the first digital sinusoidal signal and the second digital sinusoidal signal, respectively, the selection circuitry configured to repeatedly and sequentially select samples of the first digital sinusoidal signal and the second digital sinusoidal signal to generate a third digital sinusoidal signal.

30. The sinusoidal wave generator circuit of claim 29, wherein the processing circuitry is configured to process the first digital sinusoidal signal and the second digital sinusoidal signal to implement the following mathematical expression represented in the discrete domain: 。 31. The sinusoidal wave generator circuit of claim 29, wherein the processing circuitry comprises: delay circuitry to delay the first digital sinusoidal signal by one sample; adder circuitry configured to add the first digital sinusoidal signal to an output of the delay circuitry; and gain scaling circuitry configured to scale an output of the adder circuitry by a scaling factor that is a function of 2cos(π / N).

32. A method of generating a digital sinusoidal signal, comprising: receiving a first digital sinusoidal signal; delaying the first digital sinusoidal signal to generate a delayed digital sinusoidal signal; adding the first digital sinusoidal signal to the delayed digital sinusoidal signal to generate a summed digital sinusoidal signal; applying a scaling factor to the summed digital sinusoidal signal to generate a second digital sinusoidal signal; and repeatedly and sequentially selecting samples from the first digital sinusoidal signal and the second digital sinusoidal signal to generate a third digital sinusoidal signal.

33. The method of claim 32, wherein the selecting is performed at a rate that is twice a rate at which samples of the first digital sinusoidal signal are received.

34. The method of claim 32, wherein the delaying comprises delaying by one sample.

35. The method of claim 32, wherein the delaying comprises applying a first phase shift between the first digital sinusoidal signal and the delayed digital sinusoidal signal, and wherein there is a second phase shift between the first digital sinusoidal signal and the third digital sinusoidal signal, the second phase shift being equal to one-half of the first phase shift.

36. The method of claim 35, wherein the first digital sinusoidal signal has N samples in one sinusoidal period, and wherein the first phase shift is equal to 2π / N and the second phase shift is equal to π / N.

37. The method of claim 36, wherein the scaling factor is a function of a cosine of π / N.

38. The method of claim 32, wherein the scaling factor is a function of a cosine of a phase angle of a delay resulting from delaying the first digital sinusoidal signal. ​ ​

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