Key-value data store system using content addressable memory

Abstract

The present disclosure is directed to key-value data storage systems using content addressable memory. A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system additionally includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated matching orientation in the CAM block. The processing device further determines a corresponding value orientation in the value data block using the associated matching orientation and retrieves data representing a value associated with the input search key from the value orientation in the value data block.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to critical value data storage systems using content addressable memory (CAM) within memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system comprising: a memory device including a content addressable memory (CAM) block and a value data block storing a plurality of stored search keywords; and a processing device operatively coupled to the memory device to perform operations including: receiving an input search keyword; identifying a stored search keyword among the plurality of stored search keywords that matches the input search keyword, the stored search keyword having an associated matching position in the CAM block; determining a corresponding value position in the value data block using the associated matching position; and retrieving data representing a value associated with the input search keyword from the value position in the value data block.

[0004] In another aspect, this disclosure relates to a method comprising: receiving an input search keyword; identifying a stored search keyword among a plurality of stored search keywords in a CAM block of a memory device that matches the input search keyword, the stored search keyword having an associated matching orientation in the CAM block; using the associated matching orientation to determine a corresponding value orientation in a value data block of the memory device; and retrieving data representing a value associated with the input search keyword from the value orientation in the value data block.

[0005] In another aspect, this disclosure relates to a non-transitory machine-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations including: receiving an input search keyword; identifying a stored search keyword among a plurality of stored search keywords in a CAM block of a memory device that matches the input search keyword, the stored search keyword having an associated matching position in the CAM block; using the associated matching position to determine a corresponding value position in a value data block of the memory device; and retrieving data representing a value associated with the input search keyword from the value position in the value data block. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram illustrating a key value data storage system using a content addressable memory (CAM) in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of a content addressable memory (CAM) block of a critical value data storage system implemented in a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart illustrating an example method for processing a search operation in a key value data storage system using a content addressable memory (CAM) in a memory subsystem, according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0013] This disclosure relates to a critical value data storage system using content-addressable memory (CAM) in a memory subsystem. The memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and a memory module. In conjunction with... Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0014] Content-addressable memory (CAM) is a common type of memory device used in some extremely high-speed search applications, such as identifier (ID) and pattern matching. Typically, the CAM is searched by comparing input search data with a table of stored data entries and returning the memory address of the data matching the table. CAMs are often implemented in dynamic random access memory (DRAM) or synchronous random access memory (SRAM). However, both DRAM and SRAM have limited memory capacity, which limits the amount of data that can be stored and searched in a conventional CAM implementation.

[0015] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0016] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and can include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of the memory device to allow concurrent operation on each plane. The memory device can include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, the memory device can include multiple access line driver circuits and power circuitry that can be shared by planes of the memory device to facilitate concurrent access to pages containing different page types on two or more memory planes. For ease of description, these circuits may generally be referred to as independent plane driver circuits. Depending on the memory architecture employed, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a segment of data (e.g., corresponding to one or more data addresses) can result in a read operation performed on two or more of the memory planes of the memory device.

[0017] A string is a unit in a NAND flash memory device. NAND flash memory devices typically have 32 or more memory cells, each representing a bit value (e.g., 0 or 1). Therefore, a string with 32 memory cells can represent 32 data bits, and a string with 64 memory cells can represent 64 data bits. In a NAND flash memory block, individual strings are connected to allow storing data from selected cells and retrieving data from selected cells. Typically, one end of a string in a block is connected to a common source line, and the other end is connected to a bit line. Each string also contains two control mechanisms connected in series with the memory cells. A string select transistor and a ground select transistor are connected to the string select line and the ground select line, respectively. Memory cells in a NAND flash assembly are horizontally connected to word lines at their control gates to form pages. A page is a set of connected memory cells sharing the same word line and is the smallest unit of programming. NAND flash memory devices can have page sizes of 64K or 128K cells. Although conventional NAND flash memory has a larger capacity compared to DRAM and SRAM, it is generally too slow for serial data search and access.

[0018] Key value data storage systems are designed to store, retrieve, and manage a set of records. Each record may contain different fields, storing one or more values. These records are stored in a database and retrieved using keywords that uniquely identify them, and can be used to find records within the database. Compared to relational databases, in key value data storage systems, data (i.e., values) is stored as a single, opaque collection and can be formatted differently in each record. This flexibility, independent of a defined framework, allows key value data storage systems to utilize far less memory than relational databases. However, in many key value systems, data is maintained in random access memory (e.g., DRAM or SRAM) subject to the performance limitations mentioned above.

[0019] This disclosure addresses the above and other deficiencies by providing a key value data storage system using Content Addressable Memory (CAM). In one embodiment, the memory subsystem can utilize a CAM architecture implemented in a NAND flash memory device to provide both fast search and high-capacity search capabilities. Consistent with this architecture, data entries can be stored on strings in a NAND flash memory array. In contrast to the NAND implementation, each bit of a data entry is mapped to a pair of memory cells configured to be complementary. That is, the first memory cell of the pair stores the bit value and the second memory cell of the pair stores the inverse of the bit value. A search pattern representing an input search word is vertically entered on each word line of the string in the array corresponding to the CAM. In one embodiment, the input search word represents a search keyword for use in the key value data storage system. A single read operation compares the input search word (i.e., the search keyword) with all strings in a selected portion of the array (typically a sub-block in one or more planes) and identifies the storage address (i.e., the stored keyword) of the matching data.

[0020] In one embodiment, the storage address of the matching key stored in the CAM can be used as input to a lookup table or other data structure that stores the location of the corresponding value in a separate value store. The value store can be implemented in NAND flash memory or other non-volatile memory not arranged using a CAM architecture. For example, the memory subsystem controller or other control logic can identify an entry in the lookup table corresponding to the storage address of the matching key stored in the CAM, and determine from that entry the associated location of the data corresponding to the key in the value store. That data can be returned to the requester who initially provided the input search word (e.g., a host system coupled to the memory subsystem).

[0021] The advantages of this approach include, but are not limited to, improved performance of the memory subsystem. NAND-based CAM architectures enable new applications that perform high-speed and high-density pattern matching, such as those related to artificial intelligence, machine vision, and large genetic databases. These CAM architectures also improve existing database search systems and algorithms, such as index memory in cloud network connectivity and servers. Furthermore, searches in NAND-based CAMs are performed within the NAND components, thus significantly reducing the utilization of the system bus (i.e., by one or more orders of magnitude). This reduced bus requirement saves power, improves system efficiency, and / or reduces system cost. Additionally, the functionality of critical value data storage systems is implemented using less DRAM or other volatile memory, which reduces cost and power consumption in the memory subsystem.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing means (e.g., a processor).

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., PCIe bus), host system 120 can additionally utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] In one embodiment, memory device 130 may be configured to include a content-addressable memory (CAM) NAND key value database 137. As described in more detail below, the CAM-NAND key value database 137 may include CAM blocks organized as arrays of one or more memory cells in strings. Each string stores a data entry and includes memory cells connected in series between a match line and a page buffer. That is, a CAM block contains multiple match lines, and each match line is connected to one of the multiple strings in the array. The match lines of the CAM block correspond to the bit lines of the NAND block in which the CAM block is implemented. Within a given string, memory cells may be organized as complementary memory cell pairs. Each bit value of a data entry stored in a string maps to one of the complementary memory cell pairs in the string.

[0039] The CAM block can be searched by providing a search mode as input to the search lines of the CAM block. The search lines of the CAM block correspond to the word lines of the NAND block in which the CAM block is implemented. In one embodiment, the match lines of the CAM block are pre-charged to facilitate the search. That is, a voltage signal is applied to the match lines of the CAM block before the search input. During the search operation, if the input search word matches any data entry stored in the CAM block, one or more match lines (e.g., match lines corresponding to the string storing the matching data entry) become conductive and discharge signals in response to the search mode input at the search line. If the search word does not match any stored entry, all match lines are deconductive. Each match line is further connected to a page buffer (e.g., including one or more latch circuits), which receives the discharge signal and stores data indicating matching data stored along the connected match lines.

[0040] In one embodiment, the memory subsystem 110 further includes a search component 113 that facilitates searching the CAM-NAND key value database 137. Consistent with some embodiments, as shown, the search component 113 is included in the memory subsystem controller 115. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119 for performing the operations of the search component 113 described herein. In some embodiments, the memory device 130 includes at least a portion of the search component 113. In some embodiments, the search component 113 is part of the host system 120, an application, or an operating system.

[0041] Search component 113 generates a search pattern based on the received input search word, and control logic (e.g., local media controller 135) inputs the search pattern vertically along the search lines of the CAM blocks in the CAM-NAND key value database 137. If the CAM block stores a data entry that matches the input search word, the search pattern causes the matching line storing the data entry (also referred to as the "matched line") to become conductive, and because the matching line is pre-charged, the matched line provides a signal indicating that the search word is stored thereon to the connected page buffer. The location (e.g., storage address) of any matching data entry can be identified based on the signal provided by the matched line due to the conductivity of the series. More specifically, the page buffer connected to any matched line stores data in response to detecting a discharge signal indicating that the matched data is stored along the matched line. Components of search component 113 or control logic (e.g., readout circuitry) can read data from the page buffer. Based on the data read from the page buffer, search component 113 outputs an indication of whether the search word is stored in the CAM block and an indicator of the location of the matching line.

[0042] Search component 113 may apply the orientation of the matching line as input to lookup table 118 or other data structures. In one embodiment, lookup table 118 is implemented in local memory 119 (e.g., DRAM) of memory subsystem controller 115. In other embodiments, lookup table 118 may be maintained elsewhere in memory subsystem 110, including on memory device 130 (e.g., in NAND memory). Lookup table 118 may contain a mapping or other correspondence between the orientation of the matching line in the CAM block and the orientation of the associated value (i.e., data) in the value data block of CAM-NAND key value database 137. In one embodiment, the value data block is implemented on memory device 130 using NAND flash memory (e.g., TLC or QLC memory) that is not arranged using a CAM architecture and is separate from the CAM block. Search component 113 may identify an entry in lookup table 118 corresponding to the orientation of the matching line in the CAM block and determine from that entry the associated orientation of the data in the value data block corresponding to the key. That data can be returned to the requester who initially provided the search term (e.g., host system 120). Further details regarding the operation and structure of search component 113 and CAM-NAND key value database 137 are described below.

[0043] Figure 2 The first device, in the form of a memory device 130, and the memory subsystem controller 115, in the form of a memory subsystem, are, according to the embodiment, (e.g., Figure 1A simplified block diagram of communication between a second device and a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0044] Memory device 130 includes an array 250 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 250 ( Figure 2 (Not shown) can be programmed to one of at least two target data states. In one embodiment, the memory cell array 250 includes CAM blocks 252 and value data blocks 254. As described herein, CAM blocks 252 contain several stored keys vertically stored in a string, which can be compared with received search keys. When a match is determined, the orientation of the matching stored key in CAM block 252 points to the orientation of the corresponding value in value data block 254 that can be retrieved and returned to the requester. In one embodiment, the memory device 130 is organized into multiple planes. In one embodiment, for example, the memory device 130 includes four planes. However, in other embodiments, more or fewer planes may exist. Each of the planes may be configured to include one or more CAM blocks 252 and value data blocks 254.

[0045] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode the address signals. Address signals are received and decoded to access the memory cell array 250. The memory device 130 also includes an input / output (I / O) control circuitry 212 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 214 communicates with the I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch the address signals before decoding. A command register 224 communicates with the I / O control circuitry 212 and the local media controller 135 to latch incoming commands.

[0046] A controller (e.g., a local media controller 135 within memory device 130) responds to commands to control access to memory cell array 250 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 250. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control row decoding circuitry 208 and column decoding circuitry 210 in response to address commands.

[0047] The local media controller 135 also communicates with cache register 242. Cache register 242 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 250 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 242 to data register 244 for transmission to the memory cell array 250; new data can then be latched from I / O control circuitry 212 into cache register 242. During read operations, data can be transferred from cache register 242 to I / O control circuitry 212 for output to memory subsystem controller 115; new data can then be transferred from data register 244 to cache register 242. Cache register 242 and / or data register 244 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may additionally include sensing devices ( Figure 2 (Not shown in the diagram), it is used to sense the data status of the memory cells, for example, by sensing the status of the data lines connected to the memory cell array 250. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0048] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0049] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 242. The data can then be written to data register 244 for programming memory cell array 250.

[0050] In this embodiment, cache register 242 may be omitted, and data may be written directly to data register 244. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, any conductive nodes, such as commonly used conductive pads or conductive bumps, may be included to enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0051] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0052] Figure 3This is a block diagram illustrating a key value data storage system using content-addressable memory (CAM) in a memory subsystem according to an embodiment. In one embodiment, search component 113 receives an input search keyword 310 (e.g., a search word) and applies the input search keyword 310 to CAM block 252 to compare the input search keyword 310 with a plurality of stored search keywords 352. In one embodiment, search component 113 or other logic in memory subsystem 110 generates a search pattern based on the input search keyword 310. The input search keyword 310 may include a first bit sequence (e.g., "1011"). The generated search pattern may include a first set of voltage signals representing the input search keyword 310 and a second set of voltage signals representing a second bit sequence including the inverse of the first bit sequence (e.g., "0100"). In one embodiment, search component 113 or other logic includes an inverter for generating the inverse of the input search keyword and a level selector for generating the first and second signals. When generating the first and second voltage signals, the level selector can use a high voltage to represent the binary value "1" and a low voltage to represent the binary value "0", wherein the high voltage is higher than the threshold voltage (Vt) and the low voltage is lower than Vt.

[0053] To search CAM block 252, search component 113 vertically inputs search keyword 310 (i.e., representative search pattern) along the search lines of CAM block 252. The input of search keyword 310 causes any complementary memory cell pair representing the stored matching bit value to become conductive. If the string is storing matching data (i.e., matching one of the stored search keywords 352), then the entire string becomes conductive. The matching lines in CAM block 252 are pre-charged (e.g., connected to a high voltage), and because the matching lines are pre-charged, the input of search keyword 310 on the search lines causes any matching line in the block storing matching data (e.g., a stored search keyword 310 that is the same as search keyword 310 in the stored search keywords 352) to output a discharge signal because the corresponding string is conductive. The discharge signal provides an indication that matching data (e.g., input search keyword 310) is stored thereon. The discharge signal provides an indication that the matching data is stored on the string connected to the matching lines.

[0054] Each string is connected between a match line and a page buffer (e.g., including one or more latching circuits), and the page buffer of the match line stores data indicating that match data is stored along the match line in response to a signal provided by the match line due to discharge along the string. The page buffer may include one or more latching circuits. Physically, the page buffer is located below or adjacent to the memory cell array in which CAM block 252 is implemented. When a signal is conducted to the page buffer to store match data in the connected string, the page buffer latches the data based on the signal provided by the match line. The search component 113 reads data from the page buffer and provides an input search keyword 310 as an indicator of whether it is stored in the CAM block 252 being searched, along with a match location 312 (e.g., the memory address of the string in the array) as output.

[0055] In some embodiments, the search component 113 may sequentially search for matching data in CAM blocks 252 of multiple memory planes. In some embodiments, the search component 113 may search for matching data in parallel in CAM blocks 252 of multiple memory planes. Parallel searching of multiple memory planes allows all data entries stored in all CAM blocks 252 of a plane to be searched in a single search operation, rather than completing the search of all data entries in four separate search operations. Therefore, parallel searching as used in the embodiments described above allows the search component 113 to improve search speed compared to embodiments that utilize sequential searching.

[0056] In some embodiments, data entries can be stored across two or more memory planes. In these cases, the search component 113 can simultaneously search for portions of matching data across two or more memory planes. Dividing data entries across planes allows for larger word lengths compared to embodiments where data entries are stored within a single plane. For example, if each of the CAM blocks 252 supports 64-bit words, then dividing data entries across all four planes would allow the memory device to support 256-bit words (4 * 64 = 256).

[0057] In one embodiment, the matching location 312 may be used as input to lookup table 118, or other data structures that store the location corresponding to the value of the input search keyword 310 in a separate value storage area (e.g., value data block 254). Value data block 254 may be implemented in NAND flash memory (e.g., on memory device 130), or in other non-volatile memory that is not arranged using a CAM architecture and may contain several stored values ​​354. Depending on the embodiment, value data block 254 may be located at the same location on the same die as CAM block 252, or may be located on a different memory device (i.e., memory die) within memory subsystem 110. In one embodiment, lookup table 118 is maintained on the same memory device 130 as either or both of CAM block 252 and value data block 254. In another embodiment, lookup table 118 is maintained on a separate memory device. In another embodiment, lookup table 118 is maintained in local memory 119 (e.g., DRAM) of memory subsystem controller 115. Lookup table 118 may contain, for example, several entries 322 that associate each matching location 312 from CAM block 252 with other value locations 324 in value data block 254. In one embodiment, search component 113 may identify an entry in lookup table 118 that corresponds to a matching location 312 and determine from that entry the associated value location 254 in value data block 254 where the data corresponding to the input search keyword 310 (i.e., an associated stored value in stored values ​​354) is located. That data (i.e., value 330) may be returned to the requester who initially provided the input search keyword 310 (e.g., host system 120 coupled to memory subsystem 110).

[0058] Figure 4 This is a block diagram of a content addressable memory (CAM) block implemented in a critical value data storage system within a memory device according to some embodiments of the present disclosure. As shown, CAM block 252 includes match lines 302-0 to 302-N, search lines 304-0 to 304-M, and inverse search lines 306-0 to 306-M. In this embodiment, the match lines 302-0 to 302-N of CAM block 252 correspond to the bit lines of a NAND flash memory device, and the search lines 304-0 to 304-M and the inverse search lines 306-0 to 306-M of CAM block 252 correspond to the word lines of a NAND flash memory device.

[0059] Each of the matching lines 302-0 to 302-N is connected to a string comprising multiple memory cells connected in series. For example, matching line 302-0 is connected to a string comprising memory cells 308-0 to 308-X, where X = 2M. The memory cells in each string of CAM block 252 are configured as complementary pairs. For example, for the string connected to matching line 302-0, memory cells 308-0 to 308-X are programmed as complementary memory cell pairs 310-0 to 310-M.

[0060] The memory cell pairs are configured to be complementary, wherein one memory cell in the pair stores a data value (“0”) and the other memory cell in the pair stores the inverse of the data value (“1”). For example, memory cell pair 310-0 includes two memory cells. The first memory cell stores the data bit value DATA, and the second memory cell 308-0 stores... It is the inverse of the data bit value DATA. Moreover, as shown, search line 304-0 is connected to the control gate of the first memory cell and inverse search line 306-0 is connected to the control gate of the second memory cell.

[0061] Search line 304-0 receives a first signal SL representing the search bit value from the input search word, and inverse search line 306-0 receives a second signal representing the inverse of the search bit value. If SL matches DATA and match Then memory cell pair 310-0 will propagate from A to B. For example, Table 1 provided below is a truth table defining the behavior of any given memory cell pair from 310-0 to 310-M.

[0062]

[0063] Table 1

[0064] In Table 1, "SL" is the search position value. It is the inverse of the search bit value, where "DATA" is the stored bit value, and It is the inverse of the stored bit value. As shown, the complementary cell pair conducts electricity when the search data value matches the stored data value and the inverse of the search data value matches the inverse of the stored data value. In other cases, memory cell pair 310 is not conductive because the stored data does not match the search bit.

[0065] In one embodiment, each string in CAM block 252 stores a data entry, and each data bit value in the data entry is mapped to one of the memory cell pairs 310-0 to 310-M in the string. In this way, within each of the complementary memory cell pairs 310 in the string, a first memory cell stores the bit value from the data entry, and a second memory cell stores the inverse of the bit value from the data entry.

[0066] In one example where the NAND flash memory device supports a 128-bit string (i.e., X is 128), the match line 302-0 is connected to memory cells 308-0 to 308-127, which store bit values ​​including D. 0,0 -D 63,63 A 64-bit data entry. In this example, the bit value D... 0,0 Mapped to memory cell pair 310-0, which includes memory cells 308-0 and 308-1. More specifically, memory cell 308-0 stores bit value D. 0,0 And complementary memory cells store It is the position value D 0,0 The reverse.

[0067] Search mode 312 can be input vertically along search lines 304-0 to 304-M and reverse search lines 306-0 to 306-M. More specifically, search lines 304-0 to 304-M receive a first voltage signal set SL representing search word 310. 0-M Furthermore, the inverse search lines 306-0 to 306-M receive the second voltage signal set representing the inverse of the search word. Entering search mode 312 along the search line will cause any string storing matching data to become conductive, because, as discussed above, each individual memory cell pair 310 in the string will be conductive. Because matching line 302 is pre-charged, the conductive string allows matching line 302 to discharge. The page buffer connected to the conductive string latches data indicating the location of the matching data (i.e., search word 206) in CAM block 252.

[0068] Search component 113 outputs an indication of whether CAM block 252 stores search word 206 and an indicator of the location (e.g., memory address) of matching data. In some embodiments, search component 113 includes readout circuitry that reads data from the page buffer of CAM block 252 to identify its location.

[0069] In some embodiments, the two page buffers in CAM block 252 may be tied together to form a serial shift register. Consistent with these embodiments, search component 113 shifts data from the first page buffer to the second page buffer, and search component 113 includes an output compare and counter component to track the number of shifts from one page buffer to the other to identify the location of matching data stored in CAM block 252. In some embodiments, a single transistor may be used to tie the two page buffers together to form a shift register.

[0070] Figure 5 This is a flowchart illustrating an example method for processing a search operation in a key value data storage system using a content-addressable memory (CAM) within a memory subsystem, according to some embodiments of this disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The search component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0071] At operation 505, an input search keyword is received. For example, processing logic (e.g., search component 113) may receive the input search keyword 310 from a requester (e.g., host system 120). In one embodiment, the input search keyword contains a first-order sequence (e.g., "1001 1010 1011").

[0072] At operation 510, a search pattern is generated. For example, the processing logic may generate the search pattern based on the first bit sequence. In one embodiment, the search pattern includes a first voltage signal set representing the input search keyword 310. That is, the first voltage signal set represents the first bit sequence. The search pattern further includes a second voltage signal set representing a second bit sequence, the second bit sequence including the inverse of the first bit sequence (e.g., "0110 0101 0100"). Therefore, when generating the search pattern, the processing logic generates the second bit sequence by inverting the input search keyword 310 and converts the first bit sequence and the second bit sequence into the first voltage signal set and the second voltage signal set, respectively. The processing logic may generate the first voltage signal set instead of the first bit sequence and generate the second voltage signal set by generating the inverse of the first voltage signal set. When generating the first voltage signal set and the second voltage signal set, the processing logic may use a high voltage to represent the binary value "1" and a low voltage to represent the binary value "0", wherein the high voltage is higher than a threshold voltage (Vt) and the low voltage is lower than Vt.

[0073] At operation 515, a search mode is provided to the CAM block. In one embodiment, the CAM block, such as CAM block 252, comprises an array of memory cells (e.g., a NAND flash memory array). The memory cells may be organized into multiple strings, each string storing one of a plurality of stored search keys. A string contains a plurality of memory cells connected in series between a precharged match line and a page buffer. The match line is precharged and connected to a voltage signal (e.g., indicating a logic high state). The CAM block further includes a plurality of search lines, and each memory cell in a string is connected to one of the plurality of search lines.

[0074] As described above, the memory cells in each string are organized into complementary memory cell pairs. Each bit value of a data entry stored in the string is mapped to a complementary memory cell pair in the string. Specifically, the first memory cell stores the bit value and the second memory cell stores the inverse of the bit value. More specifically, the first memory cell stores a first charge representing the bit value and the second memory cell stores a second charge representing the inverse of the bit value.

[0075] When a search mode is provided to the search line of CAM block 252, the processing logic may provide a first signal representing the search bit value from the first bit sequence to the first search line connected to the first memory cell in the complementary memory cell pair, and provide a second search signal representing the inverse of the search bit value to the second search line connected to the second memory cell in the complementary memory cell pair. If the input search keyword 310 is stored in CAM block 252, the input of the search mode causes the string storing the input search word to become conductive. Because the matched line is pre-charged, the conductive string allows the matched line to discharge. That is, the string conducts the signal generated by the matching line discharge based on the input search keyword 310 matching the stored search keyword on the string connected to the matched line. The conductive string provides the signal to the page buffer connected to the other end of the string. The page buffer latches data in response to the signal provided by the matching line discharge. The latched data indicates that the matched line connected to the page buffer stores the same data entry as the input search keyword 310.

[0076] At operation 520, the stored search keywords are identified. For example, the processing logic may identify one of the stored search keywords 352 that matches the input search keyword 310. In one embodiment, the processing logic may determine whether any of the stored search keywords 352 matches the input search keyword 310 by reading data from the page buffer of CAM block 252. A matching stored search keyword among the plurality of stored search keywords 352 has an associated matching position 312 in CAM block 252. In one embodiment, the processing logic may determine the matching position 312 based on data read from the page buffer. The matching position 312 may contain one or more memory addresses corresponding to one or more strings within the array of CAM block 252.

[0077] At operation 525, the corresponding value orientation is determined. For example, the processing logic may use the associated matching orientation 312 to determine the corresponding value orientation 324 in value data block 254. In one embodiment, the processing logic utilizes a lookup table 118 comprising a plurality of entries 322. Each of the plurality of entries 322 associates a matching orientation (e.g., matching orientation 312) from CAM block 252 with a value orientation (e.g., value orientation 324) in value data block 254 where data representing a value (e.g., value 330) corresponding to a corresponding stored search keyword from CAM block 252 is stored. Depending on the embodiment, lookup table 118 may be maintained in NAND flash memory of memory device 130 or in dynamic random access memory (DRAM) elsewhere in memory subsystem 110 (e.g., in local memory 119). In one embodiment, in order to determine the corresponding value orientation 324 in the value data block 254, the processing logic may identify an entry in a plurality of entries 322 in the lookup table 118 that corresponds to the associated matching orientation 312 and associates the associated matching orientation 312 with the corresponding value orientation 324.

[0078] At operation 530, data representing a value is retrieved. For example, the processing logic may retrieve data representing a stored value (i.e., value 330) associated with the input search keyword 310 from value location 324 in value data block 254.

[0079] At operation 535, data is provided to the requester. For example, the processing logic may provide data representing the value 330 associated with the input search keyword 310 to the host system (e.g., host system 120).

[0080] Figure 6 An example machine is described as a computer system 600, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to including, coupled to, or using a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1 The operation of the search component 113) of the host system (e.g., Figure 1 (Host system 120). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0081] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0082] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0083] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 to perform the operations and steps discussed herein. Computer system 600 may additionally include a network interface device 608 for communication on network 620.

[0084] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein are stored. The instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0085] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1The search component 113 contains functional instructions. Although machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0086] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0087] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0088] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0090] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0091] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block, wherein the value data block is separate from the CAM block; and a processing device operatively coupled with the memory device to perform operations comprising: receiving an input search key; identifying one of the plurality of stored search keys matching the input search key, the one of the plurality of stored search keys having an associated matching location in the CAM block; using the associated matching location to identify an entry of a plurality of entries maintained in a lookup table on the memory device, wherein each entry of the plurality of entries associates a matching location from the CAM block with a value location in the value data block in which data representing a value corresponding to a respective stored search key from the CAM block is stored, the identified entry comprising a value location in the value data block and the value location corresponding to the associated matching location; and retrieving data representing a value associated with the input search key from the value location in the value data block.

2. The system of claim 1, wherein the CAM block comprises an array of memory cells organized into a plurality of strings, each string storing one of the plurality of stored search keys and comprising a plurality of memory cells connected in series between a pre-charged match line and a page buffer, and wherein each of the plurality of memory cells is connected to one of a plurality of search lines.

3. The system of claim 2, wherein the input search key comprises a first sequence of bits, and wherein the processing device is to further perform operations comprising: generating a search pattern based on the first sequence of bits, the search pattern comprising a first set of voltage signals representing the first sequence of bits and a second set of voltage signals representing a second sequence of bits comprising an inverse of the first sequence of bits.

4. The system of claim 3, wherein the processing device is to further perform operations comprising: providing the search pattern as input to the plurality of search lines of the CAM block, wherein the search pattern causes at least one string of the plurality of strings storing the one of the plurality of stored search keys matching the input search key to conduct electricity and to provide a signal to a page buffer in response to the input search key matching the one of the plurality of stored search keys stored on the at least one string, the signal being generated from a discharge of the pre-charged match line, and the page buffer storing data based on the signal.

5. The system of claim 1, wherein the memory device comprises a "NAND" (NOT-AND) type flash memory device, and wherein the associated matching location in the CAM block comprises a memory address of a string on the NAND type flash memory device.

6. The system of claim 1, wherein the input search key is received from a host system, and wherein the processing device is to further perform operations comprising: providing the data representing the value associated with the input search key to the host system.

7. A method comprising: receiving an input search key; identifying one of a plurality of stored search keys in a CAM block of a memory device that matches the input search key, the one of the plurality of stored search keys having an associated match location in the CAM block; using the associated match location to identify an entry of a plurality of entries in a lookup table maintained on the memory device, wherein each entry of the plurality of entries associates a match location from the CAM block with a value location in a value data block of the memory device in which data representing a value corresponding to a respective stored search key from the CAM block is stored, the identified entry comprising a value location in the value data block and the value location corresponding to the associated match location, wherein the value data block is separate from the CAM block; and retrieving data representing a value associated with the input search key from the value location in the value data block.

8. The method of claim 7, wherein the memory device comprises a "not-and" (NAND) type flash memory device, and wherein the associated match location in the CAM block comprises a memory address of a string on the NAND type flash memory device.

9. A non-transitory machine-readable storage medium storing instructions which, when executed by a processing device, cause the processing device to perform operations comprising: receiving an input search key; identifying one of a plurality of stored search keys in a CAM block of a memory device that matches the input search key, the one of the plurality of stored search keys having an associated match location in the CAM block; using the associated match location to identify an entry of a plurality of entries in a lookup table maintained on the memory device, wherein each entry of the plurality of entries associates a match location from the CAM block with a value location in a value data block of the memory device in which data representing a value corresponding to a respective stored search key from the CAM block is stored, the identified entry comprising a value location in the value data block and the value location corresponding to the associated match location, wherein the value data block is separate from the CAM block; and retrieving data representing a value associated with the input search key from the value location in the value data block.

10. The method of claim 9, wherein the memory device comprises a "not-and" (NAND) type flash memory device, and wherein the associated match location in the CAM block comprises a memory address of a string on the NAND type flash memory device.

10. The non-transitory machine-readable storage medium of claim 9, wherein the memory device comprises a "not-and" (NAND) type flash memory device, and wherein the associated matching orientation in the CAM block comprises a memory address of a string on the NAND type flash memory device.

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