Compute-in-memory (CIM) storage array

Abstract

This disclosure relates to computing in memory (CIM) storage arrays. A storage device for CIM has a storage array comprising a plurality of storage cells arranged in rows and columns. The storage cells have a first group of storage cells and a second group of storage cells. Each row of the array has a corresponding word line, wherein each storage cell of a row of the array is coupled to the corresponding word line. Each column of the array has a corresponding bit line, wherein each storage cell of a column of the array is coupled to the corresponding bit line. Control circuitry is configured to select either the first group of storage cells or the second group of storage cells in response to a group enable signal.

Description

Technical Field

[0001] This disclosure generally relates to compute-in-memory (“CIM”), and further to storage arrays for data processing, such as multiply-accumulate (“MAC”) operations. Background Technology

[0002] In-memory computing, or computing in memory, stores information in a computer's main random access memory (RAM) and performs computations at the storage cell level, rather than moving large amounts of data between main RAM and data storage devices for each computation step. Because accessing stored data is much faster when it is stored in RAM, in-memory computing allows for real-time data analysis, enabling faster reporting and decision-making in business and machine learning applications. Summary of the Invention

[0003] According to one embodiment of this disclosure, a storage device for computing in memory (CIM) is provided, comprising: a storage array including a plurality of storage cells arranged in rows and columns, the storage cells including a first group of storage cells and a second group of storage cells; a plurality of word lines, each row of the array having a corresponding word line, each storage cell of a row of the array being coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each storage cell of a column of the array being coupled to the corresponding bit line; and control circuitry configured to select the first group of storage cells and / or the second group of storage cells in response to a group enable signal.

[0004] According to another embodiment of this disclosure, a computing-in-memory (CIM) device is provided, comprising: a plurality of memory cells configured to store weight signals, the memory cells being arranged in an array of rows and columns, including a first group of memory cells and a second group of memory cells; a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array being coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array being coupled to the corresponding bit line; a sense amplifier coupled to the bit lines and configured to amplify the signals of the bit lines for a read operation; control circuitry connected to the bit lines and configured to select either the first group of memory cells or the second group of memory cells in response to a group enable signal; an input terminal configured to receive a CIM input signal; and a multiplication circuitry configured to multiply the weight signals by the CIM input signals to generate a plurality of partial products.

[0005] According to another embodiment of this disclosure, a method for a computing-in-memory (CIM) device is provided, comprising: providing a memory array having a plurality of memory cells arranged in rows and columns, the memory cells including a first group of memory cells and a second group of memory cells; providing a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array being coupled to the corresponding word line; providing a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array being coupled to the corresponding bit line; receiving a group enable signal; performing a first operation on the first group of memory cells in response to the group enable signal; and performing a second operation on the second group of memory cells in response to the group enable signal. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Furthermore, the drawings are illustrative and not restrictive, serving as examples of embodiments of the invention.

[0007] Figure 1 This is a block diagram illustrating examples of various aspects of a computing in memory (CIM) device according to some embodiments.

[0008] Figure 2 This is a schematic diagram illustrating an example of a CIM storage array according to some embodiments.

[0009] Figure 3 This is a schematic diagram illustrating an example of a CIM storage unit according to some embodiments.

[0010] Figure 4 This is a schematic diagram illustrating an example of a multiplication circuit according to some embodiments.

[0011] Figure 5 This is a schematic diagram illustrating an example of another multiplication circuit according to some embodiments.

[0012] Figure 6 This is a block diagram illustrating an example of CIM input and weight multiplication operations according to some embodiments.

[0013] Figure 7 This is a block diagram illustrating examples of CIM input and weighted multiplication and accumulation operations according to some embodiments.

[0014] Figure 8 This is a schematic diagram illustrating an example of two optional array groups of a CIM storage array according to some embodiments.

[0015] Figure 9 This is a schematic diagram illustrating an example of four optional array groups of a CIM storage array according to some embodiments.

[0016] Figure 10 This is a flowchart illustrating a CIM method according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0019] This disclosure generally relates to computation in memory (“CIM”). An example of a CIM application is the multiply-accumulate (“MAC”) operation. Computer artificial intelligence (“AI”) uses deep learning techniques, where computational systems can be organized as neural networks. For example, a neural network refers to multiple interconnected processing nodes capable of analyzing data. Neural networks compute “weights” to perform computations on new input data. Neural networks use multiple layers of computational nodes, where deeper layers perform computations based on the results of computations performed by higher layers.

[0020] Machine learning (ML) involves computer algorithms that can automatically improve through experience and the use of data. It is considered a part of artificial intelligence. Machine learning algorithms build models based on sample data (called "training data") to make predictions or decisions without explicit programming.

[0021] Neural networks can include multiple interconnected processing nodes capable of analyzing data to compare inputs with "training" data. Training data refers to the computational analysis of properties of known data to develop a model for comparing input data. Examples of AI and data training applications can be found in object recognition, where systems analyze the properties of many (e.g., thousands or more) images to determine patterns that can be used to perform statistical analysis to identify input objects.

[0022] As mentioned above, neural networks compute weights to perform computations on the input data. Neural networks use multiple layers of computational nodes, where deeper layers perform computations based on the results of computations performed by higher layers. Machine learning currently relies on the computation of dot products and absolute differences of vectors, typically calculated via MAC operations performed on the parameters, input data, and weights. The computations of large and deep neural networks often involve so many data elements that storing them in processor caches is impractical; therefore, they are usually stored in memory.

[0023] Therefore, machine learning is extremely computationally intensive in terms of calculating and comparing many different data elements. In-processor computations are orders of magnitude faster than data transfers between the processor and main memory resources. Due to the memory size required to store data, placing all data closer to the processor in a cache is very expensive for most real-world systems. Thus, data transfer becomes a major bottleneck in AI computation. As datasets increase, the time and power / energy a computing system spends moving data can eventually be several times greater than the time and power spent actually performing the computations.

[0024] CIM circuits therefore perform operations locally within memory, without having to send data to the host processor. This reduces the amount of data transferred between memory and the host processor, resulting in higher throughput and performance. Reduced data movement also lowers the overall energy consumption of data movement within the computing device.

[0025] Such a CIM device may include a storage array with storage cells configured to store weight signals, and an input driver providing the input signals. The CIM device is configured to perform logical operations on selected weight signals and input signals, such as multiplying the selected weight signals by the input signals. Multiplication and accumulation (or multiplier-accumulator) circuitry performs MAC operations, where each MAC operation calculates the product of two numbers and adds that product to an accumulator (or adder). In some embodiments, the processing device or dedicated MAC unit or device may include MAC calculation hardware logic comprising a multiplier implemented in combinational logic, followed by an adder and an accumulator storing the result. The output of the accumulator may be fed back to the input of the adder, thereby adding the output of the multiplier to the accumulator. Example processing devices include, but are not limited to, microprocessors, digital signal processors, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0026] Some weighted storage arrangements in CIM may have limited weighted storage density due to the use of large storage cells, which may also result in limited write throughput. Some disclosed embodiments for CIM employ weighted storage based on a single transistor, single capacitor (1T-1C), which can increase weighted storage density by using small-area storage cells and further improve the write throughput of the weighted storage array. Furthermore, some examples include "multi-select" weighted storage arrays that facilitate selection among multiple storage array groups, allowing different operations (e.g., reads or writes) to be performed on the selected storage array group. Moreover, these different operations can be performed simultaneously on the selected storage array group. This selective weighted storage array facilitates multitasking and improves the write throughput of the weighted storage array.

[0027] For example, a storage array group may include a first selective group and a second selective group, wherein the first group includes even-numbered columns of the array and the second group includes odd-numbered columns of the array. In response to a group enable signal, CIM weight values ​​can be selectively written to one or both of the first (even-numbered) group and / or the second (odd-numbered) group. Furthermore, in response to a group enable signal, CIM weight values ​​can be selectively read from one or both of the first (even-numbered) group and / or the second (odd-numbered) group. Further still, in response to a group enable signal, CIM weight values ​​can be selectively written to either the first (even-numbered) group or the second (odd-numbered) group, while CIM weight values ​​can be selectively read from the other of the first (even-numbered) group or the second (odd-numbered) group. The number of storage array groups is not limited to two; other embodiments may include more than two storage array groups.

[0028] Figure 1A CIM device 10 according to some disclosed embodiments is shown. The CIM device 10 includes a CIM storage array 100 having a plurality of storage cells configured to store CIM weight signals. The storage array 100 and associated components and circuitry can be connected between a ground terminal and a power supply terminal configured to receive a VDD voltage. As will be further discussed below, the storage cells are arranged in an array of rows and columns and include a plurality of storage array groups 110. Row selection circuitry 102 and column selection circuitry 104 are connected to the storage array 100 and configured to select desired rows and columns of storage cells in the array for read and write operations.

[0029] exist Figure 1 In the illustrated example, memory array 100 includes a first memory array group 110-1, a second memory array group 110-2, and so on, up to memory array group n 110-n. Control circuitry 120 is connected to the bit line and configured to select either the first or second group of memory cells in response to a group enable signal. In the illustrated example, control circuitry 120 includes control circuits 120-1, 120-2, ..., 120-n, respectively, connected to memory array groups 110-1, 110-2, ..., 110-n.

[0030] The input terminal is configured to receive the CIM input signal IN, and the multiplication circuit 130 is configured to multiply the selected weight signal stored in the memory array 100 with the input signal IN to generate a plurality of partial products P. In the illustrated embodiment, the multiplication circuit 130 includes multiplication circuits 130-1, 130-2…130-n. The partial products P are output to a single IO adder circuit 140, which is configured to add the partial products P together to produce a CIM output.

[0031] Figure 2 Further aspects of an example of the storage array 100 are shown. As described above... Figure 1 The CIM storage array 100 includes a plurality of storage cells 200 arranged in rows and columns. Each row of array 100 has a corresponding word line WL. In the example shown, array 100 has N rows. Therefore, Figure 2 The word lines shown are designated as word lines WL_0 to WL_N-1. Each memory cell 200 is coupled to the word line WL of its corresponding row. Each column of array 100 has a corresponding bit line BL / BLB. In the example shown, array 100 has Y columns. Therefore, Figure 2The bit lines shown are designated as bit lines BL[0] to BL[Y-1] and BLB[0] to BLB[Y-1]. Each memory cell 200 is coupled to its corresponding bit line BL / BLB. For example, word lines WL and bit lines BL / BLB may comprise conductive traces or lines formed of conductive materials such as metals or silicided / polycided polysilicon.

[0032] The sense amplifier 122 and control circuit 120 are connected to the bit lines BL / BLB of each column of array 100. The multiplexer (MUX) 124 is connected to the output of sense amplifier 122 and, in response to the weight selection signal W_SEL, outputs the desired weight signal stored in memory array 100 to multiplication circuit 130. Figure 2 The example shown arranges memory array 100 in two memory array groups 110-1 and 110-2, wherein the first group 110-1 includes even-numbered columns (i.e., containing even-numbered bit lines BL[0] / BLB[0], and so on up to BL[Y-2] / BLB[Y-2]), and the second group 110-2 includes odd-numbered columns (i.e., containing odd-numbered bit lines BL[1] / BLB[1], and so on up to BL[Y-1] / BLB[Y-1]). As will be discussed further below, control circuitry 120 is configured to select either memory cells in the first group 110-1 or memory cells in the second group 110-2 in response to the group enable signal GROUP_EN.

[0033] The CIM weight signal is stored in storage array 100. Each cell 200 in array 100 stores a single bit of data (i.e., logic 1 or 0). In the example shown, the weight cell is a 1T-1C storage cell, where the single bit of data is stored as charge on a capacitor. Other embodiments may use storage cells other than 1T-1C storage cells.

[0034] Figure 3 It shows Figure 2An example of a 1T-1C memory cell 200 of the shown memory array 100. The memory cell 200 has a transistor (e.g., a MOS transistor 202) and a storage capacitor 204. The transistor 202 operates as a switch and is inserted between the storage capacitor 204 and a bit line BL (or BLB), wherein a first source / drain terminal (S / D) of the transistor 202 is connected to the bit line BL / BLB and a second S / D terminal of the transistor 202 is connected to a first terminal of the capacitor 204. The second terminal of the capacitor 204 is connected to a voltage terminal configured to receive a voltage level of 1 / 2 VDD. In some examples, the VDD voltage level is 1.0V, but other embodiments may employ different VDD voltage levels depending on, for example, a specific process technology. The memory cell 200 is capable of storing a single piece of binary information as stored charge in the capacitor 204.

[0035] The gate terminal of transistor 202 is connected to word line WL. For example... Figure 2 As shown, each word line WL is connected to a plurality of memory cells 200, wherein each row of array 100 has a corresponding WL. In some embodiments, the gate terminal of transistor 202 may be an extension of the same conductive material (e.g., metal or polysilicon) used to form the word line WL.

[0036] like Figure 2 As shown, each column of the memory array 100 includes two bit lines—BL / BLB. Therefore, the first column of memory array 100 includes BL[0] and BLB[0], the second column includes BL[1] and BLB[1], and so on, up to the Yth column, which includes BL[Y-1] and BLB[Y-1]. Each bit line BL / BLB is connected to every other memory cell 200 in a given column. Therefore, the first memory cell 200-1 shown in the leftmost column of memory array 100 is connected to bit line BL[0], the second memory cell 200-2 is connected to bit line BLB[0], the third memory cell 200-3 is connected to bit line BL[0], the fourth memory cell 200-2 is connected to bit line BLB[0], and so on.

[0037] Each column of array 100 has a sense amplifier 122 connected to the bit line BL / BLB of its corresponding column. The sense amplifier 122 includes a pair of cross-connected inverters located between the bit lines BL / BLB, wherein a first inverter is connected to an input from the bit line BL and outputs to the bit line BLB. A second inverter receives an input from the corresponding bit line BLB, and its output goes to the bit line BL. This generates positive feedback that stabilizes after one of the bit lines BL / BLB is at its highest voltage and the other line BL / BLB is at its lowest possible voltage.

[0038] Typically, for read operations, the sense amplifier 122 is effectively disabled or disconnected from the corresponding bit line BL / BLB. In some examples, the sense amplifier is controlled by control circuitry 120 in response to the group enable signal GROUP_EN. The bit lines are precharged to a voltage level between a high (i.e., logic 1) logic level and a low (i.e., logic 0) logic level. In the example shown, the logic 0 voltage level can be 0V, while the logic 1 voltage level can be VDD. Therefore, the bit line precharge voltage level is 1 / 2VDD.

[0039] Select the desired word line and bit line, then drive the word line WL of the selected row high (assuming the transistor 202 of memory cell 200 is an NMOS transistor) to turn on transistor 202 and connect the storage capacitor 204 of memory cell 200 to its bit line BL / BLB. If the storage value is 1, this transfers charge from memory cell 200 to the connected bit line BL / BLB, or if the storage value is 0, this transfers charge from the connected bit line BL / BLB to memory cell 200.

[0040] Traditional memory arrays may have very long bit lines, resulting in high capacitance. Furthermore, the 1T-1C memory cells of such traditional arrays may be connected between VDD and ground, rather than between VDD and 1 / 2VDD as in the illustrated embodiment. Connecting the storage capacitor 204 to 1 / 2VDD (instead of ground) reduces the voltage swing of the storage capacitor 204 from VDD to 1 / 2VDD. This further results in lower access power compared to a full ground-to-VDD voltage swing. In some examples, the VDD voltage level is 1.0V, but other embodiments may employ different VDD voltage levels depending on, for example, a specific process technology.

[0041] For read operations, the read signal Vsig is defined as follows:

[0042]

[0043] For the CIM memory array disclosed herein, the bit lines can be shortened to optimize cell array access time. The bit line length can depend on, for example, the size of the memory array (i.e., 8, 16, 256 rows, etc.) and can be optimized for different weight densities and / or power requirements. By keeping the bit line length short, the bit line capacitance CBL can be ignored, thus the read signal Vsig level will be large (close to 1 / 2 VDD), achieving fast read and fast access times.

[0044] The corresponding sense amplifier 122 is selected by the control circuit 120 in response to the GROUP_EN signal, and the differential signal from the selected BL / BLB pair is read out by the sense amplifier 122 and output to the corresponding MUX 124. The output of the sense amplifier 122 is provided to the multiplication circuit 130, in which the CIM input signal IN is combined with the CIM weight signal.

[0045] For write operations, word lines and bit lines are selected based on the address received by row selection circuit 102 and column selection circuit 104. The word line WL of the desired row is activated, and the sense amplifier 122 is disabled by control circuit 120. Logic 0 or 1 is then written to the selected column by driving the appropriate bit line BL / BLB to the desired high or low voltage state, thereby causing the associated bit line BL / BLB to charge or discharge the storage capacitor 204 of the memory cell 200 to the desired value.

[0046] As described above, the weight data read from storage unit 200 is output by MUX 124 to multiplication circuit 130, causing the CIM weight signal to be multiplied by the input signal IN. Multiplication circuit 130 is configured to multiply the input signal IN by the weight signal W read from array 100. Figure 4 An example of a multiplication circuit 130 including a NOR gate 132 is shown. The NOR gate 132 receives a weight signal W from a memory array 100 and an inverted input signal INB to output the product P of the weight signal W and the input signal IN. Figure 5 Another example is shown, in which multiplication circuit 130 includes an AND gate 134 that receives a weight signal W from memory array 100 and an input signal IN from array 100, to output the product P of the weight signal W and the input signal IN. The product output of multiplication circuit 130 is provided to single-IO adder circuit 140.

[0047] In some examples, the multiplication circuit 130 is configured to perform a bit-sequential multiplication of the input IN and the weight W from the most significant bit of the input to the least significant bit of the input, thereby producing multiple partial products. (Other multiplication configurations are within the scope of this disclosure.) Figure 6 An example is shown where a 1-bit CIM input signal IN is multiplied by an X-bit (X is a positive integer) CIM weight signal W[X-1:0]. Part of the product is output to the accumulator of a single-IO adder circuit 140.

[0048] Figure 7 An example of this implementation is shown, illustrating the input IN[M-1:0] and weights W[X-1:0]. For example... Figure 7As shown, during the first cycle, input IN[0] is multiplied by weight W[X-1:0] to produce the first partial product 310. During the second cycle, input IN[1] is multiplied by weight W[X-1:0] to produce the second partial product 312, and so on, until the Mth cycle, when input IN[M-1] is multiplied by weight W[X-1:0] to produce the Mth partial product 314. The partial products 310-314 are then added or accumulated by the accumulator of the single IO adder circuit 140.

[0049] As described above, the disclosed examples provide multiple independently selectable groups of storage arrays, thereby allowing multitasking to provide improved write throughput for the weighted storage arrays. For example, Figure 2 The storage array 100 shown includes a first storage array group 110-1 and a second storage array group 110-2. The first storage array group 110-1 includes even-numbered columns of the storage array 100, and the second storage array group 110-2 includes odd-numbered columns of the storage array 100.

[0050] Figure 8 This shows an even array 110-1 and an odd array 110-2. Figure 8 The diagram shows only one column for each of array groups 110-1 and 110-2, but actual implementations will have several columns for each of storage array groups 110-1 and 110-2. The desired storage array group 110 is selected in response to the GROUP_EN signal received by control circuitry 120. Figure 8 In the illustrated embodiment, a single GROUP_EN signal (0,1) is used to select between two memory array groups 110-1 and 110-2. For example, desired CIM weight data can be written to memory cells 200 of even array 110-1 and / or odd array 110-2 based on the GROUP_EN signal. Furthermore, this arrangement facilitates multitasking, such as writing weight data to even array 110-1 while simultaneously reading data from odd array 110-2. For example, a desired word line such as WL_0 can be activated, and data can be read from even array 110-1 and written to odd array 110-2 under the same bit line power and word line power.

[0051] Figure 9 Another embodiment with four memory array groups 110-1, 110-2, 110-3, and 110-4 is shown. Figure 9 The image shows only one column for each array group. A more practical implementation would have several columns for each of the storage array groups 110-1, 110-2, 110-3, and 110-4. For the four storage array groups, a two-bit GROUP_EN[1:0] is used to select among the four storage array groups.

[0052] like Figure 9 The example shown provides multiple array groups, facilitating multitasking and improving the write throughput of the CIM-weighted storage array. For example, in some embodiments, four operations can be performed simultaneously on four array groups 110-1, 110-2, 110-3, and 110-4, such as a read operation on one group and a write operation on the other three groups. For example, by selecting the desired word lines and columns of array 100 by control circuitry 120 and activating the appropriate read amplifier 122, data can be read from the first group 110-1 while data is written to the second, third, and fourth groups 110-2, 110-3, and 110-4. Multiple simultaneous CIM-weighted data write operations further improve the write throughput of the storage array and can improve CIM efficiency. In further embodiments, more than two or four storage array groups can be provided.

[0053] Figure 10 An example of a CIM method according to a disclosed embodiment is shown. Figure 10 The method includes operation 1010, in which a storage array is provided, for example Figure 2 The array 100 is shown. As described above, the storage array includes a plurality of storage cells 200 arranged in rows and columns, and the array has a first group of 110-1 storage cells and a second group of 110-2 storage cells. As shown in operation 1012, a plurality of word lines WL are provided, wherein each row of array 100 has a corresponding word line WL, and each storage cell 200 of a row of array 100 is coupled to the corresponding word line WL. In operation 1014, a plurality of bit lines are provided, wherein each column of array 100 has a corresponding bit line BL / BLB, and each storage cell 200 of a column of array 100 is coupled to the corresponding bit line BL / BLB. In operation 1016, a group enable signal GROUP_EN is received. In operation 1018, a first operation (e.g., a read operation) is performed on the first group of storage cells in response to the group enable signal, and in operation 1020, a second operation (e.g., a write operation) is performed on the second group of storage cells in response to the group enable signal. In some examples, the first operation 1018 and the second operation 1020 are performed simultaneously or substantially simultaneously. Furthermore, in some embodiments, the first operation 1018 and the second operation 1020 are performed on memory cells 200 within the same selected word line WL. The CIM weight data read from memory cell 200 can then be multiplied by the CIM input signal by a multiplication circuit.

[0054] According to the aspects disclosed herein, the limitations of traditional weighted storage arrangements for CIM, such as limited weighted storage density and limited write throughput, are addressed. Specifically, the disclosed embodiments include a 1T-1C-based weighted storage for CIM, which can increase weighted storage density by using small-area storage cells and can also increase the write throughput of the weighted storage array by employing multitasking on the storage array.

[0055] The disclosed embodiments therefore include a storage device for CIM having a storage array comprising a plurality of storage cells arranged in rows and columns. The storage cells have a first set of storage cells and a second set of storage cells. Each row of the array has a corresponding word line, wherein each storage cell of a row of the array is coupled to the corresponding word line. Each column of the array has a corresponding bit line, wherein each storage cell of a column of the array is coupled to the corresponding bit line. Control circuitry is configured to select either the first set of storage cells or the second set of storage cells in response to a group enable signal.

[0056] According to a further aspect, a CIM device includes a plurality of memory cells configured to store weight signals. The memory cells are arranged in an array of rows and columns, including a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, wherein each memory cell is coupled to the corresponding word line. Each column of the array has a corresponding bit line, wherein each memory cell is coupled to the corresponding bit line. A sense amplifier is coupled to the bit line and configured to amplify the signal on the bit line for a read operation. Control circuitry is connected to the bit line and configured to select either the first group of memory cells or the second group of memory cells in response to a group enable signal. Input terminals are configured to receive input signals, and multiplication circuitry is configured to multiply the weight signals by the input signals to generate a plurality of partial products.

[0057] According to a further disclosed aspect, a CIM method includes providing a storage array having a plurality of storage cells arranged in rows and columns. The storage cells include a first group of storage cells and a second group of storage cells. Multiple word lines are provided, wherein each storage cell in a row of the array is coupled to a corresponding word line. Multiple bit lines are provided, wherein each storage cell in a column of the array is coupled to a corresponding bit line. A group enable signal is received, and in response to the group enable signal, a first operation is performed on the first group of storage cells, and in response to the group enable signal, a second operation is performed on the second group of storage cells.

[0058] This disclosure outlines various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0059] Example 1 is a storage device for computation in memory (CIM) comprising: a storage array including a plurality of storage cells arranged in rows and columns, the storage cells including a first group of storage cells and a second group of storage cells; a plurality of word lines, each row of the array having a corresponding word line, each storage cell of a row of the array being coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each storage cell of a column of the array being coupled to the corresponding bit line; and control circuitry configured to select the first group of storage cells and / or the second group of storage cells in response to a group enable signal.

[0060] Example 2 is the storage device described in Example 1, further comprising: a first sense amplifier coupled to a bit line of the first set of memory cells; and a second sense amplifier coupled to a bit line of the second set of memory cells.

[0061] Example 3 is the storage device described in Example 2, and further includes a multiplexer (MUX) connected to the first sense amplifier and the second sense amplifier.

[0062] Example 4 is the storage device described in Example 1, wherein each of the storage cells includes a transistor and a capacitor to form a single transistor single capacitor (1T-1C) storage cell.

[0063] Example 5 is the memory device described in Example 4, wherein the transistor of the 1T-1C memory cell includes a gate terminal connected to its corresponding word line.

[0064] Example 6 is the memory device described in Example 4, wherein the transistor of the 1T-1C memory cell includes: a first source / drain (S / D) terminal connected to its respective bit line; and a second source / drain (S / D) terminal connected to a first terminal of the capacitor of the 1T-1C memory cell.

[0065] Example 7 is the storage device described in Example 4, wherein the storage array includes a power input terminal configured to receive a VDD voltage, and wherein a second terminal of the capacitor of the 1T-1C storage cell is connected to receive a half VDD voltage.

[0066] Example 8 is the storage device described in Example 1, wherein the storage unit further includes a third group of storage units and a fourth group of storage units.

[0067] Example 9 is the storage device described in Example 8, wherein the control circuitry is configured to select the first group of storage cells and the third group of storage cells, or the second group of storage cells and the fourth group of storage cells, in response to a bit group enable signal.

[0068] Example 10 is the storage device described in Example 8, wherein the control circuit is configured to select the first group of storage cells, the second group of storage cells, the third group of storage cells, or the fourth group of storage cells in response to a two-bit group enable signal.

[0069] Example 11 is the storage device described in Example 1, wherein the control circuitry includes: a first control circuitry connected to bit lines of a first column of the storage array; and a second control circuitry connected to bit lines of a second column of the storage array.

[0070] Example 12 is a computation in memory (CIM) device comprising: a plurality of memory cells configured to store weight signals, the memory cells being arranged in an array of rows and columns, including a first group of memory cells and a second group of memory cells; a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array being coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array being coupled to the corresponding bit line; a sense amplifier coupled to the bit lines and configured to amplify the signals of the bit lines for a read operation; control circuitry connected to the bit lines and configured to select either the first group of memory cells or the second group of memory cells in response to a group enable signal; an input terminal configured to receive a CIM input signal; and a multiplication circuitry configured to multiply the weight signals by the CIM input signals to generate a plurality of partial products.

[0071] Example 13 is the CIM device described in Example 12, further comprising: a multiplexer (MUX) connected to the sense amplifier.

[0072] Example 14 is the CIM device described in Example 12, wherein each of the memory cells includes a transistor and a capacitor to form a single transistor single capacitor (1T-1C) memory cell.

[0073] Example 15 is the CIM device described in Example 12, wherein the storage unit further includes a third group of storage units and a fourth group of storage units.

[0074] Example 16 is the CIM device described in Example 12, further comprising: a single IO adder circuit configured to add the plurality of partial products.

[0075] Example 17 is a method for a computing-in-memory (CIM) device, comprising: providing a memory array having a plurality of memory cells arranged in rows and columns, the memory cells including a first group of memory cells and a second group of memory cells; providing a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array being coupled to the corresponding word line; providing a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array being coupled to the corresponding bit line; receiving a group enable signal; performing a first operation on the first group of memory cells in response to the group enable signal; and performing a second operation on the second group of memory cells in response to the group enable signal.

[0076] Example 18 is the method described in Example 17, wherein the first operation is a read operation and the second operation is a write operation.

[0077] Example 19 is the method described in Example 17, wherein the first operation and the second operation are performed simultaneously.

[0078] Example 20 is the method of Example 17, further comprising: writing a computed (CIM) weight signal from memory into the memory cell; reading the CIM weight signal from the memory cell; receiving a CIM input signal; and multiplying the CIM input signal by the CIM weight signal by a multiplication circuit.

Claims

1. A storage device for calculating CIM in memory, comprising: A storage array comprising a plurality of storage cells arranged in rows and columns, the storage cells comprising a first group of storage cells and a second group of storage cells; Multiple word lines, each row of the array has a corresponding word line, and each storage cell of a row of the array is coupled to the corresponding word line; Multiple bit lines, each column of the array has a corresponding bit line, and each memory cell of each column of the array is coupled to the corresponding bit line; The control circuit is configured to select the first group of memory cells and / or the second group of memory cells in response to a group enable signal; The input terminal is configured to receive CIM input signals; as well as The multiplication circuit is configured to receive a weight signal stored in a selected set of memory cells and multiply the weight signal with the CIM input signal to generate a plurality of partial products.

2. The storage device according to claim 1, further comprising: The first sense amplifier is coupled to the bit line of the first group of memory cells; as well as The second sense amplifier is coupled to the bit line of the second set of memory cells.

3. The memory device of claim 2, further comprising: A multiplexer MUX is connected to the first sense amplifier and the second sense amplifier.

4. The memory device of claim 1, wherein, Each of the memory cells includes a transistor and a capacitor to form a single-transistor single-capacitor 1T-1C memory cell.

5. The memory device of claim 4, wherein, The transistors of the 1T-1C memory cell include: gate terminals connected to their respective word lines.

6. The memory device of claim 4, wherein, The transistors in the 1T-1C memory cell include: The first source / drain S / D terminal is connected to its corresponding bit line; and The second source / drain S / D terminal is connected to the first terminal of the capacitor in the 1T-1C memory cell.

7. The memory device of claim 4, wherein, The storage array includes a power input terminal configured to receive VDD voltage, and wherein the second terminal of the capacitor of the 1T-1C storage cell is connected to receive half VDD voltage.

8. The memory device of claim 1, wherein, The storage unit also includes a third group of storage units and a fourth group of storage units.

9. The memory device of claim 8, wherein, The control circuit is configured to select the first group of memory cells and the third group of memory cells, or the second group of memory cells and the fourth group of memory cells, in response to a bit group enable signal.

10. The storage device according to claim 8, wherein, The control circuit is configured to select the first group of storage cells, the second group of storage cells, the third group of storage cells, or the fourth group of storage cells in response to a two-bit enable signal.

11. The storage device according to claim 1, wherein, The control circuit includes: A first control circuit is connected to the bit lines of the first column of the memory array; and The second control circuit is connected to the bit lines of the second column of the memory array.

12. A memory-based CIM computing device, comprising: Multiple storage cells are configured to store weight signals, and the storage cells are arranged in an array of rows and columns, including a first group of storage cells and a second group of storage cells; Multiple word lines, each row of the array has a corresponding word line, and each storage cell of a row of the array is coupled to the corresponding word line; Multiple bit lines, each column of the array has a corresponding bit line, and each memory cell of each column of the array is coupled to the corresponding bit line; The readout amplifier is coupled to the bit line and configured to amplify the signal of the bit line for readout operation; A control circuit, connected to the bit line and configured to select either the first group of memory cells or the second group of memory cells in response to a group enable signal; The input terminal is configured to receive CIM input signals; as well as The multiplication circuit is configured to multiply the weight signal with the CIM input signal to generate a plurality of partial products.

13. The CIM device according to claim 12, further comprising: A multiplexer MUX is connected to the sense amplifier.

14. The CIM device according to claim 12, wherein, Each of the memory cells includes a transistor and a capacitor to form a single-transistor single-capacitor 1T-1C memory cell.

15. The CIM device according to claim 12, wherein, The storage unit also includes a third group of storage units and a fourth group of storage units.

16. The CIM device according to claim 12, further comprising: A single-IO adder circuit is configured to add the products of the plurality of parts.

17. A method for computing a CIM device in memory, comprising: A storage array is provided having a plurality of storage cells arranged in an array of rows and columns, the storage cells including a first group of storage cells and a second group of storage cells; Multiple word lines are provided, each row of the array has a corresponding word line, and each memory cell of each row of the array is coupled to the corresponding word line; Multiple bit lines are provided, each column of the array has a corresponding bit line, and each memory cell of the column of the array is coupled to the corresponding bit line; Receive group enable signal; In response to the group enable signal, a first operation is performed on the first group of memory cells; as well as In response to the group enable signal, a second operation is performed on the second group of memory cells. The method further includes: Write the calculated CIM weight signal from the memory into the storage unit; Read the CIM weight signal from the storage unit; Receive CIM input signals; and The CIM input signal is multiplied by the CIM weight signal by the multiplication circuit.

18. The method according to claim 17, wherein, The first operation is a read operation, and the second operation is a write operation.

19. The method of claim 17, wherein, The first operation and the second operation are executed simultaneously.

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