Power supply circuit, semiconductor device, and power supply sensing circuit

Abstract

The present application relates to a power supply circuit, a semiconductor device, and a power supply sensing circuit. A power supply circuit includes at least one power detector coupled to both a first power supply voltage input via a pin or a pad and a second power supply voltage provided to a component and configured to output a sensed power supply voltage changed from the first power supply voltage in response to a drop of the second power supply voltage, and a comparator configured to compare the sensed power supply voltage with a reference voltage to output a power supply sensing result.

Description

TECHNICAL FIELD

[0001] Various embodiments of the present disclosure described herein relate to a semiconductor device, and particularly, to an apparatus and method for monitoring a power supply in a semiconductor device. BACKGROUND

[0002] A semiconductor device includes a device for efficiently controlling and managing an externally supplied power supply. The semiconductor device can include at least one regulator. The regulator can be designed to generate a constant or stable voltage and supply the constant or stable voltage to a load included in the semiconductor device. When the external power supply is unstable or the load inside the semiconductor device is too large, the voltage output from the regulator can drop or fluctuate. The semiconductor device can include a sensing circuit for checking or monitoring the voltage drop output from the regulator. SUMMARY

[0003] Embodiments of the present disclosure can provide an apparatus and method capable of efficiently managing a power supply inside a semiconductor device.

[0004] The apparatus according to an embodiment of the present disclosure can quickly detect a drop in a power supply voltage that can occur when the power supply provided to the semiconductor device is unstable due to internal operations or internal structures or the electrical load is too large. In addition, another embodiment can provide an apparatus and method capable of detecting a location or area in which a drop in the power supply voltage has occurred in the semiconductor device.

[0005] When a power supply is provided through a plurality of pins or pads included in a semiconductor device chip, a plurality of sensing circuits capable of sensing a power supply voltage can be provided for each corresponding pin or pad. The plurality of sensing circuits are coupled to both a first power supply voltage provided from the outside of the semiconductor device chip and a second power supply voltage used in internal circuits of the semiconductor device chip. When the second power supply voltage drops, the first power supply voltage can be adjusted or changed. A comparison circuit can compare the change in the first power supply voltage with a reference voltage to output a comparison result.

[0006] According to one embodiment, the comparison circuit can be selectively connected to one of the plurality of sensing circuits. The comparison circuit can reduce noise that can be caused by parasitic capacitance or the like in the process of transferring the change in the first power supply voltage output from each of the plurality of sensing circuits. In addition, the sensing circuit can identify a drop in the second power supply voltage by checking or monitoring the first power supply voltage provided through the pin or pad rather than checking or monitoring the second power supply voltage directly provided to the load in the semiconductor device chip. Further, the process for checking or monitoring the second power supply voltage can not affect the level of the second power supply voltage, so that an effect of the process on the second power supply voltage can be avoided.

[0007] In addition, according to one embodiment, a second power voltage used at another location can be selectively connected to a specific location where the second power voltage is dropped to compensate for the drop in the second power voltage.

[0008] In one embodiment, the power supply circuit can include at least one power detector coupled to a first power voltage input via a pin or a pad and a second power voltage supplied to a component and configured to output a sensed power voltage changed from the first power voltage in response to a drop in the second power voltage, and a comparator configured to compare the sensed power voltage with a reference voltage to output a power sensing result.

[0009] The at least one power detector can include a first element configured to receive the first power voltage, output the second power voltage, and maintain a difference between the first power voltage and the second power voltage to be below a preset value.

[0010] The first element can be turned on when a difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and turned off when the difference is less than the preset value.

[0011] The first element can include a diode including an anode coupled to the sensed power voltage and a cathode coupled to the second power voltage.

[0012] The at least one power detector can include a second element configured to selectively transfer the first power voltage, a third element configured to maintain a level of the first power voltage transferred by the second element, and a fourth element configured to transfer the sensed power voltage maintained or changed by the first element and the third element to the comparator in response to a sensing signal.

[0013] The sensing signal can be input to the at least one power detector and the comparator. The comparator can output the power sensing result when the sensing signal is activated.

[0014] The at least one power detector can include N power detectors, and the sensing signal can include a plurality of sensing signals. The plurality of sensing signals are respectively input to the N power detectors. The comparator can be configured to output the power sensing result when one of the plurality of sensing signals is activated.

[0015] The power supply circuit can further include at least one switch configured to couple each of the N power detectors to the comparator.

[0016] In another embodiment, a semiconductor device can include a plurality of pins or pads coupled to a first power voltage input from an external device, a power supply circuit coupled to the plurality of pins or pads and configured to output a second power voltage, and a plurality of internal circuits coupled to the power supply circuit and configured to store or process data items using the second power voltage. The power supply circuit can include a plurality of power detectors respectively coupled to one of the plurality of pins or pads and configured to respectively output a sensed power voltage changed from the first power voltage in response to a drop in the second power voltage, and a comparator configured to compare the sensed power voltage output from one of the plurality of power detectors with a reference voltage to output a power sense result.

[0017] The power supply circuit can further include a low dropout (LDO) regulator configured to receive the first power voltage and output the second power voltage having a minimum input / output voltage difference capable of stabilizing operations performed by the plurality of internal circuits.

[0018] The power supply circuit can further include a plurality of switches configured to couple each of the plurality of power detectors to the comparator.

[0019] Each of the plurality of power detectors can include a first element configured to receive the first power voltage, output the second power voltage, and maintain a difference between the first power voltage and the second power voltage to be below a preset value.

[0020] The first element can be turned on when a difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and turned off when the difference is less than the preset value.

[0021] The first element can include a diode including an anode coupled to the sensed power voltage and a cathode coupled to the second power voltage.

[0022] Each of the plurality of power detectors can include a second element configured to selectively transfer the first power voltage, a third element configured to maintain a level of the first power voltage transferred by the second element, and a fourth element configured to transfer the sensed power voltage maintained or changed by the first element and the third element to the comparator in response to a sensing signal.

[0023] Each of the plurality of sensing signals can be input to each of the plurality of power detectors and the comparator. When one of the plurality of sensing signals is activated, the comparator can output a power sense result corresponding to the activated sensing signal.

[0024] When one of the plurality of sensing signals is activated, the comparator is configured to compare a sensing power voltage output from one of the plurality of power detectors in response to the activated sensing signal with a reference voltage to output a power sensing result.

[0025] In another embodiment, a power sensing circuit is provided, which is coupled to a first power voltage input from an external device via a plurality of pins or pads and a second power voltage provided to an internal circuit, and is configured to compare the first power voltage, which is changed based on a change in the second power voltage, with a reference voltage to output a power sensing result when the change in the second power voltage occurs. The power sensing circuit can detect the change in the second power voltage without affecting the level of the second power voltage.

[0026] The power sensing circuit can include a diode including an anode coupled to the first power voltage and a cathode coupled to the second power voltage, and the diode is configured to maintain a difference between the first power voltage and the second power voltage to be below a preset value.

[0027] The diode can be turned on when the difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and can be turned off when the difference is less than the preset value.

[0028] In one embodiment, a semiconductor circuit can include a power circuit adapted to generate an internal power voltage from an external power voltage, and a load circuit adapted to operate based on the internal power voltage, the operation causing a fluctuation in the internal power voltage. The power circuit can include a diode having an anode initially pre-charged to a level of the external power voltage and a cathode coupled to the internal power voltage, and adapted to sense a level on the anode changed due to the internal power voltage, and a comparator adapted to compare the sensed level with a reference level to generate a comparison result. BRIEF DESCRIPTION OF DRAWINGS

[0029] The description herein makes reference to the accompanying drawings, wherein like reference numerals refer to like parts throughout the several views, and merits of embodiments of the present disclosure are illustrated by way of example as follows.

[0030] Figure 1 A semiconductor device chip according to an embodiment of the present disclosure is illustrated.

[0031] Figure 2 A data processing system according to an embodiment of the present disclosure is illustrated.

[0032] Figure 3 A semiconductor device chip according to another embodiment of the present disclosure is illustrated.

[0033] Figure 4A voltage sensor according to an embodiment of the present disclosure is exemplified.

[0034] Figure 5 A power supply circuit according to an embodiment of the present disclosure is exemplified.

[0035] Figure 6 A power supply circuit according to an embodiment of the present disclosure is exemplified. Figure 5 Operation of the power supply circuit shown in FIG. 1.

[0036] Figure 7 A power supply circuit according to another embodiment of the present disclosure is exemplified. DETAILED DESCRIPTION

[0037] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, elements and features of the present disclosure can be configured or arranged differently to form other embodiments that can be variations of any of the disclosed embodiments.

[0038] In the present disclosure, reference to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment," "an example embodiment," "an embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "alternative embodiments," and the like, while intended to represent that any such features are included in one or more embodiments of the present disclosure, such features can or can not be combined in the same embodiment.

[0039] In the present disclosure, the terms "include," "comprise," and their derivatives are open-ended. As used in the appended claims, these terms specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. The stated terms do not preclude that the device includes additional components (e.g., interface units, circuitry, etc.).

[0040] In the present disclosure, various units, circuits, or other components can be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that a block / circuit / component includes structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit / circuit / component can be said to be configured to perform the task even when the specified block / circuit / component is not currently operational (e.g., is not on or activated). Where a block / circuit / component is configured to perform a task, that block / circuit / component includes the structure for performing that task, where the structure is either present or is fabricated during the manufacturing process (e.g., an integrated circuit is configured to perform a task during operation). In some contexts, a block / circuit / component can be configured to perform a task even when it is not currently operational (e.g., not powered on or active). In addition to circuits / software, various non-circuit / software-based hardware can be used to implement the functions described herein, including, for example, microcode, gate arrays, pass gates, logic, etc.

[0041] As used in the present disclosure, the terms “circuit” or “logic” refer to all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and / or digital circuitry) and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s) / software (including digital signal processors), software, and memory that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and (c) circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware for operation, even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of this term in this application including any claims. As a further example, as used herein, the term “circuit” or “logic” also encompasses an implementation that is a processor (or multiple processors) or a portion of a processor plus its (or their) accompanying software and / or firmware. The term “circuit” or “logic” also encompasses, for example, an integrated circuit for storing a storage device, if applicable to a particular claim element.

[0042] As used herein, the terms “first,” “second,” “third,” etc. are used as labels for nouns that they precede, and do not necessarily describe the order, frequency, or importance of those entities. The terms “first” and “second” do not necessarily mean that the first value must be written before the second value. Additionally, although terms can be used herein to identify various elements, the elements are not limited by the terms. The terms are used to distinguish one element from another element having a same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0043] Also, the term "based on" is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that can affect a determination. That is, a determination can be solely based on those factors or based, at least in part, on those factors. For example, a decision that is "based on" B, while B is a factor that affects the determination, does not foreclose the decision from also being based on C. In other words, a determination can be based on B and C even though C is a factor that affects the determination.

[0044] In this document, a term of data, data item, data entry, or entry of data can be a sequence of bits. For example, a data item can include content of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to one embodiment, a data item can include a discrete object. According to another embodiment, a data item can include an information unit within a transmission packet between two different components.

[0045] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

[0046] Figure 1 A semiconductor device chip according to an embodiment of the present disclosure is exemplified.

[0047] Referring to Figure 1 The semiconductor device chip 200 can include electronic elements and circuits to perform a specific function. The semiconductor device chip 200 can include a plurality of pins or pads, and can receive or output a power voltage, a data item, a command, or various control signals through the plurality of pins or pads. The circuits or electronic elements included in the semiconductor device chip 200 can vary according to a design purpose, and the number of the plurality of pins or pads included in the semiconductor device chip can also vary according to a design.

[0048] The plurality of pins or pads can be used according to a preset function or purpose. For example, when a specific pin or pad among the plurality of pins or pads is set to be used for data input / output, an electrical signal (e.g., a waveform or a potential within a specific voltage range) corresponding to a data item is transmitted to the corresponding pin or pad. Also, when a power voltage is provided to a specific pin or pad, the specific pin or pad can be used to receive a power voltage for operation of internal components included in the semiconductor device chip.

[0049] Semiconductor devices such as memory systems or processors satisfying user demands have been developed to operate at higher speeds and consume less power. A semiconductor device chip 200 can include a plurality of circuits or modules to perform various functions. When a plurality of circuits, modules, or components performing a plurality of functions are formed in a plurality of different semiconductor chips, a delay and noise can occur in a process of transferring data and signals between the circuits, modules, or components of the plurality of different semiconductor chips, thereby causing a decrease in operating performance of the memory system or the processor. Recently, the semiconductor device chip 200 can be designed to include various circuits, modules, or components, thereby improving the performance of the semiconductor device and increasing the integration of the semiconductor device.

[0050] As a plurality of circuits, modules, or components are included in a single semiconductor device chip 200, a change in an electrical load inside the semiconductor device chip 200 can increase. Referring to FIG. 1, a plurality of circuits, modules, or components 210, 220, 230, 240, and 250 can be included in the semiconductor device chip 200. The plurality of circuits, modules, or components 210, 220, 230, 240, and 250 can include a processor 210, a memory controller 220, a graphics processing unit (GPU) 230, a display driver 240, and a communication interface 250. The plurality of circuits, modules, or components 210, 220, 230, 240, and 250 can be formed in a single semiconductor chip 200. Figure 1 A power supply voltage VCC can be provided through a plurality of pins or pads included in the semiconductor device chip to operate the plurality of circuits, modules, or components included in the semiconductor device chip 200. Including additional circuits for distributing and managing power in the semiconductor device chip 200 instead of circuits, modules, or components for performing operations of the semiconductor device can become an obstacle to increasing the integration of the semiconductor device. Accordingly, to provide the power supply voltage to the plurality of circuits, modules, or components in the semiconductor device chip 200, the power supply voltage VCC can be received through a plurality of pins or pads instead of a single pin or pad.

[0051] According to an embodiment, the plurality of pins or pads for receiving the power supply voltage VCC can be arranged dispersedly at different locations of the semiconductor device chip 200. When the semiconductor device chip 200 is divided into a plurality of regions (dotted lines), at least one pin or pad for receiving the power supply voltage VCC can be provided in each region of the semiconductor device chip 200.

[0052] When the power supply voltage VCC is provided through a plurality of pins or pads to supply power to the plurality of circuits, modules, or components, it can be difficult to detect a location where a power problem occurs in the semiconductor device chip 200. To detect whether an internal power supply voltage for driving the plurality of circuits, modules, or components becomes unstable, it can be actually difficult to individually check or monitor the internal power supply voltage provided to each of the plurality of circuits, modules, or components. In particular, when operations are performed by the plurality of circuits, modules, or components, the internal power supply voltage can become unstable due to an increase or decrease in an electrical load. For example, a drop in the internal power supply voltage can occur due to an excessive increase in the load. A drop in the power supply voltage provided to at least some of the plurality of circuits, modules, or components can cause an unexpected error in the semiconductor device or seriously affect the operating performance of the semiconductor device.

[0053] A semiconductor device according to an embodiment of the disclosure can include an apparatus capable of efficiently detecting a drop of a power supply voltage provided to a plurality of circuits, modules, or components. In addition, even when a power supply voltage VCC can be input through a plurality of pins or pads and provided to a plurality of circuits, modules, or components, an apparatus such as a power supply circuit can check or monitor a change or drop of the power supply voltage at a specific location or a specific portion of the semiconductor device and output a check or monitoring result. Furthermore, based on information about internal operations performed within the semiconductor device and the check or monitoring result of detecting the change or drop of the power supply voltage, the apparatus can determine which operation performed within the semiconductor device can cause instability of the power supply voltage and / or a location at which a specific operation is performed within the semiconductor device. Even in the event of a drop of the power supply voltage at a specific location or portion of the semiconductor device, the apparatus can compensate for the drop of the power supply voltage at the specific location or portion using a power supply voltage provided at another location or portion of the semiconductor device.

[0054] An apparatus such as a power supply circuit according to an embodiment can be applicable to a non-volatile memory device or a memory system including the non-volatile memory device. In addition, according to another embodiment, the power supply circuit can be applicable to a volatile memory device or a memory system including the volatile memory device. The power supply circuit can also be applicable to a processor, a system IC, etc. designed for a specific purpose. Hereinafter, with reference to Figure 1 and Figure 2 A memory system implemented in a semiconductor device chip including a power supply circuit according to an embodiment will be described.

[0055] Figure 2 A data processing system according to an embodiment of the disclosure is exemplified.

[0056] With reference to Figure 2 , a data processing system 100 can include a host 102 interfaced or coupled with a memory system such as a memory system 110. For example, the host 102 and the memory system 110 can be coupled with each other via a data bus, a host cable, etc. to perform data communication.

[0057] The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 can be considered as components or elements physically separated from each other. The memory device 150 and the controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a way.

[0058] According to one embodiment, the memory device 150 and the controller 130 can be components or elements functionally divided. In addition, according to one embodiment, a memory device 150 and a controller 130 can be implemented as a single component or element. Figure 1The single semiconductor device chip 200 or the plurality of semiconductor device chips implements the memory device 150 and the controller 130 as illustrated. According to an embodiment, when higher integration of the memory system 110 can be required, the memory device 150 and the controller 130 can be included in the single semiconductor device chip 200. The controller 130 can perform a data input / output operation in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0059] As illustrated, Figure 2 The memory device 150 can include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane can be considered as a logical or physical partition that includes at least one memory block, a drive circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0060] For example, the memory device 150 can include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane can be considered as a logical or physical partition that includes at least one memory block, a drive circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0061] In addition, according to an embodiment, a memory die can include at least one memory plane. A memory die can be understood as a set of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 through a data path. Each memory die can include an interface for exchanging data items and signals with the controller 130.

[0062] According to an embodiment, the memory device 150 can include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 2 The internal configuration of the memory device 150 as illustrated can be different according to the performance of the memory system 110. Embodiments of the present disclosure are not limited to Figure 2 the internal configuration as illustrated.

[0063] Referring to Figure 2The memory device 150 can include a power supply circuit 170 capable of supplying at least some of the voltages to the memory blocks 152, 154, 156. The power supply circuit 170 can supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the nonvolatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the nonvolatile memory cells included in the memory blocks 152, 154, 156, the power supply circuit 170 can supply the read voltage Vrd to the selected nonvolatile memory cells. During a program operation for storing data in the nonvolatile memory cells included in the memory blocks 152, 154, 156, the power supply circuit 170 can supply the program voltage Vprog to the selected nonvolatile memory cells. Also, during the read operation or the program operation performed on the selected nonvolatile memory cells, the power supply circuit 170 can supply the pass voltage Vpass to the unselected nonvolatile memory cells. During an erase operation for erasing data stored in the nonvolatile memory cells included in the memory blocks 152, 154, 156, the power supply circuit 170 can supply the erase voltage Vers to the memory blocks.

[0064] The memory device 150 can store information about various voltages supplied to the memory blocks 152, 154, 156 based on which operation is performed. For example, when the nonvolatile memory cells in the memory blocks 152, 154, 156 can store multi-bit data, a plurality of levels of the read voltage Vrd for identifying or reading the multi-bit data item can be required. The memory device 150 can include a table including information corresponding to the plurality of levels of the read voltage Vrd corresponding to the multi-bit data item. For example, the table can include bias values stored in a register, each of which corresponds to a specific level of the read voltage Vrd. The number of bias values for the read voltage Vrd for the read operation can be limited within a preset range. Also, the bias values can be quantized.

[0065] The power supply circuit 170 in the memory device 150 can generate a plurality of voltages having various levels based on the power supply voltage VCC. In this operation, the amount of the electrical load can be increased or decreased. For example, when a high-level voltage such as the program voltage Vprog is repeatedly generated and used in the memory device 150, the electrical load can rapidly increase, so that a temporary drop of the power supply voltage VCC can occur. Referring to Figure 3 The power supply circuit 210 in the semiconductor device chip 200 can detect the drop of the power supply voltage VCC and output the detection result to the controller 130.

[0066] The host 102 can include a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, a game console, a television, a projector, etc.).

[0067] The host 102 can further include at least one operating system (OS) capable of controlling functions and operations performed in the host 102. The OS can provide interoperability between the host 102 and a user intending to store data in the memory system 110, operatively interfacing with the memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, without limitation, the OS can be classified into a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified into a personal operating system and an enterprise operating system according to system requirements or user environments. The enterprise operating system can be specialized for securing and supporting high-performance computing, as compared with the personal operating system.

[0068] The mobile operating system can tend to support services or functions for mobility (e.g., power saving functions). The host 102 can include a plurality of operating systems. The host 102 can execute a plurality of operating systems interlocked with the memory system 110 corresponding to user requests. The host 102 can transmit a plurality of commands corresponding to user requests to the memory system 110, thereby performing operations corresponding to the plurality of commands within the memory system 110.

[0069] The controller 130 in the memory system 110 can control the memory device 150 in response to a request or a command input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or a program operation) to store data input from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control and manage internal operations of reading data, programming data, erasing data, etc.

[0070] According to an embodiment, the controller 130 can include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. As Figure 2 Components included in the controller 130 as shown can vary according to structures, functions, operational performance, etc. of the memory system 110.

[0071] For example, depending on the protocol of the host interface, the memory system 110 can be implemented with any one of various types of storage devices that can be electrically coupled with the host 102. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0072] The host 102 and the memory system 110 can each include a controller or an interface for transmitting and receiving signals, data, and the like according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device capable of transmitting signals, data, and the like to the host 102 or receiving signals, data, and the like from the host 102.

[0073] The host interface 132 included in the controller 130 can receive signals, commands (or requests), and / or data input from the host 102. For example, the host 102 and the memory system 110 can transmit and receive data between them using a predetermined protocol. Examples of a set of rules or procedures of data communication or an interface supported by the host 102 and the memory system 110 for transmitting and receiving data include a universal serial bus (USB), a multimedia card (MMC), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCIe or PCI-e), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a mobile industry processor interface (MIPI), and the like. According to one embodiment, the host interface 132 is a type of layer for exchanging data with the host 102, and is implemented by or driven by firmware called a host interface layer (HIL).

[0074] An integrated drive electronics (IDE) or an advanced technology attachment (ATA) can be used as one of the interfaces to transmit and receive data, and can use, for example, a cable including 40 wires connected in parallel to support data transmission and data reception between the host 102 and the memory system 110. When a plurality of memory systems 110 are connected to a single host 102, the plurality of memory systems 110 can be divided into master and slave by using a location or a dip switch to which the plurality of memory systems 110 are connected. The memory system 110 set as master can be used as a master memory device. The IDE (ATA) can include, for example, a fast ATA, an ATAPI, or an enhanced IDE (EIDE).

[0075] A serial advanced technology attachment (SATA) interface is a type of serial data communication interface compatible with various ATA standards used in an integrated drive electronics (IDE) device. The 40 wires in the IDE interface can be reduced to 6 wires in the SATA interface. For example, the 40 parallel signals for the IDE can be converted into 6 serial signals for the SATA interface. The SATA interface is widely used due to its faster data transmission and reception rate, and less resource consumption in the host 102 for data transmission and reception. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. In addition, the SATA interface can support hot plugging that allows an external device to be attached to or detached from the host 102 even when data communication is being performed between the host 102 and another device. Accordingly, the memory system 110 can be connected or disconnected as an additional device (such as a universal serial bus (USB) supported device) even when the host 102 is powered on. For example, in a host 102 having an eSATA port, the memory system 110 can be freely attached to or detached from the host 102 like an external hard disk.

[0076] A small computer system interface (SCSI) is a type of serial data communication interface for connecting a computer or a server with other peripheral devices. The SCSI can provide a high transmission speed compared to other interfaces such as IDE and SATA. In the SCSI, the host 102 and at least one peripheral device (for example, the memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In the SCSI, it is easy to connect or disconnect a device such as the memory system 110 to or from the host 102. The SCSI can support connection of 15 other devices to a single transceiver included in the host 102.

[0077] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and a plurality of peripheral devices are connected in series, and data transmission and reception between the host 102 and each of the peripheral devices can be performed in a serial data communication scheme. SAS can support connection between the host 102 and the peripheral devices through a serial cable instead of a parallel cable to easily manage devices using SAS and enhance or improve operation reliability and communication performance. SAS can support connection of eight external devices to a single transceiver included in the host 102.

[0078] NVM Express (NVMe) is an interface type based on at least Peripheral Component Interconnect Express (PCIe) designed to improve performance and design flexibility of a host 102, a server, a computing device, etc. equipped with a non-volatile memory system 110. PCIe can use a slot or a specific cable to connect a computing device (e.g., the host 102) and a peripheral device (e.g., the memory system 110). For example, PCIe can use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to implement high-speed data communication of more than several hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s) per second. According to an embodiment, a PCIe scheme can implement a bandwidth of several tens to several hundreds of gigabits per second. NVMe can support an operating speed of a non-volatile memory system 110 such as an SSD faster than a hard disk.

[0079] According to an embodiment, the host 102 and the memory system 110 can be connected through a Universal Serial Bus (USB). The Universal Serial Bus (USB) is an extensible, hot-pluggable, plug-and-play serial interface that can provide an economical and efficient standard connection between the host 102 and peripheral devices such as a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, etc. A plurality of peripheral devices such as the memory system 110 can be coupled to a single transceiver included in the host 102.

[0080] Referring to Figure 2The error correction circuit 138 can correct error bits of data read from the memory device 150 and can include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed in the memory device 150 to generate encoded data with parity bits added and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder can detect and correct error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on data read from the memory device 150, the error correction circuit 138 determines whether the error correction decoding is successful and outputs an instruction signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. The error correction circuit 138 can use the parity bits generated during the ECC encoding process for the data stored in the memory device 150 in order to correct error bits of the read data. When the number of error bits is greater than or equal to the number of correctable error bits, the error correction circuit 138 can not correct the error bits but can output a correction failure signal indicating that the correction of the error bits failed.

[0081] According to an embodiment, the error correction circuit 138 can perform an error correction operation based on encoding modulation such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), a block coded modulation (BCM), etc. The error correction circuit 138 can include all circuits, modules, systems, and / or devices for performing an error correction operation based on at least one of the above-mentioned codes.

[0082] For example, the ECC decoder can perform hard decision decoding or soft decision decoding on data transmitted from the memory device 150. Hard decision decoding can be understood as one of two methods broadly classified for error correction. Hard decision decoding can include an operation of correcting error bits by reading digital data of “0” or “1” from a non-volatile memory cell in the memory device 150. Because hard decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster than soft decision decoding.

[0083] Soft decision decoding can quantize a threshold voltage of a non-volatile memory cell in the memory device 150 by two or more quantized values (e.g., multi-bit data, an approximate value, an analog value, etc.) in order to correct error bits based on the two or more quantized values. The controller 130 can receive two or more letters or quantized values from a plurality of non-volatile memory cells in the memory device 150 and then perform decoding based on information generated by characterizing the quantized values as a combination of information such as conditional probability or likelihood.

[0084] According to an embodiment, the ECC decoder can use a low-density parity-check and generator matrix (LDPC-GM) code among methods designed for soft-decision decoding. A low-density parity-check (LDPC) code uses an algorithm that can read values of data from the memory device 150 by several bits according to reliability, not just data 1 or 0 as in hard-decision decoding, and iteratively repeats by message passing to improve reliability of the values. Then, the values are finally determined as data 1 or 0. For example, a decoding algorithm using the LDPC code can be understood as a probabilistic decoding. In contrast to hard-decision decoding in which values output from the non-volatile memory cells are encoded as 0 or 1, soft-decision decoding can determine values stored in the non-volatile memory cells based on random information. With respect to bit flips, which can be considered as errors likely to occur in the memory device 150, soft-decision decoding can provide a probability of improving correction of errors and recovery of data, and provide reliability and stability of correcting data. The LDPC-GM code can have a scheme in which an inner LDGM code can be connected in series with a high-speed LDPC code.

[0085] According to an embodiment, the ECC decoder can use, for example, a low-density parity-check convolutional code (LDPC-CC) for soft-decision decoding. The LDPC-CC can have a scheme using linear-time encoding and pipelined decoding based on a variable block length and a shift register.

[0086] According to an embodiment, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. A log-likelihood ratio (LLR) can be calculated as a non-linear function with respect to a distance between a sampled value and an ideal value. In addition, a Turbo code (TC) can include a simple code (e.g., a Hamming code) in two or three dimensions, and repeatedly decodes in a row direction and a column direction to improve reliability of the values.

[0087] A power management unit (PMU) 140 can control power supplied to the controller 130. The PMU 140 can monitor power supplied to the memory system 110 (e.g., a voltage supplied to the controller 130) and supply power to components included in the controller 130. The PMU 140 can not only detect power-on or power-off, but also generate a trigger signal to make the memory system 110 urgently back up a current state when power supplied to the memory system 110 is unstable. According to an embodiment, the PMU 140 can include a device or a component capable of accumulating power that can be used in an emergency.

[0088] According to an embodiment, the PMU 140 can include a device or a component capable of accumulating power that can be used in an emergency. Figure 1 and Figure 4The power supply circuit 210 in the semiconductor device chip described receives a detection result regarding a drop in a power supply voltage. The PMU 140 can check the safety of an operation performed in the memory system 110 in response to the detection result. Further, according to one embodiment, the PMU 140 can temporarily stop the operation of the memory system 110 in response to the detection result, or can cause the operation to be performed again when the safety or integrity of the operation is suspected.

[0089] The memory interface 142 can serve as an interface for processing commands and data transferred between the controller 130 and the memory device 150, in order to cause the controller 130 to control the memory device 150 in response to a command or request input from the host 102. In the case where the memory device 150 is a flash memory, the memory interface 142 can generate a control signal for the memory device 150 under the control of the processor 134 and can process data input to or output from the memory device 150.

[0090] For example, when the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 can provide an interface for processing commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented by or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0091] According to one embodiment, the memory interface 142 can support an open NAND flash interface (ONFi), a toggle mode, etc., for data input / output with the memory device 150. For example, the ONFi can use a data path (e.g., a channel, a lane, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between the controller 130 and the memory device 150 can be implemented through at least one interface regarding an asynchronous single data rate (SDR), a synchronous double data rate (DDR), a double data rate (DDR), etc.

[0092] The memory 144 can be used as a working memory of the memory system 110 or the controller 130 while temporarily storing transaction data of operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data output from the memory device 150 in response to a read request from the host 102 before the read data is output to the host 102. Also, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before the write data is programmed in the memory device 150. When the controller 130 controls operations of the memory device 150 such as a data read operation, a data write or program operation, a data erase operation, etc., data transmitted between the controller 130 and the memory device 150 of the memory system 110 can be temporarily stored in the memory 144.

[0093] In addition to read data or write data, the memory 144 can store information (e.g., mapping data, read requests, program requests, etc.) for inputting or outputting data between the host 102 and the memory device 150. According to an embodiment, the memory 144 can include one or more of a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc. The controller 130 can allocate some storage space in the memory 144 for components established to perform data input / output operations. For example, a write buffer established in the memory 144 can be used to temporarily store target data subjected to a program operation.

[0094] In an embodiment, the memory 144 can be implemented with volatile memory. For example, the memory 144 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 The memory 144, for example, disposed within the controller 130 is exemplified, but embodiments are not limited thereto. The memory 144 can be located inside or outside of the controller 130. For example, the memory 144 can be implemented by an external volatile memory having a memory interface that transmits data and / or signals between the memory 144 and the controller 130.

[0095] The processor 134 can control overall operations of the memory system 110. For example, the processor 134 can control a program operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 102. According to an embodiment, the processor 134 can execute firmware to control a program operation or a read operation in the memory system 110. Herein, the firmware can be referred to as a flash translation layer (FTL). Reference will be made to FIG. 2 to describe the firmware. Figure 3 and Figure 4Detailed description of an example of FTL. According to an embodiment, the processor 134 can be implemented with a microprocessor, a central processing unit (CPU), or the like.

[0096] According to an embodiment, the memory system 110 can be implemented with at least one multi-core processor. A multi-core processor is a type of circuit or chip in which two or more cores, which are regarded as different processing regions, are integrated. For example, when the plurality of cores in the multi-core processor independently drive or execute a plurality of flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be independently executed by different cores in the multi-core processor.

[0097] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Also, the memory system 110 can perform operations independent of the commands or requests input from the host 102. In one case, the operations performed by the controller 130 in response to the requests or commands input from the host 102 can be considered foreground operations, and the operations performed by the controller 130 independent of the requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. In addition, parameter setting operations corresponding to a set parameter command or a set feature command, which are set commands, transmitted from the host 102 can be considered foreground operations. As background operations performed without commands transmitted from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and processing bad blocks, and the like.

[0098] According to an embodiment, substantially similar operations can be performed as both foreground operations and background operations. For example, when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or a command input from the host 102, the garbage collection can be considered a foreground operation. When the memory system 110 performs garbage collection (e.g., automatic GC) independent of the host 102, the garbage collection can be considered a background operation.

[0099] When the memory device 150 includes a plurality of wafers (or a plurality of chips) each having a plurality of nonvolatile memory cells, the controller 130 can perform parallel processing with respect to a plurality of requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the transmitted requests or commands can be divided into a plurality of groups including at least some of a plurality of planes, a plurality of wafers, or a plurality of chips included in the memory device 150, and the plurality of groups of requests or commands are individually or in parallel processed in each plane, each wafer, or each chip.

[0100] The memory interface 142 in the controller 130 can be connected to a plurality of dies or a plurality of chips in the memory device 150 through at least one lane and at least one path. When the controller 130 allocates and stores data in the plurality of dies through each lane or each path in response to a request or a command associated with a plurality of pages including non-volatile memory cells, a plurality of operations corresponding to the request or the command can be performed simultaneously or in parallel in the plurality of dies or the plurality of planes. Such a processing method or scheme can be considered as an interleaving method. Because the data input / output speed of the memory system 110 is increased by operating in the interleaving method, the data I / O performance of the memory system 110 can be improved.

[0101] By way of example and not limitation, the controller 130 can identify a state of a plurality of lanes (or paths) associated with a plurality of dies included in the memory device 150. The controller 130 can determine a state of each lane or each path as one of a busy state, a ready state, an active state, an idle state, a normal state, and an abnormal state. The determination of which lane or path the controller passes an instruction (and / or data) through can be associated with a physical block address. The controller 130 can refer to a descriptor passed from the memory device 150. The descriptor can include a block or a page describing parameters about certain things regarding the memory device 150. The descriptor can have a predetermined format or structure. For example, the descriptor can include a device descriptor, a configuration descriptor, a cell descriptor, etc. The controller 130 can refer to or use the descriptor to determine which lane or path to exchange an instruction or data with.

[0102] Referring to Figure 2 The memory device 150 in the memory system 110 can include a plurality of memory blocks 152, 154, 156. Each of the plurality of memory blocks 152, 154, 156 includes a plurality of non-volatile memory cells. According to one embodiment, the memory blocks 152, 154, 156 can be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, 156 can include a plurality of pages that are a group of non-volatile memory cells that are read or programmed together.

[0103] In one embodiment, each memory block 152, 154, or 156 can have a three-dimensional layer stack structure for high integration. Further, the memory device 150 can include a plurality of dies each including a plurality of planes each including a plurality of memory blocks 152, 154, 156. The configuration of the memory device 150 can be varied according to the performance of the memory system 110.

[0104] Figure 2A memory device 150 including a plurality of memory blocks 152, 154, and 156 is illustrated. The plurality of memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and the like, depending on the number of bits that can be stored in one memory cell. An SLC memory block includes a plurality of pages implemented by memory cells, each storing one bit of data. An SLC memory block can have higher data I / O operation performance and higher endurance than an MLC memory block. An MLC memory block includes a plurality of pages implemented by memory cells, each storing multiple bits of data (e.g., two or more bits of data). An MLC memory block can have greater storage capacity for the same space compared to an SLC memory block. From a storage capacity perspective, an MLC memory block can be highly integrated.

[0105] In an embodiment, the memory device 150 can be implemented with MLC memory blocks such as double-level cell (DLC) memory blocks, triple-level cell (TLC) memory blocks, quad-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block can include a plurality of pages implemented by memory cells, each capable of storing 2 bits of data. A TLC memory block can include a plurality of pages implemented by memory cells, each capable of storing 3 bits of data. A QLC memory block can include a plurality of pages implemented by memory cells, each capable of storing 4 bits of data. In another embodiment, the memory device 150 can be implemented with blocks including a plurality of pages implemented by memory cells, each capable of storing five or more bits of data.

[0106] According to an embodiment, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block that stores one bit of data in one memory cell. A data input / output speed of a multi-level cell (MLC) memory block can be slower than a data input / output speed of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, a margin for a read or program operation can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform a data input / output operation at a higher speed. Accordingly, because a buffer can require a high data input / output speed to improve performance of the memory system 110, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data.

[0107] Further, according to an embodiment, the controller 130 can program data in the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Generally, a non-volatile memory cell does not support data rewriting. However, the controller 130 can use a feature of the MLC capable of storing multi-bit data to program 1-bit data in the MLC multiple times. For the MLC rewriting operation, when 1-bit data is programmed in the MLC, the controller 130 can store the number of programming times as separate operation information. According to an embodiment, an operation for equalizing threshold voltages of the MLC can be performed before another 1-bit data is programmed in the same MLC in which another bit data is respectively stored.

[0108] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as a flash memory (e.g., a NAND flash memory, a NOR flash memory, etc.). In another embodiment, the memory device 150 can be implemented by at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0109] Figure 3 A semiconductor device chip according to another embodiment of the disclosure is illustrated.

[0110] Referring to Figure 3 The semiconductor device chip 200 can include a pin or a pad through which a power supply voltage VCC is input, a power supply circuit 210 configured to generate an internal power supply voltage VCCI based on an external power supply voltage VCCE transmitted through the pin or the pad, and a component 220 driven by the internal power supply voltage VCCI. Herein, the external power supply voltage VCCE is a power supply voltage input from an external device through the pin or the pad, and the internal power supply voltage VCCI is applied to the component 220. The external power supply voltage VCCE and the internal power supply voltage VCCI are electrically coupled to each other, and a power supply circuit or any element (e.g., a conversion or switching element) can be generally arranged between the external power supply voltage VCCE and the internal power supply voltage VCCI.

[0111] According to an embodiment, Figure 3 The component 220 illustrated can include Figure 2 The memory blocks 152, 154, 156 and the power supply circuit 170 described in the above. An electrical load of the component 220 can vary based on operations performed through the memory blocks 152, 154, 156 and the power supply circuit 170. According to another embodiment, the component 220 can include Figure 2 At least some modules or circuits in the controller 130 illustrated.

[0112] According to an embodiment, the power supply circuit 210 can include a voltage regulator 212 and a voltage sensor 214. The voltage regulator 212 can be used to provide a stable power supply to an electronic device such as the memory system 110. Generally, the voltage regulator 212 can be classified into a linear regulator and a switching regulator. An example of the switching regulator can be a DC-DC converter. While the DC-DC converter can have a high conversion efficiency, the output voltage of the DC-DC converter can contain a lot of noise compared to the output voltage of the linear regulator. An example of the linear regulator can be a low dropout (LDO) regulator. The LDO regulator can have a low conversion efficiency. However, the LDO regulator can have a fast response speed. In addition, the output voltage of the LDO regulator can include a smaller amount of noise compared to the output voltage of the DC-DC converter. Generally, the LDO regulator can be suitable for a device sensitive to noise or a device requiring a high performance drive. For example, the LDO regulator, which can compensate for the disadvantage of the DC-DC converter, can be suitable for the memory system 110 operating at a high speed. The voltage regulator 212 can output an internal power supply voltage VCCI based on an external power supply voltage VCCE.

[0113] The voltage sensor 214 can detect a change or drop in the internal power supply voltage VCCI. As shown in FIG. 2A, the internal power supply voltage VCCI can fluctuate (e.g., a voltage drop phenomenon occurs) at different locations and regions in the semiconductor device chip 200 due to the operations of the components 220. For example, as the chip size increases, the length of the power supply rail and the resistance of the power supply line can increase. When a large amount of current is simultaneously consumed due to the operations of the components 220, a drop in the internal power supply voltage VCCI can occur. Because the voltage drop of the power supply line directly affects the processing speed of the transistor gate, the performance of the semiconductor device such as the memory system 110 or the memory device 150 can be degraded. Figure 1

[0114] When the voltage sensor 214 directly senses the level of the internal power supply voltage VCCI to detect a drop in the internal power supply voltage VCCI, the electrical load or burden of providing the internal power supply voltage VCCI can increase. When the voltage sensor 214 can increase the electrical load, the drop in the internal power supply voltage VCCI can be degraded (e.g., greater or for a longer time). The degraded drop in the internal power supply voltage VCCI can adversely affect the performance of the semiconductor device. Accordingly, the voltage sensor 214 according to an embodiment can detect a drop in the internal power supply voltage VCCI based on a sensed power supply voltage VCCE_S that fluctuates in response to a drop in the internal power supply voltage VCCI to output a detection result, which will be described below.

[0115] Figure 4 ​A voltage sensor according to an embodiment of the disclosure is illustrated.

[0116] Referring to Figure 4 The voltage sensor 214 can include a voltage detector 242 and a voltage comparator 244. The voltage sensor 214 is coupled to an external power voltage VCCE and an internal power voltage VCCI. The voltage sensor 214 can output a detection result SENSE_OUT related to a drop in the internal power voltage VCCI. The voltage detector 242 and the voltage comparator 244 can be controlled by a sensing signal SENSING_X.

[0117] Referring to Figure 4 The power voltage VCC can be supplied to the semiconductor device chip 200 through a plurality of pins or pads. According to an embodiment, the voltage sensor 214 can include a plurality of voltage detectors 242 each coupled to the internal power voltage VCCI and an external power voltage VCCE corresponding to the power voltage VCC supplied through the plurality of pins or pads. According to one embodiment, although the voltage sensor 214 includes a plurality of voltage detectors 242, a single comparator 244 can be included in the voltage sensor 214.

[0118] The sensing signal SENSING_X can control the voltage detector 242 and the voltage comparator 244. When a different sensing signal SENSING_X is input to one of the plurality of voltage detectors 242 and is activated, the corresponding sensing signal SENSING_X can be input to the comparator 244. When the voltage detector 242 and the voltage comparator 244 operate in response to the sensing signal SENSING_X, a region or a location can be identified based on the sensing signal SENSING_X input to one of the voltage detectors 242 corresponding to each of the plurality of pins or pads of the semiconductor device chip 200 to which the power voltage VCC is applied. Accordingly, a change in the internal power voltage VCCI supplied at a specific region or location corresponding to the sensing signal SENSING_X can be selectively detected.

[0119] The voltage detector 242 is coupled to the external supply voltage VCC and the internal supply voltage VCCI. However, the voltage detector 242 can cause a change in the sensed supply voltage VCCE_S in response to a change in the internal supply voltage VCCI. The voltage detector 242 can output the sensed supply voltage VCCE_S that is changed from the external supply voltage VCCE according to the change in the internal supply voltage VCCI to the voltage comparator 244. If the voltage detector 242 detects a drop in the internal supply voltage VCCI and outputs the internal supply voltage VCCI to the comparator 244 to compare the internal supply voltage VCCI with a reference voltage, an electrical load using the internal supply voltage VCCI can be increased. The increased electrical load can adversely affect the change in the internal supply voltage VCCI. Accordingly, the voltage detector 242 can include an element for maintaining a preset voltage difference between the internal supply voltage VCCI and the external supply voltage VCCE. For example, when a difference between the internal supply voltage VCCI and the external supply voltage VCCE is greater than a preset value, the element included in the voltage detector 242 can cause a change in the sensed supply voltage VCCE_S. When the difference between the internal supply voltage VCCI and the external supply voltage VCCE is less than the preset value, the element can maintain a constant level of the sensed supply voltage VCCE_S without fluctuation. Through these operations, the voltage detector 242 can output the sensed supply voltage VCCE_S that is changeable according to the change in the internal supply voltage VCCI to the voltage comparator 244.

[0120] To not increase an electrical load with respect to the internal supply voltage VCCI, the voltage comparator 244 can identify a change in the internal supply voltage VCCI based on the external supply voltage VCCE and the sensed supply voltage VCCE_S. The voltage sensor 214 does not directly detect or sense a level of the internal supply voltage VCCI. That is, the voltage sensor 214 can check a change in the sensed supply voltage VCCE_S to detect or identify a change or drop in the internal supply voltage VCCI. For example, the voltage comparator 244 is coupled to the sensed supply voltage VCCE_S whose level can be changed according to the change in the internal supply voltage VCCI, and to the external supply voltage VCCE input via a plurality of pins or pads to generate a reference voltage. The voltage comparator 244 can generate the reference voltage from the external supply voltage VCCE input via the plurality of pins or pads, and compare the reference voltage with the sensed supply voltage VCCE_S that is changed according to the change in the internal supply voltage VCCI. The voltage comparator 244 can output a detection result SENSE_OUT to show whether the internal supply voltage VCCI becomes lower than a preset reference voltage due to the change or drop in the internal supply voltage VCCI.

[0121] Figure 5A power supply circuit according to an embodiment of the disclosure is exemplified. Specifically, Figure 5 A semiconductor device chip 200 is described including a power supply circuit 210 and components 220. Figure 3 The power supply circuit 210 and the components 220 in the semiconductor device chip 200 are shown.

[0122] Referring to Figure 5 An internal power supply voltage VCCI output from a voltage regulator 212 included in the power supply circuit 210 can be provided to the components 220. The components 220 can include a plurality of circuits or a plurality of modules for performing a specific function or operation.

[0123] The power supply voltage VCC can be provided to the semiconductor device chip 200 through six pins or pads. In response to the six pins or pads, the voltage sensor 214 in the power supply circuit 210 can include six voltage sensing components 242#0 to 242#5 and a single voltage comparator 244. For example, the six voltage sensing components 242#0 to 242#5 can be disposed in a peripheral region of the semiconductor device chip 200, such as two regions 242#A, 242#B. According to one embodiment, each of the six voltage sensing components 242#0 to 242#5 can be arranged adjacent to each of the six pins or pads on the semiconductor device chip 200.

[0124] The first voltage sensing component 242#0 can include a diode 264 having an anode coupled to the external power supply voltage VCCE and a cathode coupled to the internal power supply voltage VCCI. When a difference between the external power supply voltage VCCE and the internal power supply voltage VCCI is equal to or greater than a threshold voltage, the diode 264 is turned on so that a level of the internal power supply voltage VCCI can be increased based on the external power supply voltage VCCE. When the difference between the external power supply voltage VCCE and the internal power supply voltage VCCI is less than the threshold voltage, the diode 264 is turned off so that the external power supply voltage VCCE and the internal power supply voltage VCCI can be electrically cut off. According to one embodiment, the diode 264 can be replaced with a diode-connected NMOS or PMOS transistor that combines a gate and a drain together. Through the diode 264, the first voltage sensing component 242#0 can generate a reference voltage VREF1 based on the external power supply voltage VCCE. Figure 4 A sensed power supply voltage VCCE_S is described.

[0125] An anode of the diode 264 is connected to the sensing node SN, and an external supply voltage VCCE can be pre-charged to the sensing node SN. To pre-charge the external supply voltage VCCE to the sensing node SN, the first voltage sensing component 242#0 can include a pre-charge switch for selectively providing the external supply voltage VCCE transmitted through a pin or a pad to the sensing node SN, and a capacitor 262 for maintaining a level of the external supply voltage VCCE delivered to the sensing node SN. Herein, the pre-charge switch can be controlled by a pre-charge signal PRECH. When the pre-charge signal PRECH is activated, the pre-charge switch is turned on and the external supply voltage VCCE transmitted through the pin or the pad can be provided to the sensing node SN.

[0126] The first voltage sensing component 242#0 can include a sensing switch that delivers the external supply voltage VCCE pre-charged in the sensing node SN to the comparator 244 in response to a first sensing signal SENSING_0. The sensing switch turned on by the first sensing signal SENSING_0 can deliver the external supply voltage VCCE maintained at the sensing node SN to the comparator 244. When a level of the internal supply voltage VCCI is lowered (i.e., dropped) such that a difference between the external supply voltage VCCE and the internal supply voltage VCCI is greater than a threshold voltage, the external supply voltage VCCE maintained at the sensing node SN fluctuates. In response to the first sensing signal SENSING_0, the sensing switch can deliver the fluctuated external supply voltage (e.g., the sensing supply voltage VCCE_S shown in FIG. 2) to the voltage comparator 244. When the internal supply voltage VCCI is not dropped, the external supply voltage VCCE pre-charged and maintained at the sensing node SN can not change, such that the maintained external supply voltage can be delivered to the voltage comparator 244 through the sensing switch. Figure 4

[0127] The power supply circuit 210 can include six voltage sensing components 242#0 to 242#5, and a plurality of sensing signals SENSING_0 to SENSING_5 can be input to each of the six voltage sensing components 242#0 to 242#5, respectively. The six voltage sensing components 242#0 to 242#5 and the comparator 244 can be coupled through a global sensing node SN_Global. One of the six voltage sensing components 242#0 to 242#5 can deliver the external supply voltage VCCE to the comparator 244, and the comparator 244 can receive a reference voltage and the delivered external supply voltage VCCE, compare the reference voltage with the delivered external supply voltage VCCE to output a detection result SENSE_OUT as a comparison result.

[0128] ​The voltage comparator 244 can include a comparator 286 that compares the reference voltage REF and the external supply voltage VCCE transmitted from one of the six voltage sensing components 242#0 to 242#5. The comparator 286 can output a detection result SENSE_OUT. When the external supply voltage VCCE is not transmitted from the six voltage sensing components 242#0 to 242#5, a global sensing node SN_Global connected to the comparator 286 is pre-charged in response to a global pre-charge signal PRECH_G. The voltage comparator 244 can generate a plurality of voltage levels through a resistor group 282 including a plurality of resistors connected in series, based on the external supply voltage VCCE transmitted through a pin or a pad. Further, the voltage comparator 244 can include a multiplexer 284 that selects one voltage level among the plurality of voltage levels generated by the resistor group 282 and outputs the selected voltage level as the reference voltage REF. A selection signal R_SEL for selecting one voltage level among the plurality of voltage levels can be input to the multiplexer 284 <w>.

[0129] The comparator 286 can be controlled by a sensing driving signal SEN D. The driving signal SEN is generated by a logic circuit 290 for performing an OR operation on a plurality of sensing signals SENSING 0 to SENSING 5 corresponding to each of the six voltage sensing components 242#0 to 242#5, respectively. Further, the comparator 244 can include a delay unit 288 that delays the driving signal SEN by a preset time to generate the sensing driving signal SEN D. According to an embodiment, the delay time of the delay unit 288 is determined based on a distance between the six voltage sensing components 242#0 to 242#5 and the comparator 244 provided on the semiconductor device chip 200. The delay time can also be determined based on a time taken to transfer the external power supply voltage VCCE from the six voltage sensing components 242#0 to 242#5. Through the logic circuit 290 and the delay unit 288 in the comparator 244, the sensing driving signal SEN D for controlling the operating margin of the comparator 286 can be generated using the plurality of sensing signals SENSING 0 to SENSING 5 corresponding to each of the six voltage sensing components 242#0 to 242#5.

[0130] The power supply circuit 210 according to an embodiment of the disclosure can utilize the external power supply voltage VCCE that changes in response to a drop in the internal power supply voltage VCCI and control the operating margin of the six voltage sensing components 242#0 to 242#5 and the comparator 244, so that the electrical load or burden that occurs in the operation of outputting the detection result SENSE OUT can be reduced.

[0131] Figure 6 The operation of the power supply circuit shown in FIG. 2A is illustrated according to an embodiment of the disclosure. Specifically, Figure 5 The operation of the power supply circuit shown in FIG. 2A is illustrated according to an embodiment of the disclosure. Specifically, Figure 6 The operation performed by the voltage sensor 214 included in the power supply circuit 210 is described.

[0132] Referring to Figure 6 The precharge signal PRECH can be activated before the components 220 in the semiconductor device chip 200 perform their operations corresponding to an external command or a preset task, etc. When the precharge signal PRECH is activated, the external power supply voltage VCCE can be precharged at the sensing nodes SN in the six voltage sensing components 242#0 to 242#5. When the components 220 in the semiconductor device chip 200 perform operations in response to an external command or a preset task, the global precharge signal PRECH G can be activated to precharge the global sensing node SN Global coupled to the comparator 286 with the external power supply voltage VCCE.

[0133] When components 220 in the semiconductor device chip 200 perform operations or preset tasks in response to external commands, an electrical load occurs. When the electrical load is excessively increased, the internal power supply voltage VCCI drops or fluctuates. For example, in Figure 6 the level of the external power supply voltage VCCE precharged at the sensing nodes SN_0, SN_1 in the first and second sensing components 242#0, 242#1 changes (or drops) due to an increase in the electrical load during a specific operation.

[0134] First, when the first sensing signal SENSING_0 input to the first sensing component 242#0 is activated, the second sensing signal SENSING_1 input to the second sensing component 242#1 can remain in an inactive state. Also, when the first sensing signal SENSING_0 is activated, the global precharge signal PRECH_G is deactivated.

[0135] Referring to Figure 5 , in response to the activation of the first sensing signal SENSING_0, the level of the external power supply voltage VCCE at the sensing node SN_0 of the first sensing component 242#0 changes in response to the drop in the internal power supply voltage VCCI, so that the potential of the global sensing node SN_Global can be lowered.

[0136] In addition, in response to the activation of the first sensing signal SENSING_0, the drive signal SEN can be activated by the logic circuit 290 in the comparator 244. The drive signal SEN is passed through the delay unit 288, so that the sensing drive signal SEN_D is activated.

[0137] The comparator 244 sequentially activates the selection signals R_SEL<0:3> and inputs the activated selection signals R_SEL<0:3> to the comparator 286. The comparator 286 can sequentially compare the reference voltages REF having different levels with the changed potential at the global sensing node SN_Global (e.g., the sensing power supply voltage VCCE_S shown in Figure 4 , and output a detection result SENSE_OUT. Thus, the comparator 244 can output how much the level or potential of the global sensing node SN_Global has changed or dropped.

[0138] For example, referring to Figure 6 , it can be determined that the external power supply voltage VCCE at the sensing node SN_0 in the first sensing component 242#0, which changes in response to the drop in the internal power supply voltage VCCI (e.g., the sensing power supply voltage VCCE_S shown in Figure 4 The level of the sensed supply voltage VCCE_S) is less than two of the four different level reference voltages REF and greater than the other two of the four different levels. The activation period (or pulse width) of the detection result SENSE_OUT can be varied according to the external supply voltage VCCE (e.g., Figure 4 The sensed supply voltage VCCE_S) is varied according to the result of the comparison with the reference voltage REF having four different levels.

[0139] On the other hand, after detecting the change in the level of the external supply voltage VCCE at the sensing node SN_0 in the first sensing component 242#0, the first sensing signal SENSING_0 is deactivated. Then, the second sensing signal SENSING_1 can be activated. When the second sensing signal SENSING_1 is activated, the level of the external supply voltage VCCE at the sensing node SN_1 in the second sensing component 242#1 can be changed in response to the drop of the internal supply voltage VCCI, such that the potential of the global sensing node SN_Global can be lowered.

[0140] In response to the activation of the second sensing signal SENSING_1, the voltage comparator 244 can re-perform the operation performed according to the activation of the first sensing signal SENSING_0. Referring to Figure 6 It can be determined that the level of the external supply voltage VCCE at the sensing node SN_1 in the second sensing component 242#1, which is changed in response to the drop of the internal supply voltage VCCI, is less than one of the reference voltages REF having four different levels and greater than the other three reference voltages REF.

[0141] As described above, when the components 220 in the semiconductor device chip 200 perform operations capable of performing operations or preset tasks based on external commands, the amount of the electrical load can vary according to the region or location of the semiconductor device chip 200. In addition, according to the amount of the electrical load based on the region or location, the degree of the drop or change in the level of the internal supply voltage VCCI is different. Referring to Figure 6 It can be determined whether the internal supply voltage VCCI has dropped or changed in the corresponding region or location for the first and second sensing components 242#0 and 242#1 arranged at different locations. In addition, it can be determined how much the level of the internal supply voltage VCCI has dropped or changed based on the plurality of reference voltages REF having different levels generated by the voltage comparator 244. The power supply circuit 210 can determine at which location or region the internal supply voltage VCCI changes or drops and how much the level of the internal supply voltage VCCI changes or drops due to the electrical load occurring when the components 220 in the semiconductor device chip 200 operate. In addition, the power supply circuit 210 can detect what type of operation performed by the components 220 in the semiconductor device chip 200 causes the drop or change in the internal supply voltage VCCI. The power supply circuit 210 can identify or estimate at which location or region the level of the internal supply voltage VCCI changes or drops and how much the level of the internal supply voltage VCCI changes or drops based on the operation performed by the components 220.

[0142] Figure 7 A power supply circuit according to another embodiment of the present disclosure is exemplified. Herein, the description can focus on the differences between the power supply circuits described with reference to Figure 5 and Figure 7 described above.

[0143] With reference to Figure 7 A plurality of switches can be added to the global sensing node SN_Global. With reference to Figure 5 and Figure 7 When the six sensing components 242#0 to 242#5 are arranged at different positions of the semiconductor device chip 200, the global sensing node SN_Global can be a very long line (e.g., a wire). In this case, as the length of the line increases, a resistance, a capacitance, or an electrical load generated in the global sensing node SN_Global can be greater. The resistance, the capacitance, or the electrical load generated in the global sensing node SN_Global can degrade the performance of the voltage sensor 214. When one of the six sensing components 242#0 to 242#5 outputs the sensed supply voltage VCCE_S to the voltage comparator 244, the other sensing components do not output the sensed supply voltage VCCE_S to the voltage comparator 244. When one of the six sensing components 242#0 to 242#5 outputs the sensed supply voltage VCCE_S, the lines (wires) connected to the other sensing components can be blocked or cut off by a plurality of switches. Although the plurality of switches can couple only one of the six sensing components 242#0 to 242#5 to the voltage comparator 244, the length of the line or the wire corresponding to the global sensing node SN_Global can be reduced or shortened. For example, when a first sensing component 242#0 among the six sensing components 242#0 to 242#5 outputs a level of the sensed supply voltage VCCE_S to the voltage comparator 244, the power supply circuit 210 can control a first switch control signal SW_FOR_SEN0. The global sensing node SN_Global connected to a second sensing component 242#1 to a sixth sensing component 242#5 can be electrically cut off.

[0144] In Figure 7 , two switches controlled by the first switch control signal SW_FOR_SEN0 for the first sensing component 242#0 are illustrated, but a plurality of switches can also be included based on the arrangement of the power supply circuit 210 in the semiconductor device chip 200. The plurality of switches can be selectively turned on or off by a plurality of switch control signals corresponding to the sensing components among the six sensing components 242#0 to 242#5 that output a level of the sensed supply voltage VCCE_S to the voltage comparator 244.

[0145] The resistor group 282 and the multiplexer 284 included in the voltage comparator 244 can be designed in various ways. Although Figure 5 and Figure 7 The plurality of resistors in the resistor group 282 shown are connected in series, but various reference voltage levels can be obtained by connecting MOS transistors with the same or different threshold voltages in series or in parallel. In addition, even if the multiplexer 284 does not select one of the plurality of reference voltage levels, the power supply circuit 210 changes or controls the body bias of the MOS transistors included in the resistor group 282 to change the threshold voltage of the MOS transistors, so that the voltage level output at the same location can be adjusted or changed. Furthermore, according to another embodiment, the resistor group 282 and the comparator 286 can be implemented in a circuit or logic including an analog-to-digital converter (ADC).

[0146] In response to the plurality of sensing signals SENSING_0 to SENSING_5 in the voltage sensor 214, the sensing power voltage VCCE_S is transferred from the sensing nodes SN of the six sensing components 242#0 to 242#5 to the global sensing node SN_Global. The sensing nodes SN and the global sensing node SN_Global have been precharged with the external power voltage VCCE. Then, the sensing power voltage VCCE_S at the sensing nodes SN can be lowered or changed in response to a drop in the internal power voltage VCCI, and the plurality of sensing signals SENSING_0 to SENSING_5 can allow the sensing power voltage VCCE_S at the sensing nodes SN with the changed level to be transferred to the global sensing node SN_Global that is precharged with the external power voltage VCCE. This transmission of the changed external power voltage can occur through charge sharing, so that subtle or slight changes can be difficult to transfer from the sensing nodes SN to the global sensing node SN_Global. According to one embodiment, in order to more easily transfer the subtle or slight changes between the sensing nodes SN and the global sensing node SN_Global, the capacitance of the sensing nodes SN is designed to be greater than the capacitance of the global sensing node SN_Global. For example, if the capacitance of the sensing nodes SN is designed to be about 100 times greater than the capacitance of the global sensing node SN_Global, the subtle or slight changes can be easily transferred from the sensing nodes SN to the global sensing node SN_Global. When the capacitance of the sensing nodes SN is too large, a level change in the sensing power voltage VCCE_S at the sensing nodes SN can not occur in response to a drop in the internal power voltage VCCI. In this case, in order to sufficiently cause a level change in the sensing power voltage VCCE_S at the sensing nodes SN in response to a drop in the internal power voltage VCCI, the operation of each voltage detector (or each sensing component) 242 can be repeatedly performed several to several tens of times.

[0147] As described above, in the power supply circuit 210 according to one embodiment of the disclosure, a plurality of sensing components can be provided on the semiconductor device chip 200 so that the power supply circuit 210 can identify or determine at which position in the semiconductor device chip 200 the level of the internal power supply voltage VCCI changes or drops or how much it changes or drops.

[0148] The semiconductor device according to one embodiment of the disclosure can efficiently identify a position where a power supply voltage drops in a chip of the semiconductor device. When a drop in the power supply voltage occurs at a specific position, a power supply voltage provided to other regions can be used to compensate for the drop in the power supply voltage at the specific position.

[0149] In addition, because the semiconductor device according to the embodiment of the disclosure can designate a time point and a position for monitoring or compensating for a drop in the power supply voltage, unnecessary overhead of a process for detecting a drop in the power supply voltage inside the semiconductor device can be reduced.

[0150] While the present teachings have been illustrated and described with respect to particular embodiments, it is clear that there can be various changes and modifications made thereto without departing from the spirit and scope of the present disclosure as defined in the appended claims. In addition, the embodiments can be combined to form additional embodiments.

[0151] CROSS-REFERENCE TO RELATED APPLICATIONS

[0152] This patent application claims the benefit of Korean Patent Application No. 10-2021-0041877, filed March 31, 2021, the entire disclosure of which is incorporated herein by reference.< / w>

Claims

1. A power supply circuit, the power supply circuit comprising: at least one power detector coupled to a first power voltage input via a pin or a pad and a second power voltage supplied to a component, and outputting a sensed power voltage changed from the first power voltage in response to a drop of the second power voltage; and a comparator comparing the sensed power voltage with a reference voltage to output a power sense result, wherein the at least one power detector includes a first element receiving the first power voltage, outputting the second power voltage, and maintaining a difference between the first power voltage and the second power voltage below a preset value, and wherein the first element includes a diode including an anode coupled to the sensed power voltage and a cathode coupled to the second power voltage. The first element is turned on when a difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and is turned off when the difference is less than the preset value.

2. The power supply circuit of claim 1, wherein, The at least one power detector includes:

3. The power supply circuit of claim 1, wherein, a second element selectively transferring the first power voltage; a third element maintaining a level of the first power voltage transferred by the second element; and a fourth element transferring the sensed power voltage maintained or changed by the first element and the third element to the comparator in response to a sense signal.

4. The power supply circuit of claim 3, the sense signal is input to the at least one power detector and the comparator, and wherein wherein the comparator outputs the power sense result when the sense signal is activated. The at least one power detector includes N power detectors, the sense signal includes a plurality of sense signals, the plurality of sense signals are respectively input to the N power detectors, and the comparator outputs the power sense result when one of the plurality of sense signals is activated.

5. The power supply circuit of claim 4, wherein, 6. The power supply circuit of claim 5, further comprising at least one switch coupling each of the N power detectors to the comparator. 7.A semiconductor device, the semiconductor device comprising: a plurality of pins or pads coupled to a first power voltage input from an external device; a power supply circuit coupled to the plurality of pins or pads and outputting a second power voltage; and a plurality of internal circuits coupled to the power supply circuit and using the second power voltage to store or process data items, wherein the power supply circuit includes: a plurality of power detectors respectively coupled to one of the plurality of pins or pads and outputting a sensed power voltage changed from the first power voltage in response to a drop of the second power voltage; and a comparator comparing the sensed power voltage output from one of the plurality of power detectors with a reference voltage to output a power sense result, ​ wherein each of the plurality of power detectors includes a first element that receives the first power voltage, outputs the second power voltage, and maintains a difference between the first power voltage and the second power voltage below a preset value, and wherein the first element includes a diode including an anode coupled to the sensed power voltage and a cathode coupled to the second power voltage.

8. The semiconductor device according to claim 7, wherein The power supply circuit further includes a low dropout (LDO) regulator that receives the first power voltage and outputs the second power voltage having a minimum input / output voltage difference capable of stabilizing operations performed by the plurality of internal circuits.

9. The semiconductor device according to claim 7, wherein The power supply circuit further includes a plurality of switches that couple each of the plurality of power detectors to the comparator.

10. The semiconductor device according to claim 7, wherein The first element is turned on when a difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and is turned off when the difference is less than the preset value.

11. The semiconductor device according to claim 7, wherein Each of the plurality of power detectors includes: a second element that selectively transfers the first power voltage; a third element that maintains a level of the first power voltage transferred by the second element; and a fourth element that transfers the sensed power voltage maintained or changed by the first element and the third element to the comparator in response to a sensing signal.

12. The semiconductor device of claim 7, wherein each of a plurality of sensing signals is input to each of the plurality of power detectors and the comparator, and wherein, when one of the plurality of sensing signals is activated, the comparator outputs the power sensing result corresponding to the activated sensing signal.

13. The semiconductor device according to claim 12, wherein When one of the plurality of sensing signals is activated, the comparator compares the sensed power voltage output from one of the plurality of power detectors in response to the activated sensing signal with the reference voltage to output the power sensing result.

14. A power sensing circuit coupled to a first power voltage input from an external device via a plurality of pins or pads and to a second power voltage supplied to an internal circuit, and when the second power voltage is changed, comparing the first power voltage which is changed based on the change of the second power voltage with a reference voltage to output a power sensing result, wherein, The power supply sensing circuit detects a change in the second power voltage without affecting a level of the second power voltage, wherein the power supply sensing circuit includes a diode including an anode coupled to the first power voltage and a cathode coupled to the second power voltage, and maintains a difference between the first power voltage and the second power voltage below a preset value.

15. The power sensing circuit of claim 14, wherein, The diode is turned on when the difference between the first power voltage and the second power voltage is equal to or greater than the preset value, and is turned off when the difference is less than the preset value.

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