memory

Abstract

A memory is provided. A programmable memory array includes a plurality of memory cells coupled to a program bond pad and a power bond pad. When a first voltage of the program bond pad is greater than a second voltage of the power bond pad, the plurality of memory cells is operated in a program mode. When the first voltage of the program bond pad is less than the second voltage of the power bond pad, the plurality of memory cells is operated in a normal mode. An electrostatic discharge protection circuit is used to conduct an electrostatic discharge current from the power bond pad to the program bond pad when an electrostatic discharge event occurs. A first path of the power bond pad to the electrostatic discharge protection circuit is less than a second path of the power bond pad to the programmable memory array. The present invention can achieve avoiding damage from electrostatic discharge stress.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit for a programmable memory. BACKGROUND

[0002] An electrostatic discharge occurs when an excess charge stored in an electronic insulator finds a path to an object of different potential, such as a ground. The sudden and instantaneous flow of current is an electrostatic discharge. When an electrostatic charge moves to an integrated circuit (IC), it can be a damaging or destructive current to the gate oxide, metal, and junctions. Electrostatic discharges usually occur when a charged body contacts an integrated circuit, a charged integrated circuit contacts a grounded surface, or a charged machine contacts an integrated circuit.

[0003] Electrostatic discharges are a common occurrence during the handling of integrated circuits. Electrostatic charges can accumulate in the semiconductor devices of an integrated circuit and can cause destructive effects. Electrostatic discharge events (or stresses) can occur during the testing phase of integrated circuit manufacturing, when the device of an integrated circuit is placed on a circuit board, and during the use of the equipment in which the integrated circuit is installed. Damage to an integrated circuit from an electrostatic discharge can partially or sometimes completely stop the operation of the integrated circuit. SUMMARY

[0004] A memory is provided. The memory includes a power bond pad, a program bond pad, a programmable memory array, and an electrostatic discharge protection circuit. The programmable memory array includes a plurality of memory cells coupled to the program bond pad and the power bond pad. The plurality of memory cells operate in a program mode when a first voltage of the program bond pad is greater than a second voltage of the power bond pad. The plurality of memory cells operate in a normal mode when the first voltage of the program bond pad is less than the second voltage of the power bond pad. The electrostatic discharge protection circuit is coupled between the power bond pad and the program bond pad. The electrostatic discharge protection circuit is to conduct an electrostatic discharge current from the power bond pad to the program bond pad when an electrostatic discharge event occurs. A first path of the power bond pad to the electrostatic discharge protection circuit is less than a second path of the power bond pad to the programmable memory array.

[0005] Furthermore, the present application provides a memory. The memory includes a power bonding pad, a programming bonding pad, a first electrostatic discharge protection circuit, and a programmable memory array. The first electrostatic discharge protection circuit is coupled between the power bonding pad and the programming bonding pad. The programmable memory array includes a plurality of memory cells. Each of the memory cells includes a P-type transistor having a gate coupled to the power bonding pad and the first electrostatic discharge protection circuit and a source coupled to the programming bonding pad. The plurality of memory cells is operated in a programming mode when a first voltage of the programming bonding pad is greater than a second voltage of the power bonding pad, and the plurality of memory cells is operated in a normal mode when the first voltage of the programming bonding pad is less than the second voltage of the power bonding pad. A first path of the power bonding pad to the first electrostatic discharge protection circuit is less than a second path of the power bonding pad to the programmable memory array, and the first path is partially overlapped with the second path. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a diagram showing an integrated circuit according to some embodiments of the present application;

[0007] Figure 2A is a diagram showing an electrostatic discharge protection circuit implemented using a diode according to some embodiments of the present application;

[0008] Figure 2B is a diagram showing an electrostatic discharge protection circuit implemented using a diode according to some embodiments of the present application;

[0009] Figure 2C is a diagram showing an electrostatic discharge protection circuit implemented using a bipolar transistor according to some embodiments of the present application;

[0010] Figure 2D is a diagram showing an electrostatic discharge protection circuit implemented using a bipolar transistor according to some embodiments of the present application;

[0011] Figure 2E is a diagram showing an electrostatic discharge protection circuit implemented using a MOS transistor according to some embodiments of the present application;

[0012] Figure 2F is a diagram showing an electrostatic discharge protection circuit implemented using a MOS transistor according to some embodiments of the present application;

[0013] Figure 2G is a diagram showing an electrostatic discharge protection circuit implemented using a MOS transistor according to some embodiments of the present application;

[0014] Figure 3 is a diagram showing a memory according to some embodiments of the present application;

[0015] Figure 4 is a memory device according to some embodiments of the present application.

[0016] Reference Signs:

[0017] 10A, 10B, 10C: memory device;

[0018] 15: memory cell;

[0019] 30: power bonding pad;

[0020] 40: program bonding pad;

[0021] 50: ground bonding pad;

[0022] 70, 70a, 70b, 70c, 70d, 70e, 70f, 70g, 80a, 80b, 80c, 80d, 80e, 80f, 80b: electrostatic discharge protection circuit;

[0023] 72c, 72e: biasing unit;

[0024] 100: integrated circuit;

[0025] 110: substrate;

[0026] 120, 120a, 120b, 120c: pin;

[0027] 125a, 125b, 125c: metal line;

[0028] 130a, 130b: input / output area;

[0029] 140: control circuit;

[0030] 145: device area;

[0031] 150: programmable memory array;

[0032] BJT1, BJT2: bipolar transistor;

[0033] D1, D2, D3, D4: diode;

[0034] M1, M2, M3, M4: transistor;

[0035] MP1, MP2: P-type transistor;

[0036] Path1: first path;

[0037] Path2: second path;

[0038] VDD: power supply;

[0039] VPP: program signal;

[0040] VSS: ground signal or ground terminal. DETAILED DESCRIPTION

[0041] So that the foregoing and other objects, features, and advantages of the present application can be readily understood, a more particular description of the application follows, as illustrated in the accompanying drawings.

[0042] For integrated circuit fabrication, as technology advances, electrostatic discharge tolerance becomes more and more important. However, semiconductor devices produced by semiconductor process technology, which are scaled down and include shallow junction depths and thin gate oxide layers, have less tolerance to electrostatic discharge events. Therefore, input / output pads of integrated circuits must be provided with electrostatic discharge protection circuits to avoid damage from electrostatic discharge stress.

[0043] Generally, the damage of an electrostatic discharge event to a device is determined by the ability of the device to dissipate the discharge energy or to withstand the current level. This is referred to as the electrostatic discharge sensitivity or electrostatic discharge susceptibility of the device. There are three main modes of electrostatic discharge events, namely, the human body model (HBM), the machine model (MM), and the charged device model (CDM). In these modes of electrostatic discharge, electrostatic charges are transferred from a human body, a charged material, or an internal device of an integrated circuit to an electrostatic discharge susceptible device, causing damage to the internal devices of the integrated circuit.

[0044] Figure 1 is a diagram showing an integrated circuit 100 according to some embodiments of the present application. The integrated circuit 100 includes a substrate (or base plate) 110, a pin (or lead) 120, and a memory (or die) 10A disposed on the substrate 110. The memory 10A includes an input / output (I / O) region 130a, a control circuit 140, and a programmable memory array 150.

[0045] The input / output region 130a includes a power bond pad 30, a program bond pad 40, and a ground bond pad 50, and each bond pad is connected to the corresponding pin 120 via an individual metal line. For example, the power bond pad 30 is connected to the pin 120b via a metal line 125b for providing a power signal VDD to the control circuit 140 and the programmable memory array 150. Further, the ground bond pad 50 is connected to the pin 120c via a metal line 125c for providing a ground signal (or ground terminal) VSS to the control circuit 140 and the programmable memory array 150. In addition, the program bond pad 40 is connected to the pin 120a via a metal line 125a for providing a program signal VPP to the control circuit 140 and the programmable memory array 150. In Figure 1 In the top view of the memory 10A, the program bond pad 40 and the power bond pad 30 are disposed on top of the programmable memory array 150 and the control circuit 140, respectively, and the ground bond pad 50 is disposed on the left side of the control circuit 140. For simplicity of illustration, Figure 1 Only the electrostatic discharge protection mechanism related to the program signal VPP is described.

[0046] The programmable memory array 150 is formed of a plurality of memory cells 15. Each memory cell 15 is a programmable memory cell. In some embodiments, the memory cell 15 can be a flash memory. In some embodiments, the memory cell 15 can be a one-time program (OTP) memory cell. When the voltage level of the program signal VPP from the pin 120a is greater than the voltage level of the power VDD (i.e., VPP > VDD), the memory cell 15 operates in a program mode, and the programmable memory array 150 can be programmed by the control circuit 140. Conversely, when the voltage level of the program signal VPP (e.g., the pin 120a is floating) is less than the voltage level of the power VDD (i.e., VPP < VDD), the memory cell 15 operates in a normal mode, and the programmable memory array 150 can be read and / or written by the control circuit 140 according to various product applications.

[0047] Compared to conventional memory, the input / output region 130a of the memory 10A further includes an electrostatic discharge protection circuit 70 disposed between the power bond pad 30 and the program bond pad 40 to provide electrostatic discharge protection to the memory cell 15. For example, the memory cell 15 includes a P-type transistor MP1. The source and bulk of the P-type transistor MP1 are connected to the program bond pad 40, while the gate of the P-type transistor MP1 is connected to the power bond pad 30. Thus, when an electrostatic discharge event in the CDM mode occurs, the electrostatic current will flow from the inside of the device through the power bond pad 30 to the program bond pad 40 via the electrostatic discharge protection circuit 70, so that the electrostatic current will not flow to the memory cell 15 and break the gate of the P-type transistor MP1. It is noted that a first path Pathl from the power bond pad 30 to the electrostatic discharge protection circuit 70 is shorter than a second path Path2 from the power bond pad 30 to the memory cell 15 of the programmable memory array 150. Moreover, the first path Pathl does not overlap the second path Path2.

[0048] Figure 2A is a diagram showing an electrostatic discharge protection circuit 70a implemented using diodes as described in some embodiments of the present application. The electrostatic discharge protection circuit 70a includes diodes Dl and D2 to provide bidirectional electrostatic discharge protection in the CDM mode between the bond pads 30 and 40. The anode of the diode Dl is coupled to the power bond pad 30, while the cathode of the diode Dl is coupled to the cathode of the diode D2. Moreover, the anode of the diode D2 is coupled to the program bond pad 40. In some embodiments, the diode Dl is disposed proximate to the power bond pad 30, while the diode D2 is disposed proximate to the program bond pad 40.

[0049] Figure 2B is a diagram showing an electrostatic discharge protection circuit 70b implemented using diodes as described in some embodiments of the present application. The electrostatic discharge protection circuit 70b includes diodes D3 and D4. Compared to Figure 2A the diodes Dl and D2 of Figure 2B the diodes D3 and D4 are Zener diodes, which have a higher reverse breakdown voltage. Moreover, the diodes D3 and D4 can be disposed similarly to Figure 2A the diodes Dl and D2 of

[0050] Figure 2Cis a diagram showing an electrostatic discharge protection circuit 70c implemented using a bipolar transistor, as described in some embodiments of the present application. The electrostatic discharge protection circuit 70c includes a bipolar transistor BJTl and a bias unit 72c. The bipolar transistor BJTl is a PNP transistor. The emitter of the bipolar transistor BJTl is coupled to the power bond pad 30, and the base is coupled to the bias unit 72c. In addition, the collector of the bipolar transistor BJTl is coupled to the program bond pad 40. When an electrostatic discharge event occurs, the bias unit 72c controls the bipolar transistor BJTl to turn on, so that the electrostatic current flows from the power bond pad 30 to the program bond pad 40 via the electrostatic discharge protection circuit 70c.

[0051] Figure 2D is a diagram showing an electrostatic discharge protection circuit 70d implemented using a bipolar transistor, as described in some embodiments of the present application. The electrostatic discharge protection circuit 70d includes a bipolar transistor BJT2. The bipolar transistor BJT2 is an NPN transistor. The collector of the bipolar transistor BJT2 is coupled to the power bond pad 30, the base is coupled to the ground terminal VSS, and the emitter is coupled to the program bond pad 40. When an electrostatic discharge event occurs, the electrostatic current flows from the power bond pad 30 to the program bond pad 40 via the bipolar transistor BJT2.

[0052] Figure 2E is a diagram showing an electrostatic discharge protection circuit 70e implemented using a MOS transistor, as described in some embodiments of the present application. The electrostatic discharge protection circuit 70e includes a transistor Ml and a bias unit 72e. In this embodiment, the transistor Ml is a P-type transistor. The source of the transistor Ml is coupled to the power bond pad 30, the gate is coupled to the bias unit 72e, and the drain is coupled to the program bond pad 40. In addition, the base of the transistor Ml is coupled to the bias unit 72e. When an electrostatic discharge event occurs, the bias unit 72e controls the transistor Ml to turn on, so that the electrostatic current flows from the power bond pad 30 to the program bond pad 40 via the transistor Ml.

[0053] Figure 2F is a diagram showing an electrostatic discharge protection circuit 70f implemented using a MOS transistor, as described in some embodiments of the present application. The electrostatic discharge protection circuit 70f includes a transistor M2. In this embodiment, the transistor M2 is an N-type transistor. The drain of the transistor M2 is coupled to the power bond pad 30, and the source is coupled to the program bond pad 40. In addition, the base and the gate of the transistor M2 are both coupled to the ground terminal VSS. When an electrostatic discharge event occurs, the electrostatic current flows from the power bond pad 30 to the program bond pad 40 via the transistor M2.

[0054] Figure 2GShows an electrostatic discharge protection circuit 70g implemented using MOS transistors according to some embodiments of the present invention. The electrostatic discharge protection circuit 70g includes transistors M3 and M4. In this embodiment, transistors M3 and M4 are P-type transistors. The source, gate, and base of transistor M3 are coupled to the power supply bonding pad 30, and the drain is coupled to transistor M4. In addition, the drain, gate, and base of transistor M4 are coupled to the programming bonding pad 40, and the source is coupled to transistor M3. In this embodiment, the connection manner of transistors M3 and M4 can be used as a diode, as Figure 2A shown. In addition, the placement positions of transistors M3 and M4 can be similar to Figure 2A diodes D1 and D2.

[0055] Figure 3 Shows a memory 10B according to some embodiments of the present invention. The memory 10B includes an input / output region 130b, a control circuit 140, and a programmable memory array 150. The configuration of the memory 10B is similar to Figure 1 that of the memory 10A. Compared with Figure 1 the memory 10A, in the memory 10B, the device region 145 having the control circuit 140 and the programmable memory array 150 is surrounded by the input / output region 130b. In addition, the power supply bonding pad 30 is disposed on the left side of the control circuit 140, and the ground bonding pad 50 is disposed at the bottom of the control circuit 140 and the programmable memory array 150. In the embodiments of the present invention, the positions where the power supply bonding pad 30, the programming bonding pad 40, the ground bonding pad 50, the control circuit 140, and the programmable memory array 150 are disposed are only examples and are not intended to limit the present invention. The power supply bonding pad 30, the programming bonding pad 40, the ground bonding pad 50, the control circuit 140, and the programmable memory array 150 can be arranged at suitable positions according to actual applications.

[0056] As previously described, the programmable memory array 150 is formed by a plurality of memory cells 15. Each memory cell 15 is a programmable memory cell. In some embodiments, the memory cell 15 can be a flash memory or a one-time programmable memory cell. When the voltage level of the programming signal VPP from the programming bonding pad 40 is greater than the voltage level of the power supply VDD from the power supply bonding pad 30 (i.e., VPP > VDD), the memory cell 15 operates in the programming mode. On the other hand, when the voltage level of the programming signal VPP is less than the voltage level of the power supply VDD (i.e., VPP < VDD), the memory cell 15 operates in the normal mode.

[0057] In Figure 3In some embodiments, the ESD protection circuit 70 is disposed within the input / output region 130b and coupled between the power bond pad 30 and the program bond pad 40 to provide bidirectional ESD protection for the power bond pad 30 and the program bond pad 40. In some embodiments, the ESD protection circuit 70 can be implemented using diodes, bipolar transistors, and / or MOS transistors, as shown in FIG. 4. Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G In some embodiments, multiple ESD protection circuits 70 can be disposed between the power bond pad 30 and the program bond pad 40 in a parallel configuration. For example, the ESD protection circuit 70 of the first cell is disposed between the power bond pad 30 and the program bond pad 40 and closer to the power bond pad 30, i.e., the distance between the ESD protection circuit 70 of the first cell and the power bond pad 30 is less than the distance between the ESD protection circuit 70 of the first cell and the program bond pad 40. In addition, the ESD protection circuit 70 of the second cell is disposed between the power bond pad 30 and the program bond pad 40 and closer to the program bond pad 40, i.e., the distance between the ESD protection circuit 70 of the second cell and the program bond pad 40 is less than the distance between the ESD protection circuit 70 of the second cell and the power bond pad 30.

[0058] As previously described, the first path Pathl from the power bond pad 30 to the ESD protection circuit 70 is less than (shorter than) the second path Path2 from the power bond pad 30 to the memory cell 15. In addition, the first path Pathl does not overlap the second path Path2. When an ESD event in the CDM mode occurs, the ESD protection circuit 70 can prevent the ESD current from damaging the memory cell 15. Similar to the P-type transistor MP1 of the memory cell 15, some devices of the control circuit 140 are coupled to both the program bond pad 40 and the power bond pad 30, such as the P-type transistor MP2. Thus, the ESD protection circuit 70 can also prevent the ESD current from damaging the control circuit 140.

[0059] Within the input / output region 130b, an electrostatic discharge protection circuit 80a is coupled and disposed between the power bond pad 30 and the ground bond pad 50. An electrostatic discharge protection circuit 80b is coupled and disposed between the program bond pad 40 and the ground bond pad 50. When an electrostatic discharge event in the HBM mode occurs, the electrostatic discharge protection circuits 80a and 80b can protect the power bond pad 30, the program bond pad 40, and the ground bond pad 50 from the electrostatic current to damage the internal circuitry of the memory 10B. In some embodiments, the electrostatic discharge protection circuits 80a and 80b can include a clamp unit to protect the internal circuitry of the memory 10B. Generally, the clamp unit can safely discharge the electrostatic discharge by limiting the voltage and allowing the high current of the electrostatic discharge to be discharged to the ground bond pad 50.

[0060] Figure 4 is shown a memory 10C according to some embodiments of the present application. The memory 10C is configured similarly to the memory 10B of Figure 3 . Compared to the memory 10B of Figure 3 , the electrostatic discharge protection circuit 70 of the memory 10C is disposed within the device region 145. Thus, compared to conventional memories, no additional area (shown as reference numeral 135) is needed to dispose the electrostatic discharge protection circuit 70. Furthermore, a first path Pathl from the power bond pad 30 to the electrostatic discharge protection circuit 70 partially overlaps a second path Path2 from the power bond pad 30 to the memory cells 15 of the programmable memory array 150, as shown by reference numeral 410. In other words, the gate of the transistor MP1 is directly coupled to the electrostatic discharge protection circuit 70 without going through the power bond pad 30. Further, when the memory 10C is integrated as an intellectual property (IP) functional block in other integrated circuits, the integrated circuits do not need to provide additional electrostatic discharge protection circuits to protect the memory cells 15.

[0061] In embodiments of the present application, by disposing the electrostatic discharge protection circuit 70 between the power bond pad 30 and the program bond pad 40, the memory cells 15 that need to be programmed by the program signal VPP can be protected from the electrostatic current, thus improving the reliability of the memory. In some embodiments, the electrostatic discharge protection circuit 70 can be disposed in a device region (e.g., the device region 145) to improve the protection of the device region from electrostatic discharge events.

[0062] While the present application has been disclosed in its preferred form with reference to the drawings, it is to be understood that the application can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore considered in all respects to be illustrative and not restrictive.

Claims

1. A memory, characterized in that, include: One power connection pad; One programming mat; A programmable memory array includes a plurality of memory cells coupled to a programming pad and a power pad, wherein the plurality of memory cells operate in a programming mode when a first voltage of the programming pad is greater than a second voltage of the power pad, and the plurality of memory cells operate in a normal mode when the first voltage of the programming pad is less than the second voltage of the power pad. as well as An electrostatic discharge protection circuit is coupled between the power supply pad and the programming pad to conduct an electrostatic discharge current from the power supply pad to the programming pad in the event of an electrostatic discharge event. The first path from the power bonding pad to the electrostatic discharge protection circuit is smaller than the second path from the power bonding pad to the programmable memory array. The electrostatic discharge protection circuit includes: A first unit and a second unit, wherein the first unit and the second unit are connected in parallel between the programming pad and the power pad; A first diode having a first anode and a first cathode coupled to the power supply pad; and A second diode having a second anode coupled to the programming pad and a second cathode coupled to the first cathode.

2. The memory as claimed in claim 1, characterized in that, Each of these memory cells includes: A P-type transistor has a gate coupled to the power pad and a source coupled to the programming pad.

3. The memory as claimed in claim 1, characterized in that, The distance between the first unit and the programming pad is less than the distance between the first unit and the power pad, and the distance between the second unit and the programming pad is greater than the distance between the second unit and the power pad.

4. A memory, characterized in that, include: One power connection pad; One programming mat; A first electrostatic discharge protection circuit is coupled between the power supply pad and the programming pad; as well as A programmable memory array comprising a plurality of memory cells, wherein each memory cell includes: A P-type transistor has a gate coupled to the power supply pad and the first electrostatic discharge protection circuit, and a source coupled to the programming pad. When a first voltage of the programming pad is greater than a second voltage of the power pad, the plurality of memory cells operate in a programming mode, and when the first voltage of the programming pad is less than the second voltage of the power pad, the plurality of memory cells operate in a normal mode. Wherein a first path from the power bonding pad to the first electrostatic discharge protection circuit is smaller than a second path from the power bonding pad to the programmable memory array, and the first path partially overlaps with the second path; The first electrostatic discharge protection circuit includes: A first unit and a second unit are connected in parallel between the programming pad and the power pad; A first diode having a first anode and a first cathode coupled to the power supply pad; and A second diode having a second anode coupled to the programming pad and a second cathode coupled to the first cathode.

5. The memory as claimed in claim 4, characterized in that, The distance between the first unit and the programming pad is less than the distance between the first unit and the power pad, and the distance between the second unit and the programming pad is greater than the distance between the second unit and the power pad.

6. The memory as claimed in claim 4, characterized in that, Including: A grounding pad is coupled to the programmable memory array; A second electrostatic discharge protection circuit is coupled between the power supply pad and the grounding pad; and A third electrostatic discharge protection circuit is coupled between the grounding pad and the programming pad.

7. The memory as claimed in claim 4, characterized in that, In the event of an electrostatic discharge (ESD) event, the first ESD protection circuit conducts an ESD current from the programmable memory array through the power pad to the programming pad.

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