Test command sequence automatic calibration method, test machine, equipment and storage medium

Abstract

The embodiments of the present disclosure relate to the field of semiconductor technology and provide a method for automatically calibrating a test command sequence, a test machine, a computer device, and a storage medium. The method for automatically calibrating a test command sequence includes: storing an ACTIVE-1 command to be sent to a dynamic random access memory, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command according to a sending order, and forming a command cache sequence; determining whether the commands in the command cache sequence meet the minimum inter-command delay, and marking commands that do not meet the minimum inter-command delay as invalid commands; and sending valid commands in the stored command cache sequence to the dynamic random access memory in sequence according to the order of storage, wherein a valid command is a command in the command cache sequence that is not marked as an invalid command. The embodiments of the present disclosure at least help to increase the probability that commands in the command cache sequence that are not marked as invalid commands will be successfully executed later by screening the commands twice.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a test command sequence automatic calibration method, a test machine, a device, and a storage medium. Background Art

[0002] The growing demand for advanced computing technology to accommodate semiconductor devices and other critical computing applications places higher demands on the command sequences that can be executed by execution devices. Because different commands implement different functions and have different latency requirements between commands, it is common for some commands in the sequence to fail to execute successfully due to timing differences with their predecessors when forming a command sequence that achieves the desired functionality.

[0003] Therefore, there is a need for a semiconductor device that can identify and effectively screen the delay requirements between a large number of commands to form a command sequence, and identify and mark different commands in the command sequence to increase the probability of successful execution of the commands in the command sequence by the execution device. Summary of the Invention

[0004] The present disclosure provides a method for automatically calibrating a test command sequence, a test machine, a device, and a storage medium, which at least helps to increase the probability that commands in a command cache sequence that are not marked as invalid commands will be successfully executed later.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a test command sequence automatic calibration method for testing a dynamic random access memory, each activation command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command, and the test command sequence automatic calibration method includes: storing the ACTIVE-1 command to be sent to the dynamic random access memory, at least one inactive command and the ACTIVE-2 command corresponding to the ACTIVE-1 command according to the sending order, and forming a command cache sequence; judging whether the commands in the command cache sequence meet the minimum delay between commands, and marking the commands that do not meet the minimum delay between commands as invalid commands; and sending the valid commands stored in the command cache sequence to the dynamic random access memory in sequence according to the storage order, wherein the valid command is the command in the command cache sequence that is not marked as the invalid command.

[0006] In some embodiments, the storing of the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory according to the sending order to form a command cache sequence includes: determining that the maximum number of clocks allowed between the ACTIVE-1 command and the corresponding ACTIVE-2 command is tAAD_max; providing a first-in-first-out buffer, the depth of the first-in-first-out buffer being configured as tAAD_max+1; storing the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory in the first-in-first-out buffer according to the sending order to form the command cache sequence, and the number of commands in the command cache sequence is less than or equal to tAAD_max+1.

[0007] In some embodiments, the ACTIVE-1 command to be sent to the dynamic random access memory, at least one of the inactive commands, and the ACTIVE-2 command corresponding to the ACTIVE-1 command are stored in the first-in-first-out buffer according to the sending order to form the command cache sequence, including: storing the ACTIVE-1 command to be sent to the dynamic random access memory in the first storage position of the first-in-first-out buffer, sequentially storing and counting subsequent commands in the first-in-first-out buffer, and determining whether the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, and determining whether the current count value is equal to tAAD_max; if the currently stored command is the inactive command and the current count value is equal to tAAD_max, storing only the ACTIVE-2 command corresponding to the ACTIVE-1 command among the subsequent commands in the last storage position of the first-in-first-out buffer to form the command cache sequence; and if the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, stopping storing subsequent commands to form the command cache sequence.

[0008] In some embodiments, determining whether the commands in the command cache sequence meet the minimum delay between commands and marking the commands that do not meet the minimum delay between commands as invalid commands includes: obtaining the command that was most recently sent before receiving the ACTIVE-1 command as the first command; obtaining the minimum delay between the i-th command in the command cache sequence and the first command, and obtaining the minimum delay between the i-th command and the first i-1 commands in the command cache sequence to determine the minimum time interval between the i-th command and the ACTIVE-1 command, where i is a positive integer greater than or equal to 1 and less than or equal to tAAD_max-1; determining whether the minimum time interval is greater than tAAD_max-1 clock cycles, and if the minimum time interval is greater than tAAD_max-1 clock cycles, marking the i-th command and all subsequent inactive commands as invalid commands.

[0009] In some embodiments, the obtaining of the minimum delay between the i-th command in the command cache sequence and the first command, and the obtaining of the minimum delay between the i-th command and the first i-1 commands in the command cache sequence to determine the minimum time interval between the i-th command and the ACTIVE-1 command, include: defining the occurrence time of the first command as time 0; defining the minimum delay between the ACTIVE-1 command and the first command as T0, defining the occurrence time of the ACTIVE-1 command as C0, and defining the minimum time interval between the i-th command in the command cache sequence and the first i-1 commands as C0. The minimum delay between the first commands is defined as Ti, the occurrence time of the i-th command is defined as Ci, and the minimum delay between the command before the i-th command in the command cache sequence and the first command is defined as tx, where x is a positive integer greater than or equal to 0 and less than or equal to i-1; compare the sizes of Ti, Ci-1+ti-1, Ci-1+ti-1,...C0+t0, and define the largest one as the time Ci when the i-th command occurs, and calculate the difference between Ci and C0 as the minimum time interval between the i-th command and the ACTIVE-1 command.

[0010] In some embodiments, if the minimum time interval is less than or equal to tAAD_max-1 clock cycles, the minimum delay between the i-th command and the ACTIVE-2 command is obtained; when the sum of the minimum delay between the i-th command and the ACTIVE-2 command and the minimum time interval is greater than tAAD_max clock cycles, the i-th command and all subsequent inactive commands are marked as invalid commands.

[0011] In some embodiments, after marking the i-th command as the invalid command, it also includes: if the invalid command is one of a read command, a write command, a register read command, and a register write command, then the previous column selection command adjacent to the invalid command is identified as the invalid command.

[0012] In some embodiments, sending the valid commands stored in the command cache sequence to the dynamic random access memory in sequence according to the order of storage includes: waiting for the minimum delay between the ACITVE-1 command and the first command, and then sending the valid commands in the command cache sequence in sequence after a preset time interval.

[0013] In some embodiments, the dynamic random access memory is LPDDR4 DRAM or LPDDR5 DRAM.

[0014] In some embodiments, a maximum number of clocks tAAD_max allowed between the ACTIVE-1 command and the corresponding ACTIVE-2 command is equal to 8.

[0015] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a test machine for testing a dynamic random access memory, wherein each activation command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command, and the test machine includes: a storage module, configured to store the ACTIVE-1 command to be sent to the dynamic random access memory, at least one inactive command and the ACTIVE-2 command corresponding to the ACTIVE-1 command according to a sending order, and form a command cache sequence; a judgment and marking module, configured to judge whether the commands in the command cache sequence meet the minimum delay between commands, and mark the commands that do not meet the minimum delay between commands as invalid commands; a sending module, configured to send the valid commands stored in the command cache sequence to the dynamic random access memory in sequence according to the storage order, wherein the valid command is the command in the command cache sequence that is not marked as the invalid command.

[0016] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a computer device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the test command sequence automatic calibration method as described above.

[0017] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the test command sequence automatic calibration method as described above.

[0018] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0019] A test command sequence automatic calibration method is provided for testing a dynamic random access memory, wherein a command cache sequence is formed including an ACTIVE-1 command, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command, and the commands in the command cache sequence are screened. Specifically, it is determined whether the commands in the command cache sequence meet the minimum delay between commands, and the commands that do not meet the minimum delay between commands are marked as invalid commands. In this way, it is beneficial to control the minimum delay between adjacent valid commands in the command cache sequence, including the ACTIVE-1 command and the ACTIVE-2 command, within the preset requirements, ensuring that the ACTIVE-1 command and the ACTIVE-2 command are effective, and ensuring that the sending of subsequent valid commands meets the timing requirements, thereby facilitating the increase in the probability that the commands in the command cache sequence that are not marked as invalid commands, i.e., valid commands, are subsequently successfully executed. The sending of valid commands can be understood as: sending the valid commands in the command cache sequence to the dynamic random access memory in sequence according to the minimum delay between adjacent valid commands, so as to test the dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart of a test command sequence automatic calibration method provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the structure of a first-in-first-out buffer in a test command sequence automatic calibration method provided by an embodiment of the present disclosure;

[0023] Figure 3A schematic diagram illustrating a method for automatically calibrating a test command sequence according to an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of functional modules of a test machine provided in another embodiment of the present disclosure;

[0025] Figure 5 A schematic structural diagram of a computer device provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] As known from the background art, the probability of successfully executing commands in a command sequence by a dynamic random access memory needs to be improved.

[0027] After analysis, it was found that in order to achieve a specific function, the command sequence formed for execution by the dynamic random access memory includes the ACTIVE-1 command and the ACTIVE-2 command. The ACTIVE-1 command and the ACTIVE-2 command can be sent immediately after each other or at intervals. In the case of interval sending, there is a minimum delay requirement between the ACTIVE-1 command and the ACTIVE-2 command, that is, the time interval between the moment when the ACTIVE-1 command is sent to the dynamic random access memory for execution and the moment when the ACTIVE-2 command is sent to the dynamic random access memory for execution cannot exceed the preset time. Otherwise, the ACTIVE-1 command and the ACTIVE-2 command will be regarded as invalid commands and will not be executed when they are sent to the dynamic random access memory. Moreover, when the ACTIVE-1 command and the ACTIVE-2 command are sent at intervals, other commands may be inserted between the ACTIVE-1 command and the ACTIVE-2 command, such as the CAS command, the MASKED WRITE command, the READ command, the MRR command, the PRECHARGE command, the Refresh command, etc. Since these commands have corresponding timing requirements with each other and with the ACTIVE-1 command and the ACTIVE-2 command, if the time interval between the times when these commands are sent to the dynamic random access memory and are executed does not meet the corresponding timing requirements, these commands will also be regarded as invalid commands and will not be executed when they are sent to the dynamic random access memory.

[0028] As can be seen, the commands to be sent between the ACTIVE-1 and ACTIVE-2 commands must not only consider their timing relationship with the commands that have already been sent, but also the timing relationship between the commands to be sent, which makes the algorithm involved relatively complex. When forming a command sequence that can achieve the expected function, it is easy for some commands in the command buffer sequence to fail to meet the timing requirements with the previous command and thus cannot be successfully executed.

[0029] The present disclosure provides a method for automatically calibrating a test command sequence, a test machine, a device, and a storage medium. In the method, a command cache sequence is formed, including an ACTIVE-1 command, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command. The commands in the command cache sequence are screened. Specifically, it is determined whether the commands in the command cache sequence meet the minimum delay between commands, and the commands that do not meet the minimum delay between commands are marked as invalid commands. The remaining commands in the command cache sequence are valid commands. In this way, the minimum delay between adjacent valid commands in the command cache sequence, including the ACTIVE-1 command and the ACTIVE-2 command, is controlled within the preset requirements, ensuring that the ACTIVE-1 command and the ACTIVE-2 command are effective, and ensuring that the sending of subsequent valid commands meets the timing requirements, thereby increasing the probability that the commands in the command cache sequence that are not marked as invalid commands are subsequently successfully executed.

[0030] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0031] An embodiment of the present disclosure provides a semiconductor device, which will be described in detail below with reference to the accompanying drawings. Figure 1 A flowchart of a test command sequence automatic calibration method provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a first-in-first-out buffer in a test command sequence automatic calibration method provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of a judgment method for automatic calibration of a test command sequence provided by an embodiment of the present disclosure.

[0032] refer to Figures 1 to 3 A test command sequence automatic calibration method is provided for testing a dynamic random access memory, wherein each activation command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command. The test command sequence automatic calibration method comprises the following steps:

[0033] S101: storing an ACTIVE-1 command, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to a dynamic random access memory according to a sending order, and forming a command cache sequence.

[0034] In some embodiments, storing an ACTIVE-1 command, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to a dynamic random access memory according to a sending order to form a command cache sequence includes the following steps:

[0035] First, the maximum number of clocks allowed between the ACTIVE-1 command and its corresponding ACTIVE-2 command is determined to be tAAD_max. In one example, the maximum number of clocks allowed between the ACTIVE-1 command and its corresponding ACTIVE-2 command, tAAD_max, is equal to 8.

[0036] Next, a FIFO buffer 100 is provided. The depth of FIFO buffer 100 is configured as tAAD_max+1. It is understood that the depth of FIFO buffer 100 configured as tAAD_max+1 means that FIFO buffer 100 can store a maximum of tAAD_max+1 commands. FIFO buffer 100 is a FIFO (First Input First Output) memory.

[0037] Then, the ACTIVE-1 command to be sent to the dynamic random access memory, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command are stored in the first-in-first-out buffer 100 according to the sending order to form a command cache sequence, and the number of commands in the command cache sequence is less than or equal to tAAD_max+1.

[0038] In this way, it is achieved that only the command located at the first storage position in the command cache sequence is the ACTIVE-1 command, and only the command located at the last storage position in the command cache sequence is the ACTIVE-2 command, laying the foundation for the ACTIVE-1 command and the ACTIVE-2 command to be activated as valid commands.

[0039] In some embodiments, storing an ACTIVE-1 command, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory in a first-in-first-out buffer 100 according to a sending order to form a command buffer sequence includes the following steps:

[0040] refer to Figure 2 , the ACTIVE-1 command to be sent to the dynamic random access memory is stored in the first storage position of the first-in-first-out buffer 100, and subsequent commands are stored in the first-in-first-out buffer 100 in sequence and counted, and it is determined whether the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, and whether the current count value is equal to tAAD_max.

[0041] Among them, if the currently stored command is an inactive command and the current count value is equal to tAAD_max, only the ACTIVE-2 command corresponding to the ACTIVE-1 command in the subsequent commands is stored in the last storage position of the first-in-first-out buffer 100 to form a command cache sequence; if the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, the storage of subsequent commands is stopped to form a command cache sequence.

[0042] It can be understood that if the second-to-last command stored in the first-in-first-out buffer 100 is not the ACTIVE-2 command, the ACTIVE-2 command will be moved to the last storage position of the first-in-first-out buffer 100 to meet the storage command capacity of the first-in-first-out buffer 100 while satisfying the requirement that the only command located at the last storage position in the command cache sequence is the ACTIVE-2 command.

[0043] It should be noted that Figure 2 COMMAND-1, COMMAND-2, COMMAND-3, COMMAND-4, COMMAND-5, COMMAND-6, and COMMAND-7 are used to indicate commands other than ACTIVE-1 and ACTIVE-2.

[0044] S102: Determine whether the commands in the command cache sequence meet the minimum inter-command delay, and mark the commands that do not meet the minimum inter-command delay as invalid commands.

[0045] It can be understood that the time when a command occurs is the time when the command is sent to the dynamic random access memory, and the minimum delay between two commands with a front-to-back position relationship in the command cache sequence is the maximum time interval allowed between the time when the two commands occur. If the difference between the actual time when the two commands occur is greater than the maximum time interval, the command located later in the two commands will be deemed an invalid command; if the difference between the actual time when the two commands occur is less than or equal to the maximum time interval, the command located later in the two commands is a valid command and can be successfully executed by the dynamic random access memory when sent to the dynamic random access memory.

[0046] In some embodiments, reference Figure 3The test command sequence automatic calibration method further includes: obtaining a first command Prior Command sent to the dynamic random access memory before the first-in-first-out buffer 100 starts storing commands; obtaining a minimum delay T0 between the ACTIVE-1 command in the command sequence and the first command Prior Command, and using the time after the minimum delay T0 as the occurrence time C0 of the ACTIVE-1 command; using any command other than the ACTIVE-1 command to be stored in the first-in-first-out buffer 100 as a command to be tested, and determining the occurrence time C0 of the command to be tested based on the minimum delay between the command to be tested and the first command Prior Command, and the minimum delay between each command located before the command to be tested and the command to be tested. i , if C i If the difference between C0 and C1 is greater than a preset value, the command to be tested is determined to be an invalid command, where i is a positive integer greater than or equal to 1.

[0047] In one example, determining whether commands in a command cache sequence meet a minimum inter-command delay and marking commands that do not meet the minimum inter-command delay as invalid commands includes the following steps:

[0048] refer to Figure 3 First, obtain the command that was most recently sent before receiving the ACTIVE-1 command as the first command PriorCommand; obtain the minimum delay between the i-th command in the command cache sequence and the first command Prior Command, and obtain the minimum delay between the first command Prior Command and the first i-1 commands in the command cache sequence to determine the minimum time interval between the i-th command and the ACTIVE-1 command, where i is a positive integer greater than or equal to 1 and less than or equal to tAAD_max-1; determine whether the minimum time interval is greater than tAAD_max-1 clock cycles. If the minimum time interval is greater than tAAD_max-1 clock cycles, mark the i-th command and all subsequent inactive commands as invalid commands.

[0049] It should be noted that the i-th command in the command cache sequence refers to the i-th command in the command cache sequence excluding the ACTIVE-1 command.

[0050] In some embodiments, the steps of obtaining a minimum delay between an i-th command and a first command (Prior Command) in a command cache sequence, and obtaining a minimum delay between the i-th command and the first (i-1) commands in the command cache sequence to determine a minimum time interval between the i-th command and an ACTIVE-1 command include:

[0051] The occurrence time of the first command Prior Command is defined as time 0; the minimum delay between the ACTIVE-1 command and the first command Prior Command is defined as T0, the occurrence time of the ACTIVE-1 command is defined as C0, the minimum delay between the i-th command and the first command Prior Command in the command cache sequence is defined as Ti, and the occurrence time of the i-th command is defined as C i The minimum delay between the command before the i-th command in the command cache sequence and the first command Prior Command is defined as tx, where x is a positive integer greater than or equal to 0 and less than or equal to i-1; compare Ti, C i-1+ t i-1 、C i-1+ t i-1 ,……C 0+ The maximum value among them is defined as the time Ci when the i-th command occurs, and the difference between Ci and C0 is calculated as the minimum time interval between the i-th command and the ACTIVE-1 command.

[0052] The following combination Figure 2 and Figure 3 Describe it in detail.

[0053] Figure 3 The diagram illustrates the ACTIVE-1 command, the second command COMMAND-1, and the third command COMMAND-2 in the command buffer sequence.

[0054] For the ACTIVE-1 command, the minimum delay T0 between the ACTIVE-1 command and the first command Prior Command is obtained, and the time after the minimum delay T0 is used as the occurrence time C0 of the ACTIVE-1 command. In one example, the occurrence time of the first command Prior Command can be defined as time 0, and the occurrence time C0 of the ACTIVE-1 command is T0.

[0055] If the second command COMMAND-1 is taken as the i-th command, that is, i is equal to 1, the command before the second command COMMAND-1 is the ACTIVE-1 command, obtain the minimum delay T1 between the second command COMMAND-1 and the first command Prior Command, obtain the minimum delay t0 between the second command COMMAND-1 and the ACTIVE-1 command, compare T1 with (C0+t0), and determine the larger one as the occurrence time C1 of the second command COMMAND-1. In an example, refer to Figure 3 , T1 is less than (C0+t0), then the generation time C1 of the second command COMMAND-1 is (C0+t0).

[0056] If the difference between C1 and C0 is greater than tAAD_max-1 clock cycles, the second command COMMAND-1 is determined to be an invalid command.

[0057] If the third command COMMAND-2 is taken as the i-th command, that is, i is equal to 2, and the commands before the third command COMMAND-2 are the ACTIVE-1 command and the second command COMMAND-1, obtain the minimum delay T2 between the third command COMMAND-2 and the first command PriorCommand, obtain the minimum delay t0 between the third command COMMAND-2 and the ACTIVE-1 command, obtain the minimum delay t1 between the third command COMMAND-2 and the second command COMMAND-1, compare T2, (C0+t0), (C1+t1), and determine the maximum of the three as the occurrence time C2 of the third command COMMAND-2. In an example, refer to Figure 3 , (C0+t0) is less than (C1+t1), and (C1+t1) is less than T2, then the generation time C2 of the third command COMMAND-2 is T2.

[0058] If the difference between C2 and C0 is greater than tAAD_max-1 clock cycles, the third command COMMAND-2 is determined to be an invalid command.

[0059] It can be understood that, by analogy, the i-th command can be used as the command to be tested, and the commands before the i-th command are the ACTIVE-1 command, the second command COMMAND-1... the i-1-th command, and the minimum delay T between the i-th command and the first command Prior Command is obtained. i , get the minimum delay t0 between the i-th command and the ACTIVE-1 command, get the minimum delay t1 between the i-th command and the second command COMMAND-1...get the minimum delay t between the i-th command and the i-1-th command COMMANDi-1 i-1 , the largest one is determined as the occurrence time C of the i-th command i .

[0060] Among them, if C iIf the difference with C0 is greater than tAAD_max-1 clock cycles, the i-th command is determined to be an invalid command. It can be understood that when the minimum delay between the i-th command and the ACTIVE-1 command is greater than tAAD_max-1 clock cycles, that is, the occurrence time of the i-th command will be later than the occurrence time of the ACTIVE-2 command, then the i-th command cannot be successfully executed by the dynamic random access memory and will be regarded as an invalid command. Therefore, judging the i-th command based on the minimum delay between the i-th command and the ACTIVE-1 command is conducive to further improving the accuracy of screening out invalid commands from the command cache sequence, so as to further ensure that the subsequent sending of valid commands meets the timing requirements, so as to increase the probability of subsequent successful execution of commands that are not marked as invalid commands in the command cache sequence. Moreover, it is beneficial to compare the timing requirements between each command in the command cache sequence and each command before the command to screen out invalid commands, thereby ensuring that the sending of subsequent valid commands meets the timing requirements, thereby increasing the probability that the commands in the command cache sequence that are not marked as invalid commands are subsequently successfully executed by the dynamic random access memory.

[0061] It should be noted that Figure 3 The first command is marked with Prior Command, the second command is marked with COMMAND-1, and the third command is marked with COMMAND-2.

[0062] In some embodiments, if the minimum time interval is less than or equal to tAAD_max-1 clock cycles, the minimum delay between the i-th command and the ACTIVE-2 command is obtained. When the sum of the minimum delay and the minimum time interval between the i-th command and the ACTIVE-2 command is greater than tAAD_max clock cycles, the i-th command and all subsequent inactive commands are marked as invalid commands. It is understood that if the sum of the minimum delay and the minimum time interval between the i-th command and the ACTIVE-2 command is greater than tAAD_max clock cycles, the i-th command is generated later than the ACTIVE-2 command, and the i-th command cannot be executed by the dynamic random access memory, that is, the i-th command is an invalid command. If the i-th command does not meet the timing requirements and cannot be successfully executed, all inactive commands after the i-th command cannot be successfully executed.

[0063] In other embodiments, if the minimum time interval is less than or equal to tAAD_max-1 clock cycles, the minimum delay between the i-th command and the ACTIVE-2 command is obtained. If the sum of the minimum delay between the i-th command and the ACTIVE-2 command and the minimum time interval is greater than tAAD_max clock cycles, the i-th command is considered an invalid command. If the i-th command is an invalid command, then a preset number of commands immediately following the i-th command are also determined to be invalid commands. It is understood that if the i-th command does not meet timing requirements and cannot be successfully executed, then the preset number of commands immediately following the i-th command cannot also be successfully executed. For example, if the command immediately following a CAS command is at least one of a WRITE command, a READ command, or an MRR command, and if the CAS command is deemed invalid after the second screening, at least one of the WRITE command, READ command, or MRR command immediately following the CAS command is also deemed invalid. It should be noted that the preset number can be 1. The preset number depends on the specific application scenario. In one embodiment of the present disclosure, the specific value of the preset number is not limited; it only needs to be a positive integer greater than or equal to 1.

[0064] It is understandable that when the minimum delay between the i-th command and the ACTIVE-2 command is greater than tAAD_max clock cycles, that is, the i-th command is generated earlier than the ACTIVE-1 command, the i-th command cannot be successfully executed by the dynamic random access memory and will be deemed an invalid command. Therefore, judging the i-th command based on the minimum delay between the i-th command and the ACTIVE-2 command is beneficial to further improve the accuracy of filtering out invalid commands from the command sequence, further ensuring that the transmission of subsequent valid commands meets the timing requirements, and increasing the probability of successful execution of commands in the command sequence that are not marked as invalid commands.

[0065] In some embodiments, after marking the i-th command as an invalid command, the test command sequence automatic calibration method may further include: if the invalid command is one of a read command, a write command, a register read command, and a register write command, then marking the immediately preceding column select command of the invalid command as an invalid command. S103: Sending valid commands in the stored command cache sequence to the dynamic random access memory in sequence according to the order of storage, wherein valid commands are commands in the command cache sequence that are not marked as invalid commands.

[0066] In some embodiments, the step of sequentially sending valid commands in the stored command cache sequence to the dynamic random access memory according to the stored order includes: after waiting for a minimum delay between the ACITVE-1 command and the first command, the Prior Command, and then sending the valid commands in the command cache sequence in sequence at intervals of a preset time. This helps avoid the dynamic random access memory receiving the ACITVE-1 command before completing the execution of the prior command, thereby ensuring normal operation of the dynamic random access memory. It should be noted that the preset time is an integer not greater than 0, and the specific value can be set according to actual application conditions.

[0067] In some embodiments, the test command sequence automatic calibration method may further include: determining a sending time interval between two adjacent valid commands based on a difference between the occurrence times of two adjacent valid commands in the command cache sequence; controlling the FIFO buffer 100 to wait for a preset time before starting to send valid commands in the command cache sequence that are not marked as invalid commands to the dynamic random access memory; and controlling the FIFO buffer 100 to wait for the sending time interval after sending the first valid command of the two adjacent valid commands before sending the second valid command of the two adjacent valid commands. This helps to provide the dynamic random access memory with time to execute each valid command, thereby avoiding the situation where the valid commands are not successfully executed.

[0068] In some embodiments, the dynamic random access memory is LPDDR4 DRAM or LPDDR5 DRAM.

[0069] For LPDDR4 (Low Power Double Data Rate 4) and LPDDR5 (Low Power Double Data Rate 5), the time interval between the sending of the ACTIVE-1 command and the ACTIVE-2 command is called tAAD_max. In one example, the maximum number of clock cycles allowed between the ACTIVE-1 command and its corresponding ACTIVE-2 command, tAAD_max, is equal to 8. It can be understood that only when the ACTIVE-1 command is the first command in the command cache sequence and the ACTIVE-2 command is the last command in the command cache sequence, and the time interval between the execution time of the ACTIVE-1 command and the generation time of the ACTIVE-2 command is less than or equal to 8 clock cycles, can the ACTIVE-1 command and ACTIVE-2 command be activated and take effect.

[0070] In summary, in the test command sequence automatic calibration method, the command cache sequence formed includes the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command, and the commands in the command cache sequence are screened. Specifically, it is determined whether the commands in the command cache sequence meet the minimum inter-command delay, and the commands that do not meet the minimum inter-command delay are marked as invalid commands, and the remaining commands in the command cache sequence are valid commands. In this way, it is beneficial to control the minimum delay between adjacent valid commands in the command cache sequence, including the ACTIVE-1 command and the ACTIVE-2 command, within the preset requirements, ensuring that the ACTIVE-1 command and the ACTIVE-2 command are effective, and ensuring that the sending of subsequent valid commands meets the timing requirements, thereby helping to increase the probability that the commands in the command cache sequence that are not marked as invalid commands will be successfully executed later.

[0071] Another embodiment of the present disclosure further provides a test machine for executing the test command sequence automatic calibration method provided in an embodiment of the present disclosure. Figure 4 A test machine provided in another embodiment of the present disclosure is described in detail. Figure 4 This is a schematic diagram of the functional modules of a test machine provided in another embodiment of the present disclosure. It should be noted that parts identical or corresponding to the above embodiments are not described again in detail.

[0072] Combined with reference Figure 2 and Figure 4 The test machine is used to test a dynamic random access memory, where each activation command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command. The test machine includes: a storage module 101, configured to store, according to a sending order, an ACTIVE-1 command to be sent to the dynamic random access memory, at least one inactive command, and an ACTIVE-2 command corresponding to the ACTIVE-1 command, and form a command cache sequence; a judgment and marking module 102, configured to judge whether the commands in the command cache sequence meet the minimum inter-command delay, and mark the commands that do not meet the minimum inter-command delay as invalid commands; a sending module 103, configured to send valid commands in the stored command cache sequence to the dynamic random access memory in sequence according to the storage order, wherein the valid commands are commands in the command cache sequence that are not marked as invalid commands.

[0073] It can be understood that the automatic calibration method of the test command sequence implemented by the test machine is conducive to controlling the minimum delay between adjacent valid commands in the command cache sequence, including the ACTIVE-1 command and the ACTIVE-2 command, within the preset requirements, ensuring that the ACTIVE-1 command and the ACTIVE-2 command are effective, and ensuring that the sending of subsequent valid commands meets the timing requirements, thereby helping to increase the probability of the commands in the command cache sequence that are not marked as invalid commands being successfully executed subsequently.

[0074] Another embodiment of the present disclosure further provides a computer device, such as Figure 5 As shown, it includes at least one processor 202; and a memory 201 that is communicatively connected to the at least one processor 202; wherein the memory 201 stores instructions that can be executed by the at least one processor 202, and the instructions are executed by the at least one processor 202 to enable the at least one processor 202 to execute the test command sequence automatic calibration method provided in one embodiment of the present disclosure.

[0075] in, Figure 5 A schematic structural diagram of a computer device provided in yet another embodiment of the present disclosure.

[0076] The memory 201 and processor 202 are connected using a bus. The bus can include any number of interconnected buses and bridges, connecting one or more processors 202 and various circuits of the memory 201. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor 202 is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor 202.

[0077] The processor 202 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory 201 can be used to store data used by the processor 202 when performing operations.

[0078] Another aspect of the present disclosure further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the test command sequence automatic calibration method provided in an embodiment of the present disclosure.

[0079] Those skilled in the art will understand that all or part of the steps in the control method of the semiconductor device provided in the above embodiments can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0080] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for automatically calibrating a test command sequence for testing a dynamic random access memory, wherein each active command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command, characterized in that: include: storing the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory according to a sending order, and forming a command cache sequence; Determining whether commands in the command cache sequence meet a minimum inter-command delay, and marking commands that do not meet the minimum inter-command delay as invalid commands; The valid commands stored in the command cache sequence are sent to the dynamic random access memory in sequence according to the order of storage, wherein the valid commands are commands in the command cache sequence that are not marked as invalid commands.

2. The method according to claim 1, characterized in that The storing, according to a sending order, the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory to form a command cache sequence includes: Determine that the maximum number of clocks allowed between the ACTIVE-1 command and the corresponding ACTIVE-2 command is tAAD_max; Providing a first-in-first-out buffer, wherein the depth of the first-in-first-out buffer is configured to be tAAD_max+1; The ACTIVE-1 command to be sent to the dynamic random access memory, at least one of the inactive commands, and the ACTIVE-2 command corresponding to the ACTIVE-1 command are stored in the first-in-first-out buffer according to the sending order to form the command cache sequence, and the number of commands in the command cache sequence is less than or equal to tAAD_max+1.

3. The method according to claim 2, characterized in that The method further comprises storing the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory in the first-in-first-out buffer according to the sending order to form the command buffer sequence, including: storing the ACTIVE-1 command to be sent to the dynamic random access memory in the first storage position of the first-in-first-out buffer, sequentially storing subsequent commands in the first-in-first-out buffer and counting them, and determining whether the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, and determining whether the current count value is equal to tAAD_max; If the currently stored command is the inactive command and the current count value is equal to tAAD_max, only the ACTIVE-2 command corresponding to the ACTIVE-1 command among subsequent commands is stored in the last storage location of the FIFO buffer to form the command buffer sequence; If the currently stored command is the ACTIVE-2 command corresponding to the ACTIVE-1 command, storage of subsequent commands is stopped to form the command cache sequence.

4. The method according to any one of claims 1 to 3, characterized in that The determining whether the commands in the command cache sequence meet the minimum inter-command delay, and marking the commands that do not meet the minimum inter-command delay as invalid commands, includes: Obtaining the command that was most recently sent before receiving the ACTIVE-1 command as the first command; Obtaining a minimum delay between an i-th command in the command cache sequence and the first command, and obtaining a minimum delay between the i-th command and the first i-1 commands in the command cache sequence, to determine a minimum time interval between the i-th command and the ACTIVE-1 command, where i is a positive integer greater than or equal to 1 and less than or equal to tAAD_max-1; It is determined whether the minimum time interval is greater than tAAD_max-1 clock cycle. If the minimum time interval is greater than tAAD_max-1 clock cycle, the i-th command and all subsequent inactive commands are marked as invalid commands.

5. The method according to claim 4, characterized in that Obtaining a minimum delay between an i-th command in the command cache sequence and the first command, and obtaining a minimum delay between the i-th command and first (i-1) commands in the command cache sequence to determine a minimum time interval between the i-th command and the ACTIVE-1 command, includes: The occurrence time of the first command is defined as time 0; The minimum delay between the ACTIVE-1 command and the first command is defined as T0, the occurrence time of the ACTIVE-1 command is defined as C0, the minimum delay between the i-th command in the command cache sequence and the first command is defined as Ti, the occurrence time of the i-th command is defined as Ci, and the minimum delay between the command before the i-th command in the command cache sequence and the first command is defined as tx, where x is a positive integer greater than or equal to 0 and less than or equal to i-1; Compare the sizes of Ti, Ci-1+ti-1, Ci-1+ti-1,...C0+t0, define the largest one as the moment Ci when the i-th command occurs, and calculate the difference between Ci and C0 as the minimum time interval between the i-th command and the ACTIVE-1 command.

6. The method according to claim 5, characterized in that If the minimum time interval is less than or equal to tAAD_max-1 clock cycles, the minimum delay between the i-th command and the ACTIVE-2 command is obtained; when the sum of the minimum delay between the i-th command and the ACTIVE-2 command and the minimum time interval is greater than tAAD_max clock cycles, the i-th command and all subsequent inactive commands are marked as invalid commands.

7. The method according to claim 6, characterized in that After marking the i-th command as the invalid command, the method further includes: If the invalid command is one of a read command, a write command, a register read command, and a register write command, then the previous column selection command immediately adjacent to the invalid command is identified as the invalid command.

8. The method according to claim 7, characterized in that The sending of the valid commands stored in the command cache sequence to the dynamic random access memory in sequence according to the order of storage includes: After waiting for a minimum delay between the ACTIVE-1 command and the first command, the valid commands in the command buffer sequence are sent in sequence at intervals of a preset time.

9. The method according to claim 8, characterized in that The dynamic random access memory is LPDDR4 DRAM or LPDDR5 DRAM.

10. The method according to claim 9, characterized in that The maximum number of clocks tAAD_max allowed between the ACTIVE-1 command and the corresponding ACTIVE-2 command is equal to 8.

11. A test machine for testing dynamic random access memory, wherein each activation command includes a corresponding ACTIVE-1 command and an ACTIVE-2 command, characterized in that: include: a storage module configured to store the ACTIVE-1 command, at least one inactive command, and the ACTIVE-2 command corresponding to the ACTIVE-1 command to be sent to the dynamic random access memory according to a sending order, and form a command cache sequence; a judging and marking module configured to judge whether the commands in the command cache sequence meet the minimum inter-command delay, and mark the commands that do not meet the minimum inter-command delay as invalid commands; The sending module is configured to send the valid commands stored in the command cache sequence to the dynamic random access memory in sequence according to the storage order, wherein the valid commands are commands in the command cache sequence that are not marked as invalid commands.

12. A computer device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the test command sequence automatic calibration method according to any one of claims 1 to 10.

13. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the test command sequence automatic calibration method according to any one of claims 1 to 10 is implemented.

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