Methods for forming alignment marks in semiconductor processes

Abstract

This invention provides a method for forming alignment marks in semiconductor processes. Trenches are simultaneously etched in both the device region and the alignment region. After filling the trenches in the alignment region with a dielectric layer, a cap epitaxial layer is formed in both the device region and the alignment region. By controlling the trench width and the thickness of the cap epitaxial layer in the alignment region, the cap epitaxial layer is not completely closed above the dielectric layer. The gap in the cap epitaxial layer serves as the alignment mark on the front side of the semiconductor substrate, and the bottom of the dielectric layer serves as the alignment mark on the back side of the semiconductor substrate. This method avoids the attenuation or disappearance of alignment signals during the planarization process after epitaxy, and does not increase alignment errors. It also ensures the clarity and accuracy of the front and back alignment signals, improving process reliability.

Description

Technical Field

[0001] This invention relates to a method for forming alignment marks in a semiconductor process. Background Technology

[0002] In existing semiconductor processes, alignment marks for photolithography are typically formed on the substrate surface first (e.g., individual alignment marks, or alignment mark patterns within the active region mask) as a starting step before other steps are performed. However, for CIS (CMOS Image Sensor) or other processes that require epitaxy before the formation of the active region, the shallow alignment marks are affected by the planarization process after epitaxy, leading to attenuation or disappearance of the alignment signal.

[0003] To address the alignment issue in semiconductor processes where epitaxy is performed before the formation of the active region, a shallow trench can be formed in the alignment region and filled with a dielectric layer as an alignment mark. Then, a deep trench can be formed in the device region and epitaxially grown. Finally, the active region is formed in the epitaxial layer. Although the alignment mark is not affected by the planarization process after epitaxy, this approach has the disadvantage of adding a shallow trench photolithography etching step, which increases the error of nested alignment. Furthermore, because the alignment mark is far from the back side of the substrate, the alignment signal is weak when performing back-side processing, making it unsuitable for semiconductor processes that require back-side processing, such as back-illuminated image sensor processes. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming alignment marks in semiconductor processes, which can avoid the attenuation or disappearance of alignment signals caused by the planarization process after epitaxy, without increasing alignment errors, while ensuring the clarity and accuracy of the front alignment signal and the back alignment signal, thereby improving process reliability.

[0005] Based on the above considerations, the present invention provides a method for forming alignment marks in a semiconductor process, comprising: providing a semiconductor substrate having a front side and a back side; defining a device region and an alignment region; simultaneously etching trenches in the device region and the alignment region on the front side of the semiconductor substrate; filling a dielectric layer in the trenches of the alignment region; forming a cap epitaxial layer in the device region and the alignment region; by controlling the trench width and the thickness of the cap epitaxial layer in the alignment region, the cap epitaxial layer is not completely closed above the dielectric layer, using the gap in the cap epitaxial layer as an alignment mark on the front side of the semiconductor substrate, and using the bottom of the dielectric layer as an alignment mark on the back side of the semiconductor substrate; and forming a semiconductor device in the device region.

[0006] Preferably, the step of filling the trench in the alignment region with a dielectric layer includes: forming an embedded epitaxial layer in the trenches of the device region and the alignment region respectively, wherein when the trench in the device region is filled with the embedded epitaxial layer, the trench in the alignment region is not filled with the embedded epitaxial layer; and filling the trench in the alignment region with a dielectric layer.

[0007] Preferably, the step of filling the trench in the alignment region with a dielectric layer includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively, wherein when the trench in the device region is filled with the polysilicon layer, the trench in the alignment region is not filled with the polysilicon layer; and filling the trench in the alignment region with a second dielectric layer.

[0008] Preferably, the step of filling the trench in the alignment region with a dielectric layer includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region, respectively; removing the polysilicon layer in the trench of the alignment region; and filling the trench in the alignment region with a second dielectric layer.

[0009] Preferably, before the step of forming the first dielectric layer in the trenches of the device region and the alignment region, the method further includes forming an embedded epitaxial layer in the trenches of the device region and the alignment region.

[0010] Preferably, the dielectric layer is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0011] Preferably, the process for forming the dielectric layer includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0012] Preferably, after the step of filling the trench in the alignment region with a dielectric layer, the method further includes planarizing the device region and the alignment region by chemical mechanical polishing.

[0013] Preferably, the method for forming the alignment marks is applied in a back-illuminated image sensor process.

[0014] Preferably, when thinning the back side of the semiconductor substrate, the process stops at the bottom of the dielectric layer.

[0015] The method for forming alignment marks in the semiconductor process of the present invention involves simultaneously etching trenches in the device region and the alignment region. After filling the trenches in the alignment region with a dielectric layer, a capping epitaxial layer is formed in both the device region and the alignment region. By controlling the trench width and the thickness of the capping epitaxial layer in the alignment region, the capping epitaxial layer is not completely closed above the dielectric layer. The gap in the capping epitaxial layer is used as an alignment mark on the front side of the semiconductor substrate (the morphology of the gap in the capping epitaxial layer is obtained using visible light as a front alignment signal), and the bottom of the dielectric layer is used as an alignment mark on the back side of the semiconductor substrate (the signal difference between the dielectric layer and the substrate is obtained using infrared light as a back alignment signal). This method has the following advantages:

[0016] (1) No additional photolithography step is required, and no alignment error is required;

[0017] (2) The alignment signal can be obtained through visible light, and the signal is clear and highly accurate;

[0018] (3) After the substrate back side is thinned, the bottom of the dielectric layer is exposed on the substrate back side or is close to the back side, the back side alignment signal is clear, and the influence of substrate distortion caused by the thinning process is small;

[0019] (4) The notch of the cap epitaxial layer does not need to be too deep, so as not to cause photoresist residue in the notch in subsequent processes. Attached Figure Description

[0020] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0021] Figure 1 This is a flowchart of a method for forming alignment marks in the semiconductor process of the present invention;

[0022] Figures 2-8 This is a schematic diagram of a method for forming alignment marks in a semiconductor process according to Embodiment 1 of the present invention;

[0023] Figures 9-15 This is a schematic diagram of a method for forming alignment marks in a semiconductor process according to Embodiment 2 of the present invention;

[0024] Figures 16-22 This is a schematic diagram of the process of forming alignment marks in a semiconductor process according to Embodiment 3 of the present invention.

[0025] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0026] To address the problems in the prior art, this invention provides a method for forming alignment marks in a semiconductor process. Trenches are simultaneously etched in both the device region and the alignment region. After filling the trenches in the alignment region with a dielectric layer, a cap epitaxial layer is formed in both the device region and the alignment region. By controlling the trench width and the thickness of the cap epitaxial layer in the alignment region, the cap epitaxial layer is not completely closed above the dielectric layer. The gap in the cap epitaxial layer serves as the alignment mark on the front side of the semiconductor substrate, and the bottom of the dielectric layer serves as the alignment mark on the back side of the semiconductor substrate. This method avoids the attenuation or disappearance of alignment signals during the planarization process after epitaxy, and does not increase alignment errors. Simultaneously, it ensures the clarity and accuracy of the front and back alignment signals, improving process reliability.

[0027] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form part of this invention. The accompanying drawings illustrate specific embodiments by way of example that enable the implementation of the invention. The exemplary embodiments are not intended to be exhaustive of all embodiments according to the invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the invention is defined by the appended claims.

[0028] Figure 1 A flowchart illustrating a method for forming alignment marks in a semiconductor process according to the present invention includes: providing a semiconductor substrate having a front side and a back side; defining a device region and an alignment region; simultaneously etching trenches in the device region and the alignment region on the front side of the semiconductor substrate; filling a dielectric layer in the trenches of the alignment region; forming capping epitaxial layers in the device region and the alignment region; by controlling the trench width and the thickness of the capping epitaxial layer in the alignment region, the capping epitaxial layer is not completely closed above the dielectric layer; using the gap in the capping epitaxial layer as an alignment mark on the front side of the semiconductor substrate; and using the bottom of the dielectric layer as an alignment mark on the back side of the semiconductor substrate; and forming a semiconductor device in the device region.

[0029] The present invention will now be described in detail with reference to specific embodiments.

[0030] Example 1

[0031] Figures 2-8 This invention illustrates a preferred embodiment of a method for forming alignment marks in a semiconductor process.

[0032] like Figure 2As shown, a semiconductor substrate 100 is provided, having a front side 100c and a back side 100d, defining a device region 100A and an alignment region 100B (separated by dashed lines). From the front side 100c of the semiconductor substrate 100, trenches 102 are simultaneously etched in both the device region 100A and the alignment region 100B using a hard mask 101. Preferably, the hard mask 101 is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0033] like Figure 3 , Figure 4 As shown, an embedded epitaxial layer 103 is formed in the trench 102 of the device region 100A and the alignment region 100B, respectively. The embedded epitaxial layer 103 and the hard mask 101 are planarized sequentially by chemical mechanical polishing and then stopped on the surface of the semiconductor substrate 100.

[0034] Preferably, the width WB of the trench 102 in the alignment region 100B is 0.2 micrometers to 5 micrometers larger than the width WA of the trench 102 in the device region 100A, so that when the trench 102 in the device region 100A is filled by the embedded epitaxial layer 103, the trench 102 in the alignment region 100B is not filled by the embedded epitaxial layer 103.

[0035] like Figure 5 , Figure 6 As shown, dielectric layers 108 are formed in device region 100A and alignment region 100B, respectively, and the dielectric layers 108 are planarized by chemical mechanical polishing and then stopped on the surface of semiconductor substrate 100.

[0036] Preferably, the dielectric layer 108 is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the dielectric layer 108 is formed by at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0037] Preferably, the trench 102 of the alignment area 100B is elongated and narrow, with a width WB not exceeding 8 micrometers, to avoid large, deep trenches from causing excessive photoresist residue at the bottom of the trench and being ejected during spin coating, forming a photoresist tail, affecting process accuracy, and thus affecting alignment signal accuracy.

[0038] like Figure 7 , Figure 8As shown, after forming the dielectric layer 108, a cap epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively. By controlling the width WB of the trench 102 in the alignment region 100B and the thickness of the cap epitaxial layer 105, the cap epitaxial layer 105 is not completely closed above the dielectric layer 108. Even after the cap epitaxial layer 105 is planarized, there is still a gap 110. The gap does not need to be too deep, so as not to cause photoresist residue in the gap in subsequent processes. In the subsequent process (not shown), a semiconductor device is formed in the device region 100A.

[0039] In this embodiment, the notch 110 of the cap epitaxial layer 105 is used as an alignment mark on the front side of the semiconductor substrate. During the front side process, the notch shape of the cap epitaxial layer 105 can be obtained by visible light as a front side alignment signal, which is clear and highly accurate. The bottom of the dielectric layer 108 is used as an alignment mark on the back side of the semiconductor substrate. During the back side process, the signal difference between the dielectric layer 108 and the substrate 100 is obtained by infrared light as a back side alignment signal. After the back side of the substrate is thinned, the bottom of the dielectric layer 108 is exposed on the back side of the substrate (preferably, the trench width of the alignment area is greater than the trench width of the device area, and the trench depth of the alignment area is greater than the trench depth of the device area. When the back side of the semiconductor substrate is thinned, the dielectric layer 108 can be used as a stop layer for the back side thinning process) or is close to the back side. The back side alignment signal is clear and is less affected by the substrate distortion caused by the thinning process. Therefore, it can avoid the attenuation or disappearance of alignment signals caused by the planarization process after epitaxy, and does not require additional photolithography steps, so it will not affect the alignment error. At the same time, it ensures the clarity and accuracy of the front and back alignment signals, and improves the reliability of the process.

[0040] Furthermore, the alignment mark formation method of this embodiment can be applied to semiconductor processes that require back-side processing, such as back-illuminated image sensor processes. Preferably, the depth H of the trench 102 in the alignment region 100B is 1.5 micrometers to 5 micrometers.

[0041] Example 2

[0042] Figures 9-15 This invention illustrates another preferred embodiment of the method for forming alignment marks in the semiconductor process of the present invention.

[0043] like Figure 9As shown, a semiconductor substrate 200 is provided, having a front side 200c and a back side 200d, defining a device region 200A and an alignment region 200B (separated by dashed lines). From the front side 200c of the semiconductor substrate 200, trenches 202 are simultaneously etched in both the device region 200A and the alignment region 200B using a hard mask 201. Preferably, the hard mask 201 is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0044] like Figure 10 , Figure 11 As shown, a first dielectric layer 206 and a polysilicon layer 207 are sequentially formed in the trenches 202 of device region 200A and alignment region 200B, respectively. The polysilicon layer 207 and the hard mask 201 are then planarized sequentially by chemical mechanical polishing, stopping at the surface of the semiconductor substrate 200. Depending on process requirements, an embedded epitaxial layer (not shown) may be formed before forming the first dielectric layer 206 in the trenches 202 of device region 200A and alignment region 200B.

[0045] Preferably, the width WB of the trench 202 in the alignment region 200B is 0.2 micrometers to 5 micrometers larger than the width WA of the trench 202 in the device region 200A, so that when the trench 202 in the device region 200A is filled with the polysilicon layer 207, the trench 202 in the alignment region 200B is not filled with the polysilicon layer 207.

[0046] like Figure 12 , Figure 13 As shown, a second dielectric layer 208 is formed in device region 200A and alignment region 200B respectively, and the second dielectric layer 208 is planarized by chemical mechanical polishing and stops on the surface of semiconductor substrate 200.

[0047] Preferably, the material of the first dielectric layer 206 and the second dielectric layer 208 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the formation process of the first dielectric layer 206 and the second dielectric layer 208 includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0048] Preferably, the trench 202 of the alignment area 200B is elongated and narrow, with a width WB not exceeding 8 micrometers, to avoid large, deep trenches from causing excessive photoresist residue at the bottom of the trench and being ejected during spin coating, forming a photoresist tail, affecting process accuracy, and thus affecting alignment signal accuracy.

[0049] like Figure 14 , Figure 15As shown, after forming the second dielectric layer 208, a cap epitaxial layer 205 is formed in the device region 200A and the alignment region 200B, respectively. By controlling the width WB of the trench 202 in the alignment region 200B and the thickness of the cap epitaxial layer 205, the cap epitaxial layer 205 is not completely closed above the second dielectric layer 208. Even after the cap epitaxial layer 205 is planarized, there is still a gap 210. The gap does not need to be too deep, so as not to cause photoresist residue in the gap in subsequent processes. In the subsequent process (not shown), a semiconductor device is formed in the device region 200A.

[0050] In this embodiment, the notch 210 of the cap epitaxial layer 205 is used as an alignment mark on the front side of the semiconductor substrate. During the front-side process, the notch shape of the cap epitaxial layer 205 can be obtained by visible light as a front-side alignment signal, which is clear and highly accurate. The bottom of the first dielectric layer 206 or the second dielectric layer 208 is used as an alignment mark on the back side of the semiconductor substrate. During the back-side process, the signal difference between the first dielectric layer 206 or the second dielectric layer 208 and the substrate 200 is obtained by infrared light as a back-side alignment signal. After the back side of the substrate is thinned, the bottom of the first dielectric layer 206 or the second dielectric layer 208 is exposed on the back side of the substrate (preferably, the trench width of the alignment area is greater than the trench width of the device area, and the trench depth of the alignment area is greater than the trench depth of the device area. When the back side of the semiconductor substrate is thinned, the first dielectric layer 206 or the second dielectric layer 208 can be used as a stop layer for the back-side thinning process) or is close to the back side. The back-side alignment signal is clear and is less affected by the substrate distortion caused by the thinning process. Therefore, it can avoid the attenuation or disappearance of alignment signals caused by the planarization process after epitaxy, and does not require additional photolithography steps, so it will not affect the alignment error. At the same time, it ensures the clarity and accuracy of the front and back alignment signals, and improves the reliability of the process.

[0051] Furthermore, the alignment mark formation method of this embodiment can be applied to semiconductor processes that require back-side processing, such as back-illuminated image sensor processes. Preferably, the depth H of the trench 202 in the alignment region 200B is 1.5 micrometers to 5 micrometers.

[0052] Example 3

[0053] Figures 16-22 This illustrates yet another preferred embodiment of the method for forming alignment marks in the semiconductor process of the present invention.

[0054] like Figure 16As shown, a semiconductor substrate 300 is provided, having a front side 300c and a back side 300d, defining a device region 300A and an alignment region 300B (separated by dashed lines). From the front side 300c of the semiconductor substrate 300, trenches 302 are simultaneously etched in both the device region 300A and the alignment region 300B using a hard mask 301. Preferably, the hard mask 301 is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0055] like Figure 17 , Figure 18 As shown, a first dielectric layer 306 and a polysilicon layer 307 are sequentially formed in the trenches 302 of device region 300A and alignment region 300B, respectively. Then, the polysilicon layer 307 in the trench 302 of alignment region 300B and the polysilicon layer 307 above the trench 302 of device region 300A are removed. Depending on process requirements, an embedded epitaxial layer (not shown) may be formed before forming the first dielectric layer 306 in the trenches 302 of device region 300A and alignment region 300B.

[0056] Preferably, the width WB of the trench 302 in the alignment region 300B is 0.2 micrometers to 5 micrometers larger than the width WA of the trench 302 in the device region 300A, so that when the trench 302 in the device region 300A is filled with the polysilicon layer 307, the trench 302 in the alignment region 300B is not filled with the polysilicon layer 307.

[0057] like Figure 19 , Figure 20 As shown, a second dielectric layer 308 is formed in device region 300A and alignment region 300B, respectively, and the second dielectric layer 308 and hard mask 301 are planarized by chemical mechanical polishing and then stopped on the surface of semiconductor substrate 300.

[0058] Preferably, the material of the first dielectric layer 306 and the second dielectric layer 308 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the formation process of the first dielectric layer 306 and the second dielectric layer 308 includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0059] Preferably, the trench 302 of the alignment area 300B is elongated and narrow, with a width WB not exceeding 8 micrometers, to avoid large, deep trenches from causing excessive photoresist residue at the bottom of the trench and being ejected during spin coating, forming a photoresist tail, affecting process accuracy, and thus affecting alignment signal accuracy.

[0060] like Figure 21 , Figure 22As shown, after forming the second dielectric layer 308, a cap epitaxial layer 305 is formed in the device region 300A and the alignment region 300B, respectively. By controlling the width WB of the trench 302 in the alignment region 300B and the thickness of the cap epitaxial layer 305, the cap epitaxial layer 305 is not completely closed above the second dielectric layer 308. Even after the cap epitaxial layer 305 is planarized, there is still a gap 310. The gap does not need to be too deep, so as not to cause photoresist residue in the gap in subsequent processes. In the subsequent process (not shown), a semiconductor device is formed in the device region 300A.

[0061] In this embodiment, the notch 310 of the cap epitaxial layer 305 is used as an alignment mark on the front side of the semiconductor substrate. During the front side process, the notch shape of the cap epitaxial layer 305 can be obtained by visible light as a front side alignment signal, which is clear and highly accurate. The bottom of the first dielectric layer 306 or the second dielectric layer 308 is used as an alignment mark on the back side of the semiconductor substrate. During the back side process, the signal difference between the first dielectric layer 306 or the second dielectric layer 308 and the substrate 300 is obtained by infrared light as a back side alignment signal. After the back side of the substrate is thinned, the bottom of the first dielectric layer 306 or the second dielectric layer 308 is exposed on the back side of the substrate (preferably, the trench width of the alignment area is greater than the trench width of the device area, and the trench depth of the alignment area is greater than the trench depth of the device area. When the back side of the semiconductor substrate is thinned, the first dielectric layer 306 or the second dielectric layer 308 can be used as a stop layer for the back side thinning process) or is close to the back side. The back side alignment signal is clear and is less affected by the substrate distortion caused by the thinning process. Therefore, it can avoid the attenuation or disappearance of alignment signals caused by the planarization process after epitaxy, and does not require additional photolithography steps, so it will not affect the alignment error. At the same time, it ensures the clarity and accuracy of the front and back alignment signals, and improves the reliability of the process.

[0062] Furthermore, the alignment mark formation method of this embodiment can be applied to semiconductor processes that require back-side processing, such as back-illuminated image sensor processes. Preferably, the depth H of the trench 302 in the alignment region 300B is 1.5 micrometers to 5 micrometers.

[0063] In summary, the method for forming alignment marks in the semiconductor process of the present invention involves simultaneously etching trenches in the device region and the alignment region. After filling the trenches in the alignment region with a dielectric layer, a cap epitaxial layer is formed in both the device region and the alignment region. By controlling the trench width and the thickness of the cap epitaxial layer in the alignment region, the cap epitaxial layer is not completely closed above the dielectric layer. The gap in the cap epitaxial layer is used as the alignment mark on the front side of the semiconductor substrate, and the bottom of the dielectric layer is used as the alignment mark on the back side of the semiconductor substrate. This method avoids the attenuation or disappearance of alignment signals caused by the planarization process after epitaxy, and does not increase alignment errors. At the same time, it ensures the clarity and accuracy of the front and back alignment signals, thereby improving process reliability.

[0064] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming alignment marks in a semiconductor process, characterized in that, include: Provides a semiconductor substrate with a front and a back side, defining the device area and alignment area; Trenches are formed simultaneously by etching the device area and alignment area on the front side of the semiconductor substrate; A dielectric layer is filled into the trench in the alignment area, and the device area and alignment area are planarized by chemical mechanical polishing; A capped epitaxial layer is formed in the device region and the alignment region. By controlling the trench width of the alignment region and the thickness of the capped epitaxial layer, the capped epitaxial layer is not completely closed above the dielectric layer. The gap in the capped epitaxial layer is used as an alignment mark on the front side of the semiconductor substrate, and the bottom of the dielectric layer located below the capped epitaxial layer is used as an alignment mark on the back side of the semiconductor substrate. Semiconductor devices are formed in the device region.

2. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The step of filling the trench in the alignment region with a dielectric layer includes: forming an embedded epitaxial layer in the trenches of the device region and the alignment region respectively; when the trench in the device region is filled with the embedded epitaxial layer, the trench in the alignment region is not filled with the embedded epitaxial layer; and filling the trench in the alignment region with a dielectric layer.

3. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The step of filling the trench in the alignment region with a dielectric layer includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively; when the trench in the device region is filled with the polysilicon layer, the trench in the alignment region is not filled with the polysilicon layer; and filling the trench in the alignment region with a second dielectric layer.

4. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The step of filling the trench in the alignment region with a dielectric layer includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region, respectively; removing the polysilicon layer in the trench of the alignment region; and filling the trench in the alignment region with a second dielectric layer.

5. The method for forming alignment marks in a semiconductor process as described in claim 3 or 4, characterized in that, Before the step of forming a first dielectric layer in the trenches of the device region and the alignment region, the method further includes: forming an embedded epitaxial layer in the trenches of the device region and the alignment region.

6. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The dielectric layer is made of at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

7. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The process for forming the dielectric layer includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

8. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The method for forming alignment marks is applied in back-illuminated image sensor technology.

9. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, When thinning the back side of the semiconductor substrate, the process stops at the bottom of the dielectric layer.

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