Semiconductor devices having electrical components built into circuit boards

Abstract

A semiconductor device (10) comprises: a substrate body (12) having a first surface (12a) and a second surface (12b); an electrical component (21, 22, 31, 32) arranged in the substrate body; a first terminal (42) and a second terminal (40) arranged on the first surface or the second surface; a first inner conductor pattern (64) arranged in a first circuit layer (L2) between the electrical component and the first surface and electrically connected to the first terminal and the electrical component; and a second inner conductor pattern (67) arranged in a second circuit layer (L5) between the electrical component and the second surface and electrically connected to the second terminal and the electrical component. The first inner conductor pattern and the second inner conductor pattern are at least partially opposite to each other within the substrate body.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having electrical components built into a circuit board. Background Art

[0002] Patent Document 1 discloses a semiconductor device. The semiconductor device includes a substrate, an electrical component disposed within the substrate, a first conductor pattern disposed on the upper surface of the substrate, and a second conductor pattern disposed on the lower surface of the substrate. The first conductor pattern is connected to the electrical component from above via a plurality of vias, and the second conductor pattern is connected to the electrical component from below via a plurality of vias. The first and second conductor patterns serve as current paths for current flowing through the electrical component.

[0003] Prior art literature

[0004] [Patent Document]

[0005] [Patent Document 1] U.S. Patent No.: 10229895. Summary of the Invention

[0006] In semiconductor devices, reducing losses in current paths requires reducing the inductance of the current paths. Connecting two or more current paths in parallel to electrical components in opposite directions is effective for reducing this inductance. However, when two current paths are arranged on the upper and lower surfaces of a substrate, as in conceivable semiconductor devices, the full benefits of the parallel arrangement of the two current paths are difficult to achieve due to the distance between them.

[0007] In view of the above circumstances, the present disclosure provides a technology capable of reducing the inductance of a current path in a semiconductor device having built-in electric components on a circuit board.

[0008] The semiconductor device disclosed in the present disclosure includes: a substrate body having a first surface and a second surface; an electrical component arranged in the substrate body; a first terminal and a second terminal arranged on the first surface or the second surface; a first circuit layer arranged between the electrical component and the first surface; a first inner conductor pattern arranged in the first circuit layer and electrically connected to the first terminal and the electrical component; a second circuit layer arranged between the electrical component and the second surface; and a second inner conductor pattern arranged in the second circuit layer and electrically connected to the second terminal and the electrical component. The first inner conductor pattern and the second inner conductor pattern are at least partially opposite to each other within the substrate body.

[0009] In the above configuration, the first inner conductor pattern and the second inner conductor pattern serve as two current paths connected to the electrical component. Since the first inner conductor pattern and the second inner conductor pattern are both arranged in the circuit layer of the substrate body, the distance between the first inner conductor pattern and the second inner conductor pattern is relatively small. As a result, the two current paths connected to the electrical component can be established in parallel in opposite directions with a relatively close positional relationship. In addition, the first inner conductor pattern is arranged between the first surface of the substrate body and the electrical component, and the second inner conductor pattern is arranged between the second surface of the substrate body and the electrical component. When the first inner conductor pattern and the second inner conductor pattern are distributed on both sides of the electrical component in this way, the structure of the substrate body can be designed symmetrically with respect to the thickness direction, and non-uniform thermal deformation of the substrate body, such as corrugation and warping, can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent through the following detailed description with reference to the accompanying drawings. In the accompanying drawings:

[0011] Figure 1 is a plan view showing the semiconductor device of the first embodiment;

[0012] Figure 2 is a circuit diagram showing a circuit structure of a semiconductor device according to a first embodiment;

[0013] Figure 3 It is along Figure 1 sectional view taken along line III-III in FIG, and for the sake of clarity, the hatching of the substrate body is omitted, and further, some overlapping configurations are illustrated by intentionally changing their positions;

[0014] Figure 4 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment;

[0015] Figure 5 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment;

[0016] Figure 6 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment;

[0017] Figure 7 is a cross-sectional view showing the structure of a semiconductor device of a fifth embodiment; and

[0018] Figure 8 is a cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION

[0019] In one embodiment of the present disclosure, semiconductor device 10 may include a third inner conductor pattern and first connecting vias 74, 78. The third inner conductor pattern is disposed in a circuit layer within the same depth range as the electrical component. The first connecting vias 74, 78 electrically connect one of the first inner conductor pattern and the second inner conductor pattern to the third inner conductor pattern. In this case, the third inner conductor pattern may at least partially oppose the other of the first and second inner conductor patterns within the substrate body. With this configuration, the third inner conductor pattern serves as the same current path as the first or second inner conductor pattern, allowing the two current paths connected to the electrical component to be positioned closer to each other and arranged parallel to each other.

[0020] In the above embodiment, the semiconductor device may include a fourth inner conductor pattern and a second connection via 77, the fourth inner conductor pattern being arranged within the same depth range as the electrical component and at a different depth than the third inner conductor pattern. The second connection via 77 electrically connects the third and fourth inner conductor patterns. In this case, the fourth inner conductor pattern may at least partially oppose the other of the first and second inner conductor patterns within the substrate body. With this configuration, in addition to the third inner conductor pattern, the fourth inner conductor pattern also serves as the same current path as the first or second inner conductor pattern. Consequently, two current paths connected to the electrical component can be established in parallel with each other in a closer positional relationship.

[0021] Alternatively, the semiconductor device may include a third connection via, replacing the second connection, electrically connecting the other of the first and second inner conductor patterns to the fourth inner conductor pattern. With this configuration, the third and fourth inner conductor patterns, which are located close to each other, can function as two current paths connected to the electrical component. Consequently, the two current paths connected to the electrical component can be established in parallel with each other in a closer positional relationship.

[0022] In one embodiment of the present disclosure, at least one of the thickness TH of the first inner conductor pattern and the thickness TH of the second inner conductor pattern can be greater than the thickness of the other inner conductor patterns in the substrate body. This configuration can achieve the desired effect of reducing inductance by increasing the cross-sectional area of at least one of the two current paths connected to the electrical component. Furthermore, by increasing the thickness of the inner conductor pattern, it is possible to achieve a desired cooling effect on the electrical component by improving thermal conductivity.

[0023] In one embodiment of the present disclosure, at least one of the first inner conductor pattern and the second inner conductor pattern may have an opening 67a in the region facing the electrical component. In the region where the electrical component is inserted between the two current paths, the effect of establishing two parallel current paths can be reduced. Therefore, by eliminating the current path in the region facing the electrical component, more current can be concentrated in other portions where the parallel establishment effect is desired.

[0024] In one embodiment of the present disclosure, the semiconductor device may further include a surface electrical component 52 disposed on the first surface and controlling the operation of the electrical component. According to the configuration of the present disclosure, it is possible to suppress temperature increases in the semiconductor device by reducing losses in the current path. Therefore, even when the surface electrical component is disposed on the first surface of the substrate body, it is possible to avoid overheating of the surface electrical component.

[0025] In one embodiment of the present disclosure, an electrical component may include power semiconductor devices 21, 22 and heat sinks 31, 32 to which the power semiconductor elements are bonded. Because relatively large currents flow through power semiconductor devices, it is highly desirable to reduce the impedance in the current path. The structure disclosed herein may be applicable to semiconductor devices including such power semiconductor devices.

[0026] (Example 1)

[0027] The semiconductor device 10 of the first embodiment will be described with reference to the accompanying drawings. The semiconductor device 10 of this embodiment is used, for example, in a power control unit of an electric vehicle, and can form a part of a power conversion circuit for power conversion between a power source and a driving motor. The electric vehicle in this embodiment broadly refers to a vehicle having a motor for driving wheels, and for example, an electric vehicle charged by external power, a hybrid vehicle having an engine in addition to a motor, a fuel cell vehicle having a fuel cell as a power source, etc. However, the application of the semiconductor device 10 according to this embodiment may not be limited to electric vehicles, and can be applied to various electrical equipment.

[0028] like Figures 1 to 3 As shown, the semiconductor device 10 includes a substrate body 12, two semiconductor elements 21 and 22, and two heat dissipation plates 31 and 32. The substrate body 12 has a plate-like or sheet-like shape. The substrate body 12 has an upper surface 12a and a lower surface 12b. The lower surface 12b is arranged on the side opposite to the upper surface 12a. The substrate body 12 is made of an insulator such as epoxy resin or other resin material. The substrate body 12 includes an upper layer 14, an intermediate layer 16, and a lower layer 18 in order from the upper surface 12a to the lower surface 12b. The upper layer 14 is a layer including the upper surface 12a of the substrate body 12. The lower layer 18 is a layer including the lower surface 12b of the substrate body 12. The intermediate layer 16 is a layer arranged between the upper layer 14 and the lower layer 18.

[0029] The X and Y directions in the drawings are parallel to the upper surface 12a and lower surface 12b of the substrate body 12 and are perpendicular to each other. The Z direction is perpendicular to the upper surface 12a and lower surface 12b of the substrate body 12 and is perpendicular to both the X and Y directions. That is, the upper layer 14, the intermediate layer 16, and the lower layer 18 are stacked along the Z direction.

[0030] The semiconductor elements 21 and 22 and the heat sinks 31 and 32 are electrical components that form part of the circuit in the semiconductor device 10, and are a group of electrical components that are electrically connected to each other within the substrate body 12. The two semiconductor elements 21 and 22 are arranged in the middle layer 16 of the substrate body 12 together with the two heat sinks 31 and 32. Each of the semiconductor elements 21 and 22 is a power semiconductor element, in particular a switching element. The switching element can be, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor elements 21 to 22 have upper surface electrodes 21a to 22a and lower surface electrodes 21b to 22b, respectively, and conduct electricity or block electricity between the corresponding upper surface electrodes 21a to 22a and the corresponding lower surface electrodes 21b to 22b, respectively.

[0031] For example, the two semiconductor elements 21 and 22 include a first semiconductor element 21 and a second semiconductor element 22. The first semiconductor element 21 and the second semiconductor element 22 are electrically connected in series within the substrate body 12. As described above, the two semiconductor elements 21 and 22 are switching elements such as IGBTs or MOSFETs. The semiconductor device 10 of this embodiment can form a part of an inverter circuit or a DC-DC converter circuit, for example. The number of semiconductor elements 21 and 22 is not limited to two. In addition, the semiconductor device 10 can include at least one other electrical component instead of the semiconductor elements 21 and 22 and the heat sinks 31 and 32.

[0032] The two heat sinks 31 and 32 each have a plate-like shape and are arranged parallel to the substrate body 12. Each heat sink 31, 32 is made of a conductor such as copper or other metal. For example, the two heat sinks 31 and 32 are arranged along the X direction. The two heat sinks 31 and 32 include a first heat sink 31 and a second heat sink 32. The first semiconductor element 21 is arranged on the first heat sink 31, and the lower surface electrode 21b of the first semiconductor element 21 is electrically connected to the first heat sink 31. Similarly, the second semiconductor element 22 is arranged on the second heat sink 32, and the lower surface electrodes 21b and 22b of the second semiconductor element 22 are electrically connected to the second heat sink 32.

[0033] The semiconductor device 10 includes a plurality of terminals 40, 42, and 44. These terminals 40, 42, and 44 are external connection terminals for connecting to an external circuit. The plurality of terminals 40, 42, and 44 are made of a conductor such as copper or other metal. For example, the plurality of terminals 40, 42, and 44 include a P terminal 40, an N terminal 42, and an O terminal 44. The plurality of terminals 40, 42, and 44 are arranged on the lower surface 12b of the substrate body 12. Here, some or all of the plurality of terminals 40, 42, and 44 can be arranged on the upper surface 12a of the substrate body 12.

[0034] The P-terminal 40 is electrically connected to the first heat sink 31 within the substrate body 12 and, through the first heat sink 31, is electrically connected to the lower surface electrode 21b of the first semiconductor element 21. The N-terminal 42 is electrically connected to the upper surface electrode 22a of the second semiconductor element 22 within the substrate body 12. The O-terminal 44 is electrically connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink 32 within the substrate body 12. In other words, the O-terminal 44 is electrically connected to each of the upper surface electrode 21a of the first semiconductor element 21 and the lower surface electrode 22b of the second semiconductor element 22. As a result, when the first semiconductor element 21 is turned on, the P-terminal 40 and the O-terminal 44 are electrically connected to each other. On the other hand, when the second semiconductor element 22 is turned on, the N-terminal 42 and the O-terminal 44 are electrically connected to each other.

[0035] The substrate body 12 has a plurality of circuit layers L1-L6 to form a multi-layer substrate structure. The plurality of circuit layers L1-L6 include a first circuit layer L1, a second circuit layer L2, a third circuit layer L3, a fourth circuit layer L4, a fifth circuit layer L5, and a sixth circuit layer L6. The first circuit layer L1 is arranged on the upper surface 12a of the substrate body 12. The second circuit layer L2 is arranged in the upper layer 14 of the substrate body 12. The third circuit layer L3 is arranged at the boundary between the upper layer 14 and the middle layer 16 of the substrate body 12. The fourth circuit layer L4 is arranged at the boundary between the middle layer 16 and the lower layer 18 of the substrate body 12. The fifth circuit layer L5 is arranged in the lower layer 18 of the substrate body 12. The sixth circuit layer L6 is arranged on the lower surface 12b of the substrate body 12.

[0036] The first circuit layer L1 includes a first conductor pattern 61. The first conductor pattern 61 is made of a conductor such as copper or another metal. The first conductor pattern 61 constitutes the control circuit 50 that controls the two semiconductor elements 21 and 22. Therefore, a plurality of surface electrical components 52 are mounted on the first conductor pattern 61. The plurality of surface electrical components 52 include, for example, a gate drive circuit that controls the switching of the semiconductor elements 21 and 22.

[0037] The first conductor pattern 61 mentioned here is a general term for one or more conductor patterns required to form the control circuit 50. That is, the first conductor pattern 61 can be a single conductor pattern or a combination of multiple conductor patterns. The same applies to the second conductor pattern 62 to the ninth conductor pattern 69 described below. Each of the second conductor pattern 62 to the ninth conductor pattern 69 is a general term for one or more conductor patterns having a common function and can be a single conductor pattern or a combination of multiple conductor patterns.

[0038] The second circuit layer L2 has a plurality of conductor patterns. Each conductor pattern is made of a conductor such as copper or other metal. The plurality of conductor patterns include a second conductor pattern 62, a third conductor pattern 63, and a fourth conductor pattern 64. Here, the plurality of conductor patterns are actually arranged on the same plane, but Figure 3 In order to make the illustration clear, the second conductor pattern 62 is intentionally shifted relative to the third conductor pattern 63 and the fourth conductor pattern 64.

[0039] The second conductor pattern 62 extends over a large portion of the second circuit layer L2 and is positioned facing the plurality of semiconductor elements 21 and 22. As a result, heat generated in the semiconductor elements 21 and 22 is diffused through the second conductor pattern 62 to a wide area of the substrate body 12. The second conductor pattern 62 also functions as a shielding layer, shielding against electromagnetic noise radiated from the semiconductor elements 21 and 22. Although not particularly limited, the second conductor pattern 62 may be connected to ground potential, thereby improving the function of the second conductor pattern 62 as a shielding layer.

[0040] The third conductor pattern 63 is connected to the O terminal 44 via a first via 71. Furthermore, the third conductor pattern 63 is connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink 32 via two second vias 72. The first vias 71 and the second vias 72 are made of a conductor such as copper or another metal. As a result, the two semiconductor elements 21 and 22 are electrically connected in series via the second conductor pattern 62 and are electrically connected to the O terminal 44 via the second conductor pattern 62. The third conductor pattern 63 forms part of the current path through which current flows through the semiconductor elements 21 and 22 and the heat sinks 31 and 32 as a set of electrical components.

[0041] The fourth conductor pattern 64 is connected to the upper surface electrode 22a of the second semiconductor element 22 through the third via 73. Furthermore, the fourth conductor pattern 64 is connected to the N terminal 42 through the fourth via. The third via 73 and the fourth via are made of a conductor such as copper or another metal. As a result, the upper surface electrode 22a of the second semiconductor element 22 is electrically connected to the N terminal 42 through the fourth conductor pattern 64.

[0042] Semiconductor elements 21 and 22 and heat sinks 31 and 32 are arranged in the third circuit layer L3 and the fourth circuit layer L4. The thickness of the heat sinks 31 and 32 is equal to the distance from the third circuit layer L3 to the fourth circuit layer L4. The semiconductor elements 21 and 22 arranged on the heat sinks 31 and 32 are arranged in the third circuit layer L3. In addition, the third circuit layer L3 and the fourth circuit layer L4 are respectively provided with a fifth conductor pattern 65 and a sixth conductor pattern 66. Each conductor pattern is made of a conductor such as copper or other metal. The use of the fifth conductor pattern 65 and the sixth conductor pattern 66 in this embodiment is not particularly limited. The fifth conductor pattern 65 and the sixth conductor pattern 66 can be connected to a ground potential, for example.

[0043] The fifth conductor pattern 65 of the third circuit layer L3 is arranged in the same depth range as the heat dissipation plates 31 and 32 in the substrate body 12. The depth range here refers to the range in the Z direction. Therefore, the fifth conductor pattern 65 has two openings 65a and 65b in accordance with the two heat dissipation plates 31 and 32. That is, in Figure 3 , the fifth conductor pattern 65 is separated and shown at the positions of the two heat dissipation plates 31 and 32 , but the actual fifth conductor pattern 65 is integrally formed in a wide range of the third circuit layer L3 .

[0044] Similarly, the sixth conductor pattern 66 of the fourth circuit layer L4 is arranged in the same depth range as the heat dissipation plates 31 and 32 in the substrate body 12. The depth range here refers to the range in the Z direction. Therefore, in line with the two heat dissipation plates 31 and 32, the sixth conductor pattern 66 is also provided with two openings 66a and 66b. That is, in Figure 3 , the sixth conductor pattern 66 is divided and shown at the positions of the two heat dissipation plates 31 and 32 , but the actual sixth conductor pattern 66 is integrally formed over a wide range of the fourth circuit layer L4 .

[0045] The fifth circuit layer L5 has a plurality of conductor patterns. Each conductor pattern is made of a conductor such as copper or other metal. The plurality of conductor patterns include a seventh conductor pattern 67 and an eighth conductor pattern 68. Here, the plurality of conductor patterns are actually arranged on the same plane, but Figure 3 In order to make the illustration clear, the seventh conductor pattern 67 is intentionally shifted relative to the eighth conductor pattern 68.

[0046] The seventh conductor pattern 67 is connected to the first heat sink 31 via a fifth via 75. Furthermore, the seventh conductor pattern 67 is connected to the P-terminal 40 via a sixth via 76. The fifth and sixth vias 75 and 76 are made of a conductor such as copper or another metal. As a result, the lower surface electrode 21b of the first semiconductor element 21 is electrically connected to the P-terminal 40 via the first heat sink 31 and the seventh conductor pattern 67. The seventh conductor pattern 67 forms part of a current path through which current flows through the semiconductor elements 21 and 22 and the heat sinks 31 and 32 as a set of electrical components.

[0047] The eighth conductor pattern 68 extends over most of the fifth circuit layer L5 and is positioned so as to face the plurality of semiconductor elements 21 and 22. As a result, heat generated in the semiconductor elements 21 and 22 is diffused across a wide area of the substrate body 12 via the eighth conductor pattern 68. The eighth conductor pattern 68 also functions as a shielding layer, shielding against electromagnetic noise radiated from the semiconductor elements 21 and 22. Although not particularly limited, the eighth conductor pattern 68 may be connected to ground potential, thereby improving the function of the eighth conductor pattern 68 as a shielding layer.

[0048] The sixth circuit layer L6 includes a ninth conductor pattern 69. This ninth conductor pattern 69 extends over a large portion of the sixth circuit layer L6 and faces the eighth conductor pattern 68 of the fifth circuit layer L5. The ninth conductor pattern 69 is made of a conductor such as copper or another metal. Heat generated in the semiconductor elements 21 and 22 is diffused across a wide area of the substrate body 12 not only through the eighth conductor pattern 68 but also through the ninth conductor pattern 69. The ninth conductor pattern 69 also functions as a shielding layer, shielding against electromagnetic noise radiated from the semiconductor elements 21 and 22. Similar to the eighth conductor pattern 68, the ninth conductor pattern 69 can be connected to ground potential, thereby improving its function as a shielding layer.

[0049] As described above, in the semiconductor device 10 of this embodiment, a set of electrical components, including the semiconductor elements 21 and 22 and the heat sinks 31 and 32, are arranged in the middle layer 16 of the substrate body 12. The P-terminal 40 and the N-terminal 42 are provided on the lower surface 12b of the substrate body 12. Within the substrate body 12, the fourth conductor pattern 64 is provided on the second circuit layer L2, which is arranged between the middle layer 16 and the upper surface 12a, and the seventh conductor pattern 67 is provided on the fifth circuit layer L5, which is arranged between the middle layer 16 and the lower surface 12b. The fourth conductor pattern 64 is electrically connected to the N-terminal 42 and the second semiconductor element 22 and serves as a current path for current flowing through the electrical components of the substrate body 12. The seventh conductor pattern 67 is also electrically connected to the P-terminal 40 and the first heat sink 31 and serves as a current path for current flowing through the electrical components of the substrate body 12 (i.e., the semiconductor elements 21 and 22 and the heat sinks 31 and 32). The fourth conductor pattern 64 and the seventh conductor pattern 67 at least partially oppose each other within the substrate body 12.

[0050] As described above, the semiconductor device 10 has a circuit structure in which two semiconductor elements 21 and 22 serving as switching elements are connected in series, forming part of an inverter circuit and a DC-DC converter circuit. In the inverter circuit and the DC-DC converter circuit, the two semiconductor elements 21 and 22 are controlled to alternately conduct, so that current flows in opposite directions through the fourth conductor pattern 64 and the seventh conductor pattern 67. At this time, the fourth conductor pattern 64 and the seventh conductor pattern 67 are at least partially opposite each other within the substrate body 12, and two current paths are established in parallel in opposite directions. As a result, the impedance in the two conductor patterns is reduced. In particular, the fourth conductor pattern 64 and the seventh conductor pattern 67 are respectively arranged in circuit layers L2 and L5 in the substrate body 12, and the distance between the two conductor patterns is relatively small. Therefore, the impedance in the two conductor patterns is effectively reduced.

[0051] Here, in order to bring the fourth conductor pattern 64 and the seventh conductor pattern 67 closer together, it is conceivable to arrange the two conductor patterns in the same upper layer 14 (or the same lower layer 18). However, if the structure is such that the two conductor patterns are arranged on the same side relative to the set of electrical components including the semiconductor elements 21 and 22 and the heat sinks 31 and 32, the structure of the substrate body 12 becomes asymmetrical in the thickness direction, which may cause uneven thermal deformation, such as warping and waviness of the substrate body 12. On the other hand, in the semiconductor device 10 of the present embodiment, the fourth conductor pattern 64 and the seventh conductor pattern 67 are arranged in the upper layer 14 and the lower layer 18 of the substrate body 12, respectively, and the semiconductor device 10 has a structure in which the semiconductor patterns are distributed on both sides of the set of electrical components. With this configuration, the structure of the substrate body 12 can be designed symmetrically with respect to the thickness direction, for example, by making the thickness of the upper layer 14 and the thickness of the lower layer 18 equal to each other, and uneven thermal deformation of the substrate body 12 can be suppressed.

[0052] The semiconductor device 10 according to the first embodiment is an embodiment of the technology disclosed in this specification, and the content of the technology is not particularly limited. The substrate body 12 in this embodiment is an example of a substrate in the present technology. The upper surface 12a and the lower surface 12b of the substrate body 12 in this embodiment are examples of the first surface and the second surface of the substrate body in the present technology, respectively. The first semiconductor element 21, the second semiconductor element 22, the first heat sink 31 and the second heat sink 32 in this embodiment are examples of electrical components in the present technology. The N terminal 42 and the P terminal 40 in this embodiment are examples of the first terminal and the second terminal in the present technology, respectively. The fourth conductor pattern 64 in this embodiment is an example of the first internal conductor pattern in the present technology. The seventh conductor pattern 67 in this embodiment is an example of the second internal conductor pattern in the present technology. The surface electrical component 52 in this embodiment is an example of a surface electrical component in the present technology.

[0053] (Example 2)

[0054] Will refer to Figure 4 A semiconductor device 110 according to a second embodiment will be described. In the semiconductor device 110 according to this embodiment, the fifth conductor pattern 65 of the third circuit layer L3 and the sixth conductor pattern 66 of the fourth circuit layer L4 are electrically connected to the fourth conductor pattern 64, which is different from the semiconductor device 10 according to the first embodiment. Hereinafter, the differences from the first embodiment will be mainly described, and configurations common to the first embodiment will be given the same reference numerals, and their description will be omitted.

[0055] The fifth conductor pattern 65 and the sixth conductor pattern 66 are provided in the third circuit layer L3 or the fourth circuit layer L4 and are arranged within the same depth range as the semiconductor elements 21 and 22 and the heat dissipation plates 31 and 32. The fifth conductor pattern 65 and the sixth conductor pattern 66 are connected to the fourth conductor pattern 64 through the fourth via. In addition, at least one seventh via is provided on the intermediate layer 16 of the substrate body 12. The seventh via is made of a conductor such as copper or other metal. As a result, the fifth conductor pattern 65 and the sixth conductor pattern 66 are electrically connected to each other. Figure 4 As clearly shown, the fifth and sixth conductor patterns 65 and 66 are closer to the seventh conductor pattern 67 than the fourth conductor pattern 64. That is, each distance from the fifth or sixth conductor pattern 65 or 66 to the seventh conductor pattern 67 is smaller than the distance from the fourth conductor pattern 64 to the seventh conductor pattern 67.

[0056] According to the configuration of this embodiment, the fifth and sixth conductor patterns 65 and 66 function as the same current paths as the fourth conductor pattern 64. The fifth and sixth conductor patterns 65 and 66, which function as current paths, are located close to the seventh conductor pattern 67, which is a current path established in parallel in opposite directions. As a result, the impedance in the semiconductor device 110 is further reduced.

[0057] The semiconductor device 110 according to the second embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The fifth conductor pattern 65 in this embodiment is an example of a third inner conductor pattern in this technology. The sixth conductor pattern 66 in this embodiment is an example of a fourth inner conductor pattern in this technology. The fourth via in this embodiment is an example of a first connecting via in this technology. The seventh via in this embodiment is an example of a second connecting via in this technology.

[0058] (Example 3)

[0059] Will refer to Figure 5 A semiconductor device 210 according to a third embodiment will now be described. The semiconductor device 210 according to this embodiment differs from the semiconductor devices 10 and 110 according to the first and second embodiments in that the fifth conductor pattern 65 of the third circuit layer L3 and the sixth conductor pattern 66 of the fourth circuit layer L4 are electrically connected to the seventh conductor pattern 67. Hereinafter, the differences from the first and second embodiments will be primarily described, and configurations common to the first and second embodiments will be given the same reference numerals, and their description will be omitted.

[0060] The semiconductor device 210 of this embodiment further includes at least one eighth via. The eighth via is arranged between the fourth circuit layer L4 and the fifth circuit layer L5, and connects the sixth conductor pattern 66 and the seventh conductor pattern 67 to each other. The eighth via is made of a conductor such as copper or other metal. As a result, the sixth conductor pattern 66 and the seventh conductor pattern 67 are electrically connected to each other. In addition, as in the second embodiment, the intermediate layer 16 of the substrate body 12 is provided with at least one seventh via. Figure 4 As clearly shown, the fifth and sixth conductor patterns 65 and 66 are closer to the fourth conductor pattern 64 than the seventh conductor pattern 67. That is, each distance from the fifth or sixth conductor pattern 65 or 66 to the fourth conductor pattern 64 is smaller than the distance from the seventh conductor pattern 67 to the fourth conductor pattern 64.

[0061] According to the configuration of this embodiment, the fifth and sixth conductor patterns 65 and 66 serve as the same current paths as the seventh conductor pattern 67. The fifth and sixth conductor patterns 65 and 66 serving as current paths are located close to the fourth conductor pattern 64, which is a current path established in parallel in opposite directions. As a result, the impedance in the semiconductor device 210 is further reduced.

[0062] The semiconductor device 210 according to the third embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The sixth conductor pattern 66 in this embodiment is an example of a third inner conductor pattern in this technology. The fifth conductor pattern 65 in this embodiment is an example of a fourth inner conductor pattern in this technology. The eighth via in this embodiment is an example of a first connecting via in this technology. The seventh via in this embodiment is an example of a second connecting via in this technology.

[0063] (Example 4)

[0064] Will refer to Figure 6 The semiconductor device 310 of the fourth embodiment will be described. In the semiconductor device 310 of this embodiment, the fifth conductor pattern 65 of the third circuit layer L3 is electrically connected to the fourth conductor pattern 64, and the sixth conductor pattern 66 of the fourth circuit layer L4 is electrically connected to the seventh conductor pattern 67. In these respects, the semiconductor device 310 of this embodiment differs from the semiconductor devices 10, 110, and 210 of Embodiments 1-3. Hereinafter, the differences from the first to third embodiments will be mainly described, and configurations common to the first to third embodiments will be given the same reference numerals, and their description will be omitted.

[0065] In the semiconductor device 310 of the present embodiment, the fifth conductor pattern 65 is connected to the fourth conductor pattern 64 through a fourth via. On the other hand, the sixth conductor pattern 66 is connected to the seventh conductor pattern 67 through at least one eighth via. The fifth conductor pattern 65 and the sixth conductor pattern 66 are arranged within the same depth range as the semiconductor elements 21 and 22 and the heat dissipation plates 31 and 32, and are close to each other.

[0066] According to the configuration of the present embodiment, the fifth conductor pattern 65 serves as the same current path as the fourth conductor pattern 64, and the sixth conductor pattern 66 serves as the same current path as the seventh conductor pattern 67. When the fifth conductor pattern 65 serving as the current path approaches the sixth conductor pattern 66 serving as the current path established in parallel in the opposite direction, the impedance in the semiconductor device 310 is further reduced.

[0067] The semiconductor device 310 according to the fourth embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The fifth conductor pattern 65 in this embodiment is an example of the third inner conductor pattern in this technology. The sixth conductor pattern 66 in this embodiment is an example of the fourth inner conductor pattern in this technology. The fourth via in this embodiment is an example of the first connecting via in this technology. The eighth via in this embodiment is an example of the third connecting via in this technology.

[0068] (Example 5)

[0069] Will refer to Figure 7 A semiconductor device 410 of a fifth embodiment will be described. In the semiconductor device 410 of this embodiment, the thickness TH of the seventh conductor pattern 67 is greater than the thicknesses of the other conductor patterns, and in this respect, the semiconductor device 410 is different from the semiconductor device 210 of the third embodiment. Hereinafter, the differences from the third embodiment will be mainly described, and the configurations common to the third embodiment will be given the same reference numerals, and their description will be omitted.

[0070] By increasing the thickness TH of the seventh conductor pattern 67, the cross-sectional area of the current path of the seventh conductor pattern 67 increases. Therefore, the effect of reducing inductance can be expected. In addition, by increasing the thickness of the seventh conductor pattern 67, the thermal conductivity of the seventh conductor pattern 67 is improved, and the cooling effect of the semiconductor elements 21 and 22 and the heat dissipation plates 31 and 32 can be expected.

[0071] The semiconductor device 310 according to the fifth embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. The thickness of the fourth conductor pattern 64 may be increased instead of or in addition to the seventh conductor pattern 67. In addition, the configuration according to this embodiment can be similarly adopted in other embodiments disclosed in this specification.

[0072] (Example 6)

[0073] Will refer to Figure 8 A semiconductor device 510 of the sixth embodiment will be described. In the semiconductor device 510 of this embodiment, an opening 67a is provided in the seventh conductor pattern 67, which is different from the semiconductor device 210 of the third embodiment. Hereinafter, the differences from the third embodiment will be mainly described, and the configurations common to the third embodiment will be given the same reference numerals, and their description will be omitted.

[0074] The opening 67a of the seventh conductor pattern 67 is provided in the range facing the second heat dissipation plate 32. In the range where the second heat dissipation plate 32 is interposed between the fourth conductor pattern 64 and the seventh conductor pattern 67 serving as the current path, the effect when the fourth conductor pattern 64 and the seventh conductor pattern 67 are established in parallel can be reduced. Therefore, in the range facing the second heat dissipation plate 32, by deleting the seventh conductor pattern 67, more current can be concentrated in other portions where the parallel path effect is expected.

[0075] The semiconductor device 510 according to the sixth embodiment is an embodiment of the technology disclosed in this specification, and the content of this technology is not particularly limited. A similar opening can be provided in the fourth conductor pattern 64 to replace or supplement the seventh conductor pattern 67. In addition, the configuration according to this embodiment can be similarly adopted in other embodiments disclosed in this specification.

[0076] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it should be understood that the present disclosure is not limited to these embodiments and configurations. The present disclosure is intended to cover various modifications and equivalent replacements. In addition, although there are various combinations and configurations, other combinations and configurations including more, less, or only a single element are also within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a substrate body having a first surface and a second surface; an electrical component disposed in the substrate body; a first terminal and a second terminal respectively disposed on the first surface or the second surface; a first inner conductor pattern arranged in a first circuit layer arranged between the electrical component and the first surface and electrically connected to the first terminal and the electrical component; and a second inner conductor pattern arranged in a second circuit layer arranged between the electrical component and the second surface and electrically connected to the second terminal and the electrical component, wherein: The first inner conductor pattern and the second inner conductor pattern are at least partially opposed to each other within the substrate body; The electrical component includes a first semiconductor element and a second semiconductor element arranged in a third circuit layer; the third circuit layer is disposed between the first inner conductor pattern and the second inner conductor pattern; and A current path of the first inner conductor pattern is parallel to and opposite to a current path of the second inner conductor pattern.

2. The semiconductor device according to claim 1, further comprising: a third inner conductor pattern arranged in a third circuit layer within the same depth range as that of the electrical component; and a first connecting via for electrically connecting one of the first inner conductor pattern and the second inner conductor pattern with the third inner conductor pattern, wherein: The third inner conductor pattern at least partially opposes the other of the first inner conductor pattern and the second inner conductor pattern within the substrate main body.

3. The semiconductor device according to claim 2, further comprising: a fourth inner conductor pattern arranged within the same depth range as the electrical component and arranged at a different depth from the third inner conductor pattern; and a second connecting via for electrically connecting the third inner conductor pattern and the fourth inner conductor pattern, wherein: The fourth inner conductor pattern at least partially opposes the other of the first and second inner conductor patterns within the substrate main body.

4. The semiconductor device according to claim 2, further comprising: a fourth inner conductor pattern arranged within the same depth range as the electrical component and arranged at a different depth from the third inner conductor pattern; and a third connecting via for electrically connecting the other of the first internal conductor pattern and the second internal conductor pattern with the fourth internal conductor pattern, wherein: The third inner conductor pattern and the fourth inner conductor pattern at least partially oppose each other within the substrate body.

5. The semiconductor device according to claim 1, wherein: At least one of a thickness of the first inner conductor pattern and a thickness of the second inner conductor pattern is larger than thicknesses of other inner conductor patterns in the substrate body.

6. The semiconductor device according to claim 1, wherein: At least one of the first inner conductor pattern and the second inner conductor pattern has an opening in a range facing the electric component.

7. The semiconductor device according to claim 1, further comprising: A surface electrical component is disposed on the first surface and controls the operation of the electrical component.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The electric component includes a power semiconductor element and a heat sink plate to which the power semiconductor element is bonded.

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