Semiconductor packaging method and semiconductor packaging structure

Abstract

The present disclosure provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging structure comprises: an encapsulation body having opposite first and second surfaces, the first surface having a plurality of recesses arranged at intervals; a plurality of packages arranged in the plurality of recesses one by one; a first wiring substrate arranged on the first surface, and each of the plurality of packages being electrically connected to the first wiring substrate; and a second wiring substrate arranged on the second surface and electrically connected to the first wiring substrate. The present disclosure can improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and semiconductor packaging structure. Background Technology

[0002] With the rapid development of science and technology, semiconductor devices have been used more and more widely in social production and daily life.

[0003] Currently, bare dies are often packaged to form packages, and multiple packages are then further packaged to form a PIP (Package in Package) structure. In a PIP structure, the multiple packages need to be electrically connected through a rewiring structure with fine wiring. However, this rewiring structure is prone to short circuits, reducing product yield. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor packaging method and semiconductor packaging structure that can improve product yield.

[0005] According to one aspect of this disclosure, a semiconductor package structure is provided, comprising:

[0006] An encapsulation having opposite first and second surfaces, the first surface having a plurality of recesses spaced apart;

[0007] Multiple packages are disposed in the multiple recesses in a corresponding manner;

[0008] A first wiring substrate is disposed on the first surface, and the plurality of the packaged components are electrically connected to the first wiring substrate;

[0009] The second wiring substrate is disposed on the second surface and electrically connected to the first wiring substrate.

[0010] Further, at least one of the packaged components includes:

[0011] A bare die has opposite front and back sides and a side connecting the front and back sides, with the front side of the bare die facing the first wiring substrate;

[0012] An encapsulation layer that at least covers the sides of the bare die;

[0013] A wiring structure is disposed on the front side of the bare die, and the solder pads on the front side of the bare die are electrically connected to the first wiring substrate in the wiring structure.

[0014] Furthermore, the front side of the die is provided with a protective layer, and the protective layer has openings that expose the solder pads on the front side of the die. The wiring structure includes:

[0015] A redistribution layer covers the protective layer and fills the opening to contact the solder pads on the front side of the die;

[0016] A conductive protrusion is disposed on the side of the redistribution layer facing away from the bare die, and the end of the conductive protrusion away from the redistribution layer is electrically connected to the first wiring substrate.

[0017] Furthermore, the encapsulation has a via penetrating the first surface and the second surface, and the semiconductor package structure includes:

[0018] A conductive structure is disposed within the via, and both the first wiring substrate and the second wiring substrate are electrically connected to the conductive structure, so that the first wiring substrate is electrically connected to the second wiring substrate.

[0019] Furthermore, the first wiring substrate has a first pre-wiring line, the second wiring substrate has a second pre-wiring line, the conductive structure and the plurality of the packaged components are electrically connected to the first pre-wiring line, and the second pre-wiring circuit is electrically connected to the conductive structure.

[0020] Furthermore, the semiconductor packaging structure further includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first wiring substrate and the first surface, and the second dielectric layer covers the second surface and surrounds the second wiring substrate; or

[0021] The first dielectric layer covers the first surface and surrounds the first wiring substrate, and the second dielectric layer covers the second wiring substrate and the second surface.

[0022] Furthermore, each of the package components includes a wiring structure on the side facing the first wiring substrate, the wiring structure being electrically connected to the first wiring substrate, and the wiring structure being electrically connected to the surface of the first wiring substrate and flush with the first surface.

[0023] According to one aspect of this disclosure, a semiconductor packaging method is provided, comprising:

[0024] An encapsulation body and multiple encapsulated components are formed. The encapsulation body has opposite first and second surfaces, and the first surface has multiple recesses spaced apart. The multiple encapsulated components are disposed in the multiple recesses in a one-to-one correspondence.

[0025] A first wiring substrate is disposed on the first surface, and the plurality of the package components are electrically connected to the first wiring substrate;

[0026] A second wiring substrate is disposed on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate.

[0027] Furthermore, at least one of the methods for forming the package includes:

[0028] A bare die is provided, the bare die having opposite front and back sides and a side connecting the front and back sides;

[0029] Form an encapsulation layer that at least covers the sides of the bare die;

[0030] A wiring structure is formed on the front side of the die, and the solder pads on the front side of the die are electrically connected to the wiring structure;

[0031] The bare die faces the first wiring substrate, and the wiring structure is electrically connected to the first wiring substrate.

[0032] Furthermore, the front side of the die is provided with a protective layer, and the protective layer has openings that expose the solder pads on the front side of the die. The wiring structure formed on the front side of the die includes:

[0033] A redistribution layer is formed to cover the protective layer, the redistribution layer filling the opening to contact the solder pads on the front side of the die;

[0034] A conductive protrusion is formed on the side of the redistribution layer opposite to the bare die, and one end of the conductive protrusion away from the redistribution layer is electrically connected to the first wiring substrate.

[0035] Furthermore, the encapsulation has a through-hole penetrating the first surface and the second surface, and a conductive structure is provided in the through-hole. Both the first wiring substrate and the second wiring substrate are electrically connected to the conductive structure, so that the first wiring substrate is electrically connected to the second wiring substrate.

[0036] Further, the first wiring substrate is disposed on the first surface including:

[0037] The first wiring substrate is tested, and the first wiring substrate that passes the test is disposed on the first surface; and / or

[0038] The second wiring substrate is disposed on the second surface including:

[0039] The second wiring substrate is tested, and the qualified second wiring substrate is placed on the second surface.

[0040] Furthermore, the semiconductor packaging method further includes:

[0041] A first dielectric layer and a second dielectric layer are formed, wherein the first dielectric layer covers the first wiring substrate and the first surface, and the second dielectric layer covers the second surface and surrounds the second wiring substrate; or

[0042] The first dielectric layer covers the first surface and surrounds the first wiring substrate, and the second dielectric layer covers the second wiring substrate and the second surface.

[0043] Further, forming a wiring structure on the front side of the bare die includes:

[0044] A redistribution layer is formed on the front side of the die, and the solder pads on the front side of the die are electrically connected to the redistribution layer;

[0045] Conductive protrusions are formed on the side of the redistribution layer opposite to the bare die, and the conductive protrusions and the redistribution layer constitute the wiring structure;

[0046] Forming an encapsulation includes:

[0047] Using the conductive protrusions as alignment marks, the package having the bare die is mounted on a first carrier plate, with the front side of the bare die facing the first carrier plate;

[0048] An encapsulation is formed covering the first carrier and the package, and the encapsulation forms the recess in a region corresponding to the package.

[0049] The semiconductor packaging method and semiconductor packaging structure disclosed herein include multiple packages disposed one-to-one in multiple recesses of an encapsulation body, so that the encapsulation body encapsulates multiple packages. Since multiple packages are electrically connected to a first wiring substrate, the multiple packages are electrically connected through the first wiring substrate, thereby solving the short circuit problem caused by the rewiring structure and improving product yield. At the same time, a second wiring substrate is disposed on the second surface of the encapsulation body and is electrically connected to the first wiring substrate, thereby realizing double-sided wiring of the packaging structure. Attached Figure Description

[0050] Figure 1 This is a flowchart of a semiconductor packaging method according to an embodiment of the present disclosure.

[0051] Figure 2 This is a schematic diagram of a silicon wafer according to an embodiment of this disclosure.

[0052] Figure 3 This is a schematic diagram of the semiconductor packaging method according to the present disclosure after the encapsulation layer has been formed.

[0053] Figure 4 This is a schematic diagram of the semiconductor packaging method according to the present disclosure after the wiring structure has been formed.

[0054] Figure 5 This is a schematic diagram of the semiconductor packaging method according to an embodiment of the present disclosure after the formation of an insulating material layer.

[0055] Figure 6This is a schematic diagram of the semiconductor packaging method according to the present disclosure after the encapsulation body has been formed.

[0056] Figure 7 This is a schematic diagram of the semiconductor packaging method according to an embodiment of the present disclosure after removing the first carrier plate.

[0057] Figure 8 This is a schematic diagram of the semiconductor packaging method according to an embodiment of the present disclosure after the first wiring substrate has been provided.

[0058] Figure 9 This is a schematic diagram of the semiconductor packaging method according to an embodiment of the present disclosure after the conductive structure has been formed.

[0059] Figure 10 This is a schematic diagram of the semiconductor packaging method according to an embodiment of the present disclosure after the second wiring substrate has been provided.

[0060] Figure 11 This is a schematic diagram of a semiconductor packaging method according to an embodiment of the present disclosure, in which multiple dies are arranged on a second substrate.

[0061] Figure 12 This is a schematic diagram of a semiconductor packaging method according to an embodiment of the present disclosure, in which multiple packages are arranged on a first substrate.

[0062] Explanation of reference numerals in the attached drawings: 1. Bare die; 2. Protective layer; 3. Rewiring layer; 4. Conductive protrusion; 5. Insulating material layer; 6. Encapsulation; 601. First surface; 602. Second surface; 7. First dielectric layer; 8. First wiring substrate; 9. Conductive structure; 10. Second wiring substrate; 11. Encapsulation layer; 12. Second dielectric layer; 13. First carrier board; 14. Second carrier board; 15. Solder pad; 16. Silicon wafer; 17. Opening; 18. Circuit lead; 100. Package. Detailed Implementation

[0063] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0064] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0065] This disclosure provides a semiconductor packaging method. For example... Figure 1 As shown, the semiconductor packaging method may include steps S100 to S120, wherein:

[0066] Step S100: Form an encapsulation body and a plurality of encapsulation components. The encapsulation body has a first surface and a second surface that are opposite to each other. The first surface has a plurality of recesses that are spaced apart. The plurality of encapsulation components are disposed in the plurality of recesses in a corresponding manner.

[0067] Step S110: A first wiring substrate is disposed on the first surface, and multiple packages are electrically connected to the first wiring substrate.

[0068] Step S120: A second wiring substrate is disposed on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate.

[0069] The semiconductor packaging method of this disclosure, such as Figure 10As shown, multiple packages 100 are disposed in multiple recesses of the encapsulation body 6 in a one-to-one correspondence, so that the encapsulation body 6 encapsulates multiple packages 100. Since multiple packages 100 are electrically connected to the first wiring substrate 8, the multiple packages 100 are electrically connected through the first wiring substrate 8, which solves the short circuit problem caused by the rewiring structure and improves the product yield. At the same time, the second wiring substrate 10 is disposed on the second surface 602 of the encapsulation body 6, and the second wiring substrate 10 is electrically connected to the first wiring substrate 8, thereby realizing double-sided wiring of the encapsulation structure. In addition, the second wiring substrate 10 and the first wiring substrate 8 are both prefabricated substrates, and their manufacturing process is carried out independently of the encapsulation process, saving the encapsulation time of the entire encapsulation process.

[0070] The steps of the semiconductor packaging method according to the present disclosure will be described in detail below:

[0071] In step S100, an encapsulation body and a plurality of encapsulation components are formed. The encapsulation body has a first surface and a second surface that are opposite to each other. The first surface has a plurality of recesses that are spaced apart. The plurality of encapsulation components are disposed in the plurality of recesses in a corresponding manner.

[0072] For example, step S100 may include steps S1000 to S1002, wherein:

[0073] Step S1000: Provide a bare die, which has opposite front and back sides and a side connecting the front and back sides.

[0074] like Figure 2 and Figure 3 As shown, the bare die 1 can be formed by dicing a silicon wafer 16. The silicon wafer 16 has an active surface. The active surface is provided with bonding pads 15. A protective layer 2 can be provided on the front side of the bare die 1. The protective layer 2 can be formed on the silicon wafer 16 before dicing. The protective layer 2 can have openings 17 that expose the bonding pads 15 of the bare die 1. The material of the protective layer 2 can be a molding compound, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties, and can be formed by lamination, spin coating, printing, molding, or other suitable methods.

[0075] Step S1001: Form an encapsulation layer that at least covers the sides of the die.

[0076] like Figure 3 As shown, before forming the encapsulation layer 11, the semiconductor packaging method of this embodiment may include: mounting a bare die 1 on a second carrier 14, with the front side of the bare die 1 facing the second carrier 14. The second carrier 14 can be a rigid carrier, such as a glass carrier, a stainless steel carrier, etc. A protective layer 2 disposed on the front side of the bare die 1 is attached to the second carrier 14. Figure 11As shown, the number of bare dies 1 mounted on the second carrier 14 can be multiple. During the arrangement of multiple bare dies 1 on the second carrier 14, the opening 17 of the protective layer 2 on the front side of the bare die 1 can serve as an alignment mark, allowing the bare dies 1 to be arranged more precisely on the second carrier 14 according to a predetermined arrangement position, thereby improving the packaging yield. The encapsulation layer 11 can cover the sides and back of the bare die 1, with the front side of the bare die 1 exposed. Of course, the encapsulation layer 11 can also only cover the sides of the bare die 1. The encapsulation layer 11 can be formed by injection molding, thermoforming, or other methods. The material of the encapsulation layer 11 can be resin, such as epoxy molding compound (EMC).

[0077] Step S1002: A wiring structure is formed on the front side of the die, and the solder pads on the front side of the die are electrically connected to the wiring structure.

[0078] like Figure 3 and Figure 4 As shown, before forming the wiring structure, this disclosure requires removing the second carrier board 14 to expose the front side of the bare die 1. Taking a protective layer 2 on the front side of the bare die 1 as an example, forming the wiring structure may include: forming a rewiring layer 3 covering the protective layer 2; the rewiring layer 3 filling the opening 17 of the protective layer 2 to contact the solder pads 15 on the front side of the bare die 1, so that the rewiring layer 3 is electrically connected to the solder pads 15 on the front side of the bare die 1; and forming a conductive protrusion 4 on the side of the rewiring layer 3 facing away from the bare die 1. One surface of the encapsulation layer 11 may be flush with the surface of the protective layer 2 facing away from the bare die 1, and the rewiring layer 3 may also partially cover the surface of the encapsulation layer 11 that is flush with the surface of the protective layer 2 facing away from the bare die 1. The rewiring layer 3 or the conductive protrusion 4 may be formed by metal sputtering, electrolytic plating, electrodeless plating, etc. In addition, as Figure 5 As shown, after forming the conductive protrusion 4, this disclosure can also form an insulating material layer 5. This insulating material layer 5 can cover the redistribution layer 3 and the encapsulation layer 11. The end face of the conductive protrusion 4 away from the redistribution layer 3 protrudes from the encapsulation layer 11, and the end face of the conductive protrusion 4 away from the redistribution layer 3 can be flush with the surface of the insulating material layer 5 away from the redistribution layer 3. Steps S1000 to S1002 described above can constitute a method for forming at least one of a plurality of packages 100. The number of packages 100 can be two, three, four, or more. The functions of the bare dies 1 in each package 100 can be different. A first encapsulation is performed using bare dies 1 with various functions to form an intermediate package structure, and each bare die 1 independently performs a redistribution process.

[0079] Step S1003: Using the aforementioned conductive protrusions as alignment marks, the package with the bare die is mounted on the first carrier plate, with the front side of the bare die inside the package facing the first carrier plate; an encapsulation body is formed covering the first carrier plate and the package, and a recess is formed in the area of ​​the encapsulation body corresponding to the package.

[0080] like Figure 6 As shown, the first carrier plate 13 can be a rigid carrier plate, such as a glass carrier plate or a stainless steel carrier plate. The end face of the conductive protrusion 4 furthest from the bare die 1 and the insulating material layer 5 are both attached to the first carrier plate 13. Using the conductive protrusion 4 as an alignment mark allows the package 100 to be more accurately positioned on the first carrier plate 13 according to a predetermined location, improving the package yield. Figure 12 As shown, this disclosure allows for the arrangement of multiple encapsulations 100 on a first carrier plate 13, with the multiple encapsulations 100 spaced apart. After forming the encapsulation, this disclosure may further include removing the first carrier plate 13. The surface of the encapsulation 6 facing the first carrier plate 13 is the first surface 601, and the surface of the encapsulation 6 facing away from the first carrier plate 13 is the second surface 602. The end face of the conductive protrusion 4 of each encapsulation 100 away from the redistribution layer 3 may be flush with the first surface 601. Furthermore, the encapsulation 6 can be formed by injection molding, thermoforming, or other methods. The material of the encapsulation 6 can be resin, such as epoxy molding compound (EMC).

[0081] In step S110, a first wiring substrate is disposed on the first surface, and multiple packages are electrically connected to the first wiring substrate.

[0082] like Figures 6 to 8As shown, before setting the first wiring substrate 8, this disclosure requires the removal of the aforementioned first carrier board 13. For example, step 110 may include: testing the first wiring substrate 8 and setting the tested and qualified first wiring substrate 8 on the first surface 601. Testing the wiring substrate before packaging avoids the use of known defective wiring substrates. The first wiring substrate 8 has a first pre-wiring line. Multiple packages 100 are electrically connected to the first pre-wiring line so that multiple packages 100 are electrically connected to the first wiring substrate 8. Specifically, the wiring structure of each package 100 is electrically connected to the first pre-wiring line. More specifically, the surface of the conductive protrusion 4 on each package 100 away from the redistribution layer 3 is electrically connected to the first pre-wiring line. The conductive protrusion 4 can be electrically connected to the first pre-wiring line by soldering. The surface of the wiring structure electrically connected to the first wiring substrate 8 is flush with the first surface 601 of the encapsulation body 6, that is, the surface of the conductive protrusion 4 away from the redistribution layer 3 is flush with the first surface 601 of the encapsulation body 6. The first wiring substrate 8 has complex multi-circuit circuits. These first wiring substrates 8 with complex multi-circuit circuits rewire multiple packages 100, improving the performance of the entire package structure. In addition, replacing the fine wiring in the rewire structure with the first wiring substrate 8 with complex multi-circuit circuits reduces the probability of short circuits, increases product yield, reduces process complexity, and forms a PIP package structure with complex circuits.

[0083] In step S120, a second wiring substrate is disposed on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate.

[0084] like Figures 8 to 10 As shown, before setting the second wiring substrate 10, the semiconductor packaging method of this disclosure may further include: forming vias penetrating the first surface 601 and the second surface 602 of the encapsulation 6; forming a conductive structure 9 within the vias, the conductive structure 9 being electrically connected to the first wiring substrate 8. The conductive structure 9 is electrically connected to a first pre-wiring line in the first wiring substrate 8. The material of the conductive structure 9 may be copper, but this disclosure does not impose any special limitations on this. For example, step 120 may include: testing the second wiring substrate 10 and setting the tested and qualified second wiring substrate 10 on the second surface 602. Testing the wiring substrate before packaging avoids the use of known defective wiring substrates. The second wiring substrate 10 is electrically connected to the conductive structure 9 within the vias, so that the second wiring substrate 10 is electrically connected to the first wiring substrate 8. The second wiring substrate 10 contains a second pre-wiring line, and the conductive structure 9 is electrically connected to the second pre-wiring circuit.

[0085] The semiconductor packaging method disclosed herein may further include:

[0086] Step S130: Form the first dielectric layer and the second dielectric layer.

[0087] like Figure 10 As shown, in one embodiment of this disclosure, the first dielectric layer 7 covers the first wiring substrate 8 and the first surface 601, and the second dielectric layer 12 covers the second surface 602 and surrounds the second wiring substrate 10. In another embodiment of this disclosure, the first dielectric layer 7 covers the first surface 601 and surrounds the first wiring substrate 8, and the second dielectric layer 12 covers the second wiring substrate 10 and the second surface 602. The material of the first dielectric layer 7 or the second dielectric layer 12 can be a molding compound, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties, and can be formed by lamination, spin coating, printing, molding, or other suitable methods. Furthermore, the semiconductor packaging method of this disclosure may also include forming a circuit lead 18 on the surface of the second wiring substrate 10 away from the encapsulation body 6, the circuit lead 18 being electrically connected to a second pre-wiring circuit in the second wiring substrate 10. The circuit lead 18 can be a solder structure, etc.

[0088] This disclosure also provides a semiconductor packaging structure. This semiconductor packaging structure can be fabricated using the semiconductor packaging method described in any of the above embodiments. For example... Figure 10 As shown, the semiconductor packaging structure may include an encapsulator 6, a package 100, a first wiring substrate 8, and a second wiring substrate 10, wherein:

[0089] The encapsulation body 6 has opposite first surfaces 601 and second surfaces 602. The first surface 601 has a plurality of recesses spaced apart. A plurality of package members 100 are disposed in the plurality of recesses in a corresponding manner. The first wiring substrate 8 is disposed on the first surface 601, and the plurality of package members 100 are electrically connected to the first wiring substrate 8. The second wiring substrate 10 is disposed on the second surface 602 and is electrically connected to the first wiring substrate 8.

[0090] At least one of the package components 100 includes a die 1, an encapsulation layer 11, and a wiring structure. The die 1 has opposite front and back sides and a side connecting the front and back sides, with the front side of the die 1 facing the first wiring substrate 8. The encapsulation layer 11 covers at least the side of the die 1. The wiring structure is disposed on the front side of the die 1, and the solder pads 15 on the front side of the die 1 are electrically connected to the first wiring substrate 8 in the wiring structure.

[0091] The die 1 has a protective layer 2 on its front side. The protective layer 2 has openings 17 that expose the solder pads 15 on the front side of the die 1. The wiring structure may include a redistribution layer 3 and conductive protrusions 4. The redistribution layer 3 covers the protective layer 2 and fills the openings 17 to contact the solder pads 15 on the front side of the die 1. The conductive protrusions 4 are located on the side of the redistribution layer 3 facing away from the die 1, and one end of the conductive protrusions 4 away from the redistribution layer 3 is electrically connected to the first wiring substrate 8.

[0092] The encapsulation 6 has a via penetrating the first surface 601 and the second surface 602. The semiconductor package structure may also include a conductive structure 9. The conductive structure 9 may be disposed within the via. Both the first wiring substrate 8 and the second wiring substrate 10 are electrically connected to the conductive structure 9, such that the first wiring substrate 8 is electrically connected to the second wiring substrate 10.

[0093] The first wiring substrate 8 has a first pre-wiring line, the second wiring substrate 10 has a second pre-wiring line, the conductive structure 9 and multiple packages 100 are electrically connected to the first pre-wiring line, and the second pre-wiring circuit is electrically connected to the conductive structure 9.

[0094] The semiconductor package structure further includes a first dielectric layer 7 and a second dielectric layer 12. The first dielectric layer 7 covers the first wiring substrate 8 and the first surface 601, and the second dielectric layer 12 covers the second surface 602 and surrounds the second wiring substrate 10. Of course, in other embodiments of this disclosure, the first dielectric layer 7 covers the first surface 601 and surrounds the first wiring substrate 8, and the second dielectric layer 12 covers the second wiring substrate 10 and the second surface 602.

[0095] Each package 100 includes a wiring structure on the side facing the first wiring substrate 8. The wiring structure is electrically connected to the first wiring substrate 8, and the surface of the first wiring substrate 8 is flush with the first surface 601.

[0096] The semiconductor packaging method and semiconductor packaging structure provided in this disclosure belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0097] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to a preferred embodiment, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A semiconductor packaging method, characterized in that, include: Forming an encapsulation body and a plurality of encapsulation components, the encapsulation body having opposite first and second surfaces, the first surface having a plurality of recesses spaced apart; Multiple packages are disposed in the multiple recesses in a corresponding manner; A first wiring substrate is disposed on the first surface, and the plurality of the package components are electrically connected to the first wiring substrate; A second wiring substrate is disposed on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate; Both the first wiring substrate and the second wiring substrate are prefabricated substrates; The formation of the encapsulation body and multiple packages includes: A bare die is provided, the bare die having opposite front and back sides and a side connecting the front and back sides; the front side of the bare die is provided with a protective layer, the protective layer having openings that expose the solder pads of the bare die; Using the opening in the protective layer on the front of the die as an alignment mark, the die is mounted on the second carrier plate according to the predetermined arrangement position. An encapsulation layer is formed that at least covers the sides of the bare die.

2. The semiconductor packaging method according to claim 1, characterized in that, After forming an encapsulation layer that at least covers the sides of the bare die, the formation of the encapsulation body and multiple packages further includes: A wiring structure is formed on the front side of the die, and the solder pads on the front side of the die are electrically connected to the wiring structure; The bare die faces the first wiring substrate, and the wiring structure is electrically connected to the first wiring substrate.

3. The semiconductor packaging method according to claim 2, characterized in that, Forming a wiring structure on the front side of the bare die includes: A redistribution layer is formed to cover the protective layer, the redistribution layer filling the opening to contact the solder pads on the front side of the die; A conductive protrusion is formed on the side of the redistribution layer opposite to the bare die, and one end of the conductive protrusion away from the redistribution layer is electrically connected to the first wiring substrate.

4. The semiconductor packaging method according to claim 1, characterized in that, The encapsulation has a through-hole penetrating the first surface and the second surface. A conductive structure is provided in the through-hole. Both the first wiring substrate and the second wiring substrate are electrically connected to the conductive structure, so that the first wiring substrate is electrically connected to the second wiring substrate.

5. The semiconductor packaging method according to claim 1, characterized in that, Depositing a first wiring substrate on the first surface includes: The first wiring substrate is tested, and the first wiring substrate that passes the test is disposed on the first surface; and / or The second wiring substrate is disposed on the second surface including: The second wiring substrate is tested, and the qualified second wiring substrate is placed on the second surface.

6. The semiconductor packaging method according to claim 1, characterized in that, The semiconductor packaging method further includes: A first dielectric layer and a second dielectric layer are formed, wherein the first dielectric layer covers the first wiring substrate and the first surface, and the second dielectric layer covers the second surface and surrounds the second wiring substrate; or The first dielectric layer covers the first surface and surrounds the first wiring substrate, and the second dielectric layer covers the second wiring substrate and the second surface.

7. The semiconductor packaging method according to claim 2, characterized in that, Forming a wiring structure on the front side of the bare die includes: A redistribution layer is formed on the front side of the die, and the solder pads on the front side of the die are electrically connected to the redistribution layer; Conductive protrusions are formed on the side of the redistribution layer opposite to the bare die, and the conductive protrusions and the redistribution layer constitute the wiring structure; Forming an encapsulation includes: Using the conductive protrusions as alignment marks, the package having the bare die is mounted on a first carrier plate, with the front side of the bare die facing the first carrier plate; An encapsulation is formed covering the first carrier and the package, and the encapsulation forms the recess in a region corresponding to the package.

8. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure is prepared by any one of the semiconductor packaging methods of claims 1 to 7, and the semiconductor packaging structure comprises: An encapsulation having opposite first and second surfaces, the first surface having a plurality of recesses spaced apart; Multiple packages are disposed in the multiple recesses in a corresponding manner; A first wiring substrate is disposed on the first surface, and the plurality of the packaged components are electrically connected to the first wiring substrate; The second wiring substrate is disposed on the second surface and electrically connected to the first wiring substrate.

9. The semiconductor packaging structure according to claim 8, characterized in that, At least one of the packaged components includes: A bare die has opposite front and back sides and a side connecting the front and back sides, with the front side of the bare die facing the first wiring substrate; An encapsulation layer that at least covers the sides of the bare die; A wiring structure is disposed on the front side of the bare die, and the solder pads on the front side of the bare die are electrically connected to the first wiring substrate in the wiring structure.

10. The semiconductor packaging structure according to claim 9, characterized in that, The die has a protective layer on its front side, and the protective layer has openings that expose the solder pads on the front side of the die. The wiring structure includes: A redistribution layer covers the protective layer and fills the opening to contact the solder pads on the front side of the die; A conductive protrusion is disposed on the side of the redistribution layer facing away from the bare die, and the end of the conductive protrusion away from the redistribution layer is electrically connected to the first wiring substrate.

11. The semiconductor packaging structure according to claim 8, characterized in that, The encapsulation has a through-hole penetrating the first surface and the second surface, and the semiconductor packaging structure further includes: A conductive structure is disposed within the via, and both the first wiring substrate and the second wiring substrate are electrically connected to the conductive structure, so that the first wiring substrate is electrically connected to the second wiring substrate.

12. The semiconductor packaging structure according to claim 11, characterized in that, The first wiring substrate has a first pre-wiring line, the second wiring substrate has a second pre-wiring line, the conductive structure and the plurality of the packaged components are electrically connected to the first pre-wiring line, and the second pre-wiring line is electrically connected to the conductive structure.

13. The semiconductor packaging structure according to claim 8, characterized in that, The semiconductor packaging structure further includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first wiring substrate and the first surface, and the second dielectric layer covers the second surface and surrounds the second wiring substrate; or The first dielectric layer covers the first surface and surrounds the first wiring substrate, and the second dielectric layer covers the second wiring substrate and the second surface.

14. The semiconductor packaging structure according to claim 8, characterized in that, Each of the aforementioned packages includes a wiring structure on the side facing the first wiring substrate. The wiring structure is electrically connected to the first wiring substrate, and the wiring structure is electrically connected to the surface of the first wiring substrate and is flush with the first surface.

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