Fan-out system package and method for integrated MIM capacitors

Abstract

The present invention relates to a fan-out system package and method for integrated MIM capacitors. It includes a base chip, a functional chipset, and a lead-out connection unit. The functional chips in the functional chipset are interconnected with the base chip and are plastic-sealed on the base chip through a plastic sealing layer. A MIM capacitor group is arranged in the plastic sealing layer, and the MIM capacitor group includes a plurality of MIM capacitors. The MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate. The first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer. The first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip. The lead-out connection unit is used to lead out the package formed by the base chip, the functional chipset, and the MIM capacitor group. The present invention effectively realizes the integration of a large capacitor system, is compatible with existing processes, reduces packaging costs, and is safe and reliable.

Description

Technical Field

[0001] The present invention relates to a fan-out system package and method, and in particular to a fan-out system package and method integrating MIM capacitors. Background Art

[0002] As the number of transistors and IO (input / output) ports in integrated circuits continues to increase, the traditional two-dimensional packaging structure can no longer meet the requirements of integration, and a higher-density three-dimensional stacked packaging structure is needed to achieve higher integration. TSV (Through Silicon Via) technology can improve the integration of integrated circuits, but TSV is difficult to implement, and the main technology is in the hands of a few companies, so the project span and technical feasibility are difficult.

[0003] Integrated circuits have an increasing demand for the capacity of power filter capacitors. Capacitors implemented on-chip are limited by the chip area, and it is difficult to increase the capacity. In existing systems, each module is packaged independently and finally connected to each other through a PCB (Printed Circuit Board) to form a system, resulting in a large size of the final system, which cannot meet the requirements of being short, small and thin.

[0004] In summary, in the integrated circuit industry, integrating large-capacity capacitors on chips or in packages is a technical difficulty, especially for high-capacity capacitor solutions. Most solutions are passive components with large external capacitors at the system PCB level. In addition, due to the use of independent packaging, the interconnection length between signals needs to be increased, which cannot meet the requirements of high frequency and high speed. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a fan-out system package and method for integrated MIM capacitors, which effectively integrates large capacitor systems, is compatible with existing processes, reduces packaging costs, and is safe and reliable.

[0006] According to the technical solution provided by the present invention, the fan-out system package of the integrated MIM capacitor includes a base chip, a functional chipset and a lead-out connection unit, wherein the functional chipset includes a plurality of functional chips, and the functional chips in the functional chipset are interconnected with the base chip and are plastic-sealed on the base chip through a plastic-sealing layer;

[0007] A MIM capacitor group is arranged in the plastic sealing layer, wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by the plastic sealing layer;

[0008] For any MIM capacitor in the MIM capacitor group, the MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer, the first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip, so that the MIM capacitor forms the required electrical connection with the base chip;

[0009] The lead-out connection unit is used to lead out the package formed by the base chip, the functional chipset and the MIM capacitor group.

[0010] On a top view plane of the plastic packaging layer, a first capacitor plate and a second capacitor plate in a MIM capacitor are in a strip shape, and the first capacitor plate and the second capacitor plate are parallel to each other;

[0011] On the cross section of the plastic packaging layer, the corresponding height directions of the first capacitor plate and the second capacitor plate in a MIM capacitor are consistent with the thickness of the plastic packaging layer.

[0012] The base chip includes a supporting substrate, an isolation dielectric layer located on the supporting substrate, and a substrate circuit layer arranged on the isolation dielectric layer, wherein:

[0013] The base chip is interconnected with the functional chip through the substrate circuit layer, and electrically connected with the MIM capacitor;

[0014] After the functional chip group is molded on the base chip through the molding layer, the supporting substrate is separated from the isolation dielectric layer, so that the required MIM capacitor group is prepared in the molding layer after the supporting substrate is separated from the isolation dielectric layer.

[0015] It also includes a plurality of substrate functional areas arranged in the substrate circuit layer, wherein the substrate functional areas in the substrate circuit layer include a chip functional area adapted to the functional chip and a capacitor functional area adapted to the MIM capacitor, wherein:

[0016] A chip functional area in the substrate circuit layer is led out through a substrate chip connection pad unit, and a capacitor functional area in the substrate circuit layer can be led out through a substrate capacitor connection pad unit;

[0017] The function chip pad of a function chip is electrically connected to a chip function area through a corresponding substrate chip connection pad unit on the front side of the substrate circuit layer, so that the function chip is interconnected with the substrate chip;

[0018] A first capacitor plate and a second capacitor plate of a MIM capacitor are electrically connected to a capacitor functional area through a substrate capacitor connection pad unit, so that the MIM capacitor is electrically connected to the substrate chip.

[0019] The lead-out connection unit and the plastic packaging layer are respectively located on two corresponding sides of the substrate circuit layer, and the isolation dielectric layer is located between the substrate circuit layer and the lead-out connection unit.

[0020] The lead-out connection unit includes a plurality of lead-out connection solder balls and a plurality of lead-out connection pads, wherein the lead-out connection solder balls correspond to the lead-out connection pads one by one, wherein:

[0021] The lead-out connection pad is located on the isolation dielectric layer and is electrically connected to the corresponding substrate functional area in the substrate circuit layer; the lead-out connection solder ball is welded on the corresponding lead-out connection pad and is electrically connected to the welded lead-out connection pad.

[0022] When encapsulating to form a MIM capacitor, a required electrode slot group is prepared in the plastic sealing layer, wherein the electrode slot group penetrates the plastic sealing layer, and the corresponding substrate capacitor connection pad unit can be exposed through the electrode slot group;

[0023] The required plate metal is filled into the prepared plate slot group to form the required first capacitor plate and second capacitor plate respectively, wherein the first capacitor plate and the second capacitor plate are both located in the plastic packaging layer.

[0024] The required plate slot group is prepared in the plastic sealing layer through the laser slotting process;

[0025] The plate metal is filled in the plate groove group based on the RDL process, and the material of the plate metal includes copper or aluminum.

[0026] A fan-out system packaging method for integrated MIM capacitors is used to prepare the fan-out system package, the packaging method comprising:

[0027] Providing a base chip and a functional chipset to be interconnected with the base chip, wherein the functional chipset includes a plurality of functional chips;

[0028] The functional chip in the functional chip group is interconnected with the base chip as required, and after the interconnection, the functional chip in the functional chip group is plastic-sealed on the front side of the base chip through a plastic sealing layer;

[0029] After the functional chip group is sealed on the front side of the base chip by using a plastic sealing layer, a MIM capacitor group is prepared in the plastic sealing layer, wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by using the plastic sealing layer;

[0030] For any MIM capacitor in the MIM capacitor group, the MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer, the first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip, so that the MIM capacitor forms the required electrical connection with the base chip;

[0031] After the MIM capacitor group is prepared, a lead-out connection unit for leading out the base chip, the functional chip group and the MIM capacitor group to form a package is prepared.

[0032] The base chip includes a supporting substrate, an isolation dielectric layer located on the supporting substrate, and a substrate circuit layer arranged on the isolation dielectric layer, wherein:

[0033] The base chip is interconnected with the functional chip through the substrate circuit layer, and electrically connected with the MIM capacitor;

[0034] After the functional chip group is molded on the base chip through the molding layer, the supporting substrate is separated from the isolation dielectric layer, so that the required MIM capacitor group is prepared in the molding layer after the supporting substrate is separated from the isolation dielectric layer.

[0035] The advantages of the present invention are as follows: based on the TSV-Less chip docking technology, a fan-out packaging structure is formed, the process difficulty is relatively small, and it is more suitable for large-scale mass production. The functional chipset is interconnected with the base chip as required, and the MIM capacitor group is electrically connected to the base chip, which effectively realizes the integration of the large capacitor system, increases the number of IOs per unit area, and has a high degree of integration. Compared with the traditional SIP packaging, the package size is reduced and the market prospect is better.

[0036] The functional chipset and MIM capacitor group are interconnected with the base chip on the wafer, which is a wafer-level packaging form, which is compatible with existing processes, has higher production efficiency and greater cost advantages. The functional chipset and the base chip are directly connected by welding and bonding, which reduces the transmission path of high-frequency signals and is suitable for high-frequency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a system package formed by the present invention.

[0038] Figure 2 FIG. 1 is a top view of the system package formed by the present invention.

[0039] Figure 3 to Figure 9 It is a cross-sectional view of the specific packaging process steps of the present invention, wherein:

[0040] Figure 3The present invention provides a cross-sectional view of a base chip and a functional chipset.

[0041] Figure 4 It is a cross-sectional view of the functional chip and the base chip after interconnection of the present invention.

[0042] Figure 5 This is a cross-sectional view of the present invention after the functional chip is plastic-sealed on the base chip.

[0043] Figure 6 This is a cross-sectional view of the present invention after the support substrate and the isolation dielectric layer are separated.

[0044] Figure 7 This is a cross-sectional view of the electrode plate slot group prepared in the present invention.

[0045] Figure 8 This is a cross-sectional view of the MIM capacitor group prepared by the present invention.

[0046] Fig. 9 This is a cross-sectional view of the lead-out connection unit prepared in the present invention.

[0047] Explanation of the accompanying drawings: 1-isolation dielectric layer, 2-substrate circuit layer, 3-lead-out connection pad, 4-plastic sealing layer, 5-first functional chip, 6-first capacitor first electrode plate, 7-first capacitor second electrode plate, 8-second capacitor first electrode plate, 9-second capacitor second electrode plate, 10-lead-out connection solder ball, 11-second functional chip, 12-substrate capacitor connection first pad, 13-substrate capacitor connection second pad, 14-functional chip pad, 15-first capacitor first plate groove, 16-substrate chip connection pad unit, 17-chip functional area, 18-capacitor functional area, 19-support substrate, 20-first capacitor second plate groove, 21-second capacitor first plate groove, 22-second capacitor second plate groove, 23-first capacitor dielectric body, 24-second capacitor dielectric body. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0049] like Figure 1 and Fig. 9 As shown: In order to effectively realize the integration of a large capacitor system, the fan-out system package of the present invention integrates MIM capacitors, specifically, including a base chip, a functional chipset and a lead-out connection unit, wherein the functional chipset includes a plurality of functional chips, and the functional chips in the functional chipset are interconnected with the base chip and are plastic-sealed on the base chip through a plastic sealing layer 4;

[0050] A MIM capacitor group is arranged in the plastic sealing layer 4, wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by the plastic sealing layer 4;

[0051] For any MIM capacitor in the MIM capacitor group, the MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer 4, the first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer 4, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip, so that the MIM capacitor forms the required electrical connection with the base chip;

[0052] The lead-out connection unit is used to lead out the package formed by the base chip, the functional chipset and the MIM capacitor group.

[0053] Specifically, the base chip can be in the form and type commonly used in the existing market, such as the base chip can be an analog chip or a digital chip. The specific type of the base chip can be selected as needed to form the required system packaging. The functional chipset includes a number of functional chips. The number and type of functional chips in the functional chipset are selected and determined as needed. For example, the functional chip can be in the form of a storage chip, a power chip, etc., which can be combined with the base chip to form the required interconnection and system packaging structure.

[0054] The functional chip in the functional chipset is interconnected with the base chip to form the required functional coordination after the interconnection. When interconnecting with the base chip, the position of the interconnection between the functional chip and the base chip and the coordination of the interconnection can be selected as needed. Generally, after determining the type of the functional chip and the coordination of the interconnection with the base chip, the functional chip can be electrically connected to the base chip to achieve the desired interconnection purpose after the electrical connection.

[0055] Figure 1 and Fig. 9 The figure shows that the functional chipset includes two functional chips, namely the first functional chip 5 and the second functional chip 11. The first functional chip 5 and the second functional chip 11 can be in the same chip form, or completely different chips, and the specific type can be selected as needed. The first functional chip 5 and the second functional chip 11 are electrically connected to the base chip respectively to achieve the desired interconnection purpose with the base chip. In the specific implementation, when the number of functional chips in the functional chipset is other, please refer to Figure 1 and Fig. 9 The connection between the first function chip 5 and the second function chip 11 and the base chip is described in detail, and will not be listed here one by one.

[0056] After the functional chip in the functional chip group is interconnected with the base chip, the functional chip group is plastic-sealed on the base chip using the plastic sealing layer 4, wherein the functional chip group can be protected after plastic sealing using the plastic sealing layer 4, thereby improving the stability and reliability of the interconnection between the functional chip group and the base chip. In order to realize the integration of large capacitors, after preparing the plastic sealing layer 4, a MIM capacitor group is prepared in the plastic sealing layer 4, that is, the MIM capacitor group is located in the plastic sealing layer 4.

[0057] In specific implementation, the MIM capacitor group includes one or more MIM (metal-insulator-metal) capacitors, and the number of MIM capacitors in the MIM capacitor group can be selected according to actual needs, so as to meet the actual application requirements. When there are multiple MIM capacitors in the plastic layer 4, adjacent MIM capacitors are spaced by the plastic layer 4, so as to ensure the stability and reliability of the MIM capacitors when working. When using MIM capacitors, the capacitance can be effectively improved, which is suitable for large power supply and low noise application scenarios.

[0058] In an embodiment of the present invention, the MIM capacitors in the MIM capacitor group adopt the same structural form, wherein the MIM capacitor includes a first capacitor plate and a second capacitor plate, and the first capacitor plate corresponds to the second capacitor plate, wherein the positive correspondence specifically refers to that the first capacitor plate and the second capacitor plate adopt the same structural form. When the MIM capacitor is located in the plastic layer 4, the first capacitor plate and the second capacitor plate are both buried in the plastic layer 4, that is, under normal circumstances, the first capacitor plate and the second capacitor plate will not be located outside the plastic layer 4. The corresponding first capacitor plate and the second capacitor plate are separated by the plastic layer 4, that is, the plastic layer 4 serves as a dielectric layer separating the first capacitor plate and the second capacitor plate, that is, a metal-dielectric layer-metal MIM capacitor form is formed.

[0059] In order to achieve electrical connection with the base chip, the first plate of the capacitor and the second plate of the capacitor are electrically connected to the base chip through the base capacitor connection pad unit on the base chip to form the electrical connection required with the base chip, so as to achieve the purpose of integrating the MIM capacitor. After the MIM capacitor is electrically connected to the base chip, the functional chipset, the MIM capacitor group and the base chip are packaged to form a package, thereby effectively integrating the functional chipset, the base chip and the large capacitor system, and improving the integration of the package. In specific implementation, the package can be led out by the lead-out connection unit to facilitate the connection after the package is led out.

[0060] Furthermore, in a top view of the plastic layer 4, a first capacitor plate and a second capacitor plate in a MIM capacitor are in the shape of long strips, and the first capacitor plate and the second capacitor plate are parallel to each other;

[0061] In the cross section of the plastic packaging layer 4 , the corresponding height directions of the first capacitor plate and the second capacitor plate in a MIM capacitor are consistent with the thickness of the plastic packaging layer 4 .

[0062] Specifically, the top view plane of the plastic layer 4 is the top view plane of the package body, and on the top view plane of the plastic layer 4, the first capacitor plate and the second capacitor plate are in the shape of long strips, and the corresponding lengths of the first capacitor plate and the second capacitor plate are smaller than the corresponding dimensions of the plastic layer 4, so that the first capacitor plate and the second capacitor plate can be buried in the plastic layer 4. On the top view plane, the long strip-shaped first capacitor plate and the second capacitor plate are parallel to each other, and the corresponding lengths of the first capacitor plate and the second capacitor plate are the same, that is, the first capacitor plate and the second capacitor plate are in positive correspondence.

[0063] The cross section of the plastic encapsulation layer 4 is the cross section of the package body. In the cross section of the plastic encapsulation layer 4, the height direction of the first capacitor plate and the second capacitor plate is consistent with the thickness of the plastic encapsulation layer 4. Generally, the corresponding upper ends of the first capacitor plate and the second capacitor plate correspond to and are exposed from the upper surface of the plastic encapsulation layer 4, and the corresponding lower ends of the first capacitor plate and the second capacitor plate are electrically connected to the substrate capacitor connection pad unit. Specifically, in the cross section of the package body, the first capacitor plate and the second capacitor plate are also parallel to each other.

[0064] Figure 1 and Fig. 9 , the MIM capacitor group includes two MIM capacitors, the two MIM capacitors are a MIM first capacitor and a MIM second capacitor, wherein the MIM first capacitor includes a first capacitor first electrode plate 6 and a first capacitor second electrode plate 7, and the MIM second capacitor includes a second capacitor first electrode plate 8 and a second capacitor second electrode plate 9. In specific implementation, the MIM first capacitor and the MIM second capacitor can adopt the same form, in which case the first capacitor first electrode plate 6, the first capacitor second electrode plate 7, the second capacitor first electrode plate 8 and the second capacitor second electrode plate 9 are all in a positive corresponding state, such as Figure 1 and Figure 2 As shown. The first capacitor first electrode plate 6 and the first capacitor second electrode plate 7 are separated by the plastic layer 4 to form a MIM capacitor structure; similarly, the second capacitor first electrode plate 8 and the second capacitor second electrode plate 9 are separated by the plastic layer 4 to form a MIM capacitor structure. The first capacitor second electrode plate 7 and the second capacitor first electrode plate 8 are also separated by the plastic layer 4. Of course, in the specific implementation, the MIM first capacitor and the MIM second capacitor can also adopt different capacitance sizes, which can be selected according to needs, and will not be repeated here.

[0065] Furthermore, the base chip includes a supporting substrate 19, an isolation dielectric layer 1 located on the supporting substrate 19, and a substrate circuit layer 2 arranged on the isolation dielectric layer 1, wherein:

[0066] The base chip is interconnected with the functional chip through the base chip circuit layer 2, and electrically connected with the MIM capacitor;

[0067] After the functional chip group is molded on the base chip by the molding layer 4 , the supporting substrate 19 is separated from the isolation dielectric layer 1 , so that the required MIM capacitor group can be prepared in the molding layer 4 .

[0068] In the embodiment of the present invention, in the formed package, the base chip includes a substrate circuit layer 2 and an isolation dielectric layer 1. In specific implementation, in order to prepare the substrate circuit layer 2 and the isolation dielectric layer 1 of the base chip, before forming the package, the base chip generally needs to include a supporting substrate 19, and the isolation dielectric layer 1 is prepared on the supporting substrate 19. The supporting substrate 19 is used to support the isolation dielectric layer 1 and the substrate circuit layer 2, that is, before forming the package, the supporting substrate 19 is used as a part of the base chip, but the chip function of the base chip is realized by the substrate circuit layer 2, and the isolation dielectric layer 1 and the supporting substrate 19 can be separated by using the commonly used technical means in the technical field, such as separating and removing the supporting substrate 19 by etching and grinding.

[0069] After the support substrate 19 is separated from the isolation dielectric layer 1, the substrate circuit layer 2 is used as the front side of the substrate chip, and the isolation dielectric layer 1 is used as the back side of the substrate chip, and the back side is the surface corresponding to the front side. When the plastic sealing layer 4 is used for plastic sealing, the plastic sealing layer 4 is pressed on the substrate circuit layer 2. Figure 5 As shown, when the plastic encapsulation layer 4 is prepared, the isolation dielectric layer 1 is supported on the supporting substrate 19. Figure 6 That is, after the plastic encapsulation layer 4 is prepared, the support substrate 19 is separated from the isolation dielectric layer 1, so that after the support substrate 19 is separated from the isolation dielectric layer 1, a MIM capacitor group is prepared.

[0070] In addition, the supporting substrate 19 is generally a silicon substrate. After separating the supporting substrate 19 from the isolation dielectric layer 1, the thickness of the formed package can be reduced. Of course, separating the supporting substrate 19 from the isolation dielectric layer 1 specifically means that it does not affect the normal operation of the base chip, and does not affect the interconnection between the base chip and the functional chipset and the lead-out connection unit.

[0071] The lead-out connection unit and the plastic encapsulation layer 4 are respectively located on the two sides corresponding to the substrate circuit layer 2 in the base chip, that is, the package lead-out unit corresponds to the back side of the base chip, and the plastic encapsulation layer 4 corresponds to the front side of the base chip. The isolation dielectric layer 1 is located between the substrate circuit layer 2 and the package lead-out unit, and the isolation dielectric layer 1 can realize the spacing between the substrate circuit layer 2 and the package lead-out unit.

[0072] Furthermore, it also includes a plurality of substrate functional areas arranged in the substrate circuit layer 2, wherein the substrate functional areas in the substrate circuit layer 2 include a chip functional area 17 adapted to the functional chip and a capacitor functional area 18 adapted to the MIM capacitor, wherein:

[0073] A chip functional area 17 in the substrate circuit layer 2 is led out through a substrate chip connection pad unit 16, and a capacitor functional area 18 in the substrate circuit layer 2 can be led out through a substrate capacitor connection pad unit;

[0074] The function chip pad 14 of a function chip is electrically connected to a chip function area 17 through the corresponding substrate chip connection pad unit 16 on the front side of the substrate circuit layer 2, so that the function chip is interconnected with the substrate chip;

[0075] The first capacitor plate and the second capacitor plate of a MIM capacitor are electrically connected to a capacitor functional area 18 through a substrate capacitor connection pad unit, so that the MIM capacitor is electrically connected to the substrate chip.

[0076] Specifically, a plurality of substrate functional areas are provided in the substrate circuit layer 2, and the substrate functional area is a circuit area for realizing corresponding functions. The circuit functions realized by the substrate functional area can be selected as needed, such as amplification, conversion, etc. The number and distribution of the substrate functional areas in the substrate circuit layer 2 can be selected as needed to meet the interconnection requirements of the base chip.

[0077] In specific implementation, the required substrate functional area can be prepared in the substrate circuit layer 2 by using the commonly used technical means in the technical field. When the formed package includes both the functional chipset and the MIM capacitor group, in order to be able to adapt and connect with the functional chipset and the MIM capacitor group, the substrate functional area includes a chip functional area 17 and a capacitor functional area 18; the chip functional area 17 is used to realize the data interaction required when interconnecting with the functional chip, and the capacitor functional area 18 is used to realize the processing required after connecting with the MIM capacitor.

[0078] Generally, a functional chip is interconnected with a corresponding chip functional area 17; a MIM capacitor is interconnected with a corresponding capacitor functional area, so that the number of chip functional areas 17 in the substrate functional area is not less than the number of functional chips in the functional chip group, and the number of capacitor functional areas 18 in the substrate functional area is not less than the number of MIM capacitors in the MIM capacitor group.

[0079] In order to achieve connection and lead-out, for any chip functional area 17, connection and lead-out is achieved through a substrate chip connection pad unit 16, that is, a chip functional area 17 corresponds to a substrate chip connection pad unit 16, so that the corresponding chip functional area 17 is led out through a substrate chip pad connection unit 16. The substrate chip connection pad unit 16 is located on the front side of the base chip, and the number of substrate chip connection pads in the substrate chip connection pad unit 16 can be related to the corresponding chip functional area 17, so as to meet the interconnection between the chip functional area 17 and the functional chip.

[0080] In specific implementation, the functional chip is interconnected with the base chip, specifically, the functional chip is interconnected with the corresponding chip functional area 17 through the corresponding electrically connected base chip connection pad unit 16, that is, the functional chip pad 14 of a functional chip is electrically connected with a chip functional area 17 through the corresponding base chip connection pad unit 16 on the front side of the base circuit layer 2. The functional chip pad 14 and the base chip connection pad unit 16 can generally be connected by welding. During welding, the functional chip pad 14 and the base chip connection pad unit 16 are aligned, that is, the electrical connection after welding is achieved.

[0081] Similarly, for any capacitor functional area 18, a substrate capacitor connection pad unit is used to connect and lead out, and there is a one-to-one correspondence between the capacitor functional area 18 and the substrate capacitor connection pad unit, and the substrate capacitor connection pad unit is also located on the front side of the substrate chip. Figure 1 and Figure 2 In the implementation form, the substrate capacitor connecting pad unit includes a substrate capacitor connecting first pad 12 and a substrate capacitor connecting second pad 13. When connected, the first plate of the capacitor is electrically connected to the first pad 12 of the substrate capacitor, and the second plate of the capacitor is electrically connected to the second pad 13 of the substrate capacitor, thereby achieving electrical connection with the capacitor functional area 18.

[0082] Furthermore, the lead-out connection unit includes a plurality of lead-out connection solder balls 10 and a plurality of lead-out connection pads 3, wherein the lead-out connection solder balls 10 correspond to the lead-out connection pads 3 in a one-to-one manner, wherein:

[0083] The lead-out connection pad 3 is located on the isolation dielectric layer 1 and is electrically connected to the corresponding substrate functional area in the substrate circuit layer 2; the lead-out connection solder ball 10 is welded on the corresponding lead-out connection pad 3 and is electrically connected to the welded lead-out connection pad 3.

[0084] In the embodiment of the invention, in order to realize the lead-out of the package body, the lead-out connection unit includes a lead-out connection solder ball 10 and a lead-out connection pad 3. The lead-out connection solder ball 10 and the lead-out connection pad 3 are in one-to-one correspondence, that is, one lead-out connection solder ball 10 is correspondingly welded to one lead-out connection pad 3. Of course, the lead-out connection solder ball 10 is adaptively connected to the corresponding substrate functional area in the substrate circuit layer 2 through the corresponding lead-out connection pad 3 welded to it.

[0085] In order to achieve adaptive electrical connection with the substrate functional area in the substrate circuit layer 2, it also includes a number of dielectric layer windows that penetrate the isolation dielectric layer 1. The lead-out connection pad 3 passes through the corresponding dielectric layer window and is adaptively electrically connected with the corresponding substrate functional area in the substrate circuit layer 2. Specifically, the lead-out connection pad 10 includes a portion covered on the isolation dielectric layer 1 and a portion filled in the dielectric layer window. The portion covered on the isolation dielectric layer 1 can achieve welding electrical connection with the lead-out connection solder ball 10, and the portion filled in the dielectric layer window is used for adaptive electrical connection with the corresponding substrate functional area, thereby achieving the purpose of leading out the entire package through the lead-out connection solder ball 10. After leading out, the lead-out connection solder ball 10 is connected to other circuits to form the required package or connection form, which is consistent with the existing ones and will not be repeated here.

[0086] Furthermore, when the MIM capacitor is encapsulated, a required electrode slot group is prepared in the plastic sealing layer 4, wherein the electrode slot group penetrates the plastic sealing layer 4, and the corresponding substrate capacitor connection pad unit can be exposed through the electrode slot group;

[0087] The required plate metal is filled into the prepared plate slot group to form the required first capacitor plate and second capacitor plate, respectively, wherein the first capacitor plate and the second capacitor plate are both located in the plastic packaging layer 4 .

[0088] It can be seen from the above description that the MIM capacitor is buried in the plastic layer 4. In order to prepare the MIM capacitor in the plastic layer 4, it is necessary to prepare the required plate slot group in the plastic layer 4, and the plate slot group is adapted to the MIM capacitor group to be prepared in the plastic layer 4. In specific implementation, a laser grooving process is used to prepare the required plate slot group in the plastic layer 4; the plate slots in the plate slot group vertically penetrate the plastic layer 4. Of course, in the top view of the plastic layer 4, the plate slots also need to be in the shape of long strips, and the corresponding substrate capacitor connection pad unit can be exposed through the plate slot group, so that the first plate and the second plate of the capacitor in the MIM capacitor are electrically connected to the corresponding capacitor functional area 18 through the exposed substrate capacitor connection pad unit.

[0089] In order to form the first capacitor plate and the second capacitor plate in the MIM capacitor, in the embodiment of the present invention, the plate metal is filled in the plate slot group through the RDL (Re-distributed layer) process, and the material of the plate metal includes copper or aluminum. Of course, in the specific implementation, the required first capacitor plate and the second capacitor plate can also be prepared by other process forms, and the specific process can be selected as needed to meet the requirements of preparing the required first capacitor plate and the second capacitor plate.

[0090] like Figure 3 to Figure 9 As shown, the fan-out system package of the integrated MIM capacitor can be prepared by the following process steps. Specifically, the packaging method includes:

[0091] Providing a base chip and a functional chipset to be interconnected with the base chip, wherein the functional chipset includes a plurality of functional chips;

[0092] The functional chips in the functional chipset are interconnected with the base chip as required, and after the interconnection, the functional chips in the functional chipset are plastic-sealed on the front side of the base chip through the plastic-sealing layer 4;

[0093] After the functional chip group is sealed on the front side of the base chip by using the sealing layer 4, a MIM capacitor group is prepared in the sealing layer 4, wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by using the sealing layer 4;

[0094] For any MIM capacitor in the MIM capacitor group, the MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer 4, the first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer 4, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip, so that the MIM capacitor forms the required electrical connection with the base chip;

[0095] After the MIM capacitor group is prepared, a lead-out connection unit for leading out the base chip, the functional chip group and the MIM capacitor group to form a package is prepared.

[0096] like Figure 3 As shown, the provided base chip also includes a supporting substrate 19, an isolation dielectric layer 1 arranged on the supporting substrate 19, and a substrate circuit layer 2 arranged on the isolation dielectric layer 1, wherein a plurality of chip functional areas 17 and a plurality of capacitor functional areas 18 are arranged in the substrate circuit layer 2. The specific situation of the substrate circuit layer 2 is referred to the above description and will not be repeated here.

[0097] Specifically, the support substrate 19 can be an existing commonly used silicon substrate. The material type and form of the support substrate 19 can be selected as needed. Of course, the support substrate 19 also needs to be in a form that can be easily separated from the isolation dielectric layer 1, specifically, it is based on the ability to prepare and support the isolation dielectric layer 1 and the substrate circuit layer 2, and to be easily separated from the isolation dielectric layer 1. The separation is to separate the support substrate 19 from the isolation dielectric layer 1, and maintain the connection and matching form between the isolation dielectric layer 1 and the substrate circuit layer 2.

[0098] In specific implementation, the isolation dielectric layer 1 includes a silicon dioxide layer or a silicon nitride layer, that is, the isolation dielectric layer 1 can be a silicon dioxide layer or a silicon nitride layer. The specific form of the isolation dielectric layer 1 can be selected as needed, so as to achieve dielectric isolation. Generally, the isolation dielectric layer 1 can be prepared on the supporting substrate 19 by using the process technology means commonly used in this technical field, and the substrate circuit layer 2 can be prepared on the isolation dielectric layer 1. The specific process mode, process conditions and process for preparing the isolation dielectric layer 1 and the substrate circuit layer 2 can be selected as needed, so as to obtain the required substrate chip. Of course, a number of substrate chip connection pad units 16 for leading out the chip functional area 17 and substrate capacitor connection pad units for leading out the capacitor functional area 18 are set on the substrate circuit layer 2. The specific lead-out connection situation can refer to the above description and will not be repeated here.

[0099] Figure 3 In the figure, the functional chips to be interconnected with the base chip are provided. The functional chips provided are the first functional chip 5 and the second functional chip 11. Of course, in the specific implementation, the number of functional chips in the functional chip group can be selected according to the actual application requirements. Specifically, the interconnection between the functional chip and the base chip specifically refers to the functional chip pad 14 of the functional chip being welded to the corresponding base chip connection pad unit 16. After welding, the functional chip is located above the corresponding chip functional area 17, such as Figure 4 The welding refers to a form that can effectively weld and fix the functional chip pad 14 and the substrate chip connection pad unit 16. The welding process is not described here. When the electrical connection is made after welding, the interconnection distance can be shortened, which is suitable for high-frequency and high-speed application scenarios.

[0100] After the functional chips in the functional chipset are interconnected with the base chip, the functional chipset is plastic-sealed on the front side of the base chip to obtain a plastic sealing layer 4, such as Figure 5 The thickness of the plastic layer 4 is greater than the height of the functional chip on the base chip, that is, the functional chip is completely buried in the plastic layer 4. The specific process and conditions for preparing the plastic layer 4 can be selected as needed to prepare the required plastic layer 4.

[0101] In the specific implementation, after the plastic sealing layer 4 is prepared, in order to prepare the MIM capacitor group, reduce the thickness of the package body and avoid warping, the support substrate 19 is separated from the isolation dielectric layer 1 by the commonly used technical means in the technical field. The specific process and conditions for separating the support substrate 19 from the isolation dielectric layer 1 can be selected as needed, so as to achieve the separation of the support substrate 19 from the isolation dielectric layer 1. Figure 6 shown.

[0102] After the support substrate 19 is separated from the isolation dielectric layer 1, the required MIM capacitor group needs to be prepared in the plastic layer 4. Specifically, a plate slot group is first prepared in the plastic layer 4, such as Figure 7 As shown, it can be known from the above description that the plate slot group penetrates the plastic sealing layer 4, and the plate slot group can be prepared by laser slotting process. Figure 1 , Figure 2 and Fig. 9 The implementation form of the MIM capacitor group, Figure 7 In the embodiment, the prepared electrode plate slot group includes a first capacitor first electrode plate slot 15, a first capacitor second electrode plate slot 20, a second capacitor first electrode plate slot 21 and a second capacitor second electrode plate slot 22, wherein the first capacitor first electrode plate slot 15 and the first capacitor geothermal electrode plate slot 20 can correspond to the first capacitor first electrode plate 6 and the first capacitor second electrode plate 7 respectively; the second capacitor first electrode plate slot 21 and the second capacitor second electrode plate slot 22 can correspond to the second capacitor first electrode plate 8 and the second capacitor second electrode plate 9 respectively.

[0103] The plastic sealing layer 4 between the first capacitor first plate groove 15 and the first capacitor second plate groove 20 forms a first capacitor dielectric body 23 in the MIM first capacitor. Through the first capacitor first plate groove 15 and the first capacitor second plate groove 20, the corresponding substrate capacitor connection first pad 12 and substrate capacitor connection second pad 13 corresponding to the MIM first capacitor can be exposed.

[0104] The plastic sealing layer 4 between the second capacitor first electrode groove 21 and the second capacitor second electrode groove 22 forms the second capacitor dielectric body 24 in the MIN second capacitor; through the second capacitor first electrode groove 21 and the second capacitor second electrode groove 22, the corresponding substrate capacitor connection first welding pad 12 and substrate capacitor connection second welding pad 13 corresponding to the MIM second capacitor can be exposed.

[0105] After the plate slot group is prepared, the capacitor plate can be prepared by RDL process. Figure 7In the case of the middle electrode groove group, after the RDL process, the first capacitor first electrode plate 6 filled in the first capacitor first electrode groove 15, the first capacitor second electrode plate 7 filled in the first capacitor second electrode groove 20; the second capacitor first electrode plate 8 filled in the second capacitor first electrode groove 21 and the second capacitor second electrode plate 9 filled in the second capacitor second electrode groove 22 are obtained. Figure 8 shown.

[0106] Right now Figure 8 In the figure, a MIM capacitor group is prepared in the plastic layer 4. From the above description, it can be seen that when the MIM capacitor is integrated in the present invention, the package does not contain the supporting body 19 and the supporting substrate 19 does not need to be subjected to the TSV process in the process. That is, the present invention is based on the TSV-Less process, which can reduce the process difficulty, is suitable for mass production, and reduces production costs.

[0107] Furthermore, when preparing the lead-out connection unit, the isolation dielectric layer 1 is selectively masked and etched to obtain a plurality of dielectric layer windows penetrating the isolation dielectric layer 1;

[0108] After obtaining the dielectric layer window, the lead-out connection pad 19 is prepared by RDL process, and the lead-out connection pad 19 covers the isolation dielectric layer 1. The lead-out connection pad 19 passes through the corresponding dielectric layer window and is electrically connected to the corresponding substrate functional area in the chip circuit 1;

[0109] The lead-out connection solder balls 10 are welded to the lead-out connection pads 19 , and the lead-out connection solder balls 10 are electrically connected to the corresponding lead-out connection pads 19 .

[0110] In the embodiment of the present invention, the isolation dielectric layer 1 can be masked and etched by common technical means in the art, that is, a dielectric layer window is obtained, and the dielectric layer window penetrates the isolation dielectric layer 1. The corresponding substrate functional area in the substrate circuit layer 2 can be exposed through the dielectric layer window.

[0111] After obtaining the dielectric layer window, the lead-out connection pad 19 is prepared by the RDL process, and the lead-out connection pad 19 covers the isolation dielectric layer 1. The lead-out connection pad 19 passes through the corresponding dielectric layer window and is electrically connected to the corresponding circuit functional area 3 in the chip circuit 1. The specific process and process for preparing the lead-out connection pad 19 can be selected as needed, so as to prepare the required lead-out connection pad 19.

[0112] After the lead-out connection pad 19 is obtained, the lead-out connection solder ball 10 can be welded on the lead-out connection pad 19. Fig. 9 , that is, the state after the lead-out connection solder ball 10 is welded to the corresponding lead-out connection pad 19 is shown.

[0113] In specific implementation, the above process is performed on a wafer, that is, the above process is a wafer-level process, which can be obtained by wafer cutting process. Figure 1 and Fig. 9 The corresponding package in .

[0114] The present invention is based on the chip docking technology of TSV-Less, forms a fan-out packaging structure, has relatively low process difficulty, and is more suitable for large-scale mass production. The functional chipset is interconnected with the base chip as required, and the MIM capacitor group is electrically connected to the base chip, that is, the large capacitor system is effectively integrated, the IO number per unit area is increased, and the integration is high. Compared with the traditional SIP (System In a Package) packaging, the package size is reduced and the market prospect is better.

[0115] The functional chipset and MIM capacitor group are interconnected with the base chip on the wafer, which is a wafer-level packaging form, which is compatible with existing processes, has higher production efficiency and greater cost advantages. The functional chipset and the base chip are directly connected by welding and bonding, which reduces the transmission path of high-frequency signals and is suitable for high-frequency applications.

Claims

1. A fan-out system package with integrated MIM capacitors, comprising a base chip, a functional chipset and a lead-out connection unit, wherein the functional chipset comprises a plurality of functional chips, the functional chips in the functional chipset are interconnected with the base chip and are plastic-sealed on the base chip through a plastic sealing layer (4); wherein: A MIM capacitor group is arranged in the plastic sealing layer (4), wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by the plastic sealing layer (4); For any MIM capacitor in the MIM capacitor group, the MIM capacitor comprises a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in a plastic sealing layer (4), the first capacitor plate and the second capacitor plate are separated by the plastic sealing layer (4), a portion of the plastic sealing layer (4) used for separating the first capacitor plate and the second capacitor plate serves as a capacitor medium of the MIM capacitor, and the first capacitor plate and the second capacitor plate are electrically connected to a corresponding substrate capacitor connection pad unit on a substrate chip, so that the MIM capacitor forms a required electrical connection with the substrate chip; The lead-out connection unit is used to lead out the package formed by the base chip, the functional chipset and the MIM capacitor group; In a top view of the plastic sealing layer (4), a first capacitor plate and a second capacitor plate in a MIM capacitor are in the shape of long strips, and the first capacitor plate and the second capacitor plate are parallel to each other; On a cross section of the plastic encapsulation layer (4), the corresponding height directions of a first capacitor plate and a second capacitor plate in a MIM capacitor are consistent with the thickness of the plastic encapsulation layer (4).

2. The fan-out system package with integrated MIM capacitor according to claim 1, characterized in that: The base chip comprises a supporting substrate (19), an isolation dielectric layer (1) located on the supporting substrate (19), and a substrate circuit layer (2) arranged on the isolation dielectric layer (1), wherein: The base chip is interconnected with the functional chip as required through the base chip circuit layer (2), and is electrically connected with the MIM capacitor as required; After the functional chip group is molded on the base chip by the molding layer (4), the supporting substrate (19) is separated from the isolation dielectric layer (1), so that the required MIM capacitor group is prepared in the molding layer (4) after the supporting substrate (19) is separated from the isolation dielectric layer (1).

3. The fan-out system package with integrated MIM capacitor according to claim 2, characterized in that: It also includes a plurality of substrate functional areas arranged in the substrate circuit layer (2), wherein the substrate functional areas in the substrate circuit layer (2) include a chip functional area (17) adapted to the functional chip and a capacitor functional area (18) adapted to the MIM capacitor, wherein: A chip functional area (17) in the substrate circuit layer (2) is led out through a substrate chip connection pad unit (16), and a capacitor functional area (18) in the substrate circuit layer (2) can be led out through a substrate capacitor connection pad unit; A function chip pad (14) of a function chip is electrically connected to a chip function area (17) via a corresponding substrate chip connection pad unit (16) on the front side of the substrate circuit layer (2), so that the function chip is interconnected with the substrate chip; A first capacitor plate and a second capacitor plate of a MIM capacitor are electrically connected to a capacitor functional area (18) via a substrate capacitor connection pad unit, so that the MIM capacitor is electrically connected to a substrate chip.

4. The fan-out system package with integrated MIM capacitor according to claim 3, wherein: The lead-out connection unit and the plastic sealing layer (4) are respectively located on two corresponding sides of the substrate circuit layer (2), and the isolation dielectric layer (1) is located between the substrate circuit layer (2) and the lead-out connection unit.

5. The fan-out system package with integrated MIM capacitor according to claim 4, characterized in that: The lead-out connection unit comprises a plurality of lead-out connection solder balls (10) and a plurality of lead-out connection pads (3), wherein the lead-out connection solder balls (10) correspond to the lead-out connection pads (3) in a one-to-one manner, wherein: The lead-out connection pad (3) is located on the isolation dielectric layer (1) and is electrically connected to the corresponding substrate functional area in the substrate circuit layer (2); the lead-out connection solder ball (10) is welded on the corresponding lead-out connection pad (3) and is electrically connected to the welded lead-out connection pad (3).

6. The fan-out system package with integrated MIM capacitor according to any one of claims 1 to 5, characterized in that: When encapsulating to form a MIM capacitor, a required electrode slot group is prepared in the plastic sealing layer (4), wherein the electrode slot group penetrates the plastic sealing layer (4), and the corresponding substrate capacitor connection pad unit can be exposed through the electrode slot group; The required plate metal is filled into the prepared plate slot group to respectively form the required first capacitor plate and second capacitor plate, wherein the first capacitor plate and the second capacitor plate are both located in the plastic sealing layer (4).

7. The fan-out system package with integrated MIM capacitor according to claim 6, characterized in that: A laser slotting process is used to prepare a required electrode slot group in the plastic sealing layer (4); The plate metal is filled in the plate groove group based on the RDL process, and the material of the plate metal includes copper or aluminum.

8. A fan-out system packaging method with integrated MIM capacitors, characterized in that: For preparing the fan-out system package according to claim 1, the packaging method comprises: Providing a base chip and a functional chipset to be interconnected with the base chip, wherein the functional chipset includes a plurality of functional chips; The functional chip in the functional chip group is interconnected with the base chip as required, and after the interconnection, the functional chip in the functional chip group is plastic-sealed on the front side of the base chip through a plastic sealing layer (4); After the functional chip group is plastic-sealed on the front side of the base chip by using the plastic-sealing layer (4), a MIM capacitor group is prepared in the plastic-sealing layer (4), wherein the MIM capacitor group includes a plurality of MIM capacitors, and the MIM capacitors in the MIM capacitor group are spaced apart from each other by using the plastic-sealing layer (4); For any MIM capacitor in the MIM capacitor group, the MIM capacitor comprises a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate, the first capacitor plate and the second capacitor plate are both buried in a plastic sealing layer (4), the first capacitor plate and the second capacitor plate are spaced apart by the plastic sealing layer (4), and the first capacitor plate and the second capacitor plate are electrically connected to a corresponding substrate capacitor connection pad unit on a substrate chip, so that the MIM capacitor forms a required electrical connection with the substrate chip; The preparation of the MIM capacitor group in the plastic packaging layer (4) comprises the following steps: A plurality of electrode plate slot groups are prepared in the plastic sealing layer (4), wherein the electrode plate slot groups penetrate the plastic sealing layer (4), and any of the electrode plate slot groups includes a first capacitor electrode plate slot and a second capacitor electrode plate slot, wherein the first capacitor electrode plate slot and the second capacitor electrode plate slot are separated by the plastic sealing layer (4), and the first capacitor electrode plate slot and the second capacitor electrode plate slot respectively expose corresponding substrate capacitor connection pad units on the substrate chip; A first capacitor electrode plate is filled in the first capacitor electrode groove and a second capacitor electrode plate is filled in the second capacitor electrode groove, wherein the first capacitor electrode plate, a portion of the plastic encapsulation layer (4) located between the first capacitor electrode plate and the second capacitor electrode plate, and the second capacitor electrode plate constitute the MIM capacitor. After the MIM capacitor group is prepared, a lead-out connection unit for leading out the base chip, the functional chip group and the MIM capacitor group to form a package is prepared.

9. The fan-out system packaging method of integrated MIM capacitor according to claim 8, characterized in that: The base chip comprises a supporting substrate (19), an isolation dielectric layer (1) located on the supporting substrate (19), and a substrate circuit layer (2) arranged on the isolation dielectric layer (1), wherein: The base chip is interconnected with the functional chip as required through the base chip circuit layer (2), and is electrically connected with the MIM capacitor as required; After the functional chip group is molded on the base chip by the molding layer (4), the supporting substrate (19) is separated from the isolation dielectric layer (1), so that the required MIM capacitor group is prepared in the molding layer (4) after the supporting substrate (19) is separated from the isolation dielectric layer (1).

Images