Memory structure and manufacturing method thereof

Abstract

The present invention provides a memory structure and a manufacturing method thereof. The memory structure includes a substrate, a bit line structure, a contact window structure, a termination layer and a capacitor structure. The substrate includes a memory array area. The bit line structure is located in the memory array area and on the substrate. The contact window structure is located in the memory array area and on the substrate on one side of the bit line structure. The termination layer is located in the memory array area and above the bit line structure. The capacitor structure is located in the memory array area. The capacitor structure passes through the termination layer and is electrically connected to the contact window structure. The bottom surface of the capacitor structure is lower than the bottom surface of the termination layer. The memory structure can effectively increase the capacitance of the capacitor structure, thereby improving the electrical performance of the memory element.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a memory structure and a manufacturing method thereof. Background Art

[0002] A memory structure has been developed, including a transistor and a capacitor coupled to each other. In this memory structure, a capacitor is used as a storage element. Therefore, how to increase the capacitance of the capacitor to improve the electrical performance of the memory element is a goal that is being continuously worked on. Summary of the invention

[0003] The present invention provides a memory structure and a manufacturing method thereof, which can effectively increase the capacitance of the capacitor structure and thus improve the electrical performance of the memory element.

[0004] The present invention provides a memory structure, comprising a substrate, a bit line structure, a contact window structure, a termination layer and a capacitor structure. The substrate comprises a memory array region. The bit line structure is located in the memory array region and on the substrate. The contact window structure is located in the memory array region and on the substrate on one side of the bit line structure. The termination layer is located in the memory array region and above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the termination layer and is electrically connected to the contact window structure. The bottom surface of the capacitor structure is lower than the bottom surface of the termination layer.

[0005] The present invention provides a method for manufacturing a memory structure, comprising the following steps. A substrate is provided. The substrate includes a memory array area. A bit line structure is formed in the memory array area. The bit line structure is located on the substrate. A contact window structure is formed in the memory array area. The contact window structure is located on the substrate on one side of the bit line structure. A termination layer is formed in the memory array area. The termination layer is located above the bit line structure. A capacitor structure is formed in the memory array area. The capacitor structure passes through the termination layer and is electrically connected to the contact window structure. The bottom surface of the capacitor structure is lower than the bottom surface of the termination layer.

[0006] Based on the above, in the memory structure and manufacturing method thereof proposed by the present invention, since the bottom surface of the capacitor structure is lower than the bottom surface of the termination layer, the overall height of the capacitor structure can be increased, thereby increasing the capacitance area of ​​the capacitor structure. Therefore, the capacitance of the capacitor structure can be effectively increased, thereby improving the electrical performance of the memory element.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1A to FIG. 1I FIG. 4 is a cross-sectional view of a manufacturing process of a memory structure according to an embodiment of the present invention.

[0009] Description of Figure Numbers:

[0010] 10: Memory structure

[0011] 100: Base

[0012] 102: Isolation Structure

[0013] 104: Bit line structure

[0014] 106,126,128,158: Contact window

[0015] 108: Wire

[0016] 110,138,152,176: Dielectric structures

[0017] 112,114,144,176a,176b,176c,176d,194: Dielectric layer

[0018] 116,132,148,160,162a,162b,162c,166a,166b,166c: barrier layer

[0019] 118,150,154,172a,172b: Hard mask layer

[0020] 120,122: mask layer

[0021] 124,156: Contact window structure

[0022] 130: Metal silicide layer

[0023] 134,136: Spacer layer

[0024] 140: Gate structure

[0025] 142: Gate

[0026] 146,164a,164c,188,190,192: Conductor layer

[0027] 162,166: Barrier material layer

[0028] 164: Conductor material layer

[0029] 164b: Virtual conductor layer

[0030] 168: Sacrificial material layer

[0031] 168a, 168b, 168c: Sacrificial layer

[0032] 170: Patterned photoresist layer

[0033] 174: Termination layer

[0034] 178: Patterned mask layer

[0035] 180:Capacitor structure

[0036] 182,186: Electrode

[0037] 184: Insulation layer

[0038] BS1, BS2: bottom surface

[0039] H: Height

[0040] OP: Opening

[0041] R1: memory array area

[0042] R2: Peripheral circuit area

[0043] T:Thickness

[0044] TS1,TS2,TS3,TS4,TS5: Top surface DETAILED DESCRIPTION

[0045] FIG. 1A to FIG. 1I FIG. 4 is a cross-sectional view of a manufacturing process of a memory structure according to an embodiment of the present invention.

[0046] Please refer to Figure 1A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 includes a memory array region R1. In addition, the substrate 100 may also include a peripheral circuit region R2. An isolation structure 102 may be provided in the substrate 100. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. In addition, a desired doping region (not shown) may be formed in the substrate 100 as required.

[0047] A bit line structure 104 is formed in the memory array region R1. The bit line structure 104 is located on the substrate 100. The bit line structure 104 may include a contact window 106 and a conductive line 108. The contact window 106 is located on the substrate 100. The material of the contact window 106 is, for example, doped polysilicon. The conductive line 108 is located on the contact window 106. Part of the conductive line 108 may be located on the dielectric structure 110. The material of the conductive line 108 is, for example, tungsten or other metal. The dielectric structure 110 may be a single-layer structure or a multi-layer structure. In the present embodiment, the dielectric structure 110 is an example of a multi-layer structure including a dielectric layer 112 and a dielectric layer 114, but the present invention is not limited thereto. The dielectric layer 112 is located on the isolation structure 102. The material of the dielectric layer 112 is, for example, silicon oxide. The dielectric layer 114 is located on the dielectric layer 112. The material of the dielectric layer 114 is, for example, silicon nitride. In addition, the bit line structure 104 may further include a barrier layer 116. The barrier layer 116 is located between the conductive line 108 and the contact window 106. A portion of the barrier layer 116 may be located between the conductive line 108 and the dielectric structure 110. The material of the barrier layer 116 is, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0048] In addition, a hard mask layer 118 may be formed on the bit line structure 104. The hard mask layer 118 may be a single-layer structure or a multi-layer structure. In the present embodiment, the hard mask layer 118 is exemplified by a multi-layer structure including a mask layer 120 and a mask layer 122, but the present invention is not limited thereto. The mask layer 120 is located on the conductive line 108. The material of the mask layer 120 is, for example, silicon nitride. The mask layer 122 is located on the mask layer 120. The material of the mask layer 122 is, for example, silicon nitride.

[0049] In addition, a contact window structure 124 is formed in the memory array region R1. The contact window structure 124 is located on the substrate 100 on one side of the bit line structure 104. The contact window structure 124 may include a contact window 126 and a contact window 128. The contact window 126 is located on the substrate 100. The material of the contact window 126 is, for example, doped polysilicon. The contact window 128 is located on the contact window 126. The material of the contact window 128 is, for example, a metal such as tungsten. In addition, the contact window structure 124 may also include at least one of a metal silicide layer 130 and a barrier layer 132. The metal silicide layer 130 is located between the contact window 126 and the contact window 128. The material of the metal silicide layer 130 is, for example, cobalt silicide (CoSi) or nickel silicide (NiSi). The barrier layer 132 is located between the contact window 128 and the metal silicide layer 130. The material of the barrier layer 132 is, for example, Ti, TiN or a combination thereof.

[0050] In addition, a spacer layer 134 may be formed on one side wall of the contact window structure 124, and a spacer layer 136 may be formed on the other side wall of the contact window structure 124. In addition, the spacer layer 134 may also be located on both side walls of the conductive line 108 on the dielectric structure 110, and the spacer layer 136 may also be located on both side walls of the bit line structure 104. The spacer layer 134 and the spacer layer 136 may be a single-layer structure or a multi-layer structure, respectively. For example, the spacer layer 134 and the spacer layer 136 may be a silicon nitride layer, a composite layer of a silicon oxide layer / silicon nitride layer (NO), or a composite layer of a silicon nitride layer / silicon oxide layer / silicon nitride layer (NON), respectively.

[0051] In addition, a dielectric structure 138 may be formed on the substrate 100 at the edge of the memory array region R1. The dielectric structure 138 may be a single-layer structure or a multi-layer structure. The material of the dielectric structure 138 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0052] On the other hand, a gate structure 140 may be formed in the peripheral circuit region R2. The gate structure 140 may include a gate 142 and a dielectric layer 144. The gate 142 is located on the substrate 100. The material of the gate 142 is, for example, doped polysilicon. The dielectric layer 144 is located between the gate 140 and the substrate 100. The material of the dielectric layer 144 is, for example, an oxide, such as silicon oxide. In addition, the gate structure 140 may further include a conductor layer 146. The conductor layer 146 is located on the gate 140. The material of the conductor layer 146 is, for example, a metal such as tungsten. In addition, the gate structure 140 may further include a barrier layer 148. The barrier layer 148 is located between the gate 142 and the conductor layer 146. The material of the barrier layer 146 is, for example, Ti, TiN, or a combination thereof. In some embodiments, a spacer layer (not shown) may be formed on the sidewall of the gate structure 140.

[0053] In addition, a hard mask layer 150 may be formed on the gate structure 140. The material of the hard mask layer 150 is, for example, silicon nitride. In addition, a dielectric structure 152 may be formed on both sides of the gate structure 140. The dielectric structure 152 may be a single-layer structure or a multi-layer structure. The material of the dielectric structure 152 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0054] On the other hand, a hard mask layer 154 covering the hard mask layer 150 and the dielectric structure 152 may be formed. The material of the hard mask layer 154 is, for example, silicon nitride. In addition, a contact window structure 156 may be formed in the hard mask layer 154 and the hard mask layer 150. The contact window structure 156 may be electrically connected to the conductor layer 146. The contact window structure 156 may include a contact window 158. The material of the contact window 158 is, for example, a metal such as tungsten. The contact window 158 is located in the hard mask layer 154 and the hard mask layer 150. In addition, the contact window structure 156 may further include a barrier layer 160. The barrier layer 160 is located between the contact window 158 and the conductor layer 146. The material of the barrier layer 160 is, for example, Ti, TiN, or a combination thereof.

[0055] Please refer to Figure 1B , a barrier material layer 162, a conductor material layer 164, a barrier material layer 166, and a sacrificial material layer 168 may be sequentially formed in the memory array region R1 and the peripheral circuit region R2. The material of the barrier material layer 162 and the barrier material layer 166 is, for example, Ti, TiN, or a combination thereof. The material of the conductor material layer 164 is, for example, a metal such as tungsten. The material of the sacrificial material layer 168 is, for example, polysilicon. The barrier material layer 162, the conductor material layer 164, the barrier material layer 166, and the sacrificial material layer 168 may be formed by appropriate deposition methods, such as chemical vapor deposition or physical vapor deposition. In other embodiments, the barrier material layer 162 and the barrier material layer 166 may be omitted.

[0056] Please refer to Figure 1C , the sacrificial material layer 168, the barrier material layer 166, the conductor material layer 164, and the barrier material layer 162 may be patterned, and a barrier layer 162a, a conductor layer 164a, a barrier layer 166a, and a sacrificial layer 168a may be formed in the memory array region R1, which are sequentially located above the contact window structure 124; a barrier layer 162b, a dummy conductor layer 164b, a barrier layer 166b, and a sacrificial layer 168b may be formed in the memory array region R1, which are not located above the contact window structure 124; and a barrier layer 162c, a conductor layer 164c, a barrier layer 166c, and a sacrificial layer 168c may be formed in the peripheral circuit region R2, which are sequentially located above the contact window structure 156. The conductor layer 164a may be electrically connected to the contact window structure 124 via the barrier layer 162a. The dummy conductor layer 164b may be located above the dielectric structure 138. The conductive layer 164c may be electrically connected to the contact structure 156 via the barrier layer 162c. The sacrificial layer 168a, the sacrificial layer 168b, and the sacrificial layer 168c may be located above the conductive layer 164a, the dummy conductive layer 164b, and the conductive layer 164c, respectively.

[0057] In addition, the method of patterning the sacrificial material layer 168, the barrier material layer 166, the conductive material layer 164, and the barrier material layer 162 may include a photolithography process, an etching process, a self-aligned double patterning (SADP) process, a patterning process using a hard mask layer, or a combination thereof. In addition, in the above patterning process, a portion of the contact window 128, a portion of the barrier layer 132, a portion of the spacer layer 134, a portion of the spacer layer 136, a portion of the mask layer 122, and a portion of the hard mask layer 154 may be removed simultaneously.

[0058] Next, a patterned photoresist layer 170 may be formed. The patterned photoresist layer 170 covers the sacrificial layer 168a and the sacrificial layer 168b in the memory array region R1 and exposes the sacrificial layer 168c in the peripheral circuit region R2. The patterned photoresist layer 170 may be formed by a photolithography process.

[0059] Please refer to Figure 1D The patterned photoresist layer 170 can be used as a mask to remove the sacrificial layer 168c in the peripheral circuit region R2 to expose the blocking layer 166c. The sacrificial layer 168c can be removed by, for example, dry etching.

[0060] Next, the patterned photoresist layer 170 may be removed. The patterned photoresist layer 170 may be removed by, for example, dry stripping or wet stripping.

[0061] Please refer to Figure 1E , a hard mask layer 172a may be formed between the sacrificial layers 168a in the memory array region R1 and between the sacrificial layers 168a and 168b. In addition, a hard mask layer 172b exposing the blocking layer 166c may be formed on the hard mask layer 154 in the peripheral circuit region R2. The material of the hard mask layer 172a and the hard mask layer 172b is, for example, a nitride, such as silicon nitride. The hard mask layer 172a and the hard mask layer 172b may be formed by, for example, first forming a hard mask material layer (not shown) and then performing an etch-back process on the hard mask material layer.

[0062] Please refer to Figure 1F, a termination layer 174 is formed in the memory array region R1 and the peripheral circuit region R2. That is, the termination layer 174 may extend from the memory array region R1 to the peripheral circuit region R2. The termination layer 174 is located above the bit line structure 104 and may be located above the contact window structure 124. The termination layer 174 may cover the sacrificial layer 168a, the sacrificial layer 168b and the hard mask layer 172a located in the memory array region R1, and may cover the barrier layer 166c and the hard mask layer 172b in the peripheral circuit region R2. The material of the termination layer 174 is, for example, a nitride, such as silicon nitride. The formation method of the termination layer 174 is, for example, a chemical vapor deposition method.

[0063] Next, a dielectric structure 176 may be formed on the termination layer 174. The dielectric structure 176 may include a dielectric layer 176a, a dielectric layer 176b, a dielectric layer 176c, and a dielectric layer 176d, but the present invention is not limited thereto. The material of the dielectric layer 176a and the dielectric layer 176c is, for example, an oxide, such as silicon oxide. The material of the dielectric layer 176b and the dielectric layer 176d is, for example, a nitride, such as silicon nitride. The dielectric layer 176a, the dielectric layer 176b, the dielectric layer 176c, and the dielectric layer 176d may be formed by, for example, chemical vapor deposition.

[0064] Please refer to Figure 1G , a patterned mask layer 178 may be formed on the dielectric structure 176. The material of the patterned mask layer 178 is, for example, polysilicon. The formation method of the patterned mask layer 178 may include a deposition process, a photolithography process, an etching process, a self-aligned double patterning (SADP) process, a patterning process using a hard mask layer, or a combination thereof.

[0065] Next, the patterned mask layer 178 may be used as a mask to remove a portion of the dielectric structure 176 and a portion of the termination layer 174, and an opening OP may be formed in the dielectric structure 176 and the termination layer 174. The opening OP exposes the sacrificial layer 168a located above the contact window structure 124. Thus, the termination layer 174 may be patterned to expose the sacrificial layer 168a located above the contact window structure 124. After the termination layer 174 is patterned, the termination layer 174 may cover the sacrificial layer 168b located at the edge of the memory array region R1 and not located above the contact window structure 124. The removal method of the portion of the dielectric structure 176 and the portion of the termination layer 174 is, for example, a dry etching method.

[0066] Please refer to Figure 1HAfter patterning the termination layer 174, the sacrificial layer 168a exposed by the opening OP may be removed, and the sacrificial layer 168b located at the edge of the memory array region R1 and not located above the contact window structure 124 may be left. After removing the sacrificial layer 168a exposed by the opening OP, the opening OP may extend toward the substrate 100, thereby increasing the depth of the opening OP, thereby increasing the capacitor structure 186 ( Fig. 1I ) of the overall height. The opening OP can expose the blocking layer 166a. The sacrificial layer 168a can be removed by, for example, dry etching.

[0067] In addition, after the termination layer 174 is patterned, the patterned mask layer 178 may be removed. The removal method of the patterned mask layer 178 is, for example, a dry etching method. In some embodiments, when the sacrificial layer 168a and the patterned mask layer 178 have similar etching rates in the etching process, the patterned mask layer 178 may be removed simultaneously in the process of removing the sacrificial layer 168a exposed by the opening OP, but the present invention is not limited thereto. In other embodiments, the sacrificial layer 168a and the patterned mask layer 178 may be removed by different etching processes.

[0068] Please refer to Fig. 1I , a capacitor structure 180 is formed in the memory array region R1. The capacitor structure 180 passes through the termination layer 174 and is electrically connected to the contact window structure 124. For example, the capacitor structure 180 can be electrically connected to the contact window structure 124 via the barrier layer 166a, the conductor layer 164a and the barrier layer 162a. In the present embodiment, the capacitor structure 180 can be a cylinder capacitor, but the present invention is not limited thereto. In addition, the method for forming a cylinder capacitor is well known to those having ordinary knowledge in the relevant technical field and is not described here. In the process of forming the capacitor structure 180, the dielectric structure 176 can be patterned, leaving the dielectric structure 176 located in the memory array region R1. In addition, in the process of forming the capacitor structure 180, the dielectric layer 176a and the dielectric layer 176c in the dielectric structure 176 can be removed.

[0069] The capacitor structure 180 includes an electrode 182, an insulating layer 184, and an electrode 186. The material of the electrode 182 is, for example, Ti, TiN, or a combination thereof. The electrode 186 is located on the electrode 182. The insulating layer 184 is located between the electrode 182 and the electrode 186. The material of the insulating layer 184 can be a dielectric material, such as a high-k material. The electrode 186 can be a single-layer structure or a multi-layer structure. In the present embodiment, the electrode 186 is an example of a multi-layer structure including a conductor layer 188, a conductor layer 190, and a conductor layer 192, but the present invention is not limited thereto. The conductor layer 188 is located on the insulating layer 184. The material of the conductor layer 188 is, for example, Ti, TiN, or a combination thereof. The conductor layer 190 is located on the conductor layer 188. The material of the conductor layer 190 is, for example, doped silicon germanium (SiGe). The conductor layer 192 is located on the conductor layer 190. The material of the conductor layer 192 is, for example, a metal such as tungsten.

[0070] In addition, a dielectric layer 194 may be formed on the capacitor structure 180. The material of the dielectric layer 194 is, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS) silicon oxide. The dielectric layer 194 may be formed by, for example, first forming a dielectric material layer using a deposition process (e.g., a chemical vapor deposition process) and then patterning the dielectric material layer.

[0071] Below, through Fig. 1I In addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

[0072] Please refer to Fig. 1I, the memory structure 10 includes a substrate 100, a bit line structure 104, a contact window structure 124, a termination layer 174 and a capacitor structure 186. The substrate 100 includes a memory array region R1. In addition, the substrate 100 may also include a peripheral circuit region R2. The bit line structure 104 is located in the memory array region R1 and is located on the substrate 100. The contact window structure 124 is located in the memory array region R1 and is located on the substrate 100 on one side of the bit line structure 104. The termination layer 174 is located in the memory array region R1 and is located above the bit line structure 104. The termination layer 174 may also be located in the peripheral circuit region R2. In addition, the top surface TS1 of the termination layer 174 located in the memory array region R1 may be higher than the top surface TS2 of the termination layer 174 located in the peripheral circuit region R2. The capacitor structure 186 is located in the memory array region R1 and is electrically connected to the contact window structure 124. The capacitor structure 186 passes through the termination layer 174 and is electrically connected to the contact window structure 124. The bottom surface BS1 of the capacitor structure 186 is lower than the bottom surface BS2 of the termination layer 174, so the overall height of the capacitor structure 186 can be increased, thereby increasing the capacitance area of ​​the capacitor structure 186. A portion of the capacitor structure 186 may be located in the opening OP.

[0073] In addition, the memory structure 10 may further include at least one of a sacrificial layer 168b, a dummy conductor layer 164b, a conductor layer 164a, and a hard mask layer 172a. The sacrificial layer 168b is located at the edge of the memory array region R1. The top surface TS3 of the sacrificial layer 168b and the bottom surface BS2 of the termination layer 174 located above the bit line structure 104 may be at the same height. A portion of the termination layer 174 may be directly disposed on the sacrificial layer 168b. That is, the termination layer 174 and the sacrificial layer 168b may be in direct contact. The dummy conductor layer 164b is located at the edge of the memory array region R1. The sacrificial layer 168b may be disposed on the dummy conductor layer 164b. The conductor layer 164a is disposed between the capacitor structure 186 and the contact window structure 124. The top surface TS4 of the conductor layer 164a and the top surface TS5 of the dummy conductor layer 164b may be at the same height.

[0074] The hard mask layer 172a is located between the termination layer 174 and the bit line structure 104. The capacitor structure 186 may be partially located in the hard mask layer 172a. In addition, the overall height of the capacitor structure 186 may be adjusted by the height H of the capacitor structure 186 located in the hard mask layer 172a, thereby increasing the capacitance area of ​​the capacitor structure 186. For example, the height H of the capacitor structure 186 located in the hard mask layer 172a may be greater than or equal to one-half of the thickness T of the hard mask layer.

[0075] The remaining components in the memory structure 10 can refer to the description of the above embodiment. In addition, the materials, configuration, formation method and function of each component in the memory structure 10 have been described in detail in the above embodiment and will not be described again here.

[0076] Based on the above embodiments, it can be known that in the memory structure 10 and the manufacturing method thereof, since the bottom surface BS1 of the capacitor structure 186 is lower than the bottom surface BS2 of the termination layer 174, the overall height of the capacitor structure 186 can be increased, thereby increasing the capacitance area of ​​the capacitor structure 186. Therefore, the capacitance of the capacitor structure 186 can be effectively increased, thereby improving the electrical performance of the memory element.

[0077] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any technician in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the claims.

Claims

1. A memory structure, It is characterized in that include: a substrate including a memory array region; a bit line structure located in the memory array region and on the substrate; A contact window structure, located in the memory array region and on the substrate at one side of the bit line structure; a termination layer located in the memory array region and above the bit line structure; A capacitor structure located in the memory array region, wherein the capacitor structure passes through the termination layer and is electrically connected to the contact window structure, and a bottom surface of the capacitor structure is lower than a bottom surface of the termination layer; A virtual conductor layer located at the edge of the memory array area; as well as A conductor layer is arranged between the capacitor structure and the contact window structure, wherein a top surface of the conductor layer is at the same height as a top surface of the virtual conductor layer.

2. The memory structure according to claim 1, It is characterized in that The substrate also includes a peripheral circuit area, The termination layer is also located in the peripheral circuit region, and A top surface of the termination layer located in the memory array region is higher than a top surface of the termination layer located in the peripheral circuit region.

3. The memory structure according to claim 1, It is characterized in that Also includes: A sacrificial layer is located at an edge of the memory array region, wherein a top surface of the sacrificial layer is at the same height as a bottom surface of the termination layer located above the bit line structure.

4. The memory structure according to claim 3, It is characterized in that The sacrificial layer is disposed on the dummy conductor layer.

5. The memory structure according to claim 1, It is characterized in that Also includes: A hard mask layer is located between the termination layer and the bit line structure, wherein the capacitor structure is partially located in the hard mask layer, and a height of the capacitor structure in the hard mask layer is greater than or equal to one half of the thickness of the hard mask layer.

6. A method for manufacturing a memory structure, It is characterized in that include: providing a substrate, wherein the substrate includes a memory array region; forming a bit line structure in the memory array region, wherein the bit line structure is located on the substrate; forming a contact window structure in the memory array region, wherein the contact window structure is located on the substrate at one side of the bit line structure; forming a termination layer in the memory array region, wherein the termination layer is located above the bit line structure; as well as A capacitor structure is formed in the memory array region, wherein The capacitor structure passes through the termination layer and is electrically connected to the contact window structure, and The bottom surface of the capacitor structure is lower than the bottom surface of the termination layer; forming a dummy conductor layer at the edge of the memory array area; as well as A first conductor layer is formed between the capacitor structure and the contact window structure, wherein a top surface of the first conductor layer is at the same height as a top surface of the dummy conductor layer.

7. The method for manufacturing a memory structure according to claim 6, It is characterized in that The substrate further includes a peripheral circuit area, and the method for manufacturing the memory structure further includes: forming a sacrificial material layer in the memory array region and the peripheral circuit region; Patterning the sacrificial material layer to form a plurality of sacrificial layers in the memory array region and the peripheral circuit region; removing the sacrificial layer located in the peripheral circuit area; forming the termination layer in the memory array region and the peripheral circuit region, wherein the termination layer covers the plurality of sacrificial layers located in the memory array region; and The stop layer is patterned to expose the sacrificial layer located above the contact window structure.

8. The method for manufacturing a memory structure according to claim 7, It is characterized in that The method for patterning the termination layer comprises: forming a dielectric structure on the termination layer; forming a patterned mask layer on the dielectric structure; and The patterned mask layer is used as a mask to remove a portion of the dielectric structure and a portion of the termination layer, thereby forming an opening in the dielectric structure and the termination layer, wherein the opening exposes the sacrificial layer located above the contact window structure.

9. The method for manufacturing a memory structure according to claim 8, It is characterized in that Also includes: After patterning the termination layer, the sacrificial layer exposed by the opening is removed, and the sacrificial layer located at the edge of the memory array area and not above the contact window structure is left, wherein the patterned mask layer is removed simultaneously in the process of removing the sacrificial layer exposed by the opening.

10. The method for manufacturing a memory structure according to claim 7, It is characterized in that After the termination layer is patterned, the termination layer covers the sacrificial layer located at the edge of the memory array region and not located above the contact window structure.

11. The method for manufacturing a memory structure according to claim 7, It is characterized in that Also includes: Before forming the sacrificial material layer, forming a conductor material layer in the memory array area and the peripheral circuit area; as well as The conductor material layer is patterned to form the first conductor layer located above the contact window structure in the memory array area, the dummy conductor layer not located above the contact window structure is formed in the memory array area, and the second conductor layer is formed in the peripheral circuit area, wherein After forming the plurality of sacrificial layers, the plurality of sacrificial layers are respectively located above the first conductor layer, the dummy conductor layer and the second conductor layer.

12. The method for manufacturing a memory structure according to claim 7, It is characterized in that Also includes: Before forming the termination layer, a hard mask layer is formed between the plurality of sacrificial layers in the memory array region, wherein After the termination layer is formed, the termination layer covers the plurality of sacrificial layers and the hard mask layer in the memory array region.

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