Inverter

Abstract

An inverter includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor includes a first gate, a first semiconductor structure, a first source, and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region. The thickness of the first source region is greater than the thickness of the first channel region and the thickness of the first drain region. The second thin film transistor includes a second gate, a second semiconductor structure, a second source, and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region. The thickness of the second channel region is greater than the thickness of the second source region and the thickness of the second drain region. The second drain is electrically connected to the first source.

Description

Technical Field

[0001] The present invention relates to an inverter. Background Art

[0002] An inverter is a device that can convert direct current into alternating current. Common inverters include N-type inverters and P-type inverters. Among them, the N-type inverter includes N-type transistors, while the P-type inverter includes P-type transistors.

[0003] Currently, silicon semiconductor materials are often used to fabricate transistors used in power supply devices. In some applications of inverters, one or more NMOS transistors or PMOS transistors are usually included. Metal oxide semiconductor materials (such as indium gallium zinc oxide) have the advantages of being easy to fabricate over a large area and having a low process temperature. Therefore, in recent years, many manufacturers have been committed to replacing silicon semiconductor materials with metal oxide semiconductor materials as the channels of transistors. However, how to apply metal oxide semiconductor materials to inverters is still a topic that many manufacturers are committed to developing. Summary of the Invention

[0004] The present invention provides an inverter with the advantage of a small area.

[0005] At least one embodiment of the present invention provides an inverter. The inverter includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the substrate. The first thin film transistor includes a first gate, a first semiconductor structure, a first source, and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. The first gate overlaps the first channel region. The thickness of the first source region is greater than the thickness of the first channel region and the thickness of the first drain region. The first source is electrically connected to the first source region. The first drain is electrically connected to the first drain region and the first gate. The second thin film transistor includes a second gate, a second semiconductor structure, a second source, and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region. The second gate overlaps the second channel region. The thickness of the second channel region is greater than the thickness of the second source region and the thickness of the second drain region. The second source is electrically connected to the second source region. The second drain is electrically connected to the second drain region and the first source.

[0006] At least one embodiment of the present invention provides an inverter. The inverter includes a substrate, a first thin-film transistor, and a second thin-film transistor. The first thin-film transistor and the second thin-film transistor are located on the substrate. The first thin-film transistor includes a first gate, a first semiconductor structure, a first source, and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region. The first gate overlaps the first channel region. The thickness of the first channel region is greater than the thickness of the first source region and the thickness of the first drain region. The first source is electrically connected to the first source region and the first gate. The first drain is electrically connected to the first drain region. The second thin-film transistor includes a second gate, a second semiconductor structure, a second source, and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region. The second gate overlaps the second channel region, and the thickness of the second source region is greater than the thickness of the second channel region and the thickness of the second drain region. The second source is electrically connected to the second source region. The second drain is electrically connected to the second drain region and the first source. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention.

[0008] Figures 2A to 2D is Figure 1 a cross-sectional schematic diagram of a manufacturing method of the inverter.

[0009] Figure 3 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention.

[0010] Figures 4A to 4D is Figure 3 a cross-sectional schematic diagram of a manufacturing method of the inverter.

[0011] Figure 5 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention.

[0012] Figure 6 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention.

[0013] Figure 7A is a circuit schematic diagram of an inverter according to an embodiment of the present invention.

[0014] Figure 7B is Figure 7A a schematic diagram of the output voltage and input voltage of the inverter.

[0015] Figure 8A is a circuit schematic diagram of an inverter according to an embodiment of the present invention.

[0016] Figure 8B is Figure 8A a schematic diagram of the output voltage and input voltage of the inverter.

[0017] Description of reference numerals:

[0018] 10A, 10B, 10C, 10D: Inverters

[0019] 100: Substrate

[0020] 110: Buffer layer

[0021] 120: Gate dielectric layer

[0022] 130: Interlayer dielectric layer

[0023] TL: First thin film transistor

[0024] TS: Second thin film transistor

[0025] ch1: First channel region

[0026] ch2: Second channel region

[0027] D1 First drain

[0028] D2 Second drain

[0029] dr1: First drain region

[0030] dr2: Second drain region

[0031] G1: First gate

[0032] G2: Second gate

[0033] HD1, HD2: Horizontal distance

[0034] L: Signal line

[0035] ND: Normal direction

[0036] OS1A, OS1A’: First metal oxide layer

[0037] OS1B, OS1B’: Second metal oxide layer

[0038] OS2A, OS2A’: First metal oxide pattern

[0039] OS2B: Second metal oxide pattern

[0040] R L , R S : Equivalent resistance value

[0041] S1: First source

[0042] S2: Second source electrode

[0043] SM1: First semiconductor structure

[0044] SM2: Second semiconductor structure

[0045] sr1: First source region

[0046] sr2: Second source region

[0047] t1, t2: Thickness

[0048] V1: First contact hole

[0049] V2: Second contact hole

[0050] V3: Third contact hole

[0051] V4: Fourth contact hole

[0052] V5: Fifth contact hole

[0053] V6: Sixth contact hole

[0054] V DD : Voltage

[0055] V in : Input voltage

[0056] V out : Output voltage

[0057] GND: Ground voltage Detailed implementation manners

[0058] Figure 1 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention

[0059] Please refer to Figure 1 , the inverter 10A includes a substrate 100, a first thin film transistor TL, and a second thin film transistor TS

[0060] The material of the substrate 100 can be glass, quartz, organic polymer, or light-impermeable / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. When using conductive material or metal, an insulating layer (not shown) is covered on the substrate 100 to avoid short-circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.

[0061] The buffer layer 110 is located on the substrate 100. The buffer layer 110 has a single-layer or multi-layer structure, and the material of the buffer layer 110 can include silicon oxide, silicon oxynitride, or other suitable materials or a stacked layer of the above materials.

[0062] The first thin-film transistor TL and the second thin-film transistor TS are located on the substrate 100. In this embodiment, the first thin-film transistor TL and the second thin-film transistor TS are located on the buffer layer 110.

[0063] The first thin-film transistor TL includes a first gate G1, a first semiconductor structure SM1, a first source S1, and a first drain D1. The second thin-film transistor TS includes a second gate G2, a second semiconductor structure SM2, a second source S2, and a second drain D2.

[0064] The first semiconductor structure SM1 is located on the buffer layer 110. The first semiconductor structure SM1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. The thickness of the first source region sr1 (e.g., the thickness t2 plus the thickness t1) is greater than the thickness of the first channel region ch1 (e.g., the thickness t1) and the thickness of the first drain region dr1 (e.g., the thickness t1).

[0065] The first semiconductor structure SM1 includes a stack of a first metal oxide layer OS1A and a first metal oxide pattern OS2A. The first metal oxide layer OS1A is disposed in a first source region sr1, a first drain region dr1, and a first channel region ch1. The first metal oxide pattern OS2A is disposed in the first source region sr1. The first metal oxide pattern OS2A does not extend to the first drain region dr1 and the first channel region ch1. In this embodiment, the first metal oxide layer OS1A coats the sidewalls and the top surface of the first metal oxide pattern OS2A, and the first metal oxide pattern OS2A is located between the first metal oxide layer OS1A and the substrate 100.

[0066] The second semiconductor structure SM2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 located between the second source region sr2 and the second drain region dr2. The thickness of the second channel region ch2 (e.g., the thickness t2 plus the thickness t1) is greater than the thickness of the second source region sr2 (e.g., the thickness t1) and the thickness of the second drain region dr2 (e.g., the thickness t1).

[0067] The second semiconductor structure SM2 includes a stack of a second metal oxide layer OS1B and a second metal oxide pattern OS2B. The second metal oxide layer OS1B is disposed in the second source region sr2, the second drain region dr2, and the second channel region ch2. The second metal oxide pattern OS2B is disposed in the second channel region ch2. The second metal oxide pattern OS2B does not extend to the second source region sr2 and the second drain region dr2. In this embodiment, the second metal oxide layer OS1B coats the sidewalls and the top surface of the second metal oxide pattern OS2B, and the second metal oxide pattern OS2B is located between the second metal oxide layer OS1B and the substrate 100.

[0068] In some embodiments, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B belong to the same film layer. In other words, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B are defined in the same patterning process. The first metal oxide pattern OS2A and the second metal oxide pattern OS2B include the same thickness and the same material. In some embodiments, the thickness t2 of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B is 5 nanometers to 25 nanometers. In some embodiments, the material of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B includes indium tungsten zinc oxide, indium gallium zinc oxide, or other metal oxides. In some embodiments, the first metal oxide pattern OS2A is doped to have a resistivity lower than that of the second metal oxide pattern OS2B.

[0069] In some embodiments, the first metal oxide layer OS1A and the second metal oxide layer OS1B belong to the same film layer. In other words, the first metal oxide layer OS1A and the second metal oxide layer OS1B are defined in the same patterning process. The first metal oxide layer OS1A and the second metal oxide layer OS1B have the same thickness and the same material. In some embodiments, the thickness t1 of the first metal oxide layer OS1A and the second metal oxide layer OS1B is 15 nanometers to 25 nanometers. In some embodiments, the material of the first metal oxide layer OS1A and the second metal oxide layer OS1B includes indium gallium zinc oxide or other metal oxides. In some embodiments, in the first metal oxide layer OS1A, the first drain region dr1 and the first source region dr1 are doped to have a resistivity lower than that of the first channel region ch1. Similarly, in the second metal oxide layer OS1B, the second drain region dr2 and the second source region dr2 are doped to have a resistivity lower than that of the second channel region ch2. Additionally, in the second channel region ch2, the carrier mobility of the second metal oxide pattern OS2B is greater than or equal to the carrier mobility of the second metal oxide layer OS1B.

[0070] Based on the above, by disposing the second metal oxide pattern OS2B in the second channel region ch2, the equivalent resistance R of the second thin film transistor TS can be reduced. S , therefore, it is not necessary to increase the length of the first channel region ch1 of the first thin film transistor TL to increase the equivalent resistance R of the first thin film transistor TL. L and the equivalent resistance R of the second thin film transistor TS. S The ratio (R L / R S ) makes the inverter 10A have the advantage of small area.

[0071] The gate dielectric layer 120 is located on the first semiconductor structure SM1 and the second semiconductor structure SM2. In this embodiment, the gate dielectric layer 120 is directly formed on the first semiconductor structure SM1 and the second semiconductor structure SM2. In some embodiments, the material of the gate dielectric layer 120 includes silicon oxide, silicon oxynitride, hafnium oxide, or other suitable materials or a stacked layer of the above materials.

[0072] The first gate G1 and the second gate G2 are located on the gate dielectric layer 120. In this embodiment, the first gate G1 and the second gate G2 are directly formed on the gate dielectric layer 120. The first gate G1 overlaps the first channel region ch1 in the normal direction ND of the upper surface of the substrate 100. The second gate G2 overlaps the second channel region ch2 in the normal direction ND of the upper surface of the substrate 100. In some embodiments, the horizontal distance HD1 between the sidewall of the first metal oxide pattern OS2A and the sidewall of the first gate G1 is less than 300 nanometers, and the horizontal distance HD2 between the sidewall of the second metal oxide pattern OS2B and the sidewall of the second gate G2 is less than 300 nanometers.

[0073] In some embodiments, the materials of the first gate G1 and the second gate G2 may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first gate G1 and the second gate G2 may also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stacked layers of metals and other conductive materials, or other materials with conductive properties.

[0074] The interlayer dielectric layer 130 is located on the first gate G1, the second gate G2, and the gate dielectric layer 120. In some embodiments, the material of the interlayer dielectric layer 130 includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, or other suitable materials or stacks of the above materials.

[0075] The interlayer dielectric layer 130 has a first contact hole V1, a second contact hole V2, a third contact hole V3, a fourth contact hole V4, a fifth contact hole V5, and a sixth contact hole V6. In this embodiment, the first contact hole V1, the third contact hole V3, the fourth contact hole V4, and the sixth contact hole V6 penetrate through the interlayer dielectric layer 130 and the gate dielectric layer 120, while the second contact hole V2 and the fifth contact hole V5 penetrate through the interlayer dielectric layer 130.

[0076] The first source S1, the first drain D1, the second source S2, the second drain D2, and the signal line L are located on the interlayer dielectric layer 130. The first drain D1 fills the first contact hole V1 to electrically connect to the first drain region dr1, and the first drain D1 fills the second contact hole V2 to electrically connect to the first gate G1. The first source S1 fills the third contact hole V3 to electrically connect to the first source region sr1. The second drain D2 fills the fourth contact hole V4 to electrically connect to the second drain region dr2, and the second drain D2 is electrically connected to the first source S1. The signal line L fills the fifth contact hole V5 to electrically connect to the second gate G2. The second source S2 fills the sixth contact hole V6 to electrically connect to the second source region sr2.

[0077] In this embodiment, due to the setting of the first metal oxide pattern OS2A, the first source region sr1 has a lower resistivity, thereby reducing the impedance between the first source S1 and the first source region sr1. In addition, by setting the first metal oxide pattern OS2A in the first source region sr1, the thickness of the first source region sr1 is greater than the thickness of the first channel region ch1, which can disperse the electric field between the first channel region ch1 and the first source S1, thereby reducing the contact impedance between the first source S1 and the first metal oxide pattern OS2A. Furthermore, by setting the second metal oxide pattern OS2B in the second channel region ch2, the thickness of the second channel region ch1 is greater than the thickness of the second drain region dr2, which can disperse the electric field between the second drain D2 and the second channel region ch2, thereby reducing the hot carrier effect.

[0078] Figures 2A to 2D is Figure 1 a cross-sectional schematic diagram of a manufacturing method of an inverter.

[0079] Please refer to Figure 2A , and form the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B on the substrate 100. In some embodiments, the method of forming the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B includes a photolithography etching process. The first metal oxide pattern OS2A' and the second metal oxide pattern OS2B belong to the same film layer, and the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B include the same material and the same thickness.

[0080] Please refer to Figure 2B, a first metal oxide layer OS1A’ and a second metal oxide layer OS1B’ are formed on the first metal oxide pattern OS2A’, the second metal oxide pattern OS2B, and the substrate 100, where the first metal oxide layer OS1A’ covers the first metal oxide pattern OS2A’, and the second metal oxide layer OS1B’ covers the second metal oxide pattern OS2B. In some embodiments, the method of forming the first metal oxide layer OS1A’ and the second metal oxide layer OS1B’ includes a photolithography etching process.

[0081] For example, a metal oxide material layer (not shown) is formed to blanket the first metal oxide pattern OS2A’, the second metal oxide pattern OS2B, and the buffer layer 110; a patterned photoresist (not shown) is formed on the surface of the metal oxide material layer; the metal oxide material layer is etched using the patterned photoresist as a mask to form the first metal oxide layer OS1A’ and the second metal oxide layer OS1B’; the patterned photoresist is removed. The first metal oxide layer OS1A’ and the second metal oxide layer OS1B’ belong to the same film layer, and the first metal oxide layer OS1A’ and the second metal oxide layer OS1B’ include the same material and the same thickness.

[0082] In this embodiment, since the first metal oxide layer OS1A’ covers the first metal oxide pattern OS2A’, and the second metal oxide layer OS1B’ covers the second metal oxide pattern OS2B, the etching solution used for etching the metal oxide material layer will not damage the surfaces of the first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B, thereby improving the yield of the semiconductor structure.

[0083] Please refer to Figure 2B and 2C , a gate dielectric layer 120 is formed on the first metal oxide layer OS1A’ and the second metal oxide layer OS1B’. A first gate G1 and a second gate G2 are formed on the gate dielectric layer 120. Using the first gate G1 and the second gate G2 as masks, a doping process P is performed to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1, and a first channel region ch1 and a second semiconductor structure SM2 including a second source region sr2, a second drain region dr2, and a second channel region ch2. In this embodiment, since the first metal oxide pattern OS2A is not shielded by the gate, the first metal oxide pattern OS2A is doped to have a resistivity lower than that of the second metal oxide pattern OS2B. In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

[0084] Please refer to Figure 2D, an interlayer dielectric layer 130 is formed over the first gate G1, the second gate G2, and the gate dielectric layer 120. First vias V1 to sixth vias V6 are formed in the interlayer dielectric layer 130.

[0085] Finally, please return to Figure 1 , a first source S1, a first drain D1, a second source S2, a second drain D2, and a signal line L are formed over the interlayer dielectric layer 130. In this embodiment, the first source S1 and the first drain D1 are connected to a first metal oxide layer OS1A, and the second source S2 and the second drain D2 are connected to a second metal oxide layer OS1B. Thus, the inverter 10A is substantially completed.

[0086] Figure 3 FIG. is a cross-sectional schematic view of an inverter according to an embodiment of the present invention. It should be noted here that Figure 3 The embodiment of Figure 1 adopts the component numbers and some contents of the embodiment of

[0087] Figure 3 The main difference between the inverter 10B of Figure 1 and the semiconductor device 10A of

[0088] Figures 4A to 4D is that Figure 3 the first metal oxide layer OS1A of the inverter 10B is located between the first metal oxide pattern OS2A and the substrate 100, and the second metal oxide layer OS1B is located between the second metal oxide pattern OS2B and the substrate 100.

[0089] Please refer to Figure 4A , a first metal oxide layer OS1A' and a second metal oxide layer OS1B' are formed over the substrate 100. In some embodiments, the method of forming the first metal oxide layer OS1A' and the second metal oxide layer OS1B' includes a photolithography etching process. The first metal oxide layer OS1A' and the second metal oxide layer OS1B' belong to the same film layer, and the first metal oxide layer OS1A' and the second metal oxide layer OS1B' include the same material and the same thickness.

[0090] Please refer to Figure 2B, a first metal oxide pattern OS2A’ and a second metal oxide pattern OS2B are formed on a first metal oxide layer OS1A’ and a second metal oxide layer OS1B’, wherein the first metal oxide pattern OS2A’ exposes a partial upper surface of the first metal oxide layer OS1A’, and the second metal oxide pattern OS2B exposes a partial upper surface of the second metal oxide layer OS1B’. In some embodiments, the method of forming the first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B includes a photolithography etching process.

[0091] For example, a metal oxide material layer (not shown) is formed to blanket the first metal oxide layer OS1A’, the second metal oxide layer OS1B’, and the buffer layer 110; a patterned photoresist (not shown) is formed on the surface of the metal oxide material layer; the metal oxide material layer is etched using the patterned photoresist as a mask to form the first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B; and the patterned photoresist is removed. The first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B belong to the same film layer, and the first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B include the same material and the same thickness.

[0092] Please refer to Figure 4B and 4C , a gate dielectric layer 120 is formed on the first metal oxide layer OS1A’, the second metal oxide layer OS1B’, the first metal oxide pattern OS2A’ and the second metal oxide pattern OS2B. A first gate G1 and a second gate G2 are formed on the gate dielectric layer 120. Using the first gate G1 and the second gate G2 as masks, a doping process P is performed to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1, and a first channel region ch1 and a second semiconductor structure SM2 including a second source region sr2, a second drain region dr2, and a second channel region ch2. In this embodiment, since the first metal oxide pattern OS2A is not shielded by the gate, the first metal oxide pattern OS2A is doped to have a resistivity lower than that of the second metal oxide pattern OS2B. In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

[0093] Please refer to Figure 4D , an interlayer dielectric layer 130 is formed on the first gate G1, the second gate G2, and the gate dielectric layer 120. First vias V1 to sixth vias V6 are formed in the interlayer dielectric layer 130.

[0094] Finally, please return to Figure 3, a first source electrode S1, a first drain electrode D1, a second source electrode S2, a second drain electrode D2, and a signal line L are formed on the interlayer dielectric layer 130. In this embodiment, the first source electrode S1 is connected to the first metal oxide pattern OS2A, the first drain electrode D1 is connected to the first metal oxide layer OS1A, and the second source electrode S2 and the second drain electrode D2 are connected to the second metal oxide layer OS1B. So far, the inverter 10B is substantially completed.

[0095] Figure 5 is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention. It must be noted here that Figure 5 The embodiment of Figure 1 adopts the component numbers and some contents of the embodiment of

[0096] Figure 5 The main difference between the inverter 10C of Figure 1 and the semiconductor device 10A of

[0097] Please refer to Figure 5 , the first semiconductor structure SM1 includes a stack of a first metal oxide layer OS1A and a first metal oxide pattern OS2A. The first metal oxide layer OS1A is disposed in the first source region sr1, the first drain region dr1, and the first channel region ch1. The first metal oxide pattern OS2A is disposed in the first channel region ch1. The first metal oxide pattern OS2A does not extend to the first drain region dr1 and the first source region sr1. In this embodiment, the first metal oxide layer OS1A covers the sidewalls and the top surface of the first metal oxide pattern OS2A, and the first metal oxide pattern OS2A is located between the first metal oxide layer OS1A and the substrate 100.

[0098] The second semiconductor structure SM2 includes a stack of a second metal oxide layer OS1B and a second metal oxide pattern OS2B. The second metal oxide layer OS1B is disposed in a second source region sr2, a second drain region dr2, and a second channel region ch2. The second metal oxide pattern OS2B is disposed in the second source region sr2. The second metal oxide pattern OS2B does not extend to the second drain region dr2 and the second channel region ch2. In this embodiment, the second metal oxide layer OS1B coats the sidewalls and the top surface of the second metal oxide pattern OS2B, and the second metal oxide pattern OS2B is located between the second metal oxide layer OS1B and the substrate 100.

[0099] In some embodiments, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B belong to the same film layer. In other words, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B are defined in the same patterning process. The first metal oxide pattern OS2A and the second metal oxide pattern OS2B have the same thickness and the same material. In some embodiments, the thickness t2 of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B is 5 nanometers to 25 nanometers. In some embodiments, the material of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B includes indium tungsten zinc oxide, indium gallium zinc oxide, or other metal oxides. In some embodiments, the second metal oxide pattern OS2B is doped to have a resistivity lower than that of the first metal oxide pattern OS2A.

[0100] In some embodiments, the first metal oxide layer OS1A and the second metal oxide layer OS1B belong to the same film layer. In other words, the first metal oxide layer OS1A and the second metal oxide layer OS1B are defined in the same patterning process. The first metal oxide layer OS1A and the second metal oxide layer OS1B have the same thickness and the same material. In some embodiments, the thickness t1 of the first metal oxide layer OS1A and the second metal oxide layer OS1B is 15 nanometers to 25 nanometers. In some embodiments, the material of the first metal oxide layer OS1A and the second metal oxide layer OS1B includes indium gallium zinc oxide or other metal oxides. In some embodiments, in the first metal oxide layer OS1A, the first drain region dr1 and the first source region dr1 are doped to have a resistivity lower than that of the first channel region ch1. Similarly, in the second metal oxide layer OS1B, the second drain region dr2 and the second source region dr2 are doped to have a resistivity lower than that of the second channel region ch2. Additionally, in the first channel region ch1, the carrier mobility of the first metal oxide pattern OS2A is greater than or equal to the carrier mobility of the first metal oxide layer OS1A.

[0101] In some embodiments, the horizontal distance HD1 between the sidewall of the first metal oxide pattern OS2A and the sidewall of the first gate G1 is less than 300 nanometers, and the horizontal distance HD2 between the sidewall of the second metal oxide pattern OS2B and one sidewall of the second gate G2 is less than 300 nanometers.

[0102] Based on the above, by disposing the first metal oxide pattern OS2A in the first channel region ch1, the equivalent resistance value R of the first thin film transistor TL can be reduced. L Therefore, it is not necessary to increase the length of the second channel region ch2 of the second thin film transistor TS to reduce the equivalent resistance value R of the first thin film transistor TL. L Compared with the equivalent resistance value R of the second thin film transistor TS. S The ratio (R L / R S ) enables the inverter 10C to have the advantage of a small area.

[0103] In addition, due to the setting of the second metal oxide pattern OS2B, the second source region sr2 has a low resistivity, thereby reducing the impedance between the second source S2 and the second source region sr2. Additionally, by disposing the second metal oxide pattern OS2B in the second source region sr2, the thickness of the second source region sr2 is greater than the thickness of the second channel region ch2, which can disperse the electric field between the second channel region ch2 and the second source S2, thereby reducing the contact impedance between the second source S2 and the second metal oxide pattern OS2B. Furthermore, by disposing the first metal oxide pattern OS2A in the first channel region ch1, the thickness of the first channel region ch1 is greater than the thickness of the first drain region dr1, which can disperse the electric field between the first drain D1 and the first channel region ch1, thereby reducing the hot carrier effect.

[0104] Figure 6 FIG. is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention. It should be noted here that Figure 6 The embodiment of Figure 5 follows the component numbers and partial content of the embodiment of

[0105] Figure 6 The main difference between the inverter 10D of Figure 5 and the semiconductor device 10C of

[0106] Figure 7A is that the first metal oxide layer OS1A of the inverter 10D is located between the first metal oxide pattern OS2A and the substrate 100, and the second metal oxide layer OS1B is located between the second metal oxide pattern OS2B and the substrate 100.It is a circuit schematic diagram of an inverter according to an embodiment of the present invention. Figure 7B is Figure 7A a schematic diagram of the output voltage and input voltage of the inverter.

[0107] Figure 7A For the specific structure of the inverter, reference can be made to Figure 1 the inverter 10A and Figure 3 the inverter 10B, which will not be elaborated here.

[0108] The first drain D1 of the first thin film transistor TL2 is electrically connected to the voltage V DD . The first gate G1 and the first source S1 of the first thin film transistor TL2 are electrically connected to the second drain D2 of the second thin film transistor TS, and the first source S1, the first gate G1, and the second drain D2 are connected to the output voltage V out . The input voltage V in is connected to the second gate G2 of the second thin film transistor TS through the signal line L. The second source S2 of the second thin film transistor TS is connected to the ground voltage GND.

[0109] In this embodiment, both the first thin film transistor TL and the second thin film transistor TS are enhancement-mode transistors. The equivalent resistance R L of the first thin film transistor TL is different from the equivalent resistance R S of the second thin film transistor TS. The ratio (R L / R S ) of the equivalent resistance R L to the equivalent resistance R S will affect the characteristics of the inverter. When R L / R S is high, the inverter is suitable for processing digital signals; when R L / R S is low, the inverter is suitable for processing analog signals.

[0110] In this embodiment, by disposing a second metal oxide pattern OS2B in the second channel region ch2 (please refer to Figure 1 and Figure 3 ), the equivalent resistance R S of the second thin film transistor TS can be reduced, thereby changing R L / R S . In other words, without adjusting the length and width of the first channel region ch1 or the length and width of the second channel region ch2, R L / R S can be changed, thereby adjusting the characteristics of the inverter.

[0111] Figure 8A It is a circuit schematic diagram of an inverter according to an embodiment of the present invention. Figure 8B is Figure 8A a schematic diagram of the output voltage and input voltage of the inverter.

[0112] Figure 8A For the specific structure of the inverter, reference can be made to Figure 5 the inverter 10C and Figure 6 the inverter 10D, which will not be elaborated here.

[0113] The first drain D1 of the first thin film transistor TL2 is electrically connected to the voltage V DD . The first gate G1 and the first source S1 of the first thin film transistor TL2 are electrically connected to the second drain D2 of the second thin film transistor TS, and the first source S1, the first gate G1, and the second drain D2 are connected to the output voltage V out . The input voltage V in is connected to the second gate G2 of the second thin film transistor TS through the signal line L. The second source S2 of the second thin film transistor TS is connected to the ground voltage GND.

[0114] In this embodiment, the first thin film transistor TL is a depletion type transistor, while the second thin film transistor TS is an enhancement type transistor. The equivalent resistance value R L of the first thin film transistor TL is different from the equivalent resistance value R S of the second thin film transistor TS. The ratio (R L / R S ) of the equivalent resistance value R L to the equivalent resistance value R S will affect the characteristics of the inverter. When R L / R S is high, the inverter is suitable for processing digital signals. When R L / R S is low, the inverter is suitable for processing analog signals.

[0115] In this embodiment, by disposing a first metal oxide pattern OS2A in the first channel region ch1 (please refer to Figure 5 and Figure 6 ), the equivalent resistance value R L of the first thin film transistor TL can be reduced, and thus R L / R S can be changed. In other words, without adjusting the length and width of the first channel region ch1 or the length and width of the second channel region ch2, R L / R S can be changed, thereby adjusting the characteristics of the inverter.

Claims

1. An inverter, comprising: A substrate; A first thin film transistor, located on the substrate, and comprising: A first gate; A first semiconductor structure, including a first source region, a first drain region, and a first channel region located between the first source region and the first drain region, wherein the first gate overlaps the first channel region, and the thickness of the first source region is greater than the thickness of the first channel region and the thickness of the first drain region; A first source, electrically connected to the first source region; and A first drain, electrically connected to the first drain region and the first gate; and A second thin film transistor, located on the substrate, and comprising: A second gate; A second semiconductor structure, including a second source region, a second drain region, and a second channel region located between the second source region and the second drain region, wherein the second gate overlaps the second channel region, and the thickness of the second channel region is greater than the thickness of the second source region and the thickness of the second drain region; A second source, electrically connected to the second source region; and A second drain, electrically connected to the second drain region and the first source.

2. The inverter according to claim 1, wherein the first semiconductor structure comprises a stack of a first metal oxide layer and a first metal oxide pattern, wherein the first metal oxide layer is disposed in the first source region, the first drain region, and the first channel region, and the first metal oxide pattern is disposed in the first source region.

3. The inverter according to claim 2, wherein the second semiconductor structure comprises a stack of a second metal oxide layer and a second metal oxide pattern, wherein the second metal oxide layer is disposed in the second source region, the second drain region, and the second channel region, and the second metal oxide pattern is disposed in the second channel region.

4. The inverter according to claim 3, wherein in the second channel region, the carrier mobility of the second metal oxide pattern is greater than or equal to the carrier mobility of the second metal oxide layer.

5. The inverter according to claim 3, wherein the thicknesses of the first metal oxide layer and the second metal oxide layer are 15 nanometers to 25 nanometers, and the thicknesses of the first metal oxide pattern and the second metal oxide pattern are 5 nanometers to 25 nanometers.

6. The inverter according to claim 3, wherein the horizontal distance between one sidewall of the first metal oxide pattern and one sidewall of the first gate is less than 300 nanometers, and the horizontal distance between one sidewall of the second metal oxide pattern and one sidewall of the second gate is less than 300 nanometers.

7. The inverter according to claim 3, wherein the first metal oxide layer covers the sidewalls and the top surface of the first metal oxide pattern, and the second metal oxide layer covers the sidewalls and the top surface of the second metal oxide pattern.

8. The inverter according to claim 3, wherein the first metal oxide layer is located between the first metal oxide pattern and the substrate, and the second metal oxide layer is located between the second metal oxide pattern and the substrate.

9. An inverter, comprising: A substrate; A first thin film transistor, located on the substrate, and comprising: A first gate; A first semiconductor structure, including a first source region, a first drain region, and a first channel region located between the first source region and the first drain region, wherein the first gate overlaps the first channel region, and the thickness of the first channel region is greater than the thickness of the first source region and the thickness of the first drain region; A first source, electrically connected to the first source region and the first gate; and A first drain, electrically connected to the first drain region; and A second thin film transistor, located on the substrate, and comprising: A second gate; A second semiconductor structure, including a second source region, a second drain region, and a second channel region located between the second source region and the second drain region, wherein the second gate overlaps the second channel region, and the thickness of the second source region is greater than the thickness of the second channel region and the thickness of the second drain region; A second source, electrically connected to the second source region; and A second drain, electrically connected to the second drain region and the first source.

10. The inverter according to claim 9, wherein the first semiconductor structure comprises a stack of a first metal oxide layer and a first metal oxide pattern, wherein the first metal oxide layer is disposed in the first source region, the first drain region, and the first channel region, and the first metal oxide pattern is disposed in the first channel region.

11. The inverter according to claim 10, wherein the second semiconductor structure comprises a stack of a second metal oxide layer and a second metal oxide pattern, wherein the second metal oxide layer is disposed in the second source region, the second drain region, and the second channel region, and the second metal oxide pattern is disposed in the second source region.

12. The inverter according to claim 11, wherein in the first channel region, the carrier mobility of the first metal oxide pattern is greater than or equal to the carrier mobility of the first metal oxide layer.

13. The inverter according to claim 11, wherein the thicknesses of the first metal oxide layer and the second metal oxide layer are 15 nanometers to 25 nanometers, and the thicknesses of the first metal oxide pattern and the second metal oxide pattern are 5 nanometers to 25 nanometers.

14. The inverter according to claim 11, wherein the horizontal distance between one sidewall of the first metal oxide pattern and one sidewall of the first gate is less than 300 nanometers, and the horizontal distance between one sidewall of the second metal oxide pattern and one sidewall of the second gate is less than 300 nanometers.

15. The inverter according to claim 11, wherein the first metal oxide layer coats sidewalls and a top surface of the first metal oxide pattern, and the second metal oxide layer coats sidewalls and a top surface of the second metal oxide pattern.

16. The inverter according to claim 11, wherein the first metal oxide layer is located between the first metal oxide pattern and the substrate, and the second metal oxide layer is located between the second metal oxide pattern and the substrate.

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