Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. In the semiconductor device, a plurality of p-type semiconductor layers is stacked on one surface side of an n-type gallium oxide semiconductor layer so as to be in contact with the n-type gallium oxide semiconductor layer, a first electrode body layer is stacked on the one surface side of the n-type gallium oxide semiconductor layer so as to be in contact with the plurality of p-type semiconductor layers and the n-type gallium oxide semiconductor layer at portions where the plurality of p-type semiconductor layers are separated from each other, a second electrode body layer is stacked on the other surface side of the n-type gallium oxide semiconductor layer so as to be in contact with the n-type gallium oxide semiconductor layer, and a shortest distance between each of the p-type semiconductor layers and the closest p-type semiconductor layer with respect to each of the p-type semiconductor layers is 0.4 µm to 1.0 µm.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] Japanese Patent Application Publication No. 2019-36593 discloses a semiconductor device having a heterojunction of an n-type gallium oxide semiconductor and a p-type semiconductor, and more specifically, a junction barrier Schottky (JBS) diode using an n-type gallium oxide semiconductor and a p-type semiconductor. This document describes that the width of the mesa-shaped portion of the trench structure possessed by the n-type gallium oxide semiconductor is preferably 0.25 μm to 5 μm. SUMMARY

[0003] For example, in a semiconductor device having a heterojunction of an n-type gallium oxide semiconductor and a p-type semiconductor such as that disclosed in Japanese Patent Application Publication No. 2019-36593, it is required to simultaneously achieve an increase in withstand voltage and a reduction in resistance.

[0004] An object of the present disclosure is to provide a semiconductor device that simultaneously achieves an increase in withstand voltage and a reduction in resistance.

[0005] The present disclosure has found that the above problem can be solved by the following means:

[0006] <Embodiment 1>

[0007] A semiconductor device having a first electrode body layer, a plurality of p-type semiconductor layers, an n-type gallium oxide semiconductor layer, and a second electrode body layer,

[0008] The plurality of p-type semiconductor layers are stacked on one face side of the n-type gallium oxide semiconductor layer so as to be in contact with the n-type gallium oxide semiconductor layer,

[0009] The first electrode body layer is stacked on the one face side of the n-type gallium oxide semiconductor layer so as to be in contact with the plurality of p-type semiconductor layers and the n-type gallium oxide semiconductor layer at portions where the plurality of p-type semiconductor layers are separated from each other,

[0010] The second electrode body layer is stacked on the other face side of the n-type gallium oxide semiconductor layer so as to be in contact with the n-type gallium oxide semiconductor layer, wherein

[0011] The p-type semiconductor layers each have a shortest distance of 0.4 μm to 1.0 μm between the p-type semiconductor layer itself and the closest p-type semiconductor layer with respect to the p-type semiconductor layer itself.

[0012] <Embodiment 2>

[0013] The semiconductor device according to Embodiment 1, wherein

[0014] The n-type gallium oxide semiconductor layer has a plurality of trench structures on a side on which a plurality of the p-type semiconductor layers are stacked,

[0015] The plurality of p-type semiconductor layers have:

[0016] a first p-type semiconductor layer stacked in the recessed portions of the plurality of trench structures at a thickness lower than a depth of the recessed portions; and

[0017] a second p-type semiconductor layer stacked on the protruded portions between the plurality of trench structures, and

[0018] the first p-type semiconductor layer is closest to the second p-type semiconductor layer,

[0019] the first electrode body layer is in contact with the first p-type semiconductor layer and the second p-type semiconductor layer, and is stacked on side surfaces of the plurality of trench structures in a manner in contact with the n-type gallium oxide semiconductor layer.

[0020] <Embodiment 3>

[0021] The semiconductor device according to Embodiment 2, wherein

[0022] the shortest distance between the first p-type semiconductor layer and the second p-type semiconductor layer and a doping density in the n-type gallium oxide semiconductor layer are designed in a manner such that a first depletion layer formed between the first p-type semiconductor layer and the n-type gallium oxide semiconductor layer in a state where a relative potential of the first electrode body layer with respect to the second electrode body layer is 0 V is connected to a second depletion layer formed between the second p-type semiconductor layer and the n-type gallium oxide semiconductor layer, and

[0023] The second electrode body layer is an ohmic electrode.

[0024] <Embodiment 4>

[0025] The semiconductor device according to Embodiment 2 or 3, wherein

[0026] The semiconductor device further has a peripheral withstand voltage structure having a plurality of the trench structures,

[0027] In the peripheral withstand voltage structure, there are:

[0028] a third p-type semiconductor layer stacked in the recessed portions of the plurality of trench structures at a thickness lower than a depth of the recessed portions; and

[0029] a fourth p-type semiconductor layer stacked on the protruded portions between the plurality of trench structures, and

[0030] the third p-type semiconductor layer is closest to the fourth p-type semiconductor layer.

[0031] <Option 5>

[0032] According to the semiconductor device described in Scheme 4, wherein...

[0033] The plurality of the third p-type semiconductor layers have two or more third p-type semiconductor layers with different thicknesses.

[0034] <Option 6>

[0035] According to the semiconductor device described in Scheme 4, wherein...

[0036] As the distance between the closest third p-type semiconductor layer and the fourth p-type semiconductor layer increases from the central side to the outer side of the semiconductor device.

[0037] <Option 7>

[0038] The semiconductor device according to any one of claims 1 to 6, wherein,

[0039] The n-type gallium oxide semiconductor layer has a doping density of 3×10⁻⁶. 17 cm -3 The above are gallium oxide substrates.

[0040] According to this disclosure, a semiconductor device can be provided that simultaneously achieves improved voltage withstand capability and reduced resistance. Attached Figure Description

[0041] The features, advantages, and technical and industrial significance of exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, wherein like symbols denote like elements, wherein:

[0042] Figure 1A This is a schematic diagram illustrating a semiconductor device according to a first embodiment of the present disclosure.

[0043] Figure 1B This is a schematic diagram illustrating an example of the process of manufacturing a semiconductor device according to the first embodiment of the present disclosure.

[0044] Figure 1C This is a schematic diagram illustrating an example of the process of manufacturing a semiconductor device according to the first embodiment of the present disclosure.

[0045] Figure 1D This is a schematic diagram illustrating an example of the process of manufacturing a semiconductor device according to the first embodiment of the present disclosure.

[0046] Figure 1E This is a schematic diagram illustrating an example of the process of manufacturing a semiconductor device according to the first embodiment of the present disclosure.

[0047] Figure 1Fis a schematic view showing one example of a process of manufacturing the semiconductor device of the first embodiment of the present disclosure.

[0048] Figure 1G is a schematic view showing one example of a process of manufacturing the semiconductor device of the first embodiment of the present disclosure.

[0049] Figure 2A is a schematic view showing the semiconductor device of the second embodiment of the present disclosure.

[0050] Figure 2B is a schematic view showing one example of a process of manufacturing the semiconductor device of the second embodiment of the present disclosure.

[0051] Figure 3 is a schematic view showing the peripheral withstand voltage structure of the semiconductor device of the third embodiment of the present disclosure.

[0052] Figure 4A is a schematic view showing one example of a process of manufacturing the semiconductor device of Reference Example 1.

[0053] Figure 4B is a schematic view showing one example of a process of manufacturing the semiconductor device of Reference Example 1.

[0054] Figure 4C is a schematic view showing one example of a process of manufacturing the semiconductor device of Reference Example 1.

[0055] Figure 4D is a schematic view showing one example of a process of manufacturing the semiconductor device of Reference Example 1.

[0056] Figure 4E is a schematic view showing one example of a process of manufacturing the semiconductor device of Reference Example 1.

[0057] Figure 5 is a graph showing the relationship between the withstand voltage and the length of the pitch with respect to the semiconductor devices of Reference Examples 1 to 10.

[0058] Figure 6 is a graph showing the relationship between the withstand voltage and the length of the pitch with respect to the semiconductor devices of Embodiments 1 to 5 and Comparative Examples 1 to 8. DETAILED DESCRIPTION

[0059] Hereinafter, the embodiments of the present disclosure will be described in detail. Furthermore, the present disclosure is not limited to the following embodiments, and can be implemented in various modifications within the scope of the present disclosure.

[0060] <First Embodiment>

[0061] A first embodiment of this disclosure provides a semiconductor device having a first electrode body layer, a plurality of p-type semiconductor layers, an n-type gallium oxide semiconductor layer, and a second electrode body layer. The plurality of p-type semiconductor layers are stacked on one side of the n-type gallium oxide semiconductor layer in a manner that they are in contact with each other. The first electrode body layer is stacked on one side of the n-type gallium oxide semiconductor layer in a manner that it is in contact with the plurality of p-type semiconductor layers and is in contact with the n-type gallium oxide semiconductor layer at the portions where the plurality of p-type semiconductor layers are separated from each other. The second electrode body layer is stacked on the other side of the n-type gallium oxide semiconductor layer in a manner that it is in contact with the n-type gallium oxide semiconductor layer. The shortest distance between each p-type semiconductor layer and the p-type semiconductor layer that is closest to each other is 0.4 μm to 1.0 μm.

[0062] Although not limited by the principle, the principle of simultaneously improving voltage withstand capability and reducing resistance in the semiconductor device of the first embodiment of this disclosure is as follows.

[0063] The study examined the situation in such cases. Figure 1A In the semiconductor device 1 shown, both improved withstand voltage and reduced resistance are achieved simultaneously. Here, the semiconductor device 1 has a first electrode body layer 10, a plurality of p-type semiconductor layers 20, an n-type gallium oxide semiconductor layer 30, and a second electrode body layer 40. The plurality of p-type semiconductor layers 20 are stacked on one side of the n-type gallium oxide semiconductor layer 30 in connection with it. The first electrode body layer 10 is stacked on one side of the n-type gallium oxide semiconductor layer 30 in connection with the plurality of p-type semiconductor layers 20 and in connection with the n-type gallium oxide semiconductor layer 30 at the portions where the plurality of p-type semiconductor layers 20 are separated from each other. The second electrode body layer 40 is stacked on the other side of the n-type gallium oxide semiconductor layer 30 in connection with it.

[0064] In the semiconductor device 1 having the structure described above, in order to improve the withstand voltage, it is considered to reduce the shortest distance d1 between each p-type semiconductor layer 20 and the p-type semiconductor layer 20 closest to each other. However, as this distance decreases, the resistance of the semiconductor device 1 increases. That is, there is a trade-off between the improvement in withstand voltage and the reduction in resistance.

[0065] In this regard, setting the shortest distance between each p-type semiconductor layer 20 and the nearest p-type semiconductor layer 20 to each other to 1.0 μm or less can particularly improve the withstand voltage. However, when the shortest distance between each p-type semiconductor layer 20 and the nearest p-type semiconductor layer 20 to each other is set to less than 0.4 μm, the resistance increases sharply.

[0066] In the semiconductor device 1 of the first embodiment of the present disclosure, the shortest distance dl between each of the p-type semiconductor layers 20 and the p-type semiconductor layer 20 closest to each of the p-type semiconductor layers 20 is 0.4 μm to 1.0 μm, so that both an increase in withstand voltage and a decrease in resistance are achieved.

[0067] Further, Figure 1A The semiconductor device of the present disclosure is not intended to be limited.

[0068] <First electrode body layer>

[0069] The first electrode body layer is stacked on one surface side of the n-type gallium oxide semiconductor layer in a manner of being in contact with the plurality of p-type semiconductor layers and being in contact with the n-type gallium oxide semiconductor layer at portions where the plurality of p-type semiconductor layers are separated from each other.

[0070] The first electrode body layer is in Schottky contact with the n-type gallium oxide semiconductor layer. The first electrode body layer can include any material such as a metal such as Fe, Cu, Mo, or W, which is capable of being in Schottky contact with the n-type gallium oxide semiconductor layer at least at a portion in contact with the n-type gallium oxide semiconductor layer.

[0071] <P-type semiconductor layer>

[0072] The plurality of p-type semiconductor layers are stacked on one surface side of the n-type gallium oxide semiconductor layer in a manner of being in contact with the n-type gallium oxide semiconductor layer. The plurality of p-type semiconductor layers are disposed to be separated from each other on one surface side of the n-type gallium oxide semiconductor layer.

[0073] As a material of the p-type semiconductor layer, for example, Ga2O3, NiO, CuO2, SnO, ZeSe, GaN, SiC, Si, GaAs, or the like can be given, but is not limited to these.

[0074] The shortest distance between each of the p-type semiconductor layers and the p-type semiconductor layer closest to each of the p-type semiconductor layers is 0.4 μm to 1.0 μm.

[0075] The shortest distance between each of the p-type semiconductor layers and the p-type semiconductor layer closest to each of the p-type semiconductor layers can be 0.4 μm or more, 0.5 μm or more, 0.6 μm or more, or 0.7 μm or more, or can be 1.0 μm or less, 0.9 μm or less, 0.8 μm or less, or 0.7 μm or less.

[0076] <N-type gallium oxide semiconductor layer>

[0077] The n-type gallium oxide semiconductor layer can use a Ga2O3 single crystal substrate produced by any method or a Ga2O3 single crystal substrate sold. The Ga2O3 single crystal substrate can be an α-Ga2O3 single crystal, a β-Ga2O3 single crystal, or a Ga2O3 single crystal having another crystal structure, and is preferably a β-Ga2O3 single crystal. The n-type gallium oxide semiconductor layer can be formed as an n-type semiconductor layer by doping Si, Sn, or the like in the substrate thereof, for example.

[0078] The n-type gallium oxide semiconductor layer can have a doping density of 3 x 10 17 cm -3 The above gallium oxide substrate.

[0079] The n-type gallium oxide semiconductor layer can have a doping density of 3 x 10 17 cm -3 to 9 x 10 18 cm -3 The n-type gallium oxide semiconductor layer can have a doping density of 3 x 10 17 cm -3 or more, 5 x 10 17 cm -3 or more, 7 x 10 17 cm -3 or more, or 9 x 10 17 cm -3 or more, 9 x 10 18 cm -3 or more, 7 x 10 18 cm -3 or more, 5 x 10 18 cm -3 or more, or 3 x 10 18 cm -3 or more.

[0080] <Second Electrode Body Layer>

[0081] The second electrode body layer is laminated on the other surface side of the n-type gallium oxide semiconductor layer so as to be in contact with the n-type gallium oxide semiconductor layer.

[0082] The second electrode body layer is in ohmic contact with the n-type gallium oxide semiconductor layer.

[0083] The second electrode body layer can include any material, such as a metal such as Ti, which is capable of being in ohmic contact with the n-type gallium oxide semiconductor layer at least in the portion in contact with the n-type gallium oxide semiconductor layer. Alternatively, the second electrode body layer can be formed in ohmic contact by heat-treating an electrode body layer disposed on the n-type gallium oxide semiconductor layer.

[0084] <Manufacturing Method>

[0085] The semiconductor device of the first embodiment of the present disclosure can be manufactured, for example, by the method shown in FIG. 8. Figures 1B-1F

[0086] First, for the n-type gallium oxide semiconductor layer 30 shown in FIG. 1, a masking 100 is formed as shown in FIG. 2. Next, as shown in FIG. 3, a trench structure 31 is formed on one face side of the n-type gallium oxide semiconductor layer 30 by etching. Then, as shown in FIG. 4, the masking 100 is removed. Thereafter, as shown in FIG. 5, the p-type semiconductor layers 21, 23 are deposited. Here, as shown in FIG. 6, the p-type semiconductor layer 21 deposited in the recesses of the trench structure 31 is left, and the p-type semiconductor layer 23 deposited on the convexes 33 of the trench structure 31 is removed, from among the p-type semiconductor layers 21, 23. Finally, as shown in FIG. 7, a first electrode body layer 10 is arranged on the one face of the n-type gallium oxide semiconductor layer 30, that is, the face on which the p-type semiconductor layer 21 is laminated, and a second electrode body layer 40 is arranged on the other face of the n-type gallium oxide semiconductor layer 30, thereby forming the semiconductor device 1 shown in FIG. 8. Figure 1B Figure 1C Figure 1D Figure 1E Figure 1F Figure 1G Figure 1A

[0087] Further, the semiconductor device of the present disclosure is not intended to be limited to the semiconductor device described above. Figures 1B-1F

[0088] In addition, as for the masking, etching, and deposition of the p-type semiconductor layer, any method for manufacturing a semiconductor device can be employed.

[0089] <Second Embodiment>

[0090] The semiconductor device of the second embodiment of the present disclosure is premised on the above-described first embodiment of the present disclosure, and the n-type gallium oxide semiconductor layer has a plurality of trench structures on the side on which a plurality of p-type semiconductor layers are laminated. Here, the plurality of p-type semiconductor layers have a first p-type semiconductor layer laminated in the recesses of the plurality of trench structures at a thickness lower than the depth of the recesses, and a second p-type semiconductor layer laminated on the convexes between the plurality of trench structures. In addition, the first p-type semiconductor layer is closest to the second p-type semiconductor layer in each of the plurality of p-type semiconductor layers. Furthermore, the first electrode body layer is in contact with the first p-type semiconductor layer and the second p-type semiconductor layer, and is laminated on the side faces of the plurality of trench structures in a manner in contact with the n-type gallium oxide semiconductor layer.

[0091] More specifically, the semiconductor device of the second embodiment of the present disclosure has, for example, a configuration as shown in FIG. 9. Figure 2A

[0092] Figure 2A is a schematic view showing the semiconductor device 2 of the second embodiment of the present disclosure.​​​​​​​​​​

[0093] like Figure 2A As shown, in the semiconductor device 2 of the second embodiment of this disclosure, the n-type gallium oxide semiconductor layer 30 has a plurality of trench structures 31 on one side where a plurality of p-type semiconductor layers 21, 23 are stacked. The plurality of p-type semiconductor layers 21, 23 have a first p-type semiconductor layer 21 stacked in the recesses of the plurality of trench structures 31 with a thickness lower than the depth of the recesses, and a second p-type semiconductor layer 23 stacked on the protrusions 33 between the plurality of trench structures 31. Here, the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23 of each of the plurality of p-type semiconductor layers 21, 23 are closest to each other. Furthermore, the first electrode body layer 10 is in contact with the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23, and is stacked on the side of the plurality of trench structures 31 in a manner in contact with the n-type gallium oxide semiconductor layer 30.

[0094] exist Figure 2A In this process, the shortest distance d2 between the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23 is 0.4 μm to 1.0 μm.

[0095] In the case of forming a semiconductor device using an n-type gallium oxide semiconductor layer and a p-type semiconductor layer as a dissimilar material, it is impossible to form a p-type semiconductor layer by ion implantation of the n-type gallium oxide semiconductor layer. In such cases, for example, consider the method described above... Figures 1B-1G The method shown is used to manufacture, as Figure 1A Semiconductor device 1 with the structure shown.

[0096] In such Figure 1A In the structure shown, in order to simultaneously improve the withstand voltage and reduce the resistance, the width of the protrusion 33 between the groove structures 31 is required to be 0.4μm to 1.0μm.

[0097] However, fine machining is required to form the groove structure 31 with such a narrow width.

[0098] In this regard, in the semiconductor device 2 of the second embodiment of this disclosure, the first p-type semiconductor layer 21 stacked in the recesses of the plurality of trench structures 31 with a thickness lower than the depth of the recesses, and the second p-type semiconductor layer 23 stacked on the protrusions 33 between the plurality of trench structures 31, are the two closest p-type semiconductor layers 21, 23 to each other. Therefore, the minimum distance d2 between the closest p-type semiconductor layers 21, 23 to each other is the thickness direction of the semiconductor device.

[0099] Therefore, in the semiconductor device 2 of the second embodiment of this disclosure, by adjusting the depth of the trench structure 31 and / or the thickness of the first p-type semiconductor layer 21, the minimum distance d2 can be adjusted. Thus, a semiconductor device in which the distance d2 between the two closest p-type semiconductor layers 21, 23 is 0.4 μm to 1.0 μm can be manufactured in a simpler manner.

[0100] The semiconductor device 2 of the second embodiment of this disclosure is, for example, capable of... Figures 1B-1E as well as Figure 2B As shown in the diagram. Specifically, in the case of... Figures 1B-1E After etching the n-type gallium oxide semiconductor layer 30 as shown, Figure 2B As shown, a first p-type semiconductor layer 21 and a second p-type semiconductor layer 23 are stacked on one side of the n-type gallium oxide semiconductor layer 30, i.e., the side with the trench structure. Finally, a first electrode body layer 10 is disposed on one side of the n-type gallium oxide semiconductor layer 30, i.e., the side where the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23 are stacked, and a second electrode body layer 40 is disposed on the other side of the n-type gallium oxide semiconductor layer 30, forming as shown in the diagram. Figure 2A Semiconductor device 2 shown.

[0101] also, Figure 2A And 2B is not intended to limit the semiconductor devices disclosed herein.

[0102] Here, the positional relationship between the first depletion layer and the second depletion layer can be controlled based on the shortest distance between adjacent first p-type semiconductor layers and second p-type semiconductor layers. Furthermore, the size of the depletion layer can be controlled based on the doping density in the n-type gallium oxide semiconductor layer.

[0103] Therefore, it is possible to design the shortest distance between adjacent first p-type semiconductor layers and second p-type semiconductor layers and the doping density in the n-type gallium oxide semiconductor layer so that the first depletion layer formed between the first p-type semiconductor layer and the n-type gallium oxide semiconductor layer is interconnected when the relative potential of the first electrode layer with respect to the second electrode layer is 0V.

[0104] <Third Implementation Method>

[0105] The semiconductor device of the third embodiment of this disclosure is based on the second embodiment described above, and further includes a peripheral voltage withstand structure having multiple trench structures. The semiconductor device of the third embodiment of this disclosure has a third p-type semiconductor layer stacked in the recesses of the multiple trench structures with a thickness lower than the depth of the recesses, and a fourth p-type semiconductor layer stacked on the protrusions between the multiple trench structures in the peripheral voltage withstand structure. Furthermore, the third p-type semiconductor layer and the fourth p-type semiconductor layer among the multiple p-type semiconductor layers are closest to each other.

[0106] Multiple third p-type semiconductor layers can have two or more third p-type semiconductor layers with different thicknesses. That is, there can be combinations of two or more third p-type semiconductor layers and fourth p-type semiconductor layers with different shortest distances between them.

[0107] In particular, the shortest distance between the closest third p-type semiconductor layer and the fourth p-type semiconductor layer increases from the central side to the outer side of the semiconductor device. Furthermore, the central side of the semiconductor device refers to the side where the first electrode body layer is disposed. In other words, regarding the peripheral withstand voltage structure, the shortest distance between the third p-type semiconductor layer and the fourth p-type semiconductor layer increases from the side closer to the first electrode body layer to the side farther away.

[0108] Figure 3 This is a schematic diagram showing the peripheral withstand voltage structure 3 in a semiconductor device according to the third embodiment of the present disclosure.

[0109] like Figure 3 As shown, the peripheral withstand voltage structure 3 has multiple trench structures 31. The peripheral withstand voltage structure 3 has a third p-type semiconductor layer 51 and a fourth p-type semiconductor layer 53. The third p-type semiconductor layer 51 is stacked in the recesses of the multiple trench structures 31 with a thickness less than the depth of the recesses. The fourth p-type semiconductor layer 53 is stacked on the protrusions 33 between the multiple trench structures 31. The third p-type semiconductor layer 51 and the fourth p-type semiconductor layer 53 of each of the multiple p-type semiconductor layers 51 and 53 are closest to each other.

[0110] Here, as Figure 3 As shown, the thickness of the third p-type semiconductor layer 51 decreases from the central side to the outer side in the peripheral voltage withstand structure 3. Consequently, the shortest distance d3a to d between the third p-type semiconductor layer 51 and the fourth p-type semiconductor layer 53 increases from the central side to the outer side in the peripheral voltage withstand structure 3.

[0111] also, Figure 3 This disclosure is not intended to limit the semiconductor devices described herein.

[0112] <Refer to Examples 1-10>

[0113] <Reference Example 1>

[0114] Using SiC, a JBS diode, i.e., the semiconductor device described in Examples 1-10, was fabricated. The doping density of the n-type semiconductor layer was 2.4 × 10⁻⁶. 16 cm -3 The p-type semiconductor layer is formed by implanting Al ions (1×10⁻⁶) as acceptors. 19 cm -3 It is formed by SiC. The shortest distance (spacing) between each p-type semiconductor layer and the nearest p-type semiconductor layer relative to each other is set to 1.0 μm.

[0115] Specifically, through such Figures 4A-4E The method shown is used to form it.

[0116] That is, firstly, such as Figure 4A As shown, dopant is doped into SiC to form an n-type semiconductor layer 60. Next, as... Figure 4B As shown, masks 100 are arranged at certain intervals on one surface of the n-type semiconductor layer 60. Then, as... Figure 4C As shown, Al ions are implanted to form multiple p-type semiconductor layers 70. Then, as... Figure 4D As shown, mask 100 is removed from one surface of n-type semiconductor layer 60. Finally, as... Figure 4E As shown, a first electrode body layer 10 and a second electrode body layer 40 are disposed on both sides of the n-type semiconductor layer 60.

[0117] Table 1 shows the structure of Reference Example 1.

[0118] <Refer to Examples 2-10>

[0119] Except that the shortest distance (spacing) between each p-type semiconductor layer and the p-type semiconductor layer closest to each p-type semiconductor layer is set to 2.0 μm, 3.0 μm, 4.0 μm, 5.0 μm, 7.0 μm, 8.0 μm, 9.0 μm, 10.0 μm and 12.0 μm respectively, the semiconductor devices of Reference Examples 2 to 10 were fabricated in the same manner as in Reference Example 1.

[0120] Table 1 shows the structures of Reference Examples 2-10.

[0121] <Experiment>

[0122] In each example of the semiconductor device, a forward current was flowed between the electrodes, and the voltage (V) between the electrodes when the current reached 1.0 mA was measured. Additionally, a voltage of 100 A / cm was measured. 2 The on-resistance below.

[0123] Table 1 shows the experimental results for each example.

[0124] <Results>

[0125] Table 1 shows the structure and test results of the semiconductor devices in Reference Examples 1-10. Additionally, Figure 5 The relationship between the withstand voltage and the length of the pitch is shown in relation to the semiconductor devices of Reference Examples 1-10.

[0126] Table 1

[0127]

[0128] As shown in Table 1 and Figure 5 As shown, as the spacing, i.e. the shortest distance between each p-type semiconductor layer and the closest p-type semiconductor layer relative to each other, decreases, the withstand voltage increases, and the on-resistance also increases.

[0129] <Examples 1-5 and Comparative Examples 1-8>

[0130] <Example 1>

[0131] Used as an n-type gallium oxide semiconductor layer (doping density 5×10⁻⁶) 17 cm -3 ) and NiO of the p-type semiconductor layer, through such Figures 1A-1G The semiconductor device of Example 1 was fabricated using the method shown.

[0132] Specifically, firstly, regarding Figure 1B The n-type gallium oxide semiconductor layer 30 shown is, for example Figure 1C As shown, mask 100 is formed. Then, as... Figure 1D As shown, a trench structure 31 is formed on one side of the n-type gallium oxide semiconductor layer 30 by etching, as... Figure 1E As shown, remove mask 100. Then, as... Figure 1F As shown, p-type semiconductor layers 21 and 23 are deposited. Here, as... Figure 1G As shown, the p-type semiconductor layer 21 deposited in the recess of the trench structure 31 in the p-type semiconductor layers 21 and 23 is left intact, while the p-type semiconductor layer 23 deposited on the protrusion 33 of the trench structure 31 is removed. Finally, a first electrode body layer 10 is disposed on one side of the n-type gallium oxide semiconductor layer 30, i.e., the side where the p-type semiconductor layer 21 is stacked, and a second electrode body layer 40 is disposed on the other side of the n-type gallium oxide semiconductor layer 30, to fabricate a structure as shown. Figure 1A Semiconductor device 1 is shown.

[0133] Here, the spacing, i.e., the shortest distance d1 between each p-type semiconductor layer 21 and the p-type semiconductor layer 21 closest to each other, is 0.4 μm.

[0134] Table 2 shows the structure of Example 1.

[0135] <Examples 2-4>

[0136] Except that the shortest distance between each p-type semiconductor layer and the closest p-type semiconductor layer relative to each p-type semiconductor layer is set to 0.5 μm, 0.7 μm and 1.0 μm respectively, the semiconductor devices of Examples 2 to 4 were fabricated in the same manner as in Example 1.

[0137] Table 2 shows the structures of Examples 2 to 4.

[0138] <Example 5>

[0139] Used as an n-type gallium oxide semiconductor layer (doping density 5×10⁻⁶) 17 cm -3 ) and NiO of the p-type semiconductor layer, through such Figures 1B-1E as well as Figure 2B The semiconductor device of Example 5 was fabricated using the method shown.

[0140] Specifically, in such Figures 1B-1E After etching the n-type gallium oxide semiconductor layer 30 as shown, Figure 2B As shown, a first p-type semiconductor layer 21 and a second p-type semiconductor layer 23 are stacked on one side of the n-type gallium oxide semiconductor layer 30, i.e., the side where the trench structure 31 is formed. Finally, a first electrode body layer 10 is disposed on one side of the n-type gallium oxide semiconductor layer 30, i.e., the side where the p-type semiconductor layers 21 and 23 are stacked, and a second electrode body layer 40 is disposed on the other side of the n-type gallium oxide semiconductor layer 30.

[0141] Here, the spacing, i.e., the shortest distance d2 between the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23, is 1.0 μm. Furthermore, the spacing in Embodiment 5 differs from that in Embodiments 1 to 4, and is the distance between the first p-type semiconductor layer 21 and the second p-type semiconductor layer 23, which is related to the thickness direction of the semiconductor device 2.

[0142] Table 2 shows the structure of Example 5.

[0143] <Experiment>

[0144] In each example of the semiconductor device, a forward current was flowed between the electrodes, and the voltage (V) between the electrodes when the current reached 1.0 mA was measured. Additionally, a voltage of 100 A / cm was measured. 2 The on-resistance below.

[0145] Table 2 shows the experimental results for each example.

[0146] <Comparative Examples 1-8>

[0147] Except that the shortest distance between each p-type semiconductor layer and the p-type semiconductor layer closest to each p-type semiconductor layer was set to 0.2 μm, 0.3 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm and 4.0 μm respectively, the semiconductor devices of Comparative Examples 1 to 8 were fabricated in the same manner as in Example 1.

[0148] Table 2 shows the structures of Comparative Examples 1 to 8.

[0149] <Results>

[0150] Table 2 shows the structure and test results of the semiconductor devices of Examples 1-5 and Comparative Examples 1-8. Additionally, Figure 6 The relationship between the withstand voltage and the length of the pitch is shown in relation to the semiconductor devices of Examples 1-5 and Comparative Examples 1-8.

[0151] Table 2

[0152]

[0153] As shown in Table 2 and Figure 6 As shown, as the spacing, i.e. the shortest distance between each p-type semiconductor layer and the closest p-type semiconductor layer relative to each other, decreases, the withstand voltage increases, and the on-resistance also increases.

[0154] Additionally, as shown in Table 2 and Figure 6 As shown, comparing Examples 1-5 with a spacing of 1.0 μm or less and Comparative Examples 3-8 with a spacing exceeding 1.0 μm, the withstand voltage increases sharply when the spacing is 1.0 μm or less. On the other hand, as shown in Table 2 and... Figure 6 As shown, comparing Examples 1 to 5 with a spacing of 1.0 μm or less and Comparative Examples 1 and 2 with a spacing of less than 0.4 μm, when the spacing is less than 0.4 μm, the increase in on-resistance relative to the increase in withstand voltage becomes drastic.

Claims

1. A semiconductor device comprising a first electrode body layer, a plurality of p-type semiconductor layers, an n-type gallium oxide semiconductor layer, and a second electrode body layer. Multiple p-type semiconductor layers are stacked on one side of the n-type gallium oxide semiconductor layer in a manner that they are in contact with the n-type gallium oxide semiconductor layer. The first electrode body layer is stacked on one side of the n-type gallium oxide semiconductor layer in such a manner that it is in contact with the plurality of p-type semiconductor layers and in contact with the n-type gallium oxide semiconductor layer at portions where the plurality of p-type semiconductor layers are separated from each other. The second electrode body layer is stacked on another side of the n-type gallium oxide semiconductor layer in a manner that is in contact with the n-type gallium oxide semiconductor layer. in, The shortest distance between each p-type semiconductor layer and the nearest p-type semiconductor layer relative to that p-type semiconductor layer is 0.4 μm to 1.0 μm. The n-type gallium oxide semiconductor layer has multiple trench structures on one side where multiple p-type semiconductor layers are stacked. The plurality of said p-type semiconductor layers have: A first p-type semiconductor layer is stacked in the recesses of the plurality of trench structures with a thickness lower than the depth of the recesses; as well as A second p-type semiconductor layer is stacked on the protrusions between the plurality of trench structures, and The first p-type semiconductor layer is closest to the second p-type semiconductor layer. The first electrode body layer is connected to the first p-type semiconductor layer and the second p-type semiconductor layer, and is stacked on the sides of the plurality of trench structures in a manner connected to the n-type gallium oxide semiconductor layer. The semiconductor device also includes a peripheral breakdown structure having multiple trench structures. The peripheral pressure-resistant structure has the following features: A third p-type semiconductor layer is stacked in the recesses of the plurality of trench structures with a thickness lower than the depth of the recesses; as well as A fourth p-type semiconductor layer is stacked on the protrusions between the plurality of trench structures, and The third p-type semiconductor layer is closest to the fourth p-type semiconductor layer.

2. The semiconductor device according to claim 1, wherein, To interconnect the first depletion layer formed between the first p-type semiconductor layer and the n-type gallium oxide semiconductor layer when the relative potential of the first electrode body layer with respect to the second electrode body layer is 0V, the design considers the shortest distance between adjacent first p-type semiconductor layers and second p-type semiconductor layers, as well as the doping density in the n-type gallium oxide semiconductor layer. The second electrode body layer is an ohmic electrode.

3. The semiconductor device according to claim 1 or 2, wherein, The plurality of the third p-type semiconductor layers have two or more third p-type semiconductor layers with different thicknesses.

4. The semiconductor device according to claim 1 or 2, wherein, As the distance between the closest third p-type semiconductor layer and the fourth p-type semiconductor layer increases from the central side to the outer side of the semiconductor device.

5. The semiconductor device according to claim 1 or 2, wherein, The n-type gallium oxide semiconductor layer has a doping density of 3×10⁻⁶. 17 cm -3 The above are gallium oxide substrates.

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