A varistor device and method based on GaN heterojunction epitaxy

Abstract

This invention discloses a varistor device and method based on GaN heterojunction epitaxy, comprising, from bottom to top, a substrate, an AlN / AlInGaN buffer layer, a uGaN buffer layer, a GaN channel layer, an AlN barrier insertion layer, an Al(In)GaN barrier layer, a GaN cap layer, and two metal electrodes; a trench is etched in the middle of the GaN channel layer, the AlN barrier insertion layer, the Al(In)GaN barrier layer, and the GaN cap layer; the two metal electrodes are distributed on both sides of the trench; the metal electrodes, from bottom to top, are a four-layer structure of Ti, Al, Ni, and Au. The fabrication method of this invention is simple, and the resulting device exhibits typical varistor characteristics.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, specifically relating to a varistor device and method based on GaN heterojunction epitaxy. Background Technology

[0002] GaN, as a third-generation semiconductor material, is a relatively stable III-V compound with superior physical properties compared to other semiconductor materials in terms of hardness, melting point, and ionization degree. Compared to first-generation semiconductor Si and second-generation semiconductor GaAs, GaN semiconductors exhibit higher power density, higher breakdown voltage, and higher electron saturation drift velocity, enabling them to withstand higher voltages and output higher energy densities. Currently, the GaN-based AlGaN / GaN structure is very mature and widely used in power and radio frequency fields. The newer AlInGaN / GaN material, with its even higher electron mobility and electron density, is becoming a very popular candidate for millimeter-wave applications.

[0003] Currently, Si, SiC, and sapphire are commonly used as substrates for GaN devices, offering a wider range of applications. GaN heterojunction epitaxial materials and their derivative devices, such as GaN HEMTs and GaN diodes, are poised to become highly promising applications in the RF power field due to their high speed, high power, high frequency, and high stability. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a varistor device and method based on GaN heterojunction epitaxy, comprising, from bottom to top, a substrate, an AlN / AlInGaN buffer layer, a uGaN buffer layer, a GaN channel layer, an AlN barrier insertion layer, an Al(In)GaN barrier layer, a GaN cap layer, and two metal electrodes; a trench is etched in the middle of the GaN channel layer, the AlN barrier insertion layer, the Al(In)GaN barrier layer, and the GaN cap layer; the two metal electrodes are distributed on both sides of the trench; the metal electrodes, from bottom to top, are a four-layer structure of Ti, Al, Ni, and Au. The fabrication method of this invention is simple, and the resulting device exhibits typical varistor characteristics.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows:

[0006] A varistor device based on GaN heterojunction epitaxy includes a substrate, an AlN / AlInGaN buffer layer, a uGaN buffer layer, a GaN channel layer, an AlN barrier insertion layer, an Al(In)GaN barrier layer, a GaN cap layer, and two metal electrodes stacked sequentially from bottom to top.

[0007] A trench is etched in the middle of the GaN channel layer, AlN barrier insertion layer, Al(In)GaN barrier layer and GaN cap layer; the two metal electrodes are distributed on both sides of the trench.

[0008] The metal electrode has a four-layer structure from bottom to top: Ti, Al, Ni, and Au.

[0009] Preferably, the etching depth for forming a groove is 10-500 nm.

[0010] Preferably, the substrate is a high-resistivity silicon with a 111 crystal plane and a thickness of 1×10⁻⁶. 6 nm; the AlN / AlInGaN buffer layer comprises one AlN layer and three layers with different Al compositions and a C doping concentration of 5×10 nm. 18 cm -3 The Al(In)GaN layer has an AlN / AlInGaN buffer layer thickness of 850nm.

[0011] Preferably, the uGaN buffer layer has a thickness of 2000 nm, the GaN channel layer has a thickness of 100 nm, the AlN barrier insertion layer has a thickness of 1 nm, and the GaN cap layer has a thickness of 2 nm.

[0012] Preferably, the Al(In)GaN barrier layer contains 45% Al and 2% In, and has a thickness of 7 nm.

[0013] Preferably, the metal electrode is composed of 20nm reactive metal Ti, 130nm catalytic metal Al, 50nm isolation metal Ni, and 50nm electrode metal Au.

[0014] A method for fabricating a varistor device based on GaN heterojunction epitaxy includes the following steps:

[0015] Step 1: Select a substrate;

[0016] Step 2: Grow an AlN / AlInGaN buffer layer on the substrate surface;

[0017] Step 3: Grow a uGaN buffer layer on the surface of the AlN / AlInGaN buffer layer;

[0018] Step 4: Grow a GaN channel layer on the surface of the uGaN buffer layer;

[0019] Step 5: Grow an AlN barrier insertion layer on the surface of the GaN channel layer;

[0020] Step 6: Grow an Al(In)GaN barrier layer on the surface of the AlN barrier insertion layer;

[0021] Step 7: Grow a GaN cap layer on the surface of the Al(In)GaN barrier layer;

[0022] Step 8: Etch the GaN cap layer, Al(In)GaN barrier layer, AlN barrier insertion layer and GaN channel layer to form a trench;

[0023] Step 9: Deposit Ti / Al / Ni / Au metal electrodes on the GaN cap layer surfaces on both sides of the trench to finally complete the varistor device based on GaN heterojunction epitaxy.

[0024] Preferably, in step 2, an AlN / AlInGaN buffer layer is grown using chemical vapor deposition; in step 3, an uGaN buffer layer is grown using chemical vapor deposition; in step 4, a GaN channel layer is grown using chemical vapor deposition; in step 5, an AlN barrier insertion layer is grown using reactive magnetron sputtering; in step 6, an Al(In)GaN barrier layer is grown using chemical vapor deposition; and in step 7, a GaN cap layer is grown using chemical vapor deposition.

[0025] Preferably, the etching method in step 8 is dry etching or wet etching to achieve trench etching of controllable depth.

[0026] Preferably, in step 9, the metal electrode is deposited using electron beam evaporation and then annealed at high temperature to achieve ohmic contact.

[0027] The beneficial effects of this invention are as follows:

[0028] (1) The present invention provides a varistor device based on GaN heterojunction epitaxy. The varistor structure consists of a narrow trench etched into the GaN channel layer and a metal attached to the surface of the epitaxial material. The turn-on voltage and nonlinearity of the device can be adjusted by adjusting the width of the narrow trench. It has the potential to be applied in fields such as on-chip integrated switches and on-chip integrated ESD protection.

[0029] (2) The present invention provides a method for fabricating a varistor device based on GaN heterojunction epitaxy. The etching technology achieves narrow trench etching with a stable etching rate, and the ohmic contact process is optimized by combining electron beam evaporation technology and rapid annealing metal electrode deposition process. The fabrication method is simple and the obtained device has typical varistor characteristics. Attached Figure Description

[0030] Figure 1 This is a cross-sectional schematic diagram of the varistor device of the present invention.

[0031] Figure 2 This is a schematic flowchart of the fabrication method of the varistor device of the present invention.

[0032] In the figure, 1-substrate, 2-AlN / AlInGaN buffer layer, 3-uGaN buffer layer, 4-GaN channel layer, 5-AlN barrier insertion layer, 6-Al(In)GaN barrier layer, 7-GaN cap layer, 8-metal electrode, 9-groove. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0034] A varistor device based on GaN heterojunction epitaxy includes a substrate 1, an AlN / AlInGaN buffer layer 2, a uGaN buffer layer 3, a GaN channel layer 4, an AlN barrier insertion layer 5, an Al(In)GaN barrier layer 6, a GaN cap layer 7, and two metal electrodes 8 stacked sequentially from bottom to top.

[0035] A trench 9 is formed by etching the middle of the GaN channel layer 4, AlN barrier insertion layer 5, Al(In)GaN barrier layer 6 and GaN cap layer 7; the two metal electrodes 8 are distributed on both sides of the trench.

[0036] The metal electrode 8 has a four-layer structure consisting of Ti, Al, Ni, and Au from bottom to top.

[0037] Preferably, the etching depth of the groove 9 formed by etching is 10-500 nm.

[0038] Preferably, the substrate 1 is a high-resistivity silicon with a 111 crystal plane and a thickness of 1×10⁻⁶. 6 nm; The AlN / AlInGaN buffer layer 2 includes one AlN layer and three layers with different Al compositions and a C doping concentration of 5×10 nm. 18 cm -3 The Al(In)GaN layer and the AlN / AlInGaN buffer layer 2 have a thickness of 850nm.

[0039] Preferably, the uGaN buffer layer 3 has a thickness of 2000 nm, the GaN channel layer 4 has a thickness of 100 nm, the AlN barrier insertion layer 5 has a thickness of 1 nm, and the GaN cap layer 7 has a thickness of 2 nm.

[0040] Preferably, the Al(In)GaN barrier layer 6 has Al and In contents of 45% and 2%, respectively, and a thickness of 7 nm.

[0041] Preferably, the metal electrode 8 is composed of 20nm reactive metal Ti, 130nm catalytic metal Al, 50nm isolation metal Ni, and 50nm electrode metal Au.

[0042] A method for fabricating a varistor device based on GaN heterojunction epitaxy includes the following steps:

[0043] Step 1: Select substrate 1;

[0044] Step 2: Grow an AlN / AlInGaN buffer layer 2 on the surface of substrate 1;

[0045] Step 3: Grow uGaN buffer layer 3 on the surface of AlN / AlInGaN buffer layer 2;

[0046] Step 4: Grow a GaN channel layer 4 on the surface of the uGaN buffer layer 3;

[0047] Step 5: Grow an AlN barrier insertion layer 5 on the surface of GaN channel layer 4;

[0048] Step 6: Grow an Al(In)GaN barrier layer 6 on the surface of the AlN barrier insertion layer 5;

[0049] Step 7: Grow a GaN cap layer 7 on the surface of the Al(In)GaN barrier layer 6;

[0050] Step 8: Etch the GaN cap layer 7, Al(In)GaN barrier layer 6, AlN barrier insertion layer 5 and GaN channel layer 4 to form a trench 9;

[0051] Step 9: Deposit Ti / Al / Ni / Au metal electrodes 8 on the GaN cap layer 7 on both sides of the trench 9, and finally complete the varistor device based on GaN heterojunction epitaxy.

[0052] Preferably, in step 2, an AlN / AlInGaN buffer layer 2 is grown using chemical vapor deposition; in step 3, an uGaN buffer layer 3 is grown using chemical vapor deposition; in step 4, a GaN channel layer 4 is grown using chemical vapor deposition; in step 5, an AlN barrier insertion layer 5 is grown using reactive magnetron sputtering; in step 6, an Al(In)GaN barrier layer 6 is grown using chemical vapor deposition; and in step 7, a GaN cap layer 7 is grown using chemical vapor deposition.

[0053] Preferably, the etching method in step 8 is dry etching or wet etching to achieve trench etching of controllable depth.

[0054] Preferably, in step 9, the metal electrode is deposited using electron beam evaporation and then rapidly annealed at high temperature to achieve ohmic contact. Specific implementation examples:

[0056] Example 1:

[0057] Combination Figure 1This embodiment provides a varistor device based on GaN heterojunction epitaxy, which includes, in sequence from bottom to top, a high-resistivity Si substrate 1, an AlN / AlInGaN buffer layer 2, a uGaN buffer layer 3, a GaN channel layer 4, an AlN barrier insertion layer 5, an Al(In)GaN barrier layer 6, a GaN cap layer 7, and a metal electrode 8. A narrow, adjustable-depth trench 9 is etched away in the middle of the GaN channel layer 4, the AlN barrier insertion layer 5, the Al(In)GaN barrier layer 6, and the GaN cap layer 7, with an etching depth of 10-500 nm. The metal electrode 8 is a Ti / Al / Ni / Au multilayer metal, and the two metal electrodes are spaced a certain distance apart.

[0058] Specifically, choose a thickness of 1×10. 6 Using high-resistivity silicon with a (111) crystal plane as the substrate for this varistor can better achieve lattice matching and alleviate thermal mismatch. An 850 nm thick AlN / AlInGaN buffer layer is grown on the high-resistivity silicon substrate. This buffer layer includes one AlN layer and three layers with different Al compositions and C doping concentrations of 5 × 10⁻⁶. 18 cm -3 An Al(In)GaN layer is used to better release the lattice stress between the Si substrate and GaN. A 2000nm uGaN layer is grown on top of this layer as a buffer layer to stabilize device performance. A 100nm GaN channel layer is grown on the uGaN layer, which is combined with a 7nm thick undoped Al(In)GaN barrier layer to form a heterojunction. The Al and In compositions of the Al(In)GaN are 45% and 2%, respectively. A 1nm thick AlN insertion layer is grown between the two layers. The introduction of the AlN insertion layer can improve the lattice mismatch between the Al(In)GaN barrier layer and GaN caused by the increased Al composition, thereby improving the 2-DEG mobility. Finally, a 2nm GaN cap layer is grown on the surface of the Al(In)GaN barrier layer for protection.

[0059] Specifically, the GaN cap layer 7, Al(In)GaN barrier layer 6, AlN barrier insertion layer 5, and part of the GaN channel layer 4 are etched to form a narrow trench 9 with an etching depth of 10-500 nm located on the GaN channel layer 4 and between the two metal electrodes 8. This completely blocks the channel path of the AlInGaN / GaN heterojunction, thereby effectively cutting off the two-dimensional electron gas channel path of the AlInGaN / GaN heterojunction epitaxy. The charge carriers can directly cross laterally from the GaN layer 4 and the buffer layer below it.

[0060] Specifically, a two-layer metal electrode is deposited, with the structure from bottom to top consisting of a 20nm reactive metal Ti, a 130nm catalytic metal Al, a 50nm isolating metal Ni, and a 50nm electrode metal Au. The first layer, Ti, undergoes a solid-state chemical reaction with the GaN cap layer on the epitaxial wafer during high-temperature annealing to form TiN with low resistivity and a high concentration of N vacancies, increasing the electron tunneling probability and contributing to a good ohmic contact. The second layer, Al, acts as a catalyst, promoting the reaction between N and Ti to form TiN. Al also reacts with Ti to form a Ti-Al binary phase, further promoting the reaction between Ti and N. The third layer, Ni, acts as an isolating layer, preventing the Au electrode metal from diffusing downwards, thereby further improving the performance of the ohmic contact.

[0061] The beneficial effects of this embodiment are as follows: This invention uses silicon-based gallium nitride (GaN) material, which has advantages such as high breakdown voltage and low on-resistance; silicon-based GaN devices can also be combined with traditional Si processes, which is conducive to integration; by using one AlN layer and three Al(In)GaN layers with different Al compositions, the lattice stress between the silicon substrate and the GaN channel can be better released, the defects caused by lattice mismatch can be alleviated, and the device reliability can be improved; the varistor structure consists of a narrow trench etched into the GaN channel layer and a metal attached to the surface of the epitaxial material, and the turn-on voltage and turn-on current density can be adjusted by adjusting the width of the narrow trench, which has the potential to be applied in fields such as on-chip integrated switches and on-chip integrated ESD protection.

[0062] Example 2:

[0063] Combination Figure 2 This embodiment provides a method for fabricating a varistor device based on GaN heterojunction epitaxy, specifically including the following steps:

[0064] S1. Select substrate 1;

[0065] S2. An AlN / AlInGaN buffer layer 2 is grown on the surface of the substrate 1;

[0066] S3. Grow a uGaN buffer layer 3 on the surface of the AlN / AlInGaN buffer layer 2;

[0067] S4. A GaN channel layer 4 is grown on the surface of the uGaN buffer layer 3;

[0068] S5. An AlN barrier insertion layer 5 is grown on the surface of the GaN channel layer 4.

[0069] S6. An Al(In)GaN barrier layer 6 is grown on the surface of the AlN barrier insertion layer 5.

[0070] S7. Grow a GaN cap layer 7 on the surface of the Al(In)GaN barrier layer 6;

[0071] S8. Etch the GaN cap layer 7, Al(In)GaN barrier layer 6, AlN barrier insertion layer 5, and part of the GaN channel layer 4 to form a narrow trench 9 located on the GaN channel layer 4 and between the two metal electrodes 8.

[0072] S9. Deposit Ti / Al / Ni / Au metal electrodes 8 on the surface of the GaN cap layer 7 to finally complete the varistor device based on GaN heterojunction epitaxy.

[0073] The beneficial effects of this embodiment are as follows: This invention uses KOH solution as a solvent for chemical wet etching, achieving narrow trench etching with a stable etching rate. The width of the narrow trench can be controlled to adjust the turn-on voltage and the nonlinearity of the device, enabling characteristic analysis of devices of various sizes. Furthermore, it combines a metal electrode deposition process based on electron beam evaporation technology and rapid annealing at 875℃ for 30 seconds to achieve ohmic contact of the metal electrode. This fabrication method is simple, low-cost, and the resulting device exhibits typical varistor characteristics.

[0074] Example 3:

[0075] Based on Example 2, the first step is to select the (111) crystal plane of Si crystal as the substrate orientation of the varistor, because the atomic distribution of the (111) crystal plane of Si crystal is uniformly distributed in a regular hexagonal pattern, which can better achieve lattice matching and reduce thermal mismatch. Before growing the buffer layer, the high-resistivity silicon epitaxial wafer is placed in an acetone and alcohol solution and repeatedly ultrasonically cleaned to remove organic impurities on the surface of the epitaxial wafer; the sample is then treated in heated HCl to remove the surface oxide layer and reduce oxygen and metal ion impurities on the surface; the epitaxial wafer sample is cleaned with deionized water to remove surface inorganic matter; and finally, it is dried with N2 to complete the surface cleaning.

[0076] The second step involves growing an AlN / AlInGaN buffer layer 2 on the cleaned epitaxial wafer surface using chemical vapor deposition.

[0077] In the third step, a uGaN buffer layer 3 is grown using chemical vapor deposition.

[0078] The fourth step is chemical vapor deposition to grow the GaN channel layer 4;

[0079] The fifth step involves inserting the AlN barrier insertion layer 5 using reactive magnetron sputtering.

[0080] Step 6: Chemical vapor deposition to grow an Al(In)GaN barrier layer 6;

[0081] Step 7: Chemical vapor deposition to grow a GaN cap layer 7;

[0082] The eighth step involves performing conventional photolithography on the sample after the GaN cap layer 7 has grown, marking the narrow etchable trench areas, and then using a wet-dry hybrid etching method for etching. Specifically...

[0083] First, perform photolithography: (1) Coating: Spin-coat the positive resist onto the sample surface; (2) Baking: Bake the sample to remove the solvent on the resist film and increase adhesion; (3) Photolithography: Use a photolithography bonding alignment machine to expose the sample under ultraviolet light; (4) Development: Immerse the sample in the developer solution, rinse the sample, and finally dry it with an N2 gun.

[0084] Then perform etching: (1) First, clean the surface for 1 hour, heat in a boiling acetone water bath for 10 minutes, ultrasonically clean with isoacetone for 5 minutes, rinse with deionized water 6 times, blow dry with nitrogen, and then dry with a hot plate. (2) Etch with KOH solution. Prepare a 4 mol / L KOH solution, heat it to 90°C, stir the solution with a magnetic tile, and etch for 90 minutes. (3) Next, clean the surface. Ultrasonically clean with anhydrous ethanol for 5 minutes. Then rinse the sample with deionized water and blow dry with nitrogen. Then remove silicon nitride and clean the surface. Etch with HF for 60 minutes, rinse the sample with deionized water, blow dry with nitrogen, and then dry with a hot plate.

[0085] In step nine, the epitaxial wafer etched with narrow trenches undergoes surface treatment. The deposition areas for the metal electrodes are marked using conventional photolithography. Electron beam evaporation is then used to complete electrode deposition, followed by high-temperature annealing to form ohmic contacts for the metal electrodes. Specifically:

[0086] First, surface treatment is performed: Since the surface of the epitaxial wafer used is a GaN cap layer, but the clean GaN surface is chemically active and easily oxidizes to form an oxide film. This oxide film has an adverse effect on ohmic resistance and, to some extent, also hinders the transport of charge carriers. Therefore, oxygen plasma treatment is performed for 2 minutes at a power of 200W, followed by acid washing with an HCl:H2O = 1:10 solution to complete the surface treatment process.

[0087] Then perform photolithography: (1) Coating: AZ5214 is selected as positive photoresist. It is spin-coated on the sample at 4000rpm for 30s to obtain a photoresist with a thickness of about 1.5um. (2) Baking: The sample is baked at 95℃ for 90s to remove the solvent on the film and enhance the adhesion between the photoresist and the silicon wafer. (3) Photolithography development: The sample is irradiated with ultraviolet light for 6.5s using Karl Suss MA6 and then treated with RZX-3038 developer for 45s to complete the development. (4) Washing and drying: Finally, the sample is washed with DI solution and dried with N2 gun.

[0088] Finally, electrode deposition and ohmic contact optimization were performed. (1) Electrode deposition: Ti / Al / Ni / Au (20 / 130 / 50 / 50nm) metal electrodes were deposited using electron beam evaporation. (2) Ohmic contact optimization: After metal stripping, the metal electrodes were rapidly annealed in an N2 environment at 875℃ for 30s using an RTP-500 rapid thermal treatment furnace to form ohmic contacts. Finally, a varistor device based on GaN heterojunction epitaxy was completed.

Claims

1. A varistor device based on GaN heterojunction epitaxy, characterized in that, It includes, in sequence from bottom to top, a substrate, an AlN / AlInGaN buffer layer, a uGaN buffer layer, a GaN channel layer, an AlN barrier insertion layer, an Al(In)GaN barrier layer, a GaN cap layer, and two metal electrodes; A trench is etched in the middle of the GaN cap layer, Al(In)GaN barrier layer, AlN barrier insertion layer, and part of the GaN channel layer; the two metal electrodes are distributed on both sides of the trench. The metal electrode has a four-layer structure from bottom to top: Ti, Al, Ni, and Au.

2. The varistor device based on GaN heterojunction epitaxy according to claim 1, characterized in that, The etching depth for forming a groove is 10-500 nm.

3. The varistor device based on GaN heterojunction epitaxy according to claim 1, characterized in that, The substrate is a high-resistivity silicon with a 111 crystal plane and a thickness of 1×10 6 nm; the AlN / AlInGaN buffer layer includes one AlN layer and three Al(In)GaN layers with different Al compositions and a C doping concentration of 5×10 18 cm⁻³, and the AlN / AlInGaN buffer layer has a thickness of 850 nm.

4. A varistor device based on GaN heterojunction epitaxy according to claim 1, characterized in that, The uGaN buffer layer has a thickness of 2000 nm, the GaN channel layer has a thickness of 100 nm, the AlN barrier insertion layer has a thickness of 1 nm, and the GaN cap layer has a thickness of 2 nm.

5. A varistor device based on GaN heterojunction epitaxy according to claim 1, characterized in that, The Al(In)GaN barrier layer contains 45% Al and 2% In, and has a thickness of 7 nm.

6. A varistor device based on GaN heterojunction epitaxy according to claim 1, characterized in that, The metal electrode is composed of 20nm reactive metal Ti, 130nm catalytic metal Al, 50nm isolation metal Ni, and 50nm electrode metal Au.

7. A method for fabricating a varistor device based on GaN heterojunction epitaxy as described in claim 1, characterized in that, Includes the following steps: Step 1: Select a substrate; Step 2: Grow an AlN / AlInGaN buffer layer on the substrate surface; Step 3: Grow a uGaN buffer layer on the surface of the AlN / AlInGaN buffer layer; Step 4: Grow a GaN channel layer on the surface of the uGaN buffer layer; Step 5: Grow an AlN barrier insertion layer on the surface of the GaN channel layer; Step 6: Grow an Al(In)GaN barrier layer on the surface of the AlN barrier insertion layer; Step 7: Grow a GaN cap layer on the surface of the Al(In)GaN barrier layer; Step 8: Etch the GaN cap layer, Al(In)GaN barrier layer, AlN barrier insertion layer and GaN channel layer to form a trench; Step 9: Deposit Ti / Al / Ni / Au metal electrodes on the GaN cap layer surfaces on both sides of the trench to finally complete the varistor device based on GaN heterojunction epitaxy.

8. The method for fabricating a varistor device according to claim 7, characterized in that, In step 2, an AlN / AlInGaN buffer layer is grown using chemical vapor deposition (CVD); in step 3, an uGaN buffer layer is grown using CVD; in step 4, a GaN channel layer is grown using CVD; in step 5, an AlN barrier insertion layer is grown using reactive magnetron sputtering (RMS); in step 6, an Al(In)GaN barrier layer is grown using CVD; and in step 7, a GaN cap layer is grown using CVD.

9. The method for fabricating a varistor device according to claim 7, characterized in that, In step 8, the etching method is either dry etching or wet etching to achieve trench etching of controllable depth.

10. The method for fabricating a varistor device according to claim 7, characterized in that, In step 9, the metal electrode is deposited using electron beam evaporation and then annealed at high temperature to achieve ohmic contact.

Images