A HEMT device structure with a P-type buried layer and its fabrication method

Abstract

This invention discloses a HEMT device structure with a P-type buried layer and its fabrication method, relating to the field of semiconductor technology. The device includes, from bottom to top, a substrate, a bottom GaN buffer layer, a top UID-GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a Si3N4 passivation layer, a source and a drain disposed at both ends of the top UID-GaN buffer layer, and a gate disposed on the AlGaN barrier layer. The source is also connected to three P-type buried layers disposed within the top UID-GaN buffer layer. In the AlGaN / GaN heterojunction epitaxy process, this invention uses a carbon-doped periodic GaN buffer layer as the bottom GaN buffer layer, which can effectively suppress leakage current flowing to the substrate in the vertical direction through the source or drain, reduce the dislocation density of the bottom GaN buffer layer, and improve the crystal quality. It can also reduce the leakage current flowing to the bottom GaN buffer layer. The HEMT device structure with three P-type buried layers connected to the source achieves a trade-off between breakdown voltage and on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a HEMT device structure with a P-type buried layer and a method for fabricating the aforementioned HEMT device structure with a P-type buried layer. Background Technology

[0002] As a third-generation semiconductor material, GaN power devices offer advantages over traditional silicon-based power devices, including higher temperature resistance, higher voltage resistance, stronger radiation resistance, and higher power output. Furthermore, the AlGaN / GaN heterojunction interface can generate a high-concentration, high-mobility two-dimensional electron gas, allowing for the formation of conductive channels without the need for n-type or p-type impurities, making it highly valuable for future applications. While theoretically GaN-based devices possess a very high critical breakdown electric field (approximately 3.3 MV / cm), and theoretically have a high breakdown voltage, the breakdown voltage of actual GaN HEMT (High Electron Mobility Transistor) devices is far lower than the theoretical value. The main reasons for premature breakdown in GaN HEMT devices are as follows:

[0003] 1. Gate electric field concentration effect. When a GaN HEMT device is off, the channel depletion region extends towards the drain. The electric field lines emitted by the positive charges in the depletion region concentrate towards the gate edge, forming a strong electric field peak at that point. The electric field distribution is very uneven, and the device breaks down due to avalanche ionization even at a small drain voltage. This is the main factor limiting the improvement of the breakdown voltage of GaN HEMT devices.

[0004] 2. Leakage current of the buffer layer. In the off state, the buffer layer with a high concentration of background carriers will form a leakage channel. Electrons injected from the source can pass through the GaN buffer layer to reach the drain. Excessive leakage current of the buffer layer will also cause premature breakdown of the device.

[0005] 3. Gate leakage current. The Schottky gate leakage current caused by the strong electric field near the gate is also one of the reasons that limits the breakdown voltage of the device.

[0006] To address the issues of gate field concentration and buffer layer leakage, common methods include adding a gate field plate and a high-resistivity buffer layer, such as doping the buffer layer with carbon or iron impurities. This is because MOCVD GaN growth inevitably introduces background n-type dopants, such as nitrogen vacancies, oxygen impurities, and carbon impurities. The insufficient resistivity of the UID-GaN buffer layer can lead to parasitic leakage paths, increasing off-state leakage current. Carbon-doped GaN reduces background carrier concentration and increases buffer layer resistivity by creating acceptor traps, thereby improving breakdown voltage. However, this reduces crystal quality, and the carbon-doped GaN also acts as acceptor traps, capturing the two-dimensional electron gas (2DEG) in the channel, leading to current collapse and limiting the improvement in breakdown voltage. Iron doping can also be used to capture background carriers. However, if only iron is used, the iron source has a memory effect, which can affect channel and barrier growth during epitaxial growth.

[0007] Therefore, effectively improving the crystal quality of GaN materials while effectively reducing the background carrier concentration is the key to the research of high-quality, high-resistivity epitaxial growth to realize GaN high breakdown voltage devices. Summary of the Invention

[0008] The purpose of this invention is to provide a method for fabricating a HEMT device structure with a P-type buried layer and a device obtained by the method, so as to solve the above-mentioned defects caused by the prior art.

[0009] A HEMT device structure with a P-type buried layer includes, from bottom to top, a substrate, a bottom GaN buffer layer, a top UID-GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a Si3N4 passivation layer, a source and a drain disposed at both ends of the top UID-GaN buffer layer, and a gate disposed on the AlGaN barrier layer. The source is also connected to three P-type buried layers disposed within the top UID-GaN buffer layer.

[0010] Furthermore, the substrate is a Si substrate with a size ranging from 2 to 8 inches.

[0011] Furthermore, the bottom GaN buffer layer is formed by periodically growing a carbon-doped GaN buffer layer and a UID-GaN buffer layer, with a thickness of 100 nm-10 μm and a carbon doping concentration of approximately 10%. 18 cm -3 -10 20 cm -3 .

[0012] Furthermore, the number of cycles of the carbon-doped GaN buffer layer and the UID-GaN buffer layer in the bottom GaN buffer layer is not less than 2.

[0013] Furthermore, the three P-type buried layers are each composed of three layers of GaN material with different Mg doping concentrations. The Mg doping concentration in the three P-type buried layers decreases from top to bottom, and the carbon doping concentration in the three P-type buried layers is 10. 17 cm -3 -10 19 cm -3 .

[0014] This invention also discloses a method for fabricating a HEMT device structure with a P-type buried layer, comprising the following steps:

[0015] (1) An unintentional doping method is used to grow a bottom GaN buffer layer on the substrate by metal-organic source chemical vapor deposition or other methods;

[0016] (2) A top UID-GaN buffer layer is grown on the bottom GaN buffer layer by metal-organic source chemical vapor deposition or other methods without intentional doping. After the top UID-GaN buffer layer grows to a certain thickness, a P-type buried layer is grown on the top UID-GaN buffer layer.

[0017] (3) After the P-type buried layer is grown, it is taken out from MOCVD and etched by inductively coupled plasma or other etching processes until the middle buffer layer is exposed, leaving the left part of the P-type buried layer in order to generate a buried layer structure connected to the source.

[0018] (4) Continue to epitaxially grow the top UID-GaN buffer layer, GaN channel layer and AlGaN barrier layer on the remaining P-type buried layer and the top UID-GaN buffer layer by MOCVD or other methods.

[0019] (5) Deposit a Si3N4 passivation layer on the AlGaN barrier layer;

[0020] (6) The Si3N4 passivation layer is etched by inductively coupled plasma process to expose the gate window, source window and drain window, and the corresponding AlGaN barrier layer is exposed. Then, the digital etching process of low-damage oxide HCl immersion is used to etch to the upper surface of the P-type buried layer on the left side of the device and to the upper surface of the channel layer on the right side of the device. Then, Ni / Au metal is deposited in the gate window to form the gate.

[0021] (7) Titanium, aluminum, nickel and gold are deposited by electron beam evaporation to form titanium / aluminum / nickel / gold metal layers for source / drain ohmic contacts. Then, they are rapidly thermally annealed in N2 environment to form the source connected to the P-type buried layer and the drain located at the right end of the top UID-GaN buffer layer.

[0022] The advantages of this invention are:

[0023] This device is a GaN-based high electron mobility transistor power device. In the AlGaN / GaN heterojunction epitaxy process, a carbon-doped periodic GaN buffer layer is used as the bottom GaN buffer layer. The thin layer with a high trap concentration can effectively suppress the leakage current flowing to the substrate in the vertical direction through the source or drain. The thin layer with a low trap concentration can reduce the dislocation density of the bottom GaN buffer layer, improve the crystal quality, and also reduce the leakage current flowing to the bottom GaN buffer layer.

[0024] The top UID-GaN buffer layer consists of three P-type buried layers with different Mg doping concentrations connected to the source, and the UID-GaN buffer layer. Because the high-concentration carbon compensation impurities used to reduce buffer layer leakage current and improve device breakdown voltage easily trap electrons in the entire 2DEG channel above the buffer layer, causing a significant degradation in characteristic on-resistance, a method based on electric field modulation was designed to embed a P-type buried layer connected to the source within a GaN buffer layer with low-concentration trap compensation impurities. The electron trapping in the top buffer layer can reduce the lateral leakage current flowing from the drain through the buffer layer to the source. Simultaneously, due to the lower trap concentration, compared to high-concentration traps, it can reduce the electron trapping effect on the 2DEG in the channel, thus reducing buffer layer leakage current. This also improves the electric field distribution in the device, enabling it to achieve a breakdown voltage comparable to high-voltage devices with a shorter gate-drain distance and a higher BFOM (BV). 2 / Ron.sp).

[0025] However, for conventional lateral P-type buried layers, the buried layer consumes some electrons in the channel, resulting in a degradation in on-resistance compared to devices without buried layers. A typical single-layer P-type buried layer has several key parameters: concentration (Nmg), distance from the gate to the drain (Ls), and spacing from the channel layer (Lbm). This study analyzes the impact of the P-type buried layer on breakdown characteristics by varying these parameters. Different values ​​of the spacing (Lbm) result in different characteristic on-resistance values ​​(Ron.sp). A smaller Lbm value leads to a larger characteristic on-resistance because holes in the P-type buried layer diffuse and recombine with some electrons in the two-dimensional electron gas. Therefore, the smaller the Lbm value, the closer the buried layer is to the channel, resulting in more recombinated electrons, reduced current, and increased on-resistance. However, when the spacing Lbm between the P-type buried layer and the channel layer is too large, the high electric field region of the P-type buried layer is far from the high electric field region of the gate plate, resulting in weaker electric field coupling modulation and a decrease in the breakdown voltage BV. As Ls decreases, the modulation effect of the P-type buried layer on the electric field increases, and the breakdown voltage also increases. There is a trade-off between the characteristic on-resistance Ron.sp and the breakdown voltage BV. In addition, the Mg doping concentration of the P-type buried layer generally has a certain impact on the characteristic on-resistance and breakdown voltage of the device. The higher the concentration of the P-type buried layer, the higher the on-resistance and breakdown voltage BV due to the consumption effect of 2DEG and the enhanced electric field modulation. Therefore, a HEMT device structure with a three-layer P-type buried layer connected to the source was designed. The Mg doping concentration in the buried layers decreases from top to bottom, with the highest concentration closest to the channel layer. This concentration better modulates the channel electric field and increases the breakdown voltage (BV). Simultaneously, the concentrations of the two lower buried Mg layers gradually decrease, reducing the trapping effect of holes on the two-dimensional electron gas in the channel. This prevents an excessive increase in the device's characteristic on-resistance, and the relatively greater distance from the channel weakens the channel electric field modulation effect, thus having a minimal impact on the device's BV. The designed device achieves a trade-off between breakdown voltage and on-resistance. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the present invention.

[0027] The structure consists of: 101 substrate, 102 bottom GaN buffer layer, 103 top UID-GaN buffer layer, 104 P-type buried layer 1, 105 P-type buried layer 2, 106 P-type buried layer 3, 107 GaN channel layer, 108 AlGaN barrier layer, 109 source, 110 drain, 111 gate, and 112 Si3N4 passivation layer. Detailed Implementation

[0028] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0029] A method for fabricating a HEMT device structure with a P-type buried layer includes the following steps:

[0030] (1) A bottom GaN buffer layer 102 is grown on the substrate 101 by unintentional doping using metal-organic source chemical vapor deposition or other methods;

[0031] (2) A top UID-GaN buffer layer 103 is grown on the bottom GaN buffer layer 102 by metal-organic source chemical vapor deposition or other methods without intentional doping. After the top UID-GaN buffer layer 103 grows to a certain thickness, a P-type buried layer is grown on the top UID-GaN buffer layer 103.

[0032] (3) After the P-type buried layer is grown, it is taken out from MOCVD and etched by inductively coupled plasma process or other etching process until the middle buffer layer is exposed, leaving the left part of the P-type buried layer in order to generate a buried layer structure connected to the source 109.

[0033] (4) Continue to epitaxially grow the top UID-GaN buffer layer 103, GaN channel layer 107 and AlGaN barrier layer 108 on the remaining P-type buried layer and the top UID-GaN buffer layer 103 by MOCVD or other methods.

[0034] (5) Deposit a Si3N4 passivation layer 112 on the AlGaN barrier layer;

[0035] (6) The Si3N4 passivation layer is etched by inductively coupled plasma process to expose the gate window, source window and drain window, and the corresponding AlGaN barrier layer is exposed. Then, the digital etching process of low-damage oxide HCl immersion is used to etch to the upper surface of the P-type buried layer on the left side of the device and to the upper surface of the channel layer 107 on the right side of the device. Then, Ni / Au metal is deposited in the gate window to form the gate 111.

[0036] (7) Titanium, aluminum, nickel and gold are deposited by electron beam evaporation to form titanium / aluminum / nickel / gold metal layers for source / drain ohmic contacts. Then, rapid thermal annealing is performed in N2 environment to finally form a source 109 connected to the P-type buried layer and a drain 110 located at the right end of the top UID-GaN buffer layer 103.

[0037] In this embodiment, the substrate 101 is made of Si material.

[0038] The HEMT device structure fabricated using the above method includes, from bottom to top, a substrate 101, a bottom GaN buffer layer 102, a top UID-GaN buffer layer 103, a GaN channel layer 107, an AlGaN barrier layer 108, a Si3N4 passivation layer 112, a source 109 and a drain 110 disposed at both ends of the top UID-GaN buffer layer 103, and a gate 111 disposed on the AlGaN barrier layer. The source 109 is also connected to three P-type buried layers disposed in the top UID-GaN buffer layer 103. The substrate 101 is a Si substrate with a size ranging from 2 to 8 inches.

[0039] In this embodiment, the bottom GaN buffer layer 102 is formed by periodically growing a carbon-doped GaN buffer layer and a UID-GaN buffer layer, with a thickness of 100 nm-10 μm and a carbon doping concentration of approximately 10%. 18 cm -3 -10 20 cm -3 Among them, the number of cycles of the carbon-doped GaN buffer layer and the UID-GaN buffer layer in the bottom GaN buffer layer 102 is not less than 2.

[0040] In this embodiment, the three P-type buried layers are each composed of three layers of GaN material with different Mg doping concentrations. The Mg doping concentration in the three P-type buried layers (P-type buried layer 104, P-type buried layer 105, and P-type buried layer 106) decreases from top to bottom. The carbon doping concentration in the three P-type buried layers is 10. 17 cm -3 -10 19 cm -3 .

[0041] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. A HEMT device structure with a P-type buried layer, characterized in that, The system includes, from bottom to top, a substrate (101), a bottom GaN buffer layer (102), a top UID-GaN buffer layer (103), a GaN channel layer (107), an AlGaN barrier layer (108), a Si3N4 passivation layer (112), a source (109) and a drain (110) disposed at both ends of the top UID-GaN buffer layer (103), and a gate (111) disposed on the AlGaN barrier layer. The source (109) is also connected to three P-type buried layers disposed in the top UID-GaN buffer layer (103). The bottom GaN buffer layer (102) is formed by periodically growing a carbon-doped GaN buffer layer and a UID-GaN buffer layer, with a thickness of 100 nm-10 μm and a carbon doping concentration of 10%. 18 cm -3 -10 20 cm -3 .

2. The HEMT device structure with a P-type buried layer according to claim 1, characterized in that, The substrate (101) is a Si substrate with a size ranging from 2 to 8 inches.

3. The HEMT device structure with a P-type buried layer according to claim 1, characterized in that, The number of cycles of the carbon-doped GaN buffer layer and the UID-GaN buffer layer in the bottom GaN buffer layer (102) is not less than 2.

4. The HEMT device structure with a P-type buried layer according to claim 3, characterized in that, The three-layer P-type buried layer consists of three layers of GaN material with different Mg doping concentrations. The Mg doping concentration decreases from top to bottom in the three-layer P-type buried layer. The carbon doping concentration in the three-layer P-type buried layer is 10. 17 cm -3 -10 19 cm -3 .

5. The method for fabricating a HEMT device structure with a P-type buried layer according to claim 4, characterized in that, Includes the following steps: (1) A bottom GaN buffer layer (102) is grown on a substrate (101) by unintentional doping using metal-organic source chemical vapor deposition; (2) A top UID-GaN buffer layer (103) is grown on the bottom GaN buffer layer (102) by unintentional doping using metal-organic source chemical vapor deposition. After the top UID-GaN buffer layer (103) grows to a certain thickness, a P-type buried layer is grown on the top UID-GaN buffer layer (103). (3) After the P-type buried layer is grown, it is taken out from MOCVD and the right side region of the P-type buried layer is etched by inductively coupled plasma process until the middle buffer layer is exposed, leaving the left side of the P-type buried layer in order to generate a buried layer structure connected to the source (109). (4) Continue to grow the top UID-GaN buffer layer (103), GaN channel layer (107) and AlGaN barrier layer (108) on the remaining P-type buried layer and the top UID-GaN buffer layer (103) by MOCVD. (5) Deposit a Si3N4 passivation layer on the AlGaN barrier layer (112); (6) The Si3N4 passivation layer (112) is etched by inductively coupled plasma process to expose the gate window, source window and drain window, and the corresponding AlGaN barrier layer (108) is exposed. Then, the device is etched by digital etching process with low damage HCl immersion. The device is etched to the upper surface of the P-type buried layer (104, 105, 106) on the left side and to the upper surface of the channel layer (107) on the right side. Then, Ni / Au metal is deposited on the gate window to form the gate (111). (7) Titanium, aluminum, nickel and gold are deposited by electron beam evaporation to deposit titanium / aluminum / nickel / gold metal layers for source / drain ohmic contacts, and then rapidly thermally annealed in N2 environment to finally form a source (109) connected to the P-type buried layer (104, 105, 106) and a drain (110) located at the right end of the top UID-GaN buffer layer (103).

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