A memory and a method for manufacturing the same

Abstract

The present invention provides a memory and a manufacturing method thereof, including: a substrate, having trenches therein; a source line layer, located in the trenches and extending upward; a metal floating gate structure, located in the trenches, including a metal floating gate layer and a blocking layer that sequentially cover the sidewalls of the source line layer from the inside to the outside; a word line layer, located on the substrate and covering the side of the blocking layer away from the source line layer. The blocking layer can block the diffusion of free metal ions to others, thereby improving the continuity of the metal floating gate layer, preventing the metal floating gate layer from breaking in a high-temperature environment, and enhancing the stability of the memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a memory and a method for manufacturing the same. Background Art

[0002] With the development of microelectronics, memories are required to provide higher speed, lower power consumption and higher integration. For traditional polysilicon floating gate memories, the thickness of the polysilicon floating gate decreases as the device feature size decreases. When the number of incident electrons with high energy increases, a large number of high-energy incident electrons will pass through the polysilicon floating gate and cause damage to the substrate, generating more defects and affecting the reliability of the device. To overcome this problem, a solution of using metal instead of polysilicon as the floating gate has been proposed. However, due to the poor stability of the metal material used in the metal floating gate layer under conditions such as high temperature, the metal floating gate layer is prone to breakage during the preparation and use of the memory, affecting the reliability of the metal floating gate memory. Summary of the Invention

[0003] The purpose of the present invention is to provide a memory and a method for manufacturing the same to solve the problem of poor continuity of the existing metal floating gate.

[0004] To achieve the above purpose, the present invention provides a memory, including:

[0005] A substrate having trenches therein;

[0006] A source line layer located in the trenches and extending upward;

[0007] A metal floating gate structure located in the trenches, including a metal floating gate layer and a barrier layer covering the sidewalls of the source line layer in sequence from inside to outside;

[0008] A word line layer located on the substrate and covering the side of the barrier layer away from the source line layer.

[0009] Optionally, it further includes:

[0010] A dielectric layer covering the word line layer, the source line layer and the metal floating gate structure;

[0011] An erase gate located on the dielectric layer.

[0012] Optionally, the thickness of the barrier layer is

[0013] Optionally, the material of the barrier layer includes hafnium oxide or titanium carbide.

[0014] Optionally, the thickness of the metal floating gate layer is

[0015] Optionally, the material of the metal floating gate layer is titanium nitride.

[0016] Based on the same inventive concept, the present invention also provides a method for manufacturing a memory, characterized by comprising:

[0017] Providing a substrate and forming a trench in the substrate;

[0018] Forming a source line layer and a metal floating gate structure in the trench, the source line layer and the metal floating gate structure are both located in the trench and extend upward, and the metal floating gate structure includes a metal floating gate layer and a blocking layer that sequentially cover the side wall of the source line layer from the inside to the outside;

[0019] Forming a word line layer on the substrate, the word line layer covering the side of the blocking layer away from the source line layer.

[0020] Optionally, the substrate includes a storage area and a non-storage area, the trench is formed in the storage area, and the step of forming the trench on the substrate includes:

[0021] Sequentially forming a stacked first oxide layer, a word line material layer, a second oxide layer, and a hard mask layer on the substrate;

[0022] Sequentially etching the hard mask layer, the second oxide layer, the word line material layer, and the first oxide layer on the storage area until an opening exposing the substrate is formed;

[0023] Continuing to etch a part of the substrate downward along the opening so that the opening extends into the substrate, and the part of the opening located in the substrate constitutes the trench.

[0024] Optionally, after forming the trench and before forming the source line layer and the metal floating gate structure in the trench, it further includes:

[0025] Conformally forming a blocking material layer, a metal floating gate material layer, and a first blocking oxide layer on the substrate, the blocking material layer, the metal floating gate material layer, and the first blocking oxide layer sequentially covering the hard mask layer and the inner wall of the opening;

[0026] Removing the first blocking oxide layer, the metal floating gate material layer, and the blocking material layer on the non-storage area.

[0027] Optionally, the step of forming the metal floating gate structure includes:

[0028] Forming a second blocking oxide layer on the first blocking oxide layer, the second blocking oxide layer extending to cover the inner wall of the opening and the hard mask layer of the non-storage area;

[0029] Etch the second barrier oxide layer and the first barrier oxide layer using an anisotropic etching process, and retain the first barrier oxide layer and the second barrier oxide layer on the sidewalls of the opening;

[0030] Using the second barrier oxide layer and the first barrier oxide layer as masks, sequentially remove the metal floating gate material layer and the barrier material layer on the hard mask layer and at the bottom of the opening. The remaining barrier material layer and metal floating gate material layer respectively form the barrier layer and the metal floating gate layer;

[0031] Remove the remaining first barrier oxide layer and second barrier oxide layer.

[0032] Optionally, use a first wet etching process to etch the metal floating gate material layer on the hard mask layer and at the bottom of the opening. The etching agent used in the first wet etching process is a mixed solution of NH4OH and hydrogen peroxide.

[0033] Optionally, use a second wet etching process to etch the barrier material layer on the hard mask layer and at the bottom of the opening. The etching agent used in the second etching process is hydrofluoric acid.

[0034] The present invention provides a memory and a method for manufacturing the same, including: a substrate having a trench therein; a source line layer located in the trench and extending upward; a metal floating gate structure located in the trench, including a metal floating gate layer and a barrier layer that sequentially cover the sidewalls of the source line layer from the inside to the outside; a word line layer located on the substrate and covering the side of the barrier layer away from the source line layer. When the memory undergoes high-temperature processes such as ion implantation or thermal oxidation, chemical bonds in the metal floating gate layer break to generate free metal ions, and the barrier layer can block the diffusion of free metal ions to other film layers; and a metal-metal chemical bond with better stability will be formed between the barrier layer and the metal floating gate layer, further preventing the diffusion of metal ions, thereby improving the continuity of the metal floating gate layer, preventing the metal floating gate layer from breaking in a high-temperature environment, and enhancing the stability of the memory. Description of the Drawings

[0035] Figure 1 It is a schematic structural diagram of a metal floating gate memory;

[0036] Figure 2 is Figure 1 a scanning electron microscope schematic diagram of the metal floating gate memory shown;

[0037] Figure 3 It is a flowchart of the method for manufacturing the memory provided by the embodiment of the present invention;

[0038] Figures 4 to 15Schematic structural diagrams corresponding to the respective steps of the method for manufacturing a memory provided by an embodiment of the present invention, wherein, Figure 15 Schematic structural diagram of a memory provided by an embodiment of the present invention;

[0039] Figure 16 is Figure 15 Schematic electron microscope diagram of the memory shown;

[0040] Among them, the reference numerals are:

[0041] A - storage area; B - non - storage area;

[0042] 300, 100 - substrate; 101 - first oxide layer; 102 - word - line material layer; 103 - second oxide layer; 104 - hard mask layer; 302, 105 - tunneling oxide layer; 106 - barrier material layer; 107 - metal floating - gate material layer; 108 - first barrier oxide layer; 109 - second barrier oxide layer; 305, 111 - source - line layer; 307, 112 - source region; 113, 310 - drain region 310;

[0043] 301 - trench; 20 - opening; 308, 21 - first sidewall; 309, 22 - second sidewall; 23 - photoresist layer; 24 - barrier layer; 304, 25 - metal floating - gate layer; 306, 26 - word - line layer; 303, 27 - gate dielectric layer; 28 - dielectric layer; 29 - erase gate. Detailed implementation manners

[0044] Figure 1 Schematic structural diagram of a metal - floating - gate memory, as Figure 1 shown, the metal - floating - gate memory includes: a substrate 300, a source - line layer 305, a metal floating - gate layer 304, and a word - line layer 306.

[0045] Specifically, the substrate 300 has a trench 301 and a source region 307 at the bottom of the trench 301. The source - line layer 305 and the metal floating - gate 304 are both located in the trench 301 and extend upward. The metal floating - gate layer 304 covers the sidewalls of the source - line layer 305. The word - line layer 306 is respectively located on the substrate 300 outside the metal floating - gate 304, and a drain region 310 is provided in the substrate 300 outside each word - line layer 306. There is also a gate dielectric layer 303 between the source - line layer 305 and the metal floating - gate layer 304. There are a first sidewall 308 and a second sidewall 309 between the metal floating - gate layer 304 and the word - line layer 306. The second sidewall 309 covers the sidewalls of the word - line layer 306 and part of the sidewalls of the metal floating - gate layer 304, and the second sidewall 309 covers at least the remaining sidewalls of the metal floating - gate layer 304.

[0046] Among them, the material of the metal floating gate layer 304 is generally titanium nitride, and the materials of the gate dielectric layer 303, the first sidewall 308 and the second sidewall 309 are all silicon oxide. Generally, the titanium nitride generated in semiconductor processes is titanium nitride (Ti3N4). A chemical bond is formed between nitrogen ions and metal titanium ions to form the crystal structure of titanium nitride. However, the thermal stability of the nitrogen-titanium chemical bond is poor. During the fabrication process of the metal floating gate memory, processes such as ion implantation, annealing, and thermal oxidation are required, and the device is in a high-temperature environment of 900 °C to 1200 °C. The nitrogen-titanium chemical bond will break in the high-temperature environment, generating free metal titanium ions. At this time, the free metal titanium ions will diffuse into the silicon oxide layer, resulting in uneven concentration of metal titanium ions in the metal floating gate layer 304, thereby affecting the continuity and uniformity of the metal floating gate layer 304; Figure 2 is Figure 1 a schematic electron microscope diagram of the metal floating gate memory shown, as Figure 2 shown. Since the thickness of the metal floating gate layer 304 is small, the diffusion of metal titanium ions may even cause the metal floating gate layer 304 to break, seriously affecting the reliability of the metal floating gate memory.

[0047] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0048] In the following text, terms such as "first" and "second" are used to distinguish between similar elements, and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms may be replaced. Similarly, if the methods described herein include a series of steps, and the steps presented herein are not necessarily the only order in which these steps can be performed, and some of the described steps may be omitted and / or some other steps not described in the text may be added to the method.

[0049] Figure 15 is a schematic structural diagram of the memory provided in this embodiment, as Figure 15 shown. The memory includes: a substrate 100, a source line layer 111, a metal floating gate structure, a word line layer 26, a dielectric layer 28, and an erase gate 29.

[0050] Specifically, the substrate 100 has a storage area A and a non-storage area B. On the substrate 100 in the storage area A, there are trenches and a source region 112 located at the bottom of the trenches. The source line layer 111 and the metal floating gate structure are both located in the trenches and extend upward. In this embodiment, the upper surface of the source line layer 111 is lower than the upper surface of the metal floating gate structure. The metal floating gate structure includes a metal floating gate layer 25 and a blocking layer 24 that sequentially cover the sidewalls of the source line layer 111 from the inside to the outside; the word line layer 26 is located on the substrate 100 and covers the side of the blocking layer 24 away from the source line layer 111; the dielectric layer 28 covers the word line layer 26, the source line layer 111, and the metal floating gate structure, and the erase gate 29 is located on the dielectric layer 28.

[0051] In addition, a tunneling oxide layer 105 is provided on the inner wall of the trench. A gate dielectric layer 27 is also provided between the metal floating gate layer 25 and the source line layer 111. A first oxide layer 101 is provided between the word line layer 26 and the substrate 100; a first sidewall 21 and a second sidewall 22 are also provided between the word line layer 26 and the blocking layer 24. The second sidewall 22 covers the side of the word line layer 26 close to the source line layer 111 and covers a part of the sidewall of the blocking layer 24. The first sidewall 21 covers at least the remaining sidewall of the blocking layer 24 and the upper surface of the word line layer 26.

[0052] Among them, the material of the metal floating gate layer 25 is titanium nitride (titanium tetranitride, Ti3N4), and the thickness of the metal floating gate layer 25 is The material of the blocking layer 24 is hafnium oxide or titanium carbide, and the thickness of the blocking layer 24 is The materials of the first sidewall 21, the second sidewall 22, and the gate dielectric layer 27 are all silicon oxide.

[0053] During the preparation process of the memory, processes such as ion implantation, annealing, and thermal oxidation are required. At this time, the memory will be in a high-temperature environment of 900 °C to 1200 °C. The nitrogen-titanium chemical bond in titanium nitride will break under high-temperature conditions, generating free metal titanium ions. The blocking layer 24 isolates the first sidewall 21 and the second sidewall 22 from the metal floating gate layer 25, preventing the free metal titanium ions from diffusing into the first sidewall 21 and the second sidewall 22; and a metal chemical bond will be formed between the metal floating gate layer 25 and the blocking layer 24. For example, when the material of the blocking layer 24 is hafnium oxide, a titanium-hafnium chemical bond will be formed between the hafnium oxide and the titanium nitride, making the free titanium ions form a stable structure, further preventing the free metal titanium ions from diffusing into other film layers and ensuring the continuity of the metal floating gate layer 25; the same is true when the material of the blocking layer 24 is titanium carbide. Figure 16 ForFigure 15 The SEM schematic diagram of the memory shown, comparing Figure 2 with Figure 16 it can be seen that after adding the barrier layer 24, the continuity of the metal floating gate layer 25 is significantly improved.

[0054] In addition, hafnium oxide and titanium carbide also have good electrical conductivity and thermal stability, and it is easy to form a film layer with a small thickness, which will not affect the performance and size of the memory. In this embodiment, the material of the barrier layer 24 is not limited, and it is only necessary to ensure that the barrier layer 24 can block the diffusion of the free metal titanium ions to other film layers.

[0055] Based on this, this embodiment also provides a method for manufacturing a memory, Figure 3 which is a flowchart of the method for manufacturing the memory. As Figure 3 shown, the method for manufacturing the memory includes:

[0056] Step S1: Provide a substrate and form a trench in the substrate;

[0057] Step S2: Form a source line layer and a metal floating gate structure in the trench. The source line layer and the metal floating gate structure are both located in the trench and extend upward. The metal floating gate structure includes a metal floating gate layer and a barrier layer that sequentially cover the side wall of the source line layer from the inside to the outside;

[0058] Step S3: Form a word line layer on the substrate, and the word line layer covers the side of the barrier layer away from the source line layer.

[0059] Figures 4 to 15 is a schematic structural diagram of the corresponding steps of the method for manufacturing the memory provided in this embodiment. Next, it will be combined with Figures 4 to 15 to describe the method for manufacturing the memory in detail.

[0060] As Figure 4 shown, provide a substrate 100. The substrate 100 has a storage area A and a non-storage area B. A stacked first oxide layer 101, a word line layer material layer 102, a second oxide layer 103, and a hard mask layer 104 are sequentially formed on the substrate 100.

[0061] As Figure 5As shown, etch the hard mask layer 104 and the second oxide layer 103 on the storage area A until the word line material layer 102 is exposed to form an opening 20; form a first sidewall 21 in the opening 20, and the first sidewall 21 covers the sidewalls of the opening 20; then continue to etch the word line material layer 102 and the first oxide layer 101 downward with the first sidewall 21 as a mask to deepen the opening 20 until the substrate 100 is exposed; form a second sidewall 22 in the opening 20, and the second sidewall 22 covers the sidewalls of the word line material layer 102 and the first oxide layer 101; then continue to etch a part of the substrate 100 with the first sidewall 21 and the second sidewall 22 as masks so that the opening 20 extends into the substrate 100, and the part of the opening 20 located in the substrate 100 constitutes the trench, wherein the depth of the trench is

[0062] Further, using the opening 20 as an alignment window, perform a first ion implantation process on the substrate 100 at the bottom of the trench to form a source region 112 in the substrate 100 at the bottom of the trench; then form a tunneling oxide layer 105 in the trench, and the tunneling oxide layer 105 covers the inner walls of the trench.

[0063] It should be noted that this embodiment only illustrates a structural schematic diagram of forming the opening 20 in the storage area A, and the opening 20 can also be formed synchronously on the non-storage area B in other alternative embodiments.

[0064] As Figure 6 shown, conformally form a barrier material layer 106, a metal floating gate material layer 107, and a first barrier oxide layer 108 on the substrate 100, and the barrier material layer 106, the metal floating gate material layer 107, and the first barrier oxide layer 108 sequentially cover the hard mask layer 104, the first sidewall 21, and the inner walls of the opening 20.

[0065] Among them, the material of the barrier material layer 106 is hafnium oxide or titanium carbide, and the thickness of the barrier material layer 106 is The material of the metal floating gate material layer 107 is titanium nitride (titanium nitride, Ti3N4), and the thickness of the metal floating gate material layer 107 is The first barrier oxide layer 108 is formed by atomic layer deposition (ALD) process, and the thickness of the first barrier oxide layer 108 is When performing the ALD process, the temperature is generally 200°C to 400°C. Selecting a process with a lower temperature can prevent the chemical bonds of the titanium nitride from breaking and the diffusion of metal titanium ions in a high-temperature environment, ensuring the continuity and uniformity of the metal floating gate material layer 107.

[0066] It should be noted that when the metal floating gate material layer 107 is formed, titanium nitride will form some metal chemical bonds with hafnium oxide or titanium carbide in the barrier material layer 106. The thermal stability of the metal chemical bonds is good, which can effectively reduce the number of free titanium ions generated in a high-temperature environment.

[0067] Further refer to Figures 6 to 7 , a photoresist layer 23 is formed on the first barrier oxide layer 108, and the photoresist layer 23 is subjected to an exposure and development process. The patterned photoresist layer 23 covers the first barrier oxide layer 108 on the storage area A; and using the photoresist layer 23 as a mask, the first barrier oxide layer 108 on the non-storage area B is removed by a dry etching process until the metal floating gate material layer 107 is exposed; finally, the photoresist layer 23 is removed by a dry ashing process.

[0068] As Figure 8 shown, using the first barrier oxide layer 108 as a mask, the metal floating gate material layer 107 and the barrier material layer 106 in the non-storage area B are sequentially removed.

[0069] As Figures 9 to 10 shown, since the first barrier oxide layer 108 will be eroded by the etchant during the etching of the metal floating gate material layer 107 and the barrier material layer 106 in the non-storage area B and cannot effectively protect the metal floating gate material layer 107, a second barrier oxide layer 109 is formed on the first barrier oxide layer 108. The second barrier oxide layer 109 covers the first barrier oxide layer 108, the hard mask layer 104 in the non-storage area B and extends to cover the inner wall of the opening 20; the same as the first barrier oxide layer 108, the second barrier oxide layer 109 is formed by the ALD process in this embodiment to prevent the damage to the metal floating gate material layer 107 caused by high-temperature processes, and the thickness of the second barrier oxide layer 109 is

[0070] Further, an anisotropic etching process is used to etch the second barrier oxide layer 109 and the first barrier oxide layer 108, and the first barrier oxide layer 108 and the second barrier oxide layer 109 on the sidewall of the opening 20 are retained.

[0071] As Figure 11As shown, using the first barrier oxide layer 108 and the second barrier oxide layer 109 as masks, the metal floating gate material layer 107 and the barrier material layer 106 on the hard mask layer 104 and at the bottom of the opening 20 are sequentially removed. The remaining barrier material layer 106 and metal floating gate material layer 107 respectively form the barrier layer 24 and the metal floating gate layer 25.

[0072] Specifically, the metal floating gate material layer 107 is etched by a first wet etching process, and the etching agent of the first wet etching process is a mixed solution of NH4OH and hydrogen peroxide; then the barrier layer material layer 106 is etched by a second wet etching process. The etching agent used in the second wet etching process is hydrofluoric acid, and the concentration of the hydrofluoric acid is relatively low. The hydrofluoric acid has good selectivity for metal compounds and can avoid corroding the substrate 100 while removing the barrier material layer 106.

[0073] As Figures 12 to 13 shown, the remaining first barrier oxide layer 108 and second barrier oxide layer 109 in the opening 20 are removed; then a gate dielectric layer 27 is formed in the opening 20, and the gate dielectric layer 27 covers the sidewalls of the metal floating gate layer 25. Since the first barrier oxide layer 108 and the second barrier oxide layer 109 will be corroded by the etching agent in the etching process, affecting the properties of the film layer, regenerating the gate dielectric layer 27 is beneficial to ensuring the reliability of the memory; finally, a source line layer 111 is formed in the opening 20, and the source line layer 111 at least fills part of the opening 20.

[0074] As Figure 14 shown, the hard mask layer 104 and the second oxide layer 103 are removed, and the word line material layer 102 and the first oxide layer 101 are etched using the first sidewall 21 as a mask. The remaining word line material layer 102 forms the word line layer 26.

[0075] Further, as Figure 15 shown, a second ion implantation process is performed on the substrate 100 outside the word line layer 26 to form a drain region 113 in the substrate 100 outside each word line layer 26; then a dielectric layer 28 and an erase gate 29 are formed on the substrate 100. The dielectric layer 28 covers the word line layer 26, the source line layer 111, and the metal floating gate structure, and the erase gate 29 is located on the dielectric layer 28 and corresponds to the metal floating gate structure.

[0076] After the second ion implantation process, an annealing process is performed on the memory. The temperature of the annealing process is 900°C to 1200°C. The nitrogen-titanium chemical bond in the metal floating gate layer 24 will break during the annealing process to form partially free metal titanium ions, and the barrier layer 25 can effectively prevent the diffusion of the metal titanium ions.

[0077] In summary, the embodiment of the present invention provides a memory and a method for manufacturing the same, including: a substrate 100 having a trench therein; a source line layer 111 located in the trench and extending upward; a metal floating gate structure located in the trench, including a metal floating gate layer 25 and a barrier layer 24 that sequentially cover the sidewall of the source line layer 111 from the inside to the outside; and a word line layer 26 located on the substrate 100 and covering the side of the barrier layer 24 away from the source line layer 111. When high-temperature processes such as ion implantation, annealing, or thermal oxidation are performed on the memory, the chemical bond in the metal floating gate layer 25 breaks to generate free metal ions, and the barrier layer 24 can block the diffusion of the free metal ions to other film layers; and a metal-metal chemical bond with better stability is formed between the barrier layer 24 and the metal floating gate layer 25, which can further prevent the diffusion of metal ions, thereby improving the continuity of the metal floating gate layer 25, preventing the metal floating gate layer 25 from breaking in a high-temperature environment, and enhancing the stability of the memory.

[0078] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed in the present invention, all of which belong to the content of the technical solution of the present invention and are still within the protection scope of the present invention.

Claims

1. A memory, characterized in that, Comprising: A substrate having trenches therein; A source line layer located within the trenches and extending upward; A metal floating gate structure located within the trenches, comprising a metal floating gate layer and a blocking layer that sequentially cover the sidewalls of the source line layer from the inside out, the material of the blocking layer being hafnium oxide or titanium carbide, and the material of the metal floating gate layer being titanium nitride; A word line layer located on the substrate and covering the side of the blocking layer away from the source line layer; There is also a sidewall between the word line layer and the blocking layer, and the sidewall covers the side of the word line layer close to the source line layer.

2. The memory according to claim 1, characterized in that, Also comprising: A dielectric layer covering the word line layer, the source line layer, and the metal floating gate structure; An erase gate located on the dielectric layer.

3. The memory according to claim 1, characterized in that, The thickness of the blocking layer is 20 Å to 30 Å.

4. The memory according to claim 1, characterized in that, The thickness of the metal floating gate layer is 30 Å to 50 Å.

5. A method for preparing a memory, characterized in that, Comprising: Providing a substrate and forming trenches in the substrate; Forming a source line layer and a metal floating gate structure in the trenches, both the source line layer and the metal floating gate structure being located within the trenches and extending upward, the metal floating gate structure comprising a metal floating gate layer and a blocking layer that sequentially cover the sidewalls of the source line layer from the inside out, the material of the blocking layer being hafnium oxide or titanium carbide, and the material of the metal floating gate layer being titanium nitride; Forming a word line layer on the substrate, the word line layer covering the side of the blocking layer away from the source line layer; There is also a sidewall between the word line layer and the blocking layer, and the sidewall covers the side of the word line layer close to the source line layer.

6. The method for preparing a memory according to claim 5, wherein The substrate includes a storage area and a non-storage area, the trenches are formed in the storage area, and the step of forming the trenches in the substrate includes: Sequentially forming a stacked first oxide layer, a word line material layer, a second oxide layer, and a hard mask layer on the substrate; Sequentially etching the hard mask layer, the second oxide layer, the word line material layer, and the first oxide layer on the storage area until an opening exposing the substrate is formed; Continuing to etch a part of the substrate downward along the opening so that the opening extends into the substrate, and the part of the opening located within the substrate constitutes the trench.

7. The method for preparing a memory according to claim 6, characterized in that, After forming the trenches and before forming the source line layer and the metal floating gate structure in the trenches, further comprising: Conformally forming a blocking material layer, a metal floating gate material layer, and a first blocking oxide layer on the substrate, the blocking material layer, the metal floating gate material layer, and the first blocking oxide layer sequentially covering the hard mask layer and the inner wall of the opening; Removing the first blocking oxide layer, the metal floating gate material layer, and the blocking material layer on the non-storage area.

8. The manufacturing method of the memory according to claim 7, characterized in that, The step of forming the metal floating gate structure includes: Forming a second blocking oxide layer on the first blocking oxide layer, the second blocking oxide layer extending to cover the inner wall of the opening and the hard mask layer on the non-storage area; Using an anisotropic etching process to etch the second blocking oxide layer and the first blocking oxide layer, and retaining the first blocking oxide layer and the second blocking oxide layer on the sidewalls of the opening; Using the second barrier oxide layer and the first barrier oxide layer as masks, the metal floating gate material layer and the barrier material layer on the hard mask layer and at the bottom of the opening are sequentially removed, and the remaining barrier material layer and metal floating gate material layer respectively form the barrier layer and the metal floating gate layer; Remove the remaining first barrier oxide layer and the second barrier oxide layer.

9. The method for preparing the memory according to claim 8, wherein Etch the metal floating gate material layer on the hard mask layer and at the bottom of the opening by using a first wet etching process, and the etchant used in the first wet etching process is A mixed solution with hydrogen peroxide.

10. The method for manufacturing a memory according to claim 8, wherein, Etch the barrier material layer on the hard mask layer and at the bottom of the opening by using a second wet etching process, and the etchant used in the second wet etching process is hydrofluoric acid.

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