Resistive switching memory device and method for forming a resistive switching memory device

Abstract

The present invention provides the manufacture of resistance switching memory devices. For example, a two-step etching method for manufacturing a non-volatile resistance memory device is disclosed. In another embodiment, a three-step etching method for manufacturing a non-volatile resistance memory device is disclosed. Other embodiments disclose a method for manufacturing a non-volatile metal nitrogen / metal oxygen resistance switching memory device. Another embodiment discloses a method for manufacturing a volatile resistance switching selector device. A process for forming a protective gasket in conjunction with manufacturing the disclosed resistance memory device is also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] U.S. Patent No. 9,425,237, filed December 31, 2014, entitled “SELECTOR DEVICE FOR TWO-TERMINAL MEMORY”, U.S. Patent No. 9,685,483, filed March 10, 2016, entitled “SELECTOR-BASED NON-VOLATILECELL FABRICATION UTILIZING IC-FOUNDRY COMPATIBLE PROCESS”, U.S. Patent No. 9,685,483, filed July 21, 2014, entitled “RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELL AND METHOD FOR FORMING THE No. 9,595,670, entitled “RRAMCEL,” U.S. Patent No. 9,768,234, filed on March 9, 2015, entitled “RESISTIVE MEMORY ARCHITECTURE AND DEVICES,” and U.S. Patent No. 10,749,110, filed on April 13, 2017, entitled “MEMORY STACK LINER COMPRISING DIELECTRIC BLOCK LAYER MATERIAL,” each of which is hereby incorporated by reference in its entirety and for all purposes. Technical Field

[0003] Embodiments of the present disclosure relate to electronic memory structures; for example, various embodiments disclose apparatus and methods for fabricating resistive switching memory structures. Background Art

[0004] The inventors have recognized a variety of solid-state memory structures for use in modern electronic memory and computing devices. Tightly controlling the processes used to manufacture modern solid-state memory structures is important to creating memory structures that function properly and to achieve close consistency between multiple devices.

[0005] In various embodiments, the inventors of the present disclosure desire to minimize the impact of variations in semiconductor manufacturing processes. Process variations may vary between multiple semiconductor wafers produced by a process, or between dies within a single wafer, or both. In turn, these process variations can result in performance variations in memory structures on a given die. Performance variations that are outside of the acceptable manufacturing range are typically considered bad parts and are discarded. This reduction in the acceptable yield of parts increases the indirect cost of the entire process. While some performance variations are small enough to remain within the target operating specifications, they can still adversely affect memory performance over time.

[0006] In view of the foregoing, the inventors desire new mechanisms for processing semiconductor wafers, and in particular, processing resistive memory structures within one or more semiconductor wafers that overcome current challenges encountered by the inventors in the art. Summary of the invention

[0007] A simplified summary of the subject disclosure is given below in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is neither intended to identify the key or important elements of the disclosed subject matter nor to delineate the scope of the subject innovation. Its purpose is only to present some concepts of the disclosed subject matter in a simplified form as a prelude to a more detailed description presented later.

[0008] In multiple embodiments disclosed herein, a method for manufacturing a resistive switching memory device is provided. In one embodiment, a two-step etching method for manufacturing a non-volatile resistive memory device is disclosed. In another embodiment, a three-step etching method for manufacturing a non-volatile resistive memory device is disclosed. Other embodiments disclose a method for manufacturing a non-volatile metal nitrogen / metal oxygen resistive switching memory device. Another embodiment discloses one or more processes for manufacturing one or more protective spacers in conjunction with manufacturing the disclosed resistive memory device. In an embodiment, another embodiment discloses an example nitrogen distribution concentration of a non-stoichiometric metal nitrogen layer (e.g., a nitrogen-rich metal or a nitrogen-poor metal) of a resistive memory device. Another embodiment discloses a method for manufacturing a volatile resistive switching selector device.

[0009] In one embodiment, a method for manufacturing a two-terminal resistance switching memory device is disclosed. The method may include depositing a metal layer, the metal layer covering a lower electrode and a dielectric material and contacting the lower electrode and the dielectric material. In multiple embodiments, the lower electrode may be formed in a gap made in the dielectric material by a damascene process, and the lower electrode and the dielectric material cover a substrate. The method may also include depositing a switching matrix covering the metal layer, wherein the switching matrix is ​​formed of a resistive material having material defect sites, and the material defect sites are configured to capture conductive particles. In addition, the method may include depositing a donor material layer covering the switching matrix, the donor material layer including a metal material containing aluminum (Al), titanium (Ti) or tungsten (W) metal material, the donor material layer being selected to provide conductive particles to the switching matrix in response to electrical stimulation, the conductive particles including aluminum, titanium or tungsten metal particles. In some embodiments, the method may optionally include depositing an optional barrier material layer covering the donor material layer. In further embodiments, the method may include depositing a conductive barrier material overlying the donor material layer, depositing a dielectric hard mask overlying the conductive barrier material, and patterning a photoresist material overlying the dielectric hard mask. In further embodiments, the method may include etching the dielectric hard mask with a first etch and stopping the first etch on the conductive barrier material, the first etch comprising a plasma etch using an etching gas selected from a first group, the first group comprising octafluorocyclobutane (C4F8), hexafluoro-2-butyne (C4F6), trifluoromethane (CHF3), carbon tetrafluoride (CF4), carbon monoxide (CO), oxygen (O2), nitrogen (N2), and argon (Ar). In other embodiments, the method may include etching the conductive barrier material, the optional barrier material layer, the donor material layer, the switching matrix and the metal layer with a second etch, and stopping the second etch on the dielectric material, the second etch comprising plasma etching using an etching gas selected from a second group, the second group comprising chlorine (Cl2), boron trichloride (BCl3), hydrogen bromide (HBr), Ar, N2, helium (He), O2, CHF3, CF4 and sulfur hexafluoride (SF6).

[0010] In another embodiment, a method for manufacturing a two-terminal resistance switching device is disclosed. The method may include: depositing a metal layer covering and contacting a lower electrode and a dielectric material, and wherein the lower electrode and the dielectric material cover a substrate; depositing a conductive selection donor layer covering the metal layer; and depositing a selector layer formed of a resistive material having a material defect site, wherein the material defect site is configured to allow conductive particles of the conductive selection donor layer to diffuse within the selector layer in response to a first polarity bias applied to the two-terminal resistance switching device. In addition, the method may include: depositing a second conductive selection donor layer covering the selector layer, wherein the second conductive selection donor layer supplies second conductive particles to the selector layer in response to a second polarity bias applied to the two-terminal resistance switching device; depositing a conductive buffer material covering the second conductive selection donor layer; depositing a dielectric hard mask covering the conductive buffer material; and patterning a photoresist material covering the dielectric hard mask. In addition, the method may include etching the dielectric hard mask with a first etch and stopping the first etch on the conductive buffer material, the first etch comprising an etching gas, the etching gas comprising at least one of C4F8, C4F6, CHF3, CF4, CO, O2, N2, or Ar. In a further embodiment, the method may include etching a majority of the conductive buffer material with a second etch and stopping the second etch without exposing the second conductive selective donor layer by the second etch, the second etch comprising an etching gas, the etching gas comprising one or more of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, and SF6. In yet another embodiment, the method may include etching with a third etch, the third etch comprising physically etching the remaining minority of the conductive buffer material, the second conductive selective donor layer, the selector layer, and the conductive selective donor layer.

[0011] The following description and accompanying drawings set forth certain illustrative aspects of the specification. However, these aspects are only indicative of a few of the many ways in which the principles of the present specification may be employed. Other advantages and novel features of the present specification will become apparent from the following detailed description of the present specification when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects or features of the present disclosure are described with reference to the accompanying drawings, wherein the same reference numerals are used to refer to the same elements throughout. In this specification, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the subject disclosure may be implemented without these specific details, or using other methods, components, materials, etc. In other cases, known structures and devices are shown in block diagram form to facilitate description of the subject disclosure.

[0013] Figure 1 A diagram showing an example deposition for a resistive switching memory according to an embodiment of the present disclosure;

[0014] Figures 2 to 5 Depicted is a method for transmitting a signal according to a further embodiment of the present invention. Figure 1 Example process for forming a discrete resistance switching memory device by deposition of;

[0015] Figure 6 depicts a sample deposition for a resistive switching memory according to alternative or additional embodiments disclosed herein;

[0016] Figures 7 to 12 In a further disclosed embodiment, a method for Figure 6 A further example process for forming a discrete resistance switching memory device by depositing;

[0017] Fig.13 A diagram depicting deposition for resistive switching memory in one or more other disclosed embodiments;

[0018] Figures 14 to 16B In one or more embodiments, a method for Fig.13 Figure 1 is a diagram of an example process for fabricating a discrete non-volatile resistive switching device by deposition;

[0019] Fig.17 illustrates an example nitrogen concentration profile of a metal nitride layer of a nonvolatile resistive switching device according to other embodiments;

[0020] Fig.18 shows a sample deposition of a resistive switching memory according to a further embodiment of the present disclosure;

[0021] Figures 19 to 21 depicts an example process for fabricating a discrete volatile resistance switching device according to still further embodiments disclosed herein;

[0022] Fig. 22 In one or more embodiments, a Fig.21 Example optional pad distribution for a discrete volatile resistive switching device;

[0023] Fig.23 A block diagram illustrating an example electronic working environment according to an embodiment of the present disclosure is shown;

[0024] Fig.24 A block diagram of an example computing environment for implementing one or more disclosed embodiments presented herein is depicted. DETAILED DESCRIPTION

[0025] As the name implies, a two-terminal resistance switching device has two terminals or electrodes. Here, the terms "electrode" and "terminal" are used interchangeably. In addition, the two-terminal resistance switching device includes a non-volatile two-terminal memory device and a volatile two-terminal switching device. Typically, the first electrode of the two-terminal resistance switching device is referred to as the "upper electrode" (TE), and the second electrode of the two-terminal resistance switching device is referred to as the "lower electrode" (BE), although it should be understood that the electrodes of the two-terminal resistance switching device can be arranged in any suitable arrangement, including a horizontal arrangement in which the components of the memory cell are (substantially) side by side rather than overlapping each other. Located between the TE and the BE of the two-terminal resistance switching device is usually an interface layer, sometimes also referred to as a switching layer, a resistance switching medium (RSM) or a resistance switching layer (RSL), however, such devices are not limited to these layers, as disclosed herein, disclosed in any publication incorporated herein by reference, or as generally understood and used in the art. One or more barrier layers, adhesion layers, ion conductive layers, seed layers, etc., can be included between or near one or more of the TE, BE or interface layers consistent with the appropriate operation of the device.

[0026] In general, the composition of the memory cell can vary from device to device, with different components selected in the device to achieve desired characteristics (e.g., volatility / non-volatility, on / off current ratio, switching time, read time, memory endurance, program / erase cycles, etc.). An example of a filament-based device may include: a conductive layer such as a metal, a metal alloy, a metal nitride (e.g., including TiN, TaN, TiW, or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer (e.g., a p-type or n-type Si carrier layer, p-type or n-type polysilicon, p-type or n-type polycrystalline SiGe, etc.); a resistive switching layer (RSL); and an active metal-containing layer that can be ionized. Under appropriate conditions, the active metal-containing layer can provide ions to the RSL to form the filament. In such an embodiment, the conductive filament (e.g., formed by ions) can facilitate conductivity through at least a subset of the RSL, and as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. Memory cells with such properties can be described as filament-based devices.

[0027] The RSL (which may also be referred to in the art as a resistance switching medium (RSM)) may include, for example, a non-doped amorphous Si layer, a semiconductor layer having intrinsic properties, a stoichiometric or non-stoichiometric silicon nitride (e.g., SiN, Si3N4, SiN x etc.), Si suboxides (e.g., SiO x, where the value of x is between 0.1 and 2), Si nitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si x Ge y O z (where x, y, and z are respectively suitable positive numbers), silicon oxide (e.g., SiO N , where N is a suitable positive number), silicon oxynitride, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is a suitable number), Al2O E (wherein E is a suitable positive number), etc., nitrides (eg, AlN, SiN), or suitable combinations thereof.

[0028] In some embodiments, a RSL (nonvolatile RSL) used as part of a nonvolatile memory device may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to capture neutral metal particles within the RSL (at least at low voltages). A large number of voids or defects may promote the formation of a thick, stable neutral metal particle structure. In such a structure, these trapped particles may keep the nonvolatile memory device in a low resistance state in the absence of external excitation (e.g., power), thereby achieving nonvolatile operation. In other embodiments, the RSL (volatile RSL) employed by the volatile selector device may have very few material voids or defects for capturing particles. Since there are few voids / defects for capturing particles, the conductive filaments formed in such RSLs may be very thin (e.g., one to several particle widths depending on the field strength, particle material or RSL material, or a suitable combination of the foregoing), and are unstable without a suitably high external excitation (e.g., electric field, voltage, current, Joule heat, or a suitable combination thereof). In addition, particles having high surface energy and good diffusivity within the RSL may be selected. This results in a conductive filament that can form quickly in response to an appropriate stimulus, but also deform easily, such as in response to an external stimulus that is reduced to below a deformation level (which can be below the formation level of an external stimulus associated with forming a volatile conductive filament, such as in response to current flowing through a selector device; see U.S. Patent Application No. 14 / 755,998, the entire contents of which are incorporated herein by reference and for all purposes). Note that the volatile RSL and conductive filament used in the selector device can have different electrical characteristics than the conductive filament and non-volatile RSL used in the non-volatile memory device. For example, the selector device RSL can have a higher material resistance and can have a higher on / off current ratio, etc.

[0029] The active metal layer for a filament-based memory cell can include: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of the subject disclosure, other suitable conductive materials and compounds, nitrides, oxides, alloys, or combinations of the foregoing or similar materials can be used for the active metal layer. Additionally, in at least one embodiment, the active metal layer can employ non-stoichiometric compounds, such as non-stoichiometric metal oxides / metal-oxygen or metal nitrides / metal-nitrogen (e.g., AlOx, AlNx, CuOx, CuNx, AgOx, AgNx, etc., where x is a suitable positive number or range of values according to the metal compound, e.g.: 0 < x < 2, 0 < x < 3, 0 < x < 4, or other numbers / ranges of values, which can have different values for different non-stoichiometric compounds) or other suitable metal compounds.

[0030] In one or more embodiments, the disclosed filament resistive switching device can include an active metal layer that includes a metal-nitrogen selected from the group consisting of TiNx, TaNx, AlNx, CuNx, WNx, and AgNx, where x is a positive number. In a further embodiment, the active metal layer can include a metal-oxygen selected from the group consisting of TiOx, TaOx, AlOx, CuOx, WOx, and AgOx. In yet another embodiment, the active metal layer can include a metal-oxygen-nitrogen selected from the group consisting of TiOaNb, AlOaNb, CuOaNb, WOaNb, and AgOaNb, where a and b are positive numbers. The disclosed filament resistive switching device can also include a switching layer that includes a switching material selected from the group consisting of SiOy, AlNy, TiOy, TaOy, AlOy, CuOy, TiNx, TiNy, TaNx, TaNy, SiOx, SiNy, AlNx, CuNx, CuNy, AgNx, AgNy, TiOx, TaOx, AlOx, CuOx, AgOx, and AgOy, where x and y are positive numbers and y is greater than x. The various combinations described above are envisioned and contemplated within the scope of the embodiments of the present invention.

[0031] In one example, the disclosed filament resistive switching device includes a particle donor layer (e.g., an active metal layer) containing a metal compound and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer includes metal-nitrogen: MNx, such as AgNx, TiNx, AlNx, etc., and the resistive switching layer includes metal-nitrogen: MNy, such as AgOy, TiOy, AlOy, etc., where y and x are positive numbers, and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer includes metal-oxygen: MOx, such as AgOx, TiOx, AlOx, etc., and the resistive switching layer includes metal-oxygen: MOy, such as AgOy, TiOy, AlOy, etc., where y and x are positive numbers, and in some cases y is greater than x. In yet another alternative embodiment, the metal compound of the particle donor layer is MNx (e.g., AgNx, TiNx, AlNx, etc.), and the resistive switching layer is selected from the group consisting of MOy (e.g., AgOy, TiOy, AlOy, etc.) and SiOy, where x and y are typically non-stoichiometric values, or vice versa in yet another embodiment.

[0032] As used herein, variables x, y, a, b, etc., representing the value or ratio of one element relative to another (or other) element in a compound may have different values ​​for each compound and are not intended to represent the same or similar values ​​or ratios between compounds. Some details related to embodiments of the subject disclosure may be found in the following U.S. patent applications licensed to the assignee of the present patent application: Application Serial No. 11 / 875,541 filed on October 19, 2007 and Application Serial No. 12 / 575,921 filed on October 8, 2009, each of which is incorporated herein by reference in its respective entirety and for all purposes, except for patent applications incorporated herein by reference elsewhere.

[0033] It should be understood that various embodiments herein may utilize a variety of memory cell technologies having different physical properties. For example, different resistance-switching memory cell technologies may have different discrete programmable resistances, different associated programming / erase voltages, and other differentiated characteristics. For example, various embodiments disclosed in the subject matter may employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and exhibits a second switching response (e.g., erasing to an erased state) to an electrical signal of a second polarity. A bipolar switching device is contrasted, for example, with a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals of the same polarity and different amplitudes.

[0034] In various embodiments, the filament-based resistive switching device can operate in a bipolar manner, behaving differently in response to external stimuli of different polarities (or directions, energy flows, energy source orientations, etc.). As an illustrative example, for a volatile filament-based selector device, in response to a first polarity stimulus exceeding a first threshold voltage (or voltage set), the filament selector device can change from a first resistive state to a second resistive state. In addition, in response to a second polarity stimulus exceeding a second threshold voltage, the filament selector device can change from a first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurable intrinsic properties (e.g., conductivity, etc.), having the same or similar threshold stimulus amplitude (although opposite in polarity or direction), etc. In other embodiments, the third state can be different from the second state, either in terms of a measurable property (e.g., a different conductivity value in response to a reverse polarity compared to a forward polarity), or in terms of a threshold stimulus associated with switching out of the first state (e.g., a different magnitude of a positive voltage required to switch to the second state compared to a magnitude of a negative voltage required to switch to the third state).

[0035] For bipolar operation of nonvolatile filament-based memory cells, a conductive path or filament is formed through the nonvolatile RSL in response to a suitable programming voltage applied to the memory cell. In particular, when the programming voltage is applied, metal ions are generated from the active metal layer and migrate into the nonvolatile RSL layer. The metal ions can occupy voids or defect sites within the nonvolatile RSL layer. In some embodiments, after the bias voltage is removed, the metal ions become neutral metal particles and remain trapped in the voids or defects of the nonvolatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the nonvolatile RSL layer, and the resistance is generally determined by the tunneling resistance through the nonvolatile RSL layer. In some resistance switching devices, an erase process can be implemented to deform the conductive filament, at least partially returning the memory cell from a low resistance state to a high resistance state. More specifically, upon application of an erase bias voltage, metal particles trapped in voids or defects of the nonvolatile RSL become mobile ions and migrate back toward the active metal layer. In the context of memory, such state changes can be associated with individual states of a binary bit. For an array of multiple memory cells, a word, byte, page, block, etc. of memory cells can be programmed or erased to represent zero or one of binary information, and the binary information is stored by actually retaining these states for a period of time. In various embodiments, multiple levels of information (e.g., multiple bits) can be stored in such a memory cell.

[0036] It will be understood by one of ordinary skill in the art or by the background provided herein that when various aspects and embodiments herein do not specify a specific memory cell technology or programming / erase voltage, it is intended that these aspects and embodiments be incorporated into any suitable memory cell technology and be operated by programming voltages / erase voltages appropriate to the memory cell technology. It should be further recognized that when circuit modifications known to one of ordinary skill in the art or changes to operating signal levels known to one of ordinary skill in the art are required to substitute for different memory cell technologies, embodiments including alternative memory cell technologies or signal level changes are considered to be within the scope of the subject disclosure.

[0037] As described above, application of a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory cell results in the formation of a conductive filament in an interface layer (e.g., RSL). By convention and as generally described herein, TE receives the programming pulse and BE is grounded (or maintained at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all embodiments. Conversely, application of an "erase pulse" to one of the electrodes (typically a pulse of opposite polarity to the programming pulse or a pulse applied to an opposite electrode to the programming pulse) disrupts the continuity of the filament, such as by driving the metal particles or other material that form the filament back to the active metal source. The characteristics of such a conductive filament and its presence or absence affect the electrical characteristics of the two-terminal memory cell, such as by reducing the resistance and / or increasing the conductance between the two terminals when the conductive filament is present and vice versa when it is not present.

[0038] After the programming or erasing pulse, a read pulse may be applied. The amplitude of the read pulse is generally lower than the programming or erasing pulse, and is generally insufficient to affect the conductive filament and / or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, the current measured when compared to a predetermined threshold current (e.g., Ion) may indicate the conductive state of the two-terminal memory cell. The threshold current may be preset based on the expected current value of the two-terminal memory device in different states (e.g., high resistance state current; corresponding currents of more than one low resistance state, etc.), suitable for a given two-terminal memory technology. For example, when the conductive filament has been formed (e.g., in response to the application of the programming pulse), the conductance of the cell is greater than otherwise, and the current (e.g., Ion) reading measured in response to the read pulse will be greater. On the other hand, when the conductive filament is removed (e.g., in response to the application of the erase pulse), the resistance of the cell is higher because the interface layer has a relatively high resistance, so the conductance of the cell is lower and the current (e.g., Ioff) reading measured in response to the read pulse will be lower. By convention, when a conductive filament is formed, the memory cell is referred to as being in an "on state" having a high conductance. When the conductive filament is not present, the memory cell is referred to as being in an "off state". A memory cell in the on state or the off state can be logically mapped to binary values, such as "1" and "0". It should be understood that the conventions used herein in connection with the state of a cell or the related logical binary mapping are not intended to be limiting, and other conventions, including opposite conventions, may be employed in connection with the disclosed subject matter. The techniques detailed herein are described and illustrated in connection with single-level cell (SLC) memory, but it should be understood that the disclosed techniques may also be used in multi-level cell (MLC) memory, in which a single memory cell can retain a set of measurable different states representing multiple bits of information.

[0039] Digital information can be stored in such devices by mapping the digital information to the nonvolatile resistance states of the two-terminal memory cells. Electronic devices containing many such two-terminal memory cells can also store large amounts of data. High-density arrays are configured to contain as many memory cells as possible for a given chip space area, thereby maximizing the data storage capacity of the memory chip or system-on-chip device.

[0040] For two-terminal memories (e.g., crossbar arrays) formed at the intersection of metal lines within a wafer, the inventors of the subject disclosure recognize two general conventions for arranging memory cells. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects (e.g., current, including leakage path current) of the surrounding circuit by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1), in which a group of multiple memory cells are isolated from the electrical effects of the surrounding circuit by one (or more) transistors. In a 1T1R environment, a single memory cell can be configured to have high current suppression between memory cells, significantly reducing the leakage path current of the 1T1R memory array. In a 1TnR environment, many independent memory cells with high device density in a given amount of silicon space can be connected to a single transistor with much lower density. Therefore, the 1TnR environment promotes higher bit density of resistive memory cells on semiconductor chips.

[0041] One example mechanism for connecting a 1T1R memory array includes a first end of a two-terminal resistance memory device connected to the drain of a transistor. The second end of the two-terminal resistance memory device can be connected to a bit line of the 1T1R memory array. Depending on the erase / programming conditions of the memory array, the source of the transistor is grounded or used as a source of an erase or programming signal. Another example mechanism involves a three-terminal memory including a transistor coupled to a volatile two-terminal resistance switching device. The first end of the volatile RSD is connected to the gate of the transistor, and the second end of the volatile RSD is connected to a voltage source. When activated, the volatile RSD allows charge to accumulate at the gate of the transistor, and when deactivated, the charge accumulated at the gate of the transistor can be captured. Other resistance switching device (RSD) circuits may be used within the scope of the present disclosure.

[0042] Overview

[0043] Figure 1A block diagram of an example resistive memory device 100 according to one or more embodiments of the present disclosure is shown. Although not specifically described, the resistive memory device 100 may be part of a semiconductor device. For example, in one or more embodiments, the resistive memory device 100 may be located within, between, or in one or more of a substrate (or a substrate for a multi-substrate device), a deposited layer, an electrical and electronic device structure, a conductive via, a metal interconnect layer, or other components known in the art that constitute a semiconductor device. As an example, the resistive memory device 100 may be formed in a backend-of-line layer of a semiconductor device. In another example, the resistive memory device 100 may be formed in a frontend-of-line layer of a semiconductor device. In other examples, the resistive memory device 100 may be partially formed in the backend layer and partially formed in the frontend layer. In addition, the aforementioned positioning may be applicable to other device depositions disclosed herein and is not limited to the resistive memory device 100.

[0044] The resistive memory device 100 may be formed to cover a substrate of a semiconductor device. Starting from the bottom layer, the resistive memory device 100 may include a conductive lower electrode 102 formed in a void or gap in a dielectric layer 104 produced by a damascene process. A bottom plate 106 is formed to cover the dielectric layer 104 and the conductive lower electrode 102. In some disclosed embodiments, the bottom plate 106 may be formed of tungsten (W), titanium nitride (TiN), etc., or a suitable combination of the foregoing substances, and may have a thickness in the range of about 50 angstroms (Å) to about 500Å. As used herein, the terms "approximately", "substantially" and other related terms, when used to modify the numerical description of the disclosed structure, refer to a suitable range for a given numerical value, which will achieve the same or similar functions as described for the disclosed structure. In the absence of explicit disclosure of such a range, in some embodiments, a range between 1% and 5% or between 1% and 10% of the numerical value, or a range that a person of ordinary skill in the art would understand as suitable for achieving the functions and characteristics of the disclosed structure in other embodiments, may be implied.

[0045] Overlying the base plate 106 is a switching matrix 108. The switching matrix 108 may have a thickness in the range of about 10Å to about 40Å. In addition, the switching matrix 108 may be formed of a material configured to allow conductive particles to drift or diffuse from an external source into the switching matrix 108 within the switching matrix 108 in response to an excitation, and is configured to form non-volatile filaments of the conductive particles in response to an excitation having appropriate characteristics. In one embodiment, the excitation may be a voltage applied to the resistive memory device 100, and the appropriate characteristics may include a voltage polarity and amplitude suitable for forming the conductive particles into non-volatile filaments, but are not limited to the excitation and characteristics. Other excitations (e.g., current, electric field, temperature, etc., or appropriate combinations of the foregoing) and appropriate characteristics of the excitation (e.g., polarity, amplitude, etc.) known in the art or made known to a person of ordinary skill in the art through the context provided herein to implement the functions and characteristics of the switching matrix 108 described herein are considered to be within the scope of the present disclosure.

[0046] Examples of the material of the switching matrix 108 include SiOx, amorphous Si, Si, TiO x 、AlO x , HfO x 、NiO x 、TaO x 、NbO x 、ZnO2、ZrO x , GdO x , metal-nitrogen (such as AlN x ), etc., or a suitable combination of the foregoing. X is a suitable value for defining a stoichiometric or non-stoichiometric composition according to the respective characteristics of the above compounds as stoichiometric and non-stoichiometric structures or mixtures to achieve the above functions of the switching matrix 108. For example, a technician may understand that non-stoichiometric AlO x In the case of a device suitable for allowing conductive particles to drift or diffuse in response to a stimulus and forming a non-volatile filament of such particles therein, "x" may have an AlO x In contrast, in the case where another compound as a stoichiometric compound allows the conductive particles to drift or diffuse and form filaments of such particles, "x" may have a value or a range of values ​​suitable for achieving a stoichiometric composition of such other compound. In the case where yet another compound as a non-stoichiometric compound and as a stoichiometric compound allows the conductive particles to drift or diffuse and form filaments of such particles, "x" may have a value or a range of values ​​suitable for achieving such a non-stoichiometric composition and a stoichiometric composition.

[0047] In one or more embodiments, the metal-oxygen material (or metal-nitrogen), such as an oxygen-poor metal oxide or an oxygen-rich metal oxide, used for the switching matrix 108 may have a Si dopant in the metal material that is less than 2% Si by atomic weight. Thus, for example, a metal containing AlO x The metal-oxygen may also contain less than 2% Si by atomic weight (e.g., between about 0.5% and about 1% in one embodiment). Silicon doping may be achieved by incorporating less than 2% silicon by atomic weight into a sputtering target of the metal containing the metal-oxygen. When the silicon-doped metal is deposited on top of the base plate 106, oxygen is provided to the resistive memory device 100 to oxidize the silicon-doped metal to form a metal-oxygen material with silicon doping.

[0048] In one embodiment, the following process may be implemented to mitigate or avoid oxidation of the base plate 106. In such an embodiment, the silicon-doped metal sputtering target may be oxidized to form a metal oxide film around the periphery of the silicon-doped metal sputtering target. As a result, the initial deposition involves sputtering the silicon-doped metal oxide onto the base plate 106 for a few seconds to several seconds (e.g., 2 to 10 seconds depending on the deposition rate). This results in a sputtered silicon-doped metal oxygen at a depth of several angstroms (e.g., 5 to 15 angstroms) on the base plate 106. Subsequently, a reactive oxygen flow is initiated to oxidize the silicon-doped metal material that is subsequently sputtered to a depth of several angstroms to several angstroms of the sputtered silicon-doped metal oxygen to continue forming the switching matrix 108.

[0049] Overlying the switching matrix 108 is a switching material-filament donor 110. In various embodiments, the thickness of the switching material-filament donor 110 may be in the range of about 50Å to about 500Å. In further embodiments, the switching material-filament donor 110 may include a material selected to provide conductive particles to the switching matrix 108 in response to a suitable stimulus (e.g., as described above). Example materials for the switching material-filament donor 110 may include Al, non-stoichiometric AlN, or x , stoichiometric or non-stoichiometric AlNO x , TiN, Ti, W, etc., or a suitable combination of the foregoing. Covering the switching material-filament donor 110 is an optional second barrier material 112, which has a thickness in the range of about 50Å to about 500Å and includes a conductive material including Ti, W, etc., or a suitable combination of the foregoing materials. In some embodiments, the resistive memory device 100 does not include the second barrier material 112.

[0050] In yet another embodiment, the metal (e.g., Al) or metal-nitrogen (or metal oxide), such as nitrogen-poor metal nitride or nitrogen-rich metal nitride, used for the switching material-filament donor 110 can have Si dopants with less than 2% Si by atomic weight in the metal material. Thus, for example, AlNx The aluminum metal or metal-nitrogen material may also contain less than 2% Si by atomic weight (e.g., between about 0.5% and about 1% in one embodiment). Silicon doping may be achieved by incorporating less than 2% silicon by atomic weight into a sputtering target of a metal containing metal-nitrogen. When the silicon-doped metal is deposited on top of the switching matrix 108, nitrogen gas is provided to the resistive memory device 100 during the deposition of the silicon-doped metal to form a metal-nitrogen with silicon doping.

[0051] Overlying the switching material-filament donor 110 (and the optional second barrier material 112) is a barrier material / upper electrode 114. The barrier material / upper electrode 114 may have a thickness in the range of about 200Å to about 1500Å and may include a material comprising TiN, Ti, W, TaN, etc., or a suitable combination of the foregoing. A dielectric hard mask 116 overlies the barrier material / upper electrode 114 and may include a material selected from SiO2, SiN, SiC, SiON, amorphous carbon, etc., or a suitable combination of the foregoing. In addition, as known in the art, a patterned resist 118 may overlie the dielectric hard mask 116.

[0052] Figure 2 Shown for the above Figure 1 1 is a block diagram of a first etch: hard mask plasma etch 200 of a resistive memory device 100. The first etch uses the patterned resist 118 as a mask to etch the dielectric hard mask 116 and form an etched dielectric hard mask 216. The first etch: hard mask plasma etch 200 may be a plasma etch using a gas selected from the group consisting of C4F8, C4F6, CHF3, CF4, CO, O2, N2, and Ar. When the barrier material / upper electrode 114 is reached, the first etch: hard mask plasma etch 200 is stopped, so that the resistive memory device 100 is substantially as Figure 2 shown.

[0053] Figure 3 A block diagram of a resist (PR) strip / post etch clean 300 is depicted. The PR strip / post etch clean 300 removes the patterned resist 118 from above the etched dielectric hard mask 216. The patterned resist 118 may be removed with O2 ash, O2 / CF4 ash, etc., or a suitable combination of the foregoing. After removing the patterned resist 118a, a cleaning process is performed to remove debris or residue from removing the patterned resist 118 or to produce a top surface of the etched dielectric hard mask 216. The cleaning process may use a dimethyl sulfoxide (DMSO) rinse, an EKC rinse, a hydrogen fluoride (HF) clean, a deionized (DI) water rinse, etc., or a suitable combination of the foregoing.

[0054] Figure 4 A block diagram of a second etch: plasma gas etch and post-etch clean 400 according to yet another embodiment of the present disclosure is shown. The second etch is performed using the etched dielectric hard mask as a mask for the second etch. The second etch removes the barrier material / upper electrode 114 (optional second barrier material 112, if present), the switching material-filament donor 110, the switching matrix 108, and the bottom plate 106 to form an etched barrier material / upper electrode 414, an optional etched second barrier material 412 (if present), an etched switching material-filament donor 410, an etched switching matrix 408, and an etched bottom plate 406. The second etch may stop on the dielectric layer 104 and may be a plasma etch using a gas selected from the group consisting of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, and SF6. The second etch: plasma gas etch and post-etch clean 400 is accomplished using a post-etch clean utilizing O2 ash, dilute HF, ultra-dilute HF, EKC clean, sulfuric peroxide mixture (SPM) rinse, H2O2 rinse, tetramethylammonium hydroxide (TMAH) rinse, DI water rinse, etc., or a suitable combination of the above methods.

[0055] Figure 5 A block diagram of a liner layer deposition 500 according to one or more further embodiments of the present disclosure is shown. The liner layer deposition 500 may cover the surface of the dielectric layer 104 exposed by the second etch: plasma gas etch and post-etch clean 400, and may cover the etched dielectric hard mask 216, the etched barrier material / upper electrode 414, the etched second barrier material 412 (if present), the etched switching material-filament donor 410, the etched switching matrix 408, and the etched bottom plate 406. The liner layer may be made of materials including SiN, SiON, SiC, atomic layer deposition (ALD), AlO x The invention is formed by materials such as the above or appropriate combinations of the above.

[0056] Figure 6 A block diagram of a resistive memory device deposition 600 according to an alternative or additional embodiment of the present disclosure is depicted. Although not specifically illustrated, the resistive memory device deposition 600 may be part of a semiconductor device (e.g., similar to the following description of Figure 160). The resistive memory deposition 600 includes a lower electrode 602 formed within a void or gap of a dielectric material 604 (e.g., produced as part of a damascene process). A base plate 606 is formed over the dielectric material 604 and the lower electrode 602, and a switching matrix 608 is formed over the base plate 606. Additionally, a switching material-filament donor 610 is formed over the switching matrix 608, an optional second barrier material 612 may optionally be formed over the switching material-filament donor 610, a barrier material / upper electrode 614 is formed over the switching material-filament donor 610 (and the optional second barrier material 612, if present), and a dielectric hard mask 616 is formed over the barrier material / upper electrode 614. Also as shown, a patterned resist 618 is formed overlying the dielectric hard mask 616. In one or more embodiments, the various layers of the resistive memory deposition 600 may have the same characteristics as described below with respect to Figure 1 Provided substantially similar thickness and material composition.

[0057] Figure 7 A block diagram of a sample first etch: hard mask plasma etch 700 in one or more embodiments of the present disclosure is depicted. The first etch may include a hard mask plasma etch (including a gas selected from the group consisting of C4F8, C4F6, CHF3, CF4, CO, O2, N2, and Ar). When the barrier material / upper electrode 614 is reached, the first etch: hard mask plasma etch 700 stops, so that the etched dielectric hard mask 716 covers the lower layer of the resistive memory deposition 600, substantially as shown in FIG. Figure 7 shown. Figure 8 A block diagram of a PR stripping / post-etch cleaning 800 according to a further embodiment of the present disclosure is depicted. The PR stripping / post-etch cleaning 800 removes the patterned resist 618 covering the etched dielectric hard mask 716, and cleans the etched dielectric hard mask 716 and the surface of the barrier material / upper electrode 614 exposed by the first etch: hard mask plasma etch 700. The PR stripping may utilize O2 ash or O2 / CF4 ash, and the post-etch cleaning may utilize EKC, DMSO, HF or DI water rinse, etc., or a suitable combination of the foregoing methods.

[0058] Fig. 9A block diagram of a sample second etch 900 according to one or more additional embodiments of the present disclosure is shown. The second etch 900 removes a portion of the barrier material / upper electrode 614, the optional second barrier material 612 (if present), the switching material-filament donor 610, and the switching matrix 608. In various embodiments, the dielectric hard mask 716 is used as a mask for the second etch 900. After the second etch 900, an etched barrier material / upper electrode 914, an optional etched second barrier material 912 (if present), an etched switching material-filament donor 910, and an etched switching matrix 908 are formed. The second etch 900 may stop on the bottom plate 606. In various embodiments, the second etch 900 may be a plasma etch using a gas selected from the group consisting of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, and SF6 and may also include a post-etch clean comprising O2 ash, dilute HF, ultra-dilute HF, EKC, SPM, H2O2, TMAH, or DI water rinse.

[0059] Fig.10 A block diagram of an exemplary optional liner layer deposition 1000 is depicted, which forms an optional liner layer 1020 over the bottom plate 606 exposed by the second etch 900 and the etched switching matrix 908, the etched switching material-filament donors 910, the optional etched second barrier material 912 (if present), the surface of the etched barrier material / upper electrode 914, and the etched dielectric hard mask 716. Using the liner layer deposition 1000, the liner layer deposition 1000 can form the liner layer 1020 of SiN, SiON, SiC, or ALD AlOx, etc., or a suitable combination of the foregoing.

[0060] Fig.11 A block diagram of a sample third etch: liner etch-back and floor etch 1100 is shown. The third etch removes the optional liner layer 1020 (if present) covering the etched dielectric hard mask 716. In addition, the third etch removes the optional liner layer 1020 (if present) covering the floor 606, removing portions of the floor 606 and stopping on the dielectric layer 604, forming an etched floor 1106 and an optional etched liner layer 1120. Fig.12 A second optional liner deposition 1200 is shown to optionally deposit a second optional liner layer 1222 that covers the surface of the dielectric layer 604 exposed by the third etch: liner etch back and floor etch 1100, covers the optional etched liner layer 1120 (if present) and covers the etched dielectric hard mask 716, as shown.

[0061] Fig.1313 shows a resistive memory deposition 1300 according to yet another embodiment of the present disclosure. The resistive memory deposition 1300 may include a dielectric layer 1304 and a lower electrode (BE) 1302 formed in the dielectric layer 1304. A tungsten (W) layer 1306 is formed to cover the dielectric layer 1304 and the BE 1302. In addition, a metal-oxygen (MO Y ) layer 1308 covers the W layer 1306, the metal-nitrogen (MN X ) Layer 1310 covers MO Y Layer 1308. MO Y Layer 1308 is configured to allow conductive metal particles to pass from MN X Layer 1310 drifts or diffuses to MO Y layer 1308, and is configured to form a MO in response to a stimulus applied to the resistive memory device. Y At least a portion of the conductive metal particles of layer 1308 are conductive filaments, and MN X Layer 1310 is configured to provide conductive metal particles to the MO in response to stimulation. Y Layer 1308. "Y" and "X" are used to form MO Y and MN X The non-stoichiometric structure of MN is a suitable positive number and is used to achieve the characteristics of the various layers described herein. In the disclosed embodiments, the MN X Layer 1310 and MO Y The metal "M" of layer 1308 can be the same metal or different metals. As an example, M can be aluminum, and MN X Layer 1310 may be AlN X Layer and MO Y Layer 1308 may be AlO Y layer, while in other examples MN X Layer 1310 may include a first metal and MO Y Layer 1308 may include a second metal that is different from the first metal.

[0062] Covered in MN X On the layer 1310 is a TiN or TaN buffer material (TiN / TaN buffer material) 1312. A dielectric hard mask 1314 covers the TiN / TaN material 1312 and may include a SiO2 material, a SiN material, a SiC material, a SiON material, an amorphous carbon material, etc. or a suitable combination of the foregoing. In addition, a patterned resist 1316 covers the dielectric hard mask 1314.

[0063] Fig.14A block diagram of a sample first etch: hard mask plasma etch 1400 is shown in accordance with one or more embodiments of the present disclosure. The first etch utilizes the patterned resist 1316 as a mask to etch the dielectric hard mask and form an etched dielectric hard mask 1414. In some embodiments, the first etch: hard mask plasma etch 1400 may be a hard mask etch disclosed elsewhere relative to other hard mask etches in the present disclosure. In further embodiments, the first etch: hard mask plasma etch 1400 may be an oxide etch chemistry. In one embodiment, the first etch: hard mask plasma etch 1400 may be a chlorine chemistry etch, a fluorine chemistry etch, or a suitable combination of the foregoing. In at least one embodiment, the hard mask etch may be a CHF3 etch. In multiple embodiments, the first etch: hard mask plasma etch 1400 stops on the TiN / TaN buffer material 1312.

[0064] Fig.14A Resist removal and optional liner deposition 1400A are depicted in further embodiments. The patterned resist 1316 may be removed with any PR stripping chemistry disclosed herein or known in the art, such as O2 ash, O2 / CF4 ash, followed by EKC, DMSO, HF, or DI water clean. Subsequently, an optional liner layer 1420A may be formed on the etched dielectric hard mask 1414 and on the surface of the TiN / TaN buffer material 1312. Fig. 14B , an optional liner etch 1400B is provided to remove an optional liner layer 1420A from the top surface of the etched dielectric hard mask 1414 and expose the top surface of the TiN / TaN buffer material 1312 to form an optional spacer 1420B. The optional liner layer 1420A may be formed of one or more materials selected from the group consisting of SiN, SiO, SiON, SiC, and SiOC.

[0065] Fig.15 A block diagram of an exemplary second etch: buffer material 1500 is shown according to further embodiments. The second etch: buffer material 1500 utilizes the etched dielectric hard mask 1414 as a dielectric layer to etch the TiN / TaN buffer material 1312 and optionally the MN X After the second etch: buffer material 1500, an etched TiN / TaN buffer material 1512 (and optionally, an etched metal-nitrogen layer 1610, see below) is formed. Fig.16). In various embodiments, the second etch may be a plasma etch comprising one or more of the following gases: Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, or SF6. In one or more embodiments, the second etch may be followed by a post-etch clean comprising an O2 ash, dilute HF, ultra-dilute HF, EKC, SPM, H2O2, TMAH, or DI water rinse. In some embodiments, the second etch may use BCl3 chlorine at a ratio of 1:1 to 3:1. In further embodiments, the second etch may be a fluorine-free etch chemistry.

[0066] Fig.15A and Fig. 15B An example optional pad etch according to a further embodiment of the present disclosure is shown. Fig.15A , performing an optional second liner deposition 1500A to produce an optional second liner layer 1522A. Note that in some embodiments, etching MN X layer 1310 to produce an etched metal-nitrogen layer 1610 as a portion of the second etch buffer material 1500, the optional second liner layer 1522A may extend to the MO Y Layer 1308. Fig. 15B Optional second liner etch 1500B is shown in FIG. 1 , removing optional second liner layer 1522A from the top of dielectric hard mask 1414, resulting in second optional liner 1522B. X In the embodiment where the layer 1310 is etched as part of the second etch buffer material 1500, the second optional spacer 1522B extends along the sidewalls of the etched metal-nitride layer 1610 to the MO Y Layer 1308. The optional second liner layer 1522A may be formed of one or more materials selected from the group consisting of SiN, SiO, SiON, SiC, and SiOC.

[0067] Fig.16 Depicted is a block diagram of an example third etch: switch matrix and backplane 1600 according to an alternative or additional embodiment of the present disclosure. The third etch may etch through the MO Y Layer 1308 and W layer 1306 (in some embodiments, in MN X The third etch process is performed on the dielectric layer 1304. After the third etch process, the memory device includes the etched W layer 1606, the etched MO layer 1608, and the etched Y Layer 1608, etched MN XLayer 1610, etched TiN / TaN buffer material 1512, and etched dielectric hard mask 1414. In various embodiments, the third etch may be a plasma etch including one or more of the following gases: Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, or SF6. In one or more embodiments, the second etch may be followed by a post-etch clean including O2 ash, dilute HF, ultra-dilute HF, EKC, SPM, H2O2, TMAH, or DI water rinse. Additionally, in various embodiments, an optional shim 1420B or a second optional shim 1522B may be provided.

[0068] Fig.16A and Fig. 16B Optional third liner deposition 1600A and third liner etching 1600B are depicted respectively according to further embodiments. The optional third liner deposition 1600A provides an optional third liner layer 1624A that covers the top surface of the dielectric layer 1304 and the etched W layer 1606, the etched MO Y Layer 1608, etched MN X 1420B (or the etched TiN / TaN buffer material 1512, or the etched dielectric hard mask 1414, depending on which optional spacers are present, if any). The optional third liner layer 1624A may be formed of one or more materials selected from the group consisting of SiN, SiO, SiON, SiC, and SiOC. In one or more embodiments, the optional third liner etch 1600B may remove the optional third liner layer 1624A from the top surface of the etched dielectric hard mask 1414 and at least a portion of the dielectric layer 1304 and form a third optional liner 1624B.

[0069] Fig.17 An example nitrogen concentration profile 1700 of a metal-nitride layer for a resistive switching memory device according to an additional embodiment of the present disclosure is shown. Nitrogen concentration profile 1700 depicts the etched MN after the third etch: switching matrix and bottom plate 1600. X The etched MO layer 1610 and the etched TiN / TaN buffer material 1512 below Y Layer 1608. For the etched MN X Layer 1610 (and the etched MO Y 1608 and adjacent portions of the etched TiN / TaN buffer material 1512) is shown as a nitrogen concentration profile 1700 showing the atomic percent nitrogen concentration along the (X) axis and the deposited thickness of the metallic nitride material along the (Y) axis. The nitrogen concentration profile 1700 can be plotted in the etched MN XLayer 1610 and etched MO Y The boundary of layer 1608 has an increased nitrogen portion 1702, which has a nitrogen atomic percentage ranging from about 20% to about 28% (up to about 30% in some embodiments). In addition, the nitrogen atomic percentage of the medium nitrogen portion 1704 is in the range of about 15% to about 20%, and the etched MN X At the boundary of the layer 1610 and the etched TiN / TaN buffer material 1512, the reduced nitrogen portion 1706 has a nitrogen atomic percentage in a range from about 10% to about 15%.

[0070] Fig.18 A block diagram of an example selector device deposition 1800 according to an alternative or additional embodiment of the present disclosure is depicted. In various embodiments, the selector device deposition 1800 may be used to form a volatile resistive switching selector device. The selector device deposition 1800 may include a lower electrode (BE) 1802 formed in a gap or void in a dielectric layer 1804. In an embodiment, the gap / void may be formed as part of a damascene process. A tungsten (W) layer 1806 is formed over the dielectric layer 1804 and the BE 1802. Overlying the W layer 1806 is a selector stack including a selection donor layer 1812 overlying a selector layer 1810, the selector layer 1810 overlying another selection donor layer 1808, the selection donor layer 1808 overlying the W layer 1806. In one or more embodiments, the selection donor layer 1812 or the selection donor layer 1808 may be formed of a metallic material capable of being ionized in response to a physical stimulus (e.g., current, voltage, electric field, magnetic field, temperature, etc., or a suitable combination of the foregoing). In one embodiment, the metallic material may be doped with a second material, such as a second metal.

[0071] Examples of suitable materials for the selective donor layer 1812 or the selective donor layer 1808 may include noble metals (e.g., Ag, Pd, Pt, Au, etc.), metal alloys or metal mixtures partially containing noble metals or noble metals doped with other metals (e.g., Ag-Al, Ag-Pt, Ag-Pd, Ag-Pd-Cu, Ag-W, Ag-Ti, Ag-TiN, Ag-TaN, etc., as described above or elsewhere herein). For example, a noble metal or its alloy may be used to facilitate the selective donor layer 1812 or the selective donor layer 1808 and the selector layer 1810 (located between the selective donor layer 1812 and the selective donor layer 1808) to reduce the interaction. As an example, the mitigated particle interactions (e.g., mitigating or avoiding chemical bonding of the selection donor layer 1808 particles or the selection donor layer 1812 particles with the particles of the selector layer 1810) can facilitate improved lifetime and reliability of the selector device formed by the selector device deposition 1800. Another example of a suitable material for the selection donor layer 1812 or the selection donor layer 1808 can include a material having relatively fast diffusing particles. Fast diffusion can include, for example, the ability to move between defect sites within a solid (e.g., voids or gaps in a molecular material), such as defined by a suitable surface energy, in the absence of suitable agglomeration forces, such as (e.g., an external voltage greater than a threshold magnitude, etc.), to promote dispersion of relatively fast diffusing particles. Materials having relatively fast diffusing particles can facilitate fast state switching of the selector device (e.g., from a non-conductive state to a conductive state) at lower bias values ​​than materials having relatively slow diffusing particles. Examples of suitable fast-diffusion materials may include Ag, Cu, Au, Co, Ni, Al, Fe, etc., suitable alloys or mixtures thereof, such metals doped with one or more other metals (e.g., Ag doped with 1% to 5% Cu, Au, Al, Pd, or Pt; Cu doped with 1% to 5% Ag, Ni, Al, Pd, Pt; Au doped with 1% to 5% Ag, Cu, Al, Pd, or Pt, etc.), or suitable combinations of the foregoing. In an example embodiment, the metal material may be silver metal doped with 1% to 5% (e.g., about 2%) platinum or palladium metal.

[0072] In various embodiments, selector layer 1810 may be an electrical insulator or an ion conductor. In addition, selector layer 1810 may be a material that is at least weakly permeable to particles of selection donor layer 1812 or selection donor layer 1808 (e.g., an oxide, a suboxide, etc.). In some embodiments, selector layer 1810 may be a non-stoichiometric material. In such embodiments, suitable materials for selector layer 1810 may include, for example, non-stoichiometric materials: SiO x 、TiO x 、AlO x , WOx 、Ti x N y O z , HfO x 、TaO x 、NbO x etc., or a suitable combination thereof, wherein x, y, and z may be suitable non-stoichiometric values. As a specific non-limiting example, the selector layer may be SiO x , where x is between about 0.1 and about 2. In some embodiments, the selector layer can be a (doped or undoped) chalcogenide or a solid electrolyte material comprising one or more of Ge, Sb, S, Te. In yet another embodiment, the selector material can include a stack of multiple of the above materials (e.g., SiOx / GeTe, TiOx / AlOx, etc.). In at least one embodiment of the present disclosure, the selector layer 1810 can be doped with a metal during fabrication to facilitate metal ion implantation from the selection donor layer 1812 or the selection donor layer 1808.

[0073] Covering the selective donor layer 1812 is a buffer material 1814. The buffer material 1814 may include TiN, TaN, or W materials, or a suitable combination of the above materials. Covering the buffer material 1814 is a dielectric hard mask 1816. A patterned resist 1818 is disposed over the dielectric hard mask 1816.

[0074] Fig.19 Shown for the above Fig.18 1800 of the resistive memory deposition 1800. The first etch uses the patterned resist 1818 as a mask to etch the dielectric hard mask 1816 and form an etched dielectric hard mask 1916. The first etch: hard mask plasma etch 1900 can be a plasma etch using a gas selected from the group consisting of C4F8, C4F6, CHF3, CF4, CO, O2, N2 and Ar. When the buffer material 1814 is reached, the first etch: hard mask plasma etch 1900 stops, so that the resistive memory deposition 1900 is substantially as Fig.19 shown.

[0075] Fig. 20It is shown that a resist stripping + cleaning is performed; second etching: buffer 2000 to remove patterned resist 1818 (e.g., O2 ash or O2 / CF4 ash, etc., or a suitable combination of the foregoing). The resist stripping can be followed by an optional cleaning (e.g., dimethyl sulfoxide (DMSO) rinse, EKC rinse, hydrogen fluoride (HF) clean, deionized (DI) water rinse, etc., or a suitable combination of the foregoing). The second etching will remove most of the buffer material 1814 to form an etched buffer material 2014, leaving a small thin layer of unetched buffer 2014A. The second etching can be a plasma etching using a gas selected from the group consisting of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4 and SF6. In a particular embodiment, the second etching utilizes a halogen etch, such as Cl2, BCl3 or HBr. A post-etch clean using O2 ash, dilute HF, ultra-dilute HF, EKC clean, sulfuric acid peroxide mixture (SPM) rinse, H2O2 rinse, tetramethylammonium hydroxide (TMAH) rinse, DI water rinse, etc., or a suitable combination of the foregoing may be used after the second etch.

[0076] Fig.21 A block diagram of an example third etch: physical etch 2100 is depicted. The physical etch initially removes the unetched buffer 2014A. The third etch: physical etch 2100 may also etch the selective donor layer 1812, the selector layer 1810, and the selective donor layer 1808. In various embodiments, the third etch: physical etch 2100 may also remove the W layer 1806. After the third etch: physical etch 2100, an etched selective donor layer 2112, an etched selector layer 2110, an etched selective donor layer 2108, and an etched W layer 2106 are formed covering the BE 1802 and the dielectric layer 1804.

[0077] In one embodiment, the third etch: physical etch 2100 may be an ion milling etch (e.g., a focused ion beam (FIB)). In a further embodiment, the third etch: physical etch 2100 may be an argon plasma etch. One or more optional cleaning processes may be performed after the third etch: physical etch 2100 to remove foreign matter from the sidewalls of the etched dielectric hard mask 1916, the etched buffer material 2014, the etched selective donor layer 2112, the etched selector layer 2110, the etched selective donor layer 2108, or the etched W layer 2106. In one embodiment, no cleaning may be performed after the third etch: physical etch 2100.

[0078] In one embodiment, reference Fig. 22, as an example, the third etch: physical etch 2100 can be implemented in the portion between the optional spacer deposition and etching. As an illustrative example, an optional spacer 2220 can be formed around the edge of the etched dielectric hard mask 1916. Similarly, a second optional spacer 2222 can be formed around the edge of the etched buffer material 2014. In this case, the second optional spacer 2222 can be implemented after the second etch, or after a portion of the physical etch 2100 that removes the unetched buffer 2014A. In the latter embodiment, the physical etch 2100 can first remove the unetched buffer layer 2014A, and then a third optional spacer 2224 can be formed adjacent to the etched buffer material 2014. In a further embodiment, the physical etch 2100 can subsequently remove one or more of the following: the selective donor layer 2112, the selector layer 2110, the selective donor layer 2108, and the W layer 2106, and the optional spacer can be formed adjacent to the etched layer. For example, in Fig. 22 In the illustrated embodiment, the physical etch 2100 etches the etched selective donor layer 2112, the etched selector layer 2110, and the etched selective donor layer 2108, and then forms the third optional spacer 2224. The physical etch 2100 may be completed by subsequently etching the W layer to form the etched W layer 2106. However, in other embodiments, the etched W layer 2106 may be formed by physical etching of the etched selective donor layer 2112, the etched selector layer 2110, and the etched selective donor layer 2108, and the third optional spacer 2224 may also be formed adjacent to the etched W layer 2106.

[0079] The figures included herein have been described with reference to various components of a memory device or a memory architecture including one or more memory devices or integrated circuit devices. It should be understood that these figures may include those components, layers and deposits specified therein, some specified components / layers / deposits, or additional components / layers / deposits. Sublayers may also be implemented as being adjacent to other sublayers in the depicted layer. In addition, it should be noted that one or more disclosed processes may be incorporated into a single process that provides collective functionality. For example, a deposition process may include an etching process, or vice versa, to facilitate deposition and etching of components of a resistive switching device by a single process. The components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0080] In view of the exemplary schematic diagram described above, it can be based on Figure 1-22, to implement process methods that may be implemented in accordance with the disclosed subject matter. Although the methods are illustrated and described as a series of block diagrams for purposes of simplicity of illustration, it should be understood and appreciated that the claimed subject matter is not limited by the order of the drawings, as some steps in the disclosed processes may be performed in an order different from that depicted and described herein and / or occur simultaneously with other steps. In addition, not all illustrated steps are required to implement the methods described herein, and in some embodiments, additional steps that are known in the art or reasonably conveyed to a person of ordinary skill in the art through the context provided herein are also considered to be within the scope of the present disclosure. In addition, where appropriate, some steps shown as part of one process may be implemented in another process (e.g., Fig.14A The optional liner deposition and optional liner etching shown in 15A / B, 15A / B and 16A / B can be implemented in other processes disclosed in this specification; within the scope of the present disclosure, other steps of one or more processes can be added or replaced in other processes disclosed herein). In addition, it should be further understood that the methods disclosed throughout this specification can be stored on an article of manufacture to facilitate the transmission and transfer of these methods to electronic devices. The term "article of manufacture" used is intended to include a computer program that can be accessed from any computer-readable device, device in combination with a carrier, or storage medium.

[0081] Example operating environment

[0082] Fig.23 A block diagram of an example operation and control environment 2300 for a memory array 2302 for a memory cell array according to aspects of the subject disclosure is shown. In some embodiments, the control environment 2300 and the memory array 2302 may be formed within a single semiconductor die, but the subject disclosure is not limited thereto, and in other embodiments, some components of the control environment may be formed on separate semiconductor dies. In at least one aspect of the subject disclosure, the memory array 2302 may include a memory selected from a plurality of memory cell technologies. In at least one embodiment, the memory array 2302 may include a two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridging memory, phase change memory, organic memory, magnetoresistive memory, etc., or a suitable combination of the foregoing. In a further embodiment, the two-terminal memory technology may be a resistive memory technology formed by the process disclosed herein.

[0083] The column controller 2306 and the sense amplifier 2308 may be formed adjacent to the memory array 2302. In addition, the column controller 2306 may be configured to activate (or identify for activation) a subset of the bit lines of the memory array 2302. The column controller 2306 may utilize control signals provided by the reference and control signal generator 2318 to activate and operate on corresponding bit lines in the bit line subset, applying appropriate programming, erasing, or reading voltages to these bit lines. Inactivated bit lines may be maintained at an inhibit voltage (also applied by the reference and control signal generator 2318) to mitigate or avoid bit disturbance effects on these inactivated bit lines.

[0084] Additionally, the operating and control environment 2300 may include a row controller 2304. The row controller 2304 may be formed adjacent to and electrically connected to the word lines of the memory array 2302. Additionally, the row controller 2304 may select a particular row of memory cells with an appropriate select voltage using control signals from the reference and control signal generator 2318. Furthermore, the row controller 2304 may facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0085] The sense amplifier 2308 may read data from or write data to an activated memory cell of the memory array 2302 selected by the column control 2306 and the row control 2304. The data read out from the memory array 2302 may be provided to the input / output buffer 2312. Likewise, the data to be written to the memory array 2302 may be received from the input / output buffer 2312 and written to the activated memory cell of the memory array 2302.

[0086] The clock source 2310 may provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of the row controller 2304 and the column controller 2306. The clock source 2310 may further facilitate the selection of word lines or bit lines in response to external or internal commands received by the operating and control environment 2300. The input / output buffer 2312 may include command and address inputs and bidirectional data inputs and outputs. Instructions are provided through the command and address inputs, and data to be written to the memory array 2302 and data to be read from the memory array 2302 are transmitted through the bidirectional data inputs and outputs, thereby facilitating connection to an external host device, such as a computer or other processing device (not shown, but see, for example, Fig.24 computer 2402, as described below).

[0087] The input / output buffer 2312 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, and receive address data and command data as well as address data for corresponding instructions. The address data may be transmitted to the row controller 2304 and the column controller 2306 via the address register 2314. In addition, input data is transmitted to the memory array 2302 via a signal input line between the sense amplifier 2308 and the input / output buffer 2312, and output data is received from the memory array 2302 via a signal output line from the sense amplifier 2308 to the input / output buffer 2312. The input data may be received from the host device, and the output data may be transmitted to the host device via the I / O bus.

[0088] The command received from the host device may be provided to the command interface 2316. The command interface 2316 may be configured to receive an external control signal from the host device and determine whether the data input to the input / output buffer 2312 is write data, a command, or an address. The input command may be transmitted to the state machine 2320.

[0089] The state machine 2320 can be configured to manage the programming and reprogramming of the memory array 2302 (and other memory groups of the plurality of memory arrays). The instructions provided to the state machine 2320 are implemented according to the control logic configuration, so that the state machine 2320 can manage the reading, writing, erasing, data input, data output and other functions associated with the memory cell array 2302. In some aspects, the state machine 2320 can send and receive acknowledgments or negative acknowledgments regarding the successful receipt or execution of various commands. In further embodiments, the state machine 2320 can decode and implement state-related commands, decode and implement configuration commands, and the like.

[0090] To implement functions such as read, write, erase, input, output, etc., the state machine 2320 can control the clock source 2310 or the reference and control signal generator 2318. The control of the clock source 2310 can cause the output pulses to be configured to facilitate the row controller 2304 and the column controller 2306 to implement specific functions. The output pulses can be transmitted to the selected bit line, for example, by the column controller 2306, or transmitted to the word line, for example, by the row controller 2304.

[0091] Combination Fig.24 , the systems, devices, and / or processes described below may be implemented in hardware such as a single integrated circuit (IC) chip, multiple ICs, an application specific integrated circuit (ASIC), etc. In addition, the order in which some or all of the process blocks appear in each process should not be considered limiting. On the contrary, it should be understood that some process blocks may be performed in a variety of orders, and not all orders are explicitly stated herein.

[0092] refer to Fig.24 , a suitable environment 2400 for implementing various aspects of the claimed subject matter includes a computer 2402. The computer 2402 includes a processing unit 2404, a system memory 2410, a codec 2414, and a system bus 2408. The system bus 2408 couples system components (including but not limited to the system memory 2410) to the processing unit 2404. The processing unit 2404 can be any of a variety of available processors. Dual microprocessors and other multi-processor architectures can also be used as the processing unit 2404.

[0093] The system bus 2408 can be any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus and / or a local bus using any of a variety of available bus architectures including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Plug-in Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association Bus (PCMCIA), FireWire (IEEE1394), and Small Computer System Interface (SCSI).

[0094] The system memory 2410 includes a volatile memory 2410A and a non-volatile memory 2410B. A basic input / output system (BIOS), which includes basic programs for transferring information between elements within the computer 2402 during startup, for example, is stored in the non-volatile memory 2410B. In addition, according to the present invention, the codec 2414 may include at least one of an encoder or a decoder, wherein at least one of the encoder or the decoder may include hardware, software, or a combination of hardware and software. Although the codec 2414 is depicted as a separate component, the codec 2414 may be included in the non-volatile memory 2410B. As an illustration and not limitation, the non-volatile memory 2410B may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory, a dual-end memory, etc. The volatile memory 2410A includes a random access memory (RAM), and in some embodiments may include a cache memory. By way of illustration and not limitation, RAM may take many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0095] The computer 2402 may also include removable / non-removable, volatile / nonvolatile computer storage media. Fig.24 Shown, for example, disk storage 2406. Disk storage 2406 includes, but is not limited to, the following devices: disk drive, solid state drive (SSD), floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card or memory stick. In addition, disk storage 2406 can include storage media alone or in combination with other storage media, including but not limited to CD drives such as high-density disk read-only memory (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive) or digital versatile disk ROM drive (DVD-ROM). In order to facilitate the connection of disk storage device 2406 to system bus 2408, a removable or non-removable interface, such as storage interface 2412, is generally used. It is understood that storage device 2406 can store information related to the user. This information can be stored in or provided to an application running on a server or user device. In one embodiment, the user can be informed (for example, through output device 2432) of the type of information stored in disk storage 2406 or transmitted to a server or application. The user may be provided an opportunity to opt-in or opt-out (eg, via input from input device 2442) of the collection and / or sharing of such information with the server or application.

[0096] It should be understood that Fig.24 Software is depicted that acts as an intermediary between a user and the basic computer resources described in a suitable operating environment 2400. Such software includes an operating system 2406A. The operating system 2406A, which may be stored on disk storage 2406, is used to control and allocate the resources of the computer system 2402. Application programs 2406C utilize the management of resources by the operating system 2406A through program modules 2406D, and program data 2406D stored in system memory 2410 or disk storage 2406, such as startup / shutdown transaction tables, etc. It should be understood that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

[0097] The user enters commands or information into the computer 2402 through input devices 2442. Input devices 2442 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game controller, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to the processing unit 2404 through the system bus 2408 via input ports 2440. Input ports 2440 include, for example, serial ports, parallel ports, game ports, and universal serial buses (USB). Output devices 2432 use some of the same types of ports as input devices 2442. Thus, for example, a USB port can be used to provide input to the computer 2402 and output information from the computer 2402 to the output device 2432. Output adapters 2430 are provided to illustrate that there are some output devices 2432 that require special adapters, such as monitors, speakers, and printers, among other output devices 2432. By way of illustration and not limitation, output adapters 2430 include video and sound cards that provide a means of connection between output devices 2432 and system bus 2408. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 2438.

[0098] Computer 2402 can work in a networked environment using a logical connection to one or more remote computers (e.g., remote computer 2424). Remote computer 2424 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer device, smart phone, tablet computer or other network node, and typically includes many elements described relative to computer 2402. For simplicity, remote computer 2424 only illustrates memory storage device 2426. Remote computer 2424 is logically connected to computer 2402 through network 2422, and then connected via communication interface 2420. Network 2422 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs) and cellular networks. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks, such as integrated services digital networks (ISDN) and their variants, packet switching networks, and digital subscriber lines (DSL).

[0099] The communication interface 2420 refers to the hardware / software used to connect the network 2422 to the bus 2408. Although the communication interface 2420 is shown as being internal to the computer 2402 for clarity, it may also be external to the computer 2402. The hardware / software required to connect to the network 2422 includes, for example purposes only, internal and external technologies such as modems including conventional telephone grade modems, cable modems, and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

[0100] The illustrated aspects of the present disclosure may also be implemented in a distributed computing environment, where certain tasks are performed by remote processing devices linked through a communications network. In a distributed computing environment, program modules or stored information, instructions, etc. may be located in local or remote memory devices.

[0101] In addition, it should be understood that the various components described herein may include circuits that may include components and circuit elements of suitable values ​​to implement the disclosed embodiments of the subject matter. In addition, it should be understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a group of components may be implemented in a single IC chip. In other embodiments, one or more corresponding components may be manufactured or implemented on a separate IC chip.

[0102] With respect to the various functions performed by the above-described components, architectures, circuits, processes, etc., the terms used to describe these components (including references to "means") are intended to correspond to any components (e.g., functional equivalents) for performing the specific functions of the described components, unless otherwise specified, even if not structurally equivalent to the disclosed structures (which perform the functions in the exemplary aspects of the embodiments shown herein). In this regard, it should also be recognized that the embodiments include systems and computer-readable media having computer-executable instructions for performing the actions and / or events of the various processes.

[0103] Furthermore, while a particular feature may be disclosed with reference to only one of several embodiments, that feature may be combined with one or more other features of other embodiments in any manner as desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes" and "comprising" and variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "comprising".

[0104] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" satisfies any of the foregoing. In addition, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from the context to refer to the singular.

[0105] After reading this disclosure, one of ordinary skill in the art may envision further embodiments. For example, in various embodiments, erase operations may be initiated on multiple ReRAM devices (eg, 16, 32, etc.) simultaneously.

[0106] In other embodiments, combinations or sub-combinations of the embodiments disclosed above may be advantageously performed. For ease of understanding, the block diagrams and flow charts of the architecture are grouped. However, it should be understood that combinations of blocks, addition of new blocks, rearrangement of blocks, etc. are contemplated in alternative embodiments of the present disclosure.

[0107] It should also be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes thereto will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A method for manufacturing a two-terminal resistance switching memory device, the method comprising: depositing a metal layer covering and contacting a lower electrode and a dielectric material, wherein the lower electrode is formed within a void created in the dielectric material, wherein the void is created using a damascene process, wherein the lower electrode and the dielectric material cover a substrate; depositing a switching matrix overlying the metal layer, the switching matrix formed of a resistive material having material defect sites, wherein the material defect sites are configured to trap conductive particles; Depositing a donor material layer covering the switching matrix, the donor material layer comprising a metal material including aluminum (Al), titanium (Ti) or tungsten (W) metal material, the donor material layer being selected to provide conductive particles to the switching matrix in response to electrical stimulation, the conductive particles comprising Al, Ti or W metal particles; optionally depositing an optional barrier material layer overlying the donor material layer; depositing a conductive first barrier material overlying the optional barrier material layer or the donor material layer; depositing a dielectric hard mask covering the conductive first barrier material; patterning a photoresist material overlying the dielectric hard mask; etching the dielectric hard mask with a first etch and stopping the first etch on the conductive first barrier material, the first etch comprising a plasma etch using an etching gas selected from a first group, the first group comprising octafluorocyclobutane (C4F8), hexafluoro-2-butyne (C4F6), trifluoromethane (CHF3), carbon tetrafluoride (CF4), carbon monoxide (CO), oxygen (O2), nitrogen (N2), and argon (Ar); and The conductive first barrier material, the optional barrier material layer, the donor material layer, the switching matrix and the metal layer are etched with a second etch, and the second etch is stopped on the dielectric material, the second etch comprising plasma etching using an etching gas selected from a second group, the second group comprising chlorine (Cl2), boron trichloride (BCl3), hydrogen bromide (HBr), Ar, N2, helium (He), O2, CHF3, CF4 and sulfur hexafluoride (SF6).

2. The method according to claim 1, further comprising, after the first etching: Stripping the photoresist using O2 ash or O2 / CF4 ash; and The etched dielectric hard mask is cleaned using EKC, dimethyl sulfoxide (DMSO), hydrogen fluoride (HF), or deionized (DI) water rinse.

3. The method according to claim 1, further comprising, after the second etching: Cleaning the surface of the two-terminal resistance switching memory device exposed by the second etching with O2 ash; and The surface of the two-terminal resistance-switching memory device is cleaned with at least one of dilute HF, ultra-dilute HF, EKC, sulfuric acid peroxide mixture (SPM), hydrogen peroxide (H2O2), tetramethylammonium hydroxide (TMAH), or deionized water rinse.

4. The method according to claim 1, further comprising depositing a liner material, the liner material covering the top surface of the dielectric material exposed by the first etch or the second etch and the surfaces of the dielectric hard mask, the conductive first barrier material, the optional barrier material layer, the donor material layer, the switching matrix and the metal layer, wherein the liner material comprises SiN, SiON, SiC or AlO x .

5. The method according to claim 1 further comprises depositing a metal layer with a thickness ranging from 50Å to 500Å using W or TiN material.

6. The method of claim 1, further comprising depositing the switching matrix with a material selected from a third group, the third group comprising SiO x , amorphous Si, Si, TiO x 、AlO x , HfO x 、NiO x 、TaO x 、NbO x 、ZnO2、ZrO x and GdO x , wherein the thickness of the switching matrix is ​​in the range of 10 Å to 40 Å.

7. The method according to claim 1, wherein: The metal material of the donor material layer is selected from a third group, the third group including elemental Al, elemental Ti, elemental W, non-stoichiometric AlNx, non-stoichiometric AlNOx and non-stoichiometric TiN, and wherein the thickness of the donor material layer is in the range of 50Å to 500Å.

8. The method according to claim 7, wherein: The conductive first barrier material is in physical contact with the donor material layer and the conductive first barrier material comprises TiN or TaN, and wherein the conductive first barrier material has a second thickness in a range of 200 Å to 1500 Å.

9. The method according to claim 1, wherein: The optional barrier material layer includes Ti or W and has a thickness in the range of 50Å to 500Å.

10. The method according to claim 1, wherein: The dielectric hard mask includes SiO2 material, SiN material, SiC material, SiON material or amorphous carbon.

11. A method for manufacturing a two-terminal resistance switching device, the method comprising: depositing a metal layer covering and contacting a lower electrode and a dielectric material, wherein the lower electrode and the dielectric material cover a substrate; depositing a conductive selective donor layer overlying the metal layer; depositing a selector layer formed of a resistive material having material defect sites configured to allow conductive particles of the conductive select donor layer to diffuse within the selector layer in response to a first polarity bias applied to the two-terminal resistive switching device; depositing a second conductive selection donor layer overlying the selector layer, the second conductive selection donor layer supplying second conductive particles to the selector layer in response to a second polarity bias applied to the two-terminal resistance switching device; depositing a conductive buffer material covering the second conductive selective donor layer; depositing a dielectric hard mask covering the conductive buffer material; patterning a photoresist material overlying the dielectric hard mask; etching the dielectric hard mask with a first etch and stopping the first etch on the conductive buffer material, the first etch comprising an etching gas comprising at least one of C4F8, C4F6, CHF3, CF4, CO, O2, N2, or Ar; etching a majority of the conductive buffer material with a second etch and stopping the second etch without exposing the second conductive selective donor layer by the second etch, the second etch comprising an etching gas comprising at least one of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, or SF6; as well as Etching is performed with a third etch, the third etch comprising physically etching the remaining minor portion of the conductive buffer material, the second conductive selective donor layer, the selector layer, and the conductive selective donor layer.

12. The method according to claim 11, wherein: The physical etching further includes etching the metal layer and stopping the physical etching on the dielectric material.

13. The method according to claim 11, wherein: The physical etching is argon plasma etching or ion milling etching.

14. The method according to claim 11, further comprising forming a liner layer covering the etched stack, the etched stack comprising at least: The conductive selective donor layer, the selector layer, the second conductive selective donor layer and the conductive buffer material.

15. The method according to claim 11, wherein: The third etch further includes etching the metal layer and stopping the third etch on the dielectric material.

16. The method according to claim 11, wherein: Depositing the conductive selective donor layer or the second conductive selective donor layer further includes depositing a doped silver material for the conductive selective donor layer or the second conductive selective donor layer, respectively.

17. The method according to claim 16, wherein: The doped silver material is doped with a platinum dopant or a palladium dopant.

18. The method according to claim 16, wherein: Depositing the selector layer further comprises depositing a layer selected from SiO x 、TiO x 、AlO x , WO x 、Ti x N y O z , HfO x 、TaO x 、SiO x Stacking with GeTe and TiO x With AlO x A stack consisting of a group of non-stoichiometric materials.

19. The method according to claim 11, wherein: The conductive selective donor layer and the second conductive selective donor layer include platinum-doped silver material.

20. The method of claim 11, further comprising forming one or more optional spacers adjacent to at least one of: the dielectric hard mask being etched; a majority of the conductive buffer material being etched; or The conductive selective donor layer is etched, the selector layer is etched, and the second conductive selective donor layer is etched.

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