Method for reducing gate height difference and semiconductor structure

Abstract

The method comprises the following steps that S1, a substrate on which secondary side wall etching is to be carried out is provided, the substrate comprises a PMOS area and an NMOS area, grid structures are formed on the PMOS area and the NMOS area, and second side wall layers are formed on the surface of the substrate and the grid structures; s2, forming a planarization material layer on the substrate, wherein the surface of the planarization material layer is higher than the gate structure; s3, synchronously etching the planarization material and the second side wall layer and the gate structure below the planarization material until the height difference of the gate structure of the PMOS region and the NMOS region is reduced to be within a target range; s4, the remaining planarization material is removed; and S5, etching the second side wall layer to obtain a gate side wall. Before the second grid side wall etching process is started, the grid height difference is reduced or even eliminated, and the influence on other subsequent processes is avoided.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and particularly relates to a method for reducing the gate height difference and a semiconductor structure. Background Art

[0002] In the 28-nanometer HKMG (high-k metal gate) process, the SiGe process will cause partial loss of the gate silicon oxide hard mask layer in the gate structure of the PMOS region. At the same time, the NMOS region is protected by the photoresist layer. Therefore, after the SiGe process, there is often a gate height difference between the PMOS region and the NMOS region. This height difference will remain until the process of the interlayer dielectric layer 0 (ILD0). The existence of the height difference will affect other process steps such as film growth, photoresist coating, and etching load. This requires multiple oxidation deposition and chemical mechanical polishing cycles in subsequent processes to eliminate this height difference and achieve height consistency. This process is cumbersome and costly.

[0003] Therefore, it is necessary to provide a method that can reduce the gate height difference earlier, combined with the second gate sidewall etching process, so that the gate height difference is reduced or even eliminated before the start of the second sidewall etching, reducing the difficulty of subsequent processes and providing the possibility for simplifying subsequent steps. Summary of the Invention

[0004] The present invention is to solve all or part of the above-mentioned prior art problems, and provides a method for reducing the gate height difference and a semiconductor structure.

[0005] A method for reducing the gate height difference provided by the present invention includes the following steps:

[0006] S1: Provide a substrate to be subjected to the second sidewall etching. The substrate includes a PMOS region and an NMOS region. Gate structures are formed on both the PMOS region and the NMOS region, and a second sidewall layer is formed on the surface of the substrate and the gate structures.

[0007] S2: Form a planarization material layer on the substrate, and the surface of the planarization material layer is higher than the gate structure.

[0008] S3: Synchronously etch the planarization material and the second sidewall layer and the gate structure thereunder until the gate height difference between the PMOS region and the NMOS region is reduced to the target range.

[0009] S4: Remove the remaining planarization material.

[0010] S5: Etch the second sidewall layer to obtain a gate sidewall.

[0011] In step S1, the gate structure from top to bottom is a hard mask layer, a gate material layer, and a gate dielectric layer in sequence.

[0012] The gate structure from top to bottom is a hard mask layer, a dummy gate polysilicon layer, a titanium nitride layer, and a hafnium oxide layer in sequence. The hard mask layer includes a gate oxidation hard mask and a gate nitride hard mask layer.

[0013] In step S1, the hard mask layer includes a gate oxidation hard mask and a gate nitride hard mask layer, and the epitaxial layer is a germanium-silicon epitaxial layer.

[0014] In the said step S1, the second spacer layer is composed of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0015] In step S2, the planarization material is spin-on carbon.

[0016] In step S3, the synchronous etching uses low selectivity etching, and the etching rate ratio of the planarization material to the second spacer layer and the gate structure is (1:2) to (2:1). By customizing the etching time to control the etching amount, the gate height difference between the PMOS region and the NMOS region is reduced or even eliminated. Meanwhile, during the etching process, the planarization material protects the spacer layer under the gate from being damaged.

[0017] In step S4, the remaining planarization material is removed by ashing.

[0018] The present invention also provides a semiconductor structure, which is prepared by using the method for reducing the gate height difference described in any of the above technical methods.

[0019] Compared with the prior art, the technical solution provided by the present invention can reduce or even eliminate the gate height difference between the PMOS region and the NMOS region before the start of the second gate spacer etching process, that is, the gate height difference is eliminated earlier, avoiding the influence of the gate height difference on subsequent other processes, and there is no need to specifically eliminate the height difference through multiple oxidation deposition and chemical mechanical polishing cycle steps in subsequent processes, saving process costs; in addition, the present invention is not a separate set of process steps, but is combined with the production process of the second spacer etching process, saving at least one dry etching and post-etching cleaning process step. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments described in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 Flowchart of a method for reducing the gate height difference provided by the present invention;

[0022] Figure 2 Schematic diagram of a semiconductor structure including a gate structure in a PMOS region and an NMOS region provided in Embodiment 1 of the present invention;

[0023] Figure 3 Schematic diagram of the semiconductor structure after being processed by step S2 in Embodiment 1;

[0024] Figure 4 Schematic diagram of the semiconductor structure after being processed by step S3 in Embodiment 1;

[0025] Figure 5 Schematic diagram of the semiconductor structure after being processed by step S4 in Embodiment 1;

[0026] Figure 6 Schematic diagram of the semiconductor structure after being processed by step S5 in Embodiment 1.

[0027] Description of reference numerals:

[0028] 1. Substrate; 2. PMOS region; 3. NMOS region; 201. Epitaxial layer; 4. Gate structure; 401. Gate oxide layer; 402. Gate nitride layer; 403. Pseudo-gate polysilicon layer; 404. Titanium nitride layer; 405. Hafnium oxide layer; 501. Silicon nitride layer; 502. Silicon oxide layer; 503. Silicon nitride layer; 6. Planarization material. Detailed implementation manners

[0029] The following description and drawings fully disclose the specific implementation manners of the present invention, enabling those skilled in the art to practice them. Other implementation manners may include structural, logical, electrical, process, and other changes. Embodiments only represent possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments.

[0030] In the 28-nanometer HKMG process, the spacer is one of the key structures, mainly used to define the source / drain regions of transistors and provide a mask for subsequent ion implantation. There are usually two main spacer formation processes. After the gate structure is formed, the first gate spacer (Spacer1) process is carried out to prepare for the subsequent lightly doped implantation (LDD process). After the lightly doped implantation, the SiGe process is usually carried out to improve the electrical performance of PMOS, specifically including forming a germanium-silicon hard mask layer, removing the germanium-silicon hard mask layer in the PMOS region using photolithography and etching processes, using the remaining germanium-silicon hard mask layer as an etching mask to etch Sigma-shaped trenches on both sides of the gate structure of PMOS, and performing germanium-silicon epitaxial growth to fill the trenches.

[0031] In the above SiGe process, during the trench etching process, the surface of the gate structure in the PMOS region is not shielded by a germanium-silicon hard mask, resulting in the gate structure height of the PMOS being lower than that of the NMOS, forming a gate height difference. The existence of this height difference will affect subsequent processes such as film growth and photoresist coating. After the SiGe process is completed, the second gate spacer (Spacer2) process is usually carried out to prepare for the subsequent heavily doped implantation (source / drain ion implantation). Therefore, the present invention provides a method for reducing the gate height difference, which reduces or even eliminates the gate structure height difference between the PMOS region and the NMOS region before the second spacer etching, reduces the difficulty of subsequent processes, and also provides the possibility for simplifying subsequent steps.

[0032] Example 1

[0033] A method for reducing the gate height difference provided in this embodiment is as Figure 1 and Figure 2 shown, including the following steps:

[0034] S1: Provide a substrate 1 to be subjected to the second spacer etching. The substrate includes a PMOS region 2 and an NMOS region 3. Gate structures 4 are formed on both the PMOS region 2 and the NMOS region 3. A second spacer layer is formed on the surface of the substrate 1 and the gate structures 4.

[0035] It can be understood that the substrate 1 to be subjected to the second spacer etching in this application is the substrate that has completed the SiGe process and deposited the second spacer layer. In the normal process, after depositing the second spacer layer, etching treatment will be directly carried out subsequently to obtain the required second gate spacer to prepare for the subsequent source / drain ion implantation.

[0036] In this step, the substrate 1 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The semiconductor material generally includes the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon germanium, or compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.). The semiconductor material may be doped or undoped.

[0037] The gate structure 4 has a height difference. From top to bottom, the gate structure 4 includes a gate oxide layer 401, a gate nitride layer 402, a dummy gate polysilicon layer 403, a titanium nitride layer 404, and a hafnium oxide layer 405.

[0038] The second sidewall layer is composed of one or more of silicon nitride, silicon oxide, and silicon oxynitride. The sidewall layer can protect the gate structure, prevent the source-drain injection with a large dose from being too close to the channel so that source-drain punch-through occurs, reduce the short-channel effect, effectively improve the reliability and performance of the device, and at the same time can also reduce power consumption and noise. In this embodiment, the second sidewall layer is a silicon nitride layer 503, and the first sidewall layer includes a silicon nitride layer 501 and a silicon oxide layer 502.

[0039] Epitaxial layers 201 are formed on the source-drain regions on both sides of the gate structure 4 on the PMOS region 2. The epitaxial layer 201 is a germanium-silicon epitaxial layer.

[0040] S2: Spin-coat a planarization material 6 on the substrate 1 to cover the surfaces of the substrate 1 and the gate structure 4. Refer to Figure 3 , the planarization material is spin-on carbon. On the one hand, the planarization material is used to reduce the height difference of the gate structures in the PMOS region 2 and the NMOS region 3. On the other hand, it protects the sidewall layer under the gate from being damaged during the etching process. In other embodiments, the planarization material may also be barc (bottom anti-reflection coating material), other carbon films, or organic films (i.e., mainly composed of carbon, hydrogen, and oxygen), and utilize its high filling rate characteristic to achieve a better planarization function.

[0041] S3: Synchronously etch the planarization material 6, the second sidewall layer below it, and the gate structure 4 until the height difference of the gate structures 4 in the PMOS region 2 and the NMOS region 3 is reduced to the target range. Refer to Figure 4 . In this step of etching, a low selectivity etching is used. The etching rate ratio of the planarization material to the second sidewall layer and the gate structure is (1:2) to (2:1). The etching amount is controlled by customizing the etching time to reduce or even eliminate the gate height difference between the PMOS region 2 and the NMOS region 3.

[0042] S4: Remove the remaining planarization material 6. Refer to Figure 5 . The remaining planarization material is removed by ashing, which will not affect other film layers.

[0043] S5: Etch the lower part of the second sidewall layer of the PMOS region 2 and the NMOS region 3 to obtain the target gate sidewall topography, see Figure 6 . According to the target gate sidewall topography and requirements, adjust the selectivity ratio of silicon nitride to silicon oxide, and perform one-step or multi-step etching.

[0044] The present invention also provides a semiconductor structure obtained by the method for reducing the gate height difference provided by any of the above technical solutions.

[0045] It should be understood that some common English nouns or letters used in this application for the convenience of clear description are only used for exemplary reference rather than limiting interpretation or specific usage, and the protection scope of this application should not be limited by their possible Chinese translations or specific letters. It should also be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for reducing the gate height difference, characterized in that It includes the following steps: S1: Provide a substrate to be subjected to second sidewall etching. The substrate includes a PMOS region and an NMOS region. Gate structures are formed on both the PMOS region and the NMOS region, and a second sidewall layer is formed on the surfaces of the substrate and the gate structures. S2: Form a planarization material layer on the substrate, and the surface of the planarization material layer is higher than the gate structures. S3: Simultaneously etch the planarization material, the second sidewall layer and the gate structures below it until the height difference between the gate structures in the PMOS region and the NMOS region is reduced to the target range. S4: Remove the remaining planarization material. S5: Etch the second sidewall layer to obtain gate sidewalls.

2. The method for reducing the gate height difference according to claim 1, wherein In step S1, the gate structure includes a hard mask layer, a gate material layer and a gate dielectric layer from top to bottom.

3. A method for reducing the gate height difference according to claim 1, characterized in that The gate structure includes a hard mask layer, a dummy gate polysilicon layer, a titanium nitride layer, and a hafnium oxide layer from top to bottom.

4. A method for reducing the gate height difference according to claim 2 or 3, characterized in that, The hard mask layer includes a gate oxidation hard mask and a gate nitride hard mask layer.

5. A method for reducing the gate height difference according to claim 1, characterized in that, In step S1, an epitaxial layer is formed on the source-drain regions on both sides of the gate structure in the PMOS region, and the epitaxial layer is a germanium-silicon epitaxial layer.

6. A method for reducing the gate height difference according to claim 1, characterized in that, In step S1, the second sidewall layer is composed of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

7. A method for reducing the gate height difference according to claim 1, characterized in that, In step S2, the planarization material is spin-on carbon.

8. A method for reducing the gate height difference according to claim 1, characterized in that, In step S3, the simultaneous etching uses low-selectivity etching, and the etching rate ratio of the planarization material to the second sidewall layer and the gate structure is (1:2) to (2:1).

9. A method for reducing the gate height difference according to claim 1, characterized in that In step S4, the remaining planarization material is removed by ashing.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by using the method for reducing the gate height difference according to any one of claims 1 to 9.

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