Resistive switching memory with confined filaments and methods thereof

Abstract

A resistance-switching memory cell having a filament-based switching mechanism is provided. By way of example, a resistance-switching memory cell having a resistance filament confined to a core of the cell is disclosed. In other examples, methods for fabricating a resistance-switching memory cell to confine a conductive filament formed in the resistance-switching memory cell to a central portion of the core of the cell are disclosed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] U.S. Patent No. 9,425,237, filed on December 31, 2014, entitled “SELECTOR DEVICE FOR TWO-TERMINAL MEMORY,” U.S. Patent No. 10,873,023, filed on March 24, 2017, entitled “USING ALUMINUM AS ETCH STOP LAYER,” U.S. Patent No. 10,522,754, filed on April 5, 2017, entitled “LINER LAYER FOR A DIELECTRIC BLOCK LAYER,” and U.S. Patent No. 10,749,110, filed on April 13, 2017, entitled “MEMORY STACK LINER INCLUDING DIELECTRIC BLOCK LAYER MATERIAL,” are each incorporated herein by reference in their entirety and for all purposes. Technical Field

[0003] Embodiments of the present disclosure relate to electronic memory structures; for example, various embodiments disclose apparatus and methods for fabricating resistive switching memory structures. Background Art

[0004] Resistive switching memory represents the latest innovation in the field of integrated circuit technology. Although most resistive switching memories are in the development stage, the inventors have demonstrated various technical concepts of resistive switching memory, and various technical concepts are in one or more verification stages to prove or refute related theories or technologies. The inventors believe that the resistive switching memory technology shows convincing evidence to prove that it has substantial advantages over competing technologies in the semiconductor electronics industry.

[0005] The inventors believe that the resistance switching memory cell can be configured to have multiple states with different resistance values. For example, for a single-bit cell, the resistance switching memory cell can be configured to exist in a relatively low resistance state, or, alternatively, in a relatively high resistance state. Multi-bit cells may have additional states where the resistances are different from each other and are different from the relatively low resistance state and the relatively high resistance state. The different resistance states of the resistance switching memory cell represent different logical information states, facilitating digital storage operations. Therefore, the inventors believe that an array of many such memory cells can provide digital memory storage of many bits.

[0006] The inventors have successfully induced a resistance switching memory to enter one or another resistance state in response to an external condition. Thus, in transistor parlance, applying or removing an external condition can be used to program or deprogram (e.g., erase) the memory. In addition, depending on the physical composition and electrical arrangement, the resistance switching memory cell can generally maintain a programmed or deprogrammed state. Depending on the characteristics of the memory cell device, maintaining the state may require other conditions to be met (e.g., the presence of a minimum operating voltage, the presence of a minimum operating temperature, etc.) or not to be met.

[0007] Several proposals have been made by inventors to actually utilize resistance switching technology to include transistor-based memory applications. For example, resistance switching elements are often theorized as viable replacements, at least in part, for metal oxide semiconductor (MOS) type memory transistors for electronic storage of digital information. Models of resistance switching memory devices offer several potential technical advantages over non-volatile FLASH MOS type transistors.

[0008] In view of the foregoing, the inventors desire new mechanisms for processing semiconductor wafers, and in particular for processing resistive memory structures within one or more semiconductor wafers, and for overcoming current challenges in the art encountered by the inventors. Summary of the invention

[0009] A simplified summary of the subject disclosure is given below in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is neither intended to identify the important or key elements of the disclosed subject matter nor to delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to a more detailed description presented later.

[0010] Embodiments of the present disclosure provide resistance switching memory cells with a filament-based switching mechanism. In addition, these resistance switching memory cells can have a resistance filament confined to the core of the cell. In an embodiment, a method for manufacturing such a resistance switching memory cell is disclosed.

[0011] In an embodiment, a method for manufacturing a resistance switching device is provided. The method may include providing a bottom electrode formed in a dielectric material covering a substrate of the device and forming a conductive layer covering the bottom electrode and the dielectric layer and contacting the bottom electrode and the dielectric layer. In addition, the method may include: forming a first resistance switching layer covering the conductive layer, wherein the first resistance switching layer is a resistive material; and etching a gap in the first resistance switching layer and exposing a portion of the conductive layer to the gap. In addition, the method may include: depositing a second resistance switching layer, producing a second gap in the second resistance switching layer, the second resistance switching layer conformally covering the first resistance switching layer and the portion of the conductive layer exposed by the gap, wherein the second resistance switching layer is configured to allow diffusion of conductive particles within the second resistance switching layer. In addition, the method may include forming a top electrode covering the second resistance switching layer and filling the second gap, wherein the top electrode includes conductive particles and provides conductive particles for diffusion within the second resistance switching layer in response to an electrical excitation applied to the resistance switching device. In addition to the foregoing, the method may include: forming an optional barrier layer covering the top electrode and a hard mask material covering the top electrode and the optional barrier layer; forming and patterning a photoresist covering the hard mask material; and etching the hard mask, the optional barrier layer, the top electrode, the second resistance switching layer, and the first resistance switching layer to form a discrete resistance switching device.

[0012] In another embodiment, the subject disclosure provides a method of forming a resistive switching device. The method may include: forming a conductive metal layer covering a bottom electrode and in physical contact with the bottom electrode and a dielectric layer in which the bottom electrode is located, wherein the bottom electrode and the dielectric layer cover a substrate; and forming a switching layer having a first thickness above the conductive layer, wherein the switching layer includes a resistive switching material that is at least partially permeable to conductive particles. In addition, the method may include: forming a barrier layer covering the switching layer, the barrier layer blocking the permeability of the conductive particles therein; etching a gap in the barrier layer and exposing a portion of the switching layer to the gap, and etching the portion of the switching layer exposed to the gap in the barrier layer with a second etch; and causing the portion of the switching layer to have a second thickness that is less than the first thickness of the switching layer. In addition, the method may include forming a top electrode covering and contacting both the barrier layer and the portion of the resistive switching layer, and etching the top electrode, the barrier layer, and the switching layer with a third etch to form a discrete resistive switching device.

[0013] In yet another embodiment, the method may include manufacturing a resistive switching device. The method may include: forming a conductive layer on a bottom electrode located within a dielectric layer of a semiconductor substrate; and forming a switching layer covering the conductive layer and in physical contact with the conductive layer, wherein the switching layer includes a resistive material that is at least partially permeable to conductive particles. The method may also include: forming a top electrode layer covering the switching layer and in physical contact with the switching layer, wherein the top electrode layer provides conductive particles that drift into the switching layer in response to applying an electrical excitation across the bottom electrode and the top electrode; and forming a covering layer covering the top electrode layer. The method may also include etching the covering layer, the top electrode layer, and the switching layer to form a discrete resistive switching device, wherein the etching includes chemically etching at least the switching layer to produce a wet etched portion of the etched switching layer. In addition to the foregoing, the method may include passivating the periphery of the etched switching layer or the etched top electrode layer to a certain depth within the resistive switching device and forming a passivation shell around the core of the resistive switching device, wherein the resistance of the passivation shell is higher than the resistive material of the switching layer, and the permeability of the passivation shell to the conductive particles is lower than the resistive material of the switching layer.

[0014] The following description and accompanying drawings set forth certain illustrative aspects of the present specification. However, these aspects are only indicative of a few of the various ways in which the principles of the present specification may be employed. Other advantages and novel features of the present specification will become apparent from the following detailed description of the specification when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Aspects or features of the present invention are described with reference to the accompanying drawings, wherein the same reference numerals are used to refer to the same elements throughout. In this specification, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the subject disclosure may be practiced without these specific details, or practiced with other methods, components, materials, etc. In other cases, known structures and devices are shown in block diagram form to facilitate description of the subject disclosure.

[0016] Figure 1 depicts a block diagram of an example resistive memory cell deposition according to one or more disclosed embodiments;

[0017] Figures 2 to 7 Shows the deposition Figure 1 A block diagram of steps of an example resistive memory cell;

[0018] Figure 8 depicts a block diagram of an example etch for forming a resistive memory cell having filaments confined near a core of the device in an embodiment;

[0019] Fig. 9 A block diagram showing an example filament of a disclosed resistive memory cell in one embodiment is shown;

[0020] Fig.10 depicts a block diagram of an example deposition of a lower layer for a resistive memory cell in further embodiments;

[0021] Fig.11 shows a block diagram of an example central barrier layer etch according to further disclosed embodiments;

[0022] Fig.12 Depicted in some embodiments by Fig.11 A block diagram of a process for etching a central barrier layer to expose a central switching layer;

[0023] Fig.13 The covering barrier layer and Fig.12 Block diagram of top electrode deposition of the central switching layer;

[0024] Fig.14 depicts a block diagram of an upper layer deposition covering an activated central switching layer in a further embodiment;

[0025] Fig.15 A block diagram of a resistive memory cell etch for forming a discrete resistor device is shown in one embodiment;

[0026] Fig.16 depicts a block diagram of an example deposition of a resistive memory cell according to further embodiments of the present disclosure;

[0027] Fig.17 In the embodiment, the Fig.16 A block diagram of an example etch of a deposition;

[0028] Fig.18 depicts a block diagram of an example passivated sidewall and non-passivated core of a resistance-switching filament in further embodiments;

[0029] Fig.18A , 18B and 18C depicts a block diagram of an example passivation of a resistive switching device in some embodiments;

[0030] Fig.18D , 18E and 18F depicts a block diagram of a sample passivation of a resistive switching device according to alternative or additional embodiments;

[0031] Fig.19 A flow chart showing an example method of manufacturing a resistive switching device in various embodiments;

[0032] Fig. 20 depicts a flow chart of a sample method of manufacturing a resistive switching device according to additional embodiments;

[0033] Fig.21depicts a flow chart of an example method of manufacturing a resistive switching device according to further embodiments;

[0034] Fig. 22 A block diagram illustrating an example electronic operating environment according to an embodiment of the present disclosure is shown;

[0035] Fig.23 A block diagram of an example computing environment for implementing one or more disclosed embodiments presented herein is depicted. DETAILED DESCRIPTION

[0036] As the name implies, a two-terminal resistance switching device has two terminals or electrodes. In this document, the terms "electrode" and "terminal" are used interchangeably; in addition, the two-terminal resistance switching device includes a non-volatile two-terminal memory device and a volatile two-terminal switching device. Typically, the first electrode of the two-terminal resistance switching device is referred to as the "top electrode" (TE) and the second electrode of the two-terminal resistance switching device is referred to as the "bottom electrode" (BE), although it should be understood that the electrodes of the two-terminal resistance switching device can be arranged in any suitable arrangement, including a horizontal arrangement, in which the components of the memory cell are (substantially) side by side rather than overlapping each other. There is typically an interface layer between the TE and BE of a two-terminal resistive switching device, sometimes also referred to as a switching layer, resistive switching medium (RSM) or resistive switching layer (RSL); such devices are not limited to these layers, however, as disclosed herein, in publications incorporated herein by reference or incorporated therein, as generally understood and utilized in the art, or as reasonably conveyed to a person of ordinary skill in the art by the context provided herein and its supplementary or incorporated publications to the general understanding of the art, one or more barrier layers, adhesion layers, ion conducting layers, seed layers, particle source layers, etc. may be included between or adjacent to one or more of the TE, BE or interface layers consistent with proper operation of such a device.

[0037] In general, the composition of a memory cell can vary from device to device, with different components, materials, or deposition processes selected to achieve desired characteristics (e.g., stoichiometry / non-stoichiometry, volatility / non-volatility, on / off current ratios, switching time, read time, storage endurance, program / erase cycles, etc.). An example of a filament-based device may include: a conductive layer, such as a metal, a metal alloy, a metal nitride (e.g., including TiN, TaN, TiW, or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer (e.g., a p-type or n-type Si carrier layer, p-type or n-type polysilicon, p-type or n-type polycrystalline SiGe, etc.); a resistive switching layer (RSL); and an active metal-containing layer that can be ionized. Under appropriate conditions, the active metal-containing layer can provide ions to the RSL to form a filament. In such an embodiment, a conductive filament (e.g., formed by ions) can promote conductivity through at least a subset of the RSL, and as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. A memory cell with such characteristics can be described as a filament-based device.

[0038] The RSL (which may also be referred to in the art as a resistance switching medium (RSM)) may include, for example, a non-doped amorphous Si layer, a semiconductor layer having intrinsic properties, a stoichiometric or non-stoichiometric silicon nitride (e.g., SiN, Si3N4, SiN x etc.), Si suboxides (e.g., SiO x , where the value of x is between 0.1 and 2), Si nitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si x Ge y O z (where x, y, and z are respectively suitable positive numbers), silicon oxides (e.g., SiO N , where N is a suitable positive number), silicon oxynitride, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is a suitable number), Al2O E (wherein E is a suitable positive number), etc., nitrides (e.g., AlN, SiN), or suitable combinations thereof.

[0039] In some embodiments, an RSL used as part of a nonvolatile memory device (nonvolatile RSL) may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to capture neutral metal particles within the RSL (e.g., at low voltages). A large number of voids or defects may facilitate the formation of a thick, stable structure of neutral metal particles. In such a structure, these trapped particles may maintain the nonvolatile memory device in a low resistance state in the absence of external excitation (e.g., electricity), thereby achieving nonvolatile operation. In other embodiments, an RSL used for a volatile selector device (volatile RSL) may have very few material voids or defects to capture particles. Since there are few voids / defects to capture particles, the conductive filaments formed in such an RSL may be very thin (e.g., one to several particle widths, depending on the field strength, particle material or RSL material, or a suitable combination of the foregoing) and are unstable without a suitably high external excitation (e.g., an electric field, voltage, current, Joule heat, or a suitable combination thereof). In addition, the particles can be selected to have high surface energy and good diffusivity within the RSL. This enables the conductive filaments to form quickly in response to a suitable stimulus, but also to deform easily, for example, in response to an external stimulus below the deformation level (which can be below the formation level of an external stimulus associated with the formation of volatile conductive filaments, such as in response to a current flowing through the selector device; see U.S. Patent No. 9,633,724 B2, which is incorporated herein by reference in its entirety and for all purposes). Note that the volatile RSL and conductive filaments used in the selector device can have different electrical properties than the conductive filaments and non-volatile RSL used in the non-volatile memory device. For example, the selector device RSL can have a higher material resistance and can have a higher on / off current ratio.

[0040] Among them, the active metal-containing layer for the filament-based memory cell may include: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf) and palladium (Pd). Other suitable conductive materials, as well as stoichiometric or non-stoichiometric: compounds, nitrides, oxides, alloys, mixtures or combinations of the foregoing or similar materials, may be used for the active metal-containing layer in some aspects of the subject disclosure. In addition, in at least one embodiment, non-stoichiometric compounds, such as non-stoichiometric metal oxides / metal oxides or metal nitrogen / metal nitrides (e.g., AlO x 、AlN x , CuO x , CuN x 、AgOx , AgN x etc., where x is a suitable positive number or range of numbers, for example: 0 < x < 2, 0 < x < 3, 0 < x < 4 or other numbers / ranges of numbers, depending on the metal compound, which may have different values for different non-stoichiometric compounds) or other suitable metal compounds can be used for the active metal layer.

[0041] In one or more embodiments, the disclosed filamentary resistive switching device may include an active metal layer comprising a nitrogen metal selected from the group consisting of TiN x , TaN x , AlN x , CuN x , WN x and AgN x , where x is a positive number (or range of numbers) that can vary depending on the nitrogen metal material. In additional embodiments, the active metal layer may comprise an oxygen metal selected from the group consisting of TiO x , TaO x , AlO x , CuO x , WO x and AgO x , where x is a positive number (or range of numbers) that can also vary depending on the oxygen metal material. In additional embodiments, the active metal layer may comprise a nitrogen-oxygen metal selected from the group consisting of TiO a N b , AlO a N b , CuO a N b , WO a N b and AgO a N b , where a and b are suitable positive numbers / ranges of numbers. The disclosed filamentary resistive switching device may further include a switching layer comprising a material selected from the group consisting of SiO y , AlN y , TiO y , TaO y , AlO y , CuO y , TiN x , TiN y , TaN x , TaN y , SiO x , SiN y , AlN x , CuN x , CuN y , AgN x、AgN y 、TiO x 、TaO x 、AlO x , CuO x 、AgO x and AgO y Switching materials in the group consisting of, wherein x and y are positive numbers (or ranges), y is greater than x. Various combinations of the above are contemplated and considered within the scope of embodiments of the present invention.

[0042] In one example, the disclosed filamentary resistive switching device includes a particle donor layer (e.g., an active metal layer) containing a stoichiometric or non-stoichiometric metal compound (or mixture) and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer includes nitrogen metal: MN x , such as AgN x 、TiN x 、AlN x etc., and the resistance switching layer includes nitrogen metal: MN y , such as AgO y 、TiO y 、AlO y etc., where y and x are positive numbers (or ranges), and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer includes oxygen metal:MO x , such as AgO x 、TiO x 、AlO x etc., and the resistance switching layer includes oxygen metal:MO y , such as AgO y 、TiO y 、AlO y etc., wherein y and x are positive numbers (or ranges), and in some cases y is greater than x. In yet another alternative, the metal compound of the particle donor layer is MN x (e.g. AgN x 、TiN x 、AlN x etc.), and the resistance switching layer is selected from MO y (e.g. AgO y 、TiO y 、AlO y etc.) and SiO y A group consisting of wherein x and y are generally non-stoichiometric values, or in yet another embodiment, vice versa.

[0043] As used herein, variables x, y, a, b, etc., representing the value or ratio of one element relative to another (or other) element in a compound or mixture may have different values ​​(or ranges) suitable for each compound / mixture and are not intended to represent the same or similar values ​​or ratios between compounds. A mixture may refer to non-stoichiometric materials containing free elements therein (e.g., metal-rich nitrides or oxides (metal oxides / nitrides with free metal atoms), metal-poor nitrides or oxides (metal oxides / nitrides with free oxygen / nitrogen atoms)) and other combinations of elements that do not form traditional stoichiometric compounds as understood in the art. Some details related to embodiments disclosed in the subject matter may be found in the following U.S. patent applications issued to the assignee of the present patent application: Application Nos. 11 / 875,541 filed on October 19, 2007 and 12 / 575,921 filed on October 8, 2009; each of the foregoing patent applications is incorporated herein by reference in its respective entirety and for all purposes, except for the patent applications incorporated herein by reference elsewhere.

[0044] It should be understood that various embodiments herein can utilize various memory cell technologies having different physical characteristics. For example, different resistance-switching memory cell technologies can have different discrete programmable resistances, different associated programming / erase voltages, and other differentiated characteristics. For example, various embodiments disclosed herein can employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and exhibits a second switching response (e.g., erasing to an erased state) to an electrical signal of a second polarity. For example, a bipolar switching device is contrasted with a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to an electrical signal having the same polarity and different amplitudes.

[0045] In various embodiments, the filament-based resistive switching device can operate in a bipolar manner, behaving differently in response to external stimuli of different polarities (or directions, energy flows, energy source directions, etc.). For a volatile filament-based selector device, as an illustrative example, in response to a first polarity stimulus exceeding a first threshold voltage (or voltage set), the filamentary selector device can change from a first resistive state to a second resistive state. In addition, in response to a second polarity stimulus exceeding a second threshold voltage, the filamentary selector device can change from a first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurable different characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus magnitude (although opposite polarity or direction), etc. In other embodiments, the third state can be different from the second state, either in terms of a measurable characteristic (e.g., a different conductivity value in response to a reverse polarity compared to a forward polarity) or in terms of a threshold stimulus associated with a transition away from the first state (e.g., a different magnitude of a positive voltage required to transition to the second state compared to the magnitude of a negative voltage required to transition to the third state).

[0046] For bipolar operation of non-volatile filament-based memory cells, a conductive path or filament is formed through the non-volatile RSL in response to a suitable programming voltage applied to the memory cell. In particular, upon application of the programming voltage, metal ions are generated from the active metal-containing layer and migrate into the non-volatile RSL layer. The metal ions may occupy voids or defect locations within the non-volatile RSL layer. In some embodiments, upon removal of the bias voltage, the metal ions become neutral metal particles and remain trapped in the voids or defects of the non-volatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is generally determined by the tunneling resistance through the non-volatile RSL layer. In some resistive switching devices, an erase process may be implemented to deform the conductive filament, at least partially returning the memory cell from a low resistance state to a high resistance state. More specifically, upon application of an erase bias voltage, metal particles trapped in voids or defects of the nonvolatile RSL become mobile ions and migrate back toward the active metal layer. In the context of memory, this state change can be associated with the states of a binary bit. For an array of multiple memory cells, a word, byte, page, block, etc. of memory cells can be programmed or erased to represent zero or one of binary information, and by retaining these states over time while effectively storing binary information. In various embodiments, multiple levels of information (e.g., multiple bits) can be stored in such a memory cell.

[0047] Without specifying a particular memory cell technology or programming / erase voltage for the various aspects and embodiments herein, such aspects and embodiments are intended to be incorporated with any suitable memory cell technology and operated by programming / erase voltages appropriate for that technology, as known to one of ordinary skill in the art or made known by the context provided herein. It should also be understood that where substitution of a different memory cell technology would require circuit modifications known to one of ordinary skill in the art or changes in operating signal levels known to such a person of ordinary skill, embodiments that include the substituted memory cell technology or signal level changes are considered to be within the scope of the subject disclosure.

[0048] As described above, applying a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory can cause a conductive filament to form in an interface layer (e.g., RSL). By convention and as generally described herein, TE receives the programming pulse and BE is grounded (or maintained at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all embodiments. Conversely, applying an "erase pulse" to one of the electrodes (typically a pulse of opposite polarity to the programming pulse or to the opposite electrode to the programming pulse) can disrupt the continuity of the filament, for example, by driving metal particles or other materials that form the filament back to the active metal source. The characteristics of this conductive filament and its presence or absence affect the electrical characteristics of the two-terminal memory cell, for example, reducing the resistance and / or increasing the conductance between the two terminals when the conductive filament is present relative to when it is not present.

[0049] After the programming or erasing pulse, a read pulse may be applied. The amplitude of the read pulse is typically lower than the programming or erasing pulse and is typically insufficient to affect the conductive filament and / or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, the measured current (e.g., Ion) when compared to a predetermined threshold current may indicate the conductive state of the two-terminal memory cell. The threshold current may be pre-set based on the expected current values ​​of the two-terminal memory device in different states (e.g., high-resistance state current; individual currents of one or more low-resistance states, etc.), applicable to a given two-terminal memory technology. For example, when the conductive filament has been formed (e.g., in response to the application of a programming pulse), the conductance of the cell is greater than otherwise, and the measured current (e.g., Ion) read in response to the read pulse will be greater. On the other hand, when the conductive filament is removed (e.g., in response to the application of an erase pulse), the resistance of the cell is higher because the interface layer has a relatively high resistance, so the conductance of the cell is lower and the measured current (e.g., Ioff) read in response to the read pulse will be lower. By convention, when a conductive filament is formed, the memory cell is said to be in an "on state" and have a high conductance. When the conductive filament is not present, the memory cell is said to be in an "off state." A memory cell in an on state or an off state can be logically mapped to binary values, such as "1" and "0." It should be understood that the conventions used herein associated with the state of a cell or the associated logical binary mapping are not intended to be limiting, as other conventions, including opposite conventions, may be used in conjunction with the disclosed subject matter. The techniques detailed herein are described and illustrated in conjunction with single-level cell (SLC) memory, but it should be understood that the disclosed techniques may also be used in multi-level cell (MLC) memory, where a single memory cell can retain a set of measurable different states representing multiple bits of information.

[0050] Digital information can be stored in such a device by mapping it to the nonvolatile resistance states of a two-terminal memory cell. Electronic devices containing many of these two-terminal memory cells are also capable of storing large amounts of data. High-density arrays are configured to contain as many memory cells as possible for a given area of ​​chip space, thereby maximizing the data storage capacity of a memory chip or system-on-chip device.

[0051] For two-terminal memories (e.g., crossbar arrays) formed at the intersection of metal lines within a wafer, the inventors of the present disclosure recognize two general conventions for the arrangement of memory cells. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects (e.g., current, including leakage path current) of the surrounding circuit by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1), in which a group of multiple memory cells is isolated from the electrical effects of the surrounding circuit by one (or more) transistors. In the 1T1R context, a single memory cell can be configured to have high current suppression between memory cells, thereby significantly reducing the leakage path current of the 1T1R memory array. In the 1TnR context, many individual memory cells with high device density in a given amount of silicon space can be connected to a single transistor with very low density. Therefore, the 1TnR context promotes higher bit density of resistive memory cells on semiconductor chips.

[0052] An example mechanism for connecting a 1T1R memory array includes a first terminal of a two-terminal resistor memory device connected to the drain of a transistor. The second terminal of the two-terminal resistor memory device can be connected to a bit line of the 1T1R memory array. Depending on the erase / programming conditions of the memory array, the source of the transistor is grounded or used as a source of an erase or programming signal. Another example mechanism involves a three-terminal memory including a transistor coupled to a volatile two-terminal resistor switching device. The first terminal of the volatile RSD is connected to the gate of the transistor, and the second terminal of the volatile RSD is connected to a voltage source. When activated, the volatile RSD allows charge to accumulate at the gate of the transistor, and when deactivated, the charge accumulated at the gate of the transistor can be captured. Other resistor switching device (RSD) circuits may be used within the scope of the present disclosure.

[0053] Overview

[0054] Figure 1 A block diagram of an example resistive memory device deposition 100 is shown in accordance with various embodiments of the present disclosure. The resistive memory device deposition includes a conductive bottom plate 106 formed as a layer overlying a discrete bottom electrode 102 embedded within a dielectric layer 104. In various embodiments, the conductive bottom plate 106 may be any suitable conductive material. Examples include doped semiconductor materials (e.g., appropriately doped silicon, polysilicon, silicon germanium, etc.) and conductive metals, conductive compounds, alloys, mixtures, etc. As examples, the conductive bottom plate 106 may include W, TiN, TaN, etc. In at least one embodiment, the conductive bottom plate 106 may be a W metal having a flat upper surface, such as Figure 1 The orientation in the illustration of (see also, for example, U.S. Patent No. 10,522,754, which is incorporated herein by reference).

[0055] In one or more embodiments, the conductive base plate 106 may have a thickness of about to about Thickness within a range. As used herein, the terms "approximately," "about," and other related terms, when used to modify the numerical description of the disclosed structure, refer to a suitable range for a given number that will achieve the same or similar functions as described for the disclosed structure. In the absence of explicit disclosure of these ranges, a range within typical manufacturing tolerances understood by those of ordinary skill in the art may be implied. Alternatively, in some embodiments, a range between 1% and 5% or between 1% and 10% of the number may be implied, or in other embodiments, a range that a person of ordinary skill in the art would understand as being suitable for achieving the functions and features of the disclosed structure may be implied. Related terms used for qualitative (rather than quantitative) descriptions may be understood to imply explicitly stated substitutions or changes, changes understood in the art to achieve the functions or purposes described for a particular component or process, or a suitable combination of the foregoing.

[0056] The resistive memory device deposition 100 includes a first switching layer (also referred to as a sacrificial switching layer) 108 and a second switching layer 110 configured to position a filament formed within the resulting resistive switching memory device to the core (e.g., near the center) of the resistive switching memory device. As an illustrative contrast, consider the general case of a resistive memory deposition having a single electrically insulating switching layer in contact with a conductive backplane 106 and permeable to conductive particles (e.g., see below). Figure 3 ). As long as there is good conductivity and electric field strength, a filament structure of conductive particles can be formed through the electrically insulating switching layer. This condition is usually met if there is good surface continuity between the electrically insulating switching layer and the conductive base plate 106. Figure 3 , good surface continuity can be observed over the entire shared surface of the switching layer 108 and the bottom plate 206. However, due to the etching process, for such a discrete etching device (e.g., see below Fig.17) may be problematic with discrete etching devices having surface impurities, chemical etching byproducts, and the like at the periphery or outer surface of the discrete etching device. For example, filaments that form near-surface impurities or etching byproducts at the periphery of a discrete etching device may be damaged due to surface or material impurities created by etching. Damaged filaments can impair the expected performance characteristics of the switching device, create non-uniformities between different cells on a die or between different dies in a wafer, reduce cell life, prevent proper reverse switching, cause shorts or other problems. Embodiments of the present disclosure provide resistive switching devices and means for making such devices that confine filaments to the core or center of the resistive switching device, wherein the material is purer and the effects of etching at the periphery of the switching device are reduced or have no effect on the conductive filaments. Thus, these embodiments can enhance device performance, uniformity, and overall effectiveness.

[0057] In various embodiments, the first switching layer 108 can be constructed to resist drift or diffusion of conductive particles within the first switching layer 108 (e.g., general permeability of conductive particles within the first switching layer 108) compared to the second switching layer 110. For example, the first switching layer 108 can be more structurally dense than the second switching layer 110. This design is provided to mitigate or avoid the formation of conductive filaments within the first switching layer 108 and confine the filaments to the second switching layer 110. In one or more embodiments, the first switching layer 108 can be formed using an atomic layer deposition process. As an example, the atomic layer deposition process can produce a stoichiometric composition for the first resistive switching layer 108. In other embodiments, the second switching layer 110 can be formed to allow drift or diffusion of conductive particles therein. In one embodiment, the second switching layer 110 can be formed by a physical vapor deposition process. As another example, the physical vapor deposition process can produce a non-stoichiometric composition for the second resistive switching layer 110. In at least one embodiment, the first switching layer 108 and the second switching layer 110 can include the same material. As an example, but not limiting, the first switching layer 108 may include a material in a stoichiometric form and the second switching layer 110 may also include a material in a non-stoichiometric form. In other embodiments, the first switching layer 108 and the second switching layer 110 may be formed partially of different materials and partially of a common material, or may be formed entirely of different materials.

[0058] like Figure 1As shown, gaps in the first switching layer 108 allow the second switching layer 110 to contact (or come close to contacting) the conductive bottom plate 106. By utilizing materials or processes that result in the preferential formation of conductive filaments within the second switching layer 110, the first switching layer 108 can act as a boundary or blocking region that confines the filaments to the area where the second switching layer 110 is adjacent to the conductive bottom plate 106. Thus, when etching a resistive switching device from the resistive memory deposition 100 (e.g., see below), the first switching layer 108 can be used to form conductive filaments. Figure 8 and Fig. 9 ), the filament will be away from the outside of the resistive switching device and will not be damaged by byproducts of device etching.

[0059] In addition to the above, the resistive memory deposition 100 includes a top electrode-filament donor layer 112 covering the second switching layer 110. The top electrode-filament donor layer 112 can be a source of conductive particles that form conductive filaments within the second switching layer 110 (e.g., an active metal layer, etc.). In addition, a barrier layer 114 and optionally one or more additional layers can be disposed on the top electrode-filament donor layer 112, the one or more additional layers can include an adhesion layer, an ion conductive layer, a passivation layer, a diffusion mitigation layer, etc.

[0060] Figures 2 to 7 Describes in more detail Figure 1 The resistance memory is deposited 100. Figure 2 As shown, the bottom plate layer 206 is formed to cover the bottom electrode 102 and the dielectric layer 104. In various embodiments, the dielectric layer 104 may include any suitable non-conductive dielectric material, such as silicon material, silicon oxide material, etc. The bottom electrode 102 may include a conductive material, such as a metal, a conductive metal compound, a metal alloy, a metal mixture, etc., or a doped semiconductor, etc., or a suitable combination of the foregoing.

[0061] refer to Figure 3 , the first switching layer 308 is formed to cover the bottom plate layer 206. The first switching layer 308 may include a metal-nitrogen material, a metal-oxygen material, a silicon material, a silicon compound, etc. In one embodiment, the first switching layer 308 may be a stoichiometric composition of any of the above. In another embodiment, the first switching layer 308 may be deposited using an atomic layer deposition process. In at least one embodiment, the first switching layer 308 may be formed of AlOx or AlNx material, HfOx material, etc., or a suitable combination of the foregoing, where x is a suitable stoichiometric value (or in at least one embodiment, a non-stoichiometric value).

[0062] like Figure 4As shown, gaps can be formed in the first switching layer 308 to form an etched first switching layer 408. In one embodiment, the gaps can be a damascene process, in another embodiment, can be chemically etched, or in other embodiments, can be physically etched. In at least one embodiment, the gaps can expose a surface 410 of the bottom plate layer 206 to the gaps. However, in alternative embodiments, a very thin layer (e.g., a few angstroms to two nanometers) of the first switching layer 308 can remain covering the bottom plate layer 206, and in other further embodiments, the gaps can expose the surface of the bottom plate layer 206 unevenly, such that islands of the first switching layer 308 still cover small portions (patches) of the exposed surface 410 of the bottom plate layer 206.

[0063] refer to Figure 5 , the second switching layer 510 is formed to cover the exposed surface 410 of the etched first switching layer 408 and the bottom plate layer 206. In various embodiments, the second switching layer 510 can be formed by a physical vapor deposition process. In some embodiments, the second switching layer 510 can be formed as a non-stoichiometric composition that is at least partially permeable to conductive particles (e.g., ions, atoms, molecules, etc.). As a specific example, the second switching layer 510 can be formed as a non-stoichiometric composition of conductive particles that is at least partially permeable to the top electrode (e.g., see below Figure 6 Examples of suitable materials for the second switching layer 510, although not exhaustive, may include SiOx, amorphous Si, Si, TiO x 、AlO x , HfO x 、NiO x 、TaO x 、NbO x 、ZnO2、ZrO x , GdO x , Nitrogen metals (e.g., AlN x ), etc., or a suitable combination thereof. X is a suitable value for defining a stoichiometric or non-stoichiometric composition according to the respective characteristics of the above-mentioned compounds as stoichiometric and non-stoichiometric structures or mixtures to achieve the functions of the above-mentioned switching matrix 108. For example, a person of ordinary skill may understand that non-stoichiometric AlO xSuitable for allowing conductive particles to drift or diffuse and to form non-volatile filaments of such particles therein in response to an excitation, "x" may have a value or range of values ​​suitable for achieving a non-stoichiometric composition of such AlOx. Conversely, in the case of another compound that acts as a stoichiometric compound allowing conductive particles to drift or diffuse and to form filaments of such particles, "x" may have a value or range of values ​​suitable for achieving a stoichiometric composition of such other compound. In the case of another compound that acts as a non-stoichiometric compound and as a stoichiometric compound allowing conductive particles to drift or diffuse and to form filaments of such particles, "x" may have a value or range of values ​​suitable for achieving such non-stoichiometric and stoichiometric compositions.

[0064] Based on the depth to which the first switching layer 510 is etched, the second switching layer 510 may be in physical contact with the floor layer 206, partially in physical contact with the floor layer 206, or not in physical contact with the floor layer 206. For example, where a thin layer (e.g., a few angstroms to a few nanometers) of the etched first switching layer remains covering the exposed surface 410, the second switching layer 510 will not be in physical contact with the floor layer 206. In some embodiments, where islands of the first switching layer 308 still cover a small portion of the exposed surface 410 of the floor layer 206, the second switching layer 510 may be partially in physical contact with the floor layer 206. Conversely, where the exposed surface 410 is not completely covered by the first switching layer 308, the second switching layer 510 may be in physical contact with the floor layer 206 over the entire exposed surface 410.

[0065] like Figure 5 As shown, the second switching layer 510 can have a pit 512 in the top surface of the second switching layer 510. The pit 512 can result from forming the second switching layer 510 to fill the gap etched in the etched first switching layer 408. Any post-deposition cleaning or treatment of the second switching layer 510, such as CMP or other process to planarize the top surface of the second switching layer 510 (away from the pit 512), or surface treatment to remove impurities on top of the second switching layer 510 can be performed to retain the pit 512.

[0066] refer to Figure 6, a top electrode-filament donor layer 612 is deposited to cover the second switching layer 510. The top electrode-filament donor layer 612 fills the pit 512 covering the exposed surface 410 of the bottom plate layer 206. This causes the area of ​​the top electrode-filament donor layer 612 located within the pit 512 to be closer to the bottom plate layer 206 only within the exposed surface 410 area of ​​the bottom plate layer 206. The shortened distance between the top electrode-filament donor layer 612 and the bottom plate layer 206 in response to the voltage applied between the bottom electrode 102 and the top electrode-filament donor 612 causes the electric field in the exposed surface 410 area of ​​the bottom plate layer 206 to increase. In turn, this increased electric field causes the conductive ions of the top electrode-filament donor layer 612 to be preferentially formed within the exposed surface 410 area of ​​the bottom plate layer 206, reducing or avoiding the formation of conductive ions outside the exposed surface 410 area of ​​the bottom plate layer 206 (e.g., see below). Fig. 9 ) forms a conductive filament that conducts ions. This limits the formation of the conductive filament to the core of the resistive memory device.

[0067] In various embodiments, the top electrode-filament donor layer 612 can be selected from a material including particles that can be ionized, for example, in response to an electric field, a voltage, a current, a suitable temperature, etc., or a suitable combination of the foregoing. In addition, the material can be selected to include particles of a material that, in addition to being able to be ionized, is also at least partially permeable to the second switching layer 510. In response to a suitable physical stimulus (e.g., an electric field, a voltage, a current, a temperature, etc., or a suitable combination of the foregoing), the (ionized) conductive particles drift from the top electrode-filament donor layer 612 into the second switching layer 510 to form conductive filaments within the second switching layer 510 to achieve resistive switching as described herein or known in the art. In some examples, the material of the top electrode-filament donor layer 612 can include a non-stoichiometric (or, where appropriate, a stoichiometric) metal-nitrogen material, an Al material, an Al metal, a non-stoichiometric AlN x , stoichiometric or non-stoichiometric AlNO x , TiN, Ti, W, etc., or appropriate combinations of the foregoing.

[0068] In other embodiments, the metal (e.g., Al) or metal nitride (or metal oxide), such as nitrogen-poor metal nitride or nitrogen-rich metal nitride, used for the top electrode-filament donor layer 612 may have less than 2% Si by atomic weight of Si dopant in the metal material. Thus, for example, aluminum metal or a metal including AlN xThe metal-nitrogen material may also contain less than 2% Si by atomic weight (e.g., in one embodiment, between about 0.5% and about 1%). Silicon doping may be achieved by incorporating less than 2% silicon by atomic weight into a sputtering target of a metal containing a metal nitride. When the silicon-doped metal is deposited on top of the switching matrix 108, nitrogen gas is provided to the resistive memory device deposition 100 during the deposition of the silicon-doped metal to form a nitrogen metal with silicon doping. In one or more embodiments, Si dopants may also be provided to the second switching layer 510 or the first switching layer 308 or both. In further embodiments, Si dopants may be provided to other switching layers or top electrodes disclosed herein where appropriate.

[0069] Figure 7 Deposition 700 of one or more optional layers covering the top electrode-filament donor layer 612 is shown. An optional barrier layer / additional layer 714 is depicted, which may be excluded in some embodiments. In one embodiment, the optional barrier layer / additional layer 714 may include a barrier layer selected from a material that resists the permeability of the conductive particles of the top electrode-filament donor layer 612. In other embodiments, the barrier layer may include a material that resists the permeability of oxygen or other reactive gases or plasmas used in semiconductor manufacturing, resists the permeability of atmospheric gases, resists chemical bonding with one or more etching materials used in semiconductor manufacturing, etc. In some embodiments, the barrier layer may be selected from materials including TiN, Ti, W, TaN, etc. or a suitable combination of the foregoing. The optional additional layer may include one or more of the following: an adhesion layer, an etch stop layer, a passivation layer, a seed layer, a dielectric layer, a conductive plug layer, or other suitable layers known in the art, or a suitable combination of the foregoing. A dielectric hard mask 716 may be provided on the optional barrier layer / additional layer 714. In one embodiment, the dielectric hard mask 716 may include a material selected from SiO2, SiN, SiC, SiON, amorphous carbon, etc., or a suitable combination thereof. In addition, a patterned photoresist 718 may cover the dielectric hard mask 716 as known in the art.

[0070] Figure 8 A block diagram of an example resistive device etch and pattern removal 800 is depicted. The one or more etching steps may include etching the dielectric hard mask 716, the optional barrier layer / additional layer 714, the top electrode-filament donor layer 612, the second switching layer 512, and the etched first switching layer 408. In some embodiments, the one or more etching steps may also etch the bottom plate layer 206 to form an etched bottom plate 806, although in other embodiments the bottom plate layer 206 is not etched and the optional unetched bottom plate remains as shown. Figure 8 Shown by the dashed line.

[0071] In various embodiments, the resistor device etch and pattern removal 800 may include a first etching process to etch the dielectric hard mask 716 and form an etched dielectric hard mask 816. In one embodiment, the first etching process may stop on the optional barrier / additional layer 714, or one or more barrier / additional layers 714 may be etched to form an etched optional barrier / additional layer 814. In the absence of the optional barrier / additional layer 714, the first etching process may stop on the top electrode-filament donor layer 612. In the case where the first etching process stops on the optional barrier / additional layer(s) 714, a second etching may be utilized to remove the remaining portion of the optional barrier / additional layer 714 and stop on the top electrode-filament donor layer 612.

[0072] In at least one disclosed embodiment, the first etching process can be a plasma etch using a gas selected from the group consisting of C4F8, C4F6, CHF3, CF4, CO, O2, N2 and Ar. Subsequently, an optional photoresist (PR) stripping / post-etch cleaning can be implemented. In one embodiment, the PR strips (removal of patterned photoresist after the first etching process) can utilize O2 ash, O2 / CF4 ash, etc., or a suitable combination of the foregoing. An optional cleaning process can be implemented to remove debris or residues generated by removing the PR strips, or the stopping surface of the dielectric hard mask 816 to be etched, or the subsequent surface of the optional barrier layer / additional layer 714 or the top electrode-filament donor layer 612 for further etching. The optional cleaning process can use dimethyl sulfoxide (DMSO) rinse, EKC rinse, hydrogen fluoride (HF) clean, deionized (DI) water rinse, etc., or a suitable combination of the foregoing.

[0073] After the first etching process and the optional PR stripping / first etching cleaning, a second etching process can be performed to etch the additional material layer. The second etching process can use the etched dielectric hard mask 816 as a mask for the second etching process. The second etching process can optionally etch any remaining optional barrier layer / additional layer 714 (if present) to optionally form an etched optional barrier layer / additional layer 814. Regardless of the optional barrier layer / additional layer 714, the second etching process can etch the top electrode-filament donor layer 612 to form an etched top electrode 812, can etch the second switching layer 510 to form an etched second switching layer 810, and can etch the previously etched first switching layer 408 to form a further etched first switching layer 808. In one embodiment, the second etching process can etch the bottom plate layer 206, or in another embodiment, the third etching process can etch the bottom plate layer 206, or in another embodiment, the bottom plate layer 206 can remain unetched. The second etch may be a plasma etch using a gas selected from the group consisting of Cl2, BCl3, HBr, Ar, N2, He, O2, CHF3, CF4, and SF6. Post-etch cleaning using O2 ash, dilute HF, ultra-dilute HF, EKC cleaning, sulfur peroxide mixture (SPM) rinse, H2O2 rinse, tetramethylammonium hydroxide (TMAH) rinse, DI water rinse, etc., or a suitable combination of the foregoing may be optionally used to complete the second etch process.

[0074] After the resistive device etch and pattern removal 800 is completed, a discrete resistive switching device 820 is formed. The discrete resistive switching device 820 can be configured to have a plurality of resistance states measured between the etched top electrode 812 (or etched hard mask 816, depending on the embodiment) and the bottom electrode 102. The plurality of resistance states include a high resistance state, in which no conductive filament provides electrical continuity between the etched top electrode 812 and the etched bottom plate 806 through the etched second switching layer 810. The plurality of resistance states also include a low resistance state, in which a conductive filament is formed within the etched second switching layer 810 between the etched top electrode 812 and the etched bottom plate 806.

[0075] Fig. 9A block diagram of an example filament 900 of a discrete resistance switching device 820 is depicted. An example conductive filament 920 is shown, which represents an example path of conductive particles from the etched top electrode 812 to the etched bottom plate 806. The filament 920 can be formed by a conductive particle or group of particles from the etched top electrode 812 that drift within the etched second switching layer 810 in response to a suitable stimulus (or stimuli) applied to the discrete resistance switching device 820. Upon forming the filament 920 that establishes sufficient electrical continuity between the etched top electrode 812 and the etched bottom plate 806, the discrete resistance switching device 820 enters a low resistance mode. In response to a second electrical stimulus (e.g., of opposite polarity, or a different field, current, voltage, temperature, etc., or a combination), the electrical filament 920 can deform (e.g., by dispersion of the conductive particles forming the filament or drift of the conductive particles away from the etched base plate 806) sufficiently to disrupt the electrical continuity of the electrical filament 920, causing the discrete resistance switching device 820 to enter a high resistance mode.

[0076] Fig.10 A block diagram of a bottom plate, switching layer, and barrier layer deposition 1000 according to another embodiment of the present disclosure is shown. As disclosed elsewhere herein or known in the art, the bottom electrode 102 is formed within the dielectric layer 104. A bottom plate layer 1006 is formed to cover the bottom electrode 102 and the dielectric layer 104. In some embodiments, one or more optional layers may be formed between the bottom electrode 102 and the dielectric layer 104 and the bottom plate layer 1006. The one or more optional layers may include an adhesion layer, a seed layer, a conductive layer, the like, or a suitable combination. In other embodiments, the bottom plate layer 1006 may be in direct physical contact with the bottom electrode 102 and the dielectric layer 104. A resistive switching layer 1008 is formed to cover the bottom plate layer 1006, and a barrier layer 1010 is formed to cover the resistive switching layer 1008.

[0077] Fig.11 A barrier layer etch 1100 is shown, which forms a gap in barrier layer 1010, exposing the surface of switching layer 1008 to the gap. Barrier layer etch 1100 results in barrier layer 1110 being etched. Fig.12A controlled etch / treatment process 1200 is depicted to form a treated / activated switching segment 1212. The controlled etch / treatment process 1200 can be configured to increase the likelihood of forming conductive filaments within the treated / activated switching segment 1212. In one embodiment, the controlled etch / treatment process 1200 can remove a portion of the switching layer 1008, resulting in a thinner treated / activated switching segment 1212, thereby enhancing the electric field density within the treated / activated switching segment 1212 in response to a voltage. In another embodiment, the controlled etch / treatment process 1200 can increase the permeability of conductive particles within the treated / activated switching segment 1212 compared to the surrounding area of ​​the switching layer 1008 to increase the likelihood of forming filaments within the treated / activated switching segment 1212. For example, improved permeability can be achieved by reducing the density of the treated / etched switching segments 1212, appropriate doping of the treated / etched switching segments 1212 (e.g., with ion donor materials), light particle bombardment of the treated / activated switching segments 1212, etc., or a suitable combination of the above.

[0078] like Fig.13 As shown, a top electrode-filament donor layer 1314 can be deposited on the etched barrier layer 1110. The top electrode-filament donor layer 1314 is in physical contact with the etched barrier layer 1110 and the treated / etched switching segment 1212. As described herein or known in the art, the top electrode-filament donor layer 1314 can be formed of a material that provides conductive particles to the treated / etched switching segment 1212. Fig.14 Shown is the formation of an optional barrier / additional layer 1416, a dielectric hard mask layer 1418, and a patterned photoresist 1420. These layers may be as described in this disclosure, or as known in the art.

[0079] Fig.15 Depicted is a method for Fig.14 15. The resistive device etch and resist removal 1500 may utilize more than two etching steps to form discrete resistive devices 1520 as shown. In particular, the resistive device etch and resist removal 1500 may form an etched dielectric hard mask 1518, an optionally etched barrier layer / additional layer 1516 (if present), an etched top electrode 1514, an etched barrier layer 1510, and an etched resistive switching layer 1508. In some embodiments, the resistive device etch and resist removal 1500 may etch the bottom plate layer 1006 to form an etched bottom plate 1506. In other embodiments, the resistive device etch and resist removal 1500 may stop on the bottom plate layer 1006 and an optional unetched bottom plate may remain, as shown by the dashed lines.

[0080] Fig.16 Depicted is a bottom plate, switching layer, top electrode, and capping layer deposition 1600 according to additional embodiments of the present disclosure. As shown, a bottom plate layer 1606 is disposed overlying the bottom electrode 102 and the dielectric layer 104. In some embodiments, the bottom plate layer 1606 is a conductive material that makes physical contact with the bottom electrode 102 and the dielectric layer 104, while in other embodiments, one or more optional intermediate layers (e.g., adhesion layers, seed layers, conductive layers, diffusion barriers, etc.) may be present.

[0081] As shown, covering the bottom plate layer 1606 is a switching layer 1608, a top electrode layer 1610, and a capping layer 1612. The switching layer 1608 and the top electrode layer 1610 may include materials disclosed in the present specification or known in the art suitable for use as these layers of a resistive switching memory or a selector device. In various embodiments, as described herein, the capping layer 1612 may be a barrier layer. For example, the capping layer 1612 may include a conductive material, such as W metal, TiN, TaN, aluminum material, doped silicon material, or other suitable conductive material, which is used as a diffusion barrier material to reduce or prevent metal diffusion of the top electrode layer 1612 through the capping layer 1612, a passivation material to reduce or prevent contamination of elements (e.g., oxygen, other reactive gases or elements) above the capping layer 1612 from reaching the top electrode layer 1612, an etch stop material for stopping etching of layers above the capping layer 1612, an adhesion layer for adhering materials deposited above the capping layer 1612, etc., or a suitable combination of the foregoing.

[0082] Fig.17 Shown for Fig.16 The resistive device etch 1700 of the deposition stack may include one or more etching steps to form an etched cap layer 1712, an etched top electrode layer 1710, an etched switching layer 1708, and an optional etched bottom plate 1706. In one embodiment, the resistive device etch 1706 stops on the bottom plate layer 1606 and the optional unetched bottom plate remains, such as Fig.17 As shown, discrete resistive switching devices 1720 are produced by resistive device etching 1700, but one of ordinary skill in the art will appreciate that in semiconductor processing, many discrete resistive switching devices 1720 on a die or wafer may be produced by etching a deposition stack.

[0083] refer to Fig.18 , the sidewall passivation process 1800 forms a passivated sidewall 1814 around the periphery or outer area of ​​the etched top electrode layer 1710 and the etched switching layer 1708. In some embodiments, as included in Fig.18 Both the etched top electrode layer 1710 and the etched switching layer 1708 are shown (eg, see below). Fig.18A , 18B 18C), the sidewall passivation 1800 may be limited to the etched switching layer 1708 or to the etched top electrode layer 1710 (eg, see below). Fig.18D , 18E and 18F).

[0084] The sidewall passivation 1800 can create a thickness of material around the outer portion of the etched top electrode layer 1710 or the etched switching layer 1708 that mitigates or avoids the formation of conductive filaments within the passivation sidewalls 1814. The thickness of the material is measured from the outer surface of the discrete resistance switching device 1720 to the depth within the discrete resistance switching device 1720. The depth does not need to be uniform about the device. Nevertheless, because the passivation sidewalls 1814 are confined to the outer / outer portion, the conductive filaments can be (effectively) confined to the center or core region of the discrete resistance switching device 1720.

[0085] Fig.18A , 18B 18 and 18C show a first embodiment 1800A of sidewall passivation. Fig.18A Depicted is a chemical etch for resistive device etching 1700, which is suitable for forming etch cracks / voids / byproducts 1802A within the etched top electrode layer 1710 and the outer portion of the etched switching layer 1708. In some embodiments, the depth of the etch cracks / voids / byproducts 1802A can be at least and can be larger in other embodiments. In various embodiments, the chemical etch used to create the etch cracks / voids / byproducts 1802A can be a wet chemical etch or a plasma etch using a liquid / gas such as Cl2, BCl3, HBr, or CHF3. In one embodiment, an optional post-etch clean (which can include a non-reactive or minimally reactive wet clean, such as an ultra-dilute HF clean, an EKC clean, an SPM rinse, an H2O2 rinse, a deionized water rinse, etc., or a suitable combination) can be used to remove some of the etch byproducts from the etch cracks / voids / byproducts 1802A. Fig.18B An oxidation process 1802B is shown for oxidizing the material to a value greater than 100 Å in the etched top electrode layer 1710 and the etched switching layer 1708. The depth of Fig. 18C The high resistance oxide shell 1814C is shown. Compared to the switching layer core 1812C, the high resistance oxide shell 1814C will have a relatively low electric field in response to the voltage applied to the discrete resistance switching device 1720. This localizes the formation of filaments within the switching layer core 1812C and mitigates or avoids the formation of conductive filaments within the high resistance oxide shell 1814C.

[0086] In various embodiments, the etched top electrode layer 1710 can be an aluminum-nitrogen material, such as a non-stoichiometric aluminum-nitrogen-rich material or a non-stoichiometric aluminum-oxygen-rich material. Alternatively or additionally, in some embodiments, the etched switching layer 1708 can be a non-stoichiometric aluminum-nitrogen-rich material or a non-stoichiometric aluminum-oxygen-rich material. Because aluminum tends to oxidize in a self-limiting manner known as anodization, it is difficult to significantly oxidize aluminum to a low temperature in an aluminum-containing material. Therefore, the chemical / plasma etch used to form the etch cracks / voids / byproducts 1802A is selected to achieve voids and cracks greater than Depth, so that the oxidation treatment 1802B reaches more than In various embodiments, the oxidation treatment 1802B may be high temperature oxygen (e.g., 140 to 270 degrees Celsius, or up to 350 degrees Celsius or any suitable value or range between 140 and 350 degrees Celsius), or oxygen plasma or O2 ash.

[0087] By achieving greater than Oxygen permeation can be greater than This in turn confines the switching layer core 1812C to less than the width of the etched switching layer 1708 and the etched top electrode layer 1710. Although aluminum metal has a physically self-limiting anodic oxidation property, it is believed that the first embodiment 1800A of the sidewall passivation can achieve a passivation effect unknown to conventional aluminum-containing materials.

[0088] Fig.18D , 18E 18 and 18F depict a second embodiment 1800B of sidewall passivation according to further embodiments of the present disclosure. Fig.17 After the resistor device etch 1700 is shown, a highly selective etch 1802D may be performed on the discrete resistor switching device 1720. The highly selective etch 1802D may be selective to the material of the etched top electrode layer 1710, removing up to greater than 1802D to form a double etched filament donor 1810D that defines the central core of the discrete resistive switching device 1720. Subsequently, a high resistance conformal oxide deposition 1804F is performed to conformally fill the outer portion of the etched top electrode layer 1710 removed by the high selective etching 1802D. In one embodiment, the conformal oxide deposition 1804F can be an atomic layer deposition (ALD) oxide deposition. In addition, the oxide deposition 1804F covers the peripheral surface of the discrete resistive switching device 1720, the top surface of the etched cap layer 1712, and the top surface of the dielectric layer 104 (or the bottom plate 1606). The conformal oxide deposition 1804F has a high resistance, minimizing the current and electric field therein, thereby mitigating or avoiding the formation of conductive filaments within the conformal oxide deposition 1804F. As a result of the second embodiment 1800B of the sidewall passivation, this effectively confines the filaments to the switching layer core 1810D.

[0089] In one embodiment, the highly selective etching 1802D may include very dilute ammonium hydroxide or very dilute TMAH. In one embodiment, the dilution ratio may be greater than about 8000 parts of ammonium hydroxide or TMAH to a solvent (e.g., water). In another embodiment, the dilution ratio may be in the range of about 10000:1 ammonium hydroxide or TMAH to a solvent to about 14000:1 ammonium hydroxide or TMAH to a solvent. In another embodiment, the etched top electrode layer 1710 may be a non-stoichiometric aluminum-nitrogen-rich material (e.g., formed using a PVD process). In another embodiment, the etched switching layer 1708 may be a stoichiometric or non-stoichiometric aluminum oxide material (e.g., formed using a PVD process) that resists highly selective etching 1802D with very dilute ammonium hydroxide or TMAH. In another embodiment, the etched capping layer 1712 or the etched bottom plate 1706 may be a Ti or W metal or other conductive material that is suitably resistant to highly selective etching 1802D.

[0090] The figures included herein are described with respect to several components, layers, and materials of a resistive switching device or a die or wafer including many resistive switching devices. It should be understood that such figures may include those components, layers, and materials specified therein, portions of those components, layers, and materials specified, or additional components / layers / materials that are not explicitly depicted but are known in the art or reasonably communicated to a person skilled in the art in the context provided herein. Sublayers may also be implemented as adjacent other sublayers within the depicted layer. In addition, it should be noted that one or more disclosed processes may be combined into a single process that provides a polymeric function. For example, a deposition process may include an etching process, or vice versa, to facilitate deposition and etching of components of an integrated circuit device by a single process. The components of the disclosed architecture may also interact with one or more other components that are not specifically described herein but are known to a person skilled in the art.

[0091] In view of the above exemplary figures, refer to Figure 19-21 The process methods that can be implemented according to the disclosed subject matter will be better understood by referring to the flow chart of FIG. Figure 19-21 The methods are shown and described as a series of blocks, but it is understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in a different order and / or concurrently with other blocks depicted and described herein. In addition, not all of the illustrated blocks may be required to implement the methods described herein, and in some embodiments, additional steps that are known in the art or reasonably conveyed to one of ordinary skill in the art through the context provided herein are also considered to be within the scope of the present disclosure. In addition, some steps shown as part of one process may be implemented in another process as appropriate (e.g., Fig.14 The optional barrier / additional layers, dielectric hardmask, and patterned photoresist shown in FIG. 1 may be used in other processes disclosed herein (e.g., covering Fig.16 Deposition); within the scope of the present disclosure, other steps of one or more processes may be added or substituted for other processes disclosed herein). In addition, it should be further understood that the methods disclosed throughout this specification can be stored on an article to facilitate the transmission and transfer of these methods to electronic devices. The term article used is intended to encompass a computer program accessible from any computer-readable device, device in combination with a carrier, or storage medium.

[0092] refer to Fig.19, depicts a flow chart of an example method 1900 for fabricating a resistive memory device according to one or more embodiments of the present disclosure. At 1902, method 1900 may include forming a conductive layer over a bottom electrode and a dielectric layer. In one embodiment, the conductive layer may be a metal layer (e.g., W metal), a conductive metal compound (e.g., a metal nitride such as TiN, TaN, etc.), or other suitable conductive material. In some embodiments, the conductive layer is in physical contact with the bottom electrode or the dielectric layer; while in other embodiments, one or more intermediate layers may be located therebetween (e.g., an adhesion layer, a seed layer, a passivation layer, a diffusion barrier layer, an ion conducting layer, etc., or a suitable combination).

[0093] At 1904, method 1900 may include forming a first switching layer overlying the conductive layer. In one or more embodiments, the first switching layer may be in physical contact with the conductive layer. The first switching layer may be formed to have a thickness of about Peace In addition, the first switching layer may be formed of a resistive material. In various embodiments, the first switching layer may include a resistive metal-nitrogen material or a resistive metal-oxygen material. In one embodiment, the first switching layer may be formed as a relatively molecularly dense layer (compared to the second switching layer; see below) that resists permeability within the first switching layer of conductive particles of the resistive memory device. In at least one embodiment, the first switching layer may be a stoichiometric metal oxide material (e.g., AlO) formed by an ALD process. x wait).

[0094] At 1906, method 1900 may include etching a gap in the first switching layer to form an etched first switching layer. Etching the gap may include removing a thickness of the first switching layer. In one embodiment, etching the gap may include removing the entire thickness of the first switching layer in a portion of the first switching layer, exposing the top surface of the conductive layer to the gap. In another embodiment, etching the gap may include retaining a thin layer (e.g., a few angstroms to a few nanometers) of the first switching layer to cover the top surface of the conductive layer in the gap. In yet another embodiment, etching the gap may include retaining only very thin islands (e.g., a few angstroms thick) of the first switching layer such that portions of the top surface of the conductive layer are exposed to the gap not covered by the very thin islands of the first switching layer. Examples of materials for the first switching layer include SiOx, amorphous Si, Si, TiO x 、AlO x , HfO x 、NiO x 、TaO x 、NbO x 、ZnO2、ZrO x , GdO x , Nitrogen metals (e.g., AlNx ), etc., or a suitable combination of the foregoing.

[0095] At 1908, method 1900 may include depositing a second switching layer over the gap and the first switching layer, forming a second gap in the second switching layer. The second switching layer may have a thickness of about Peace In one or more embodiments, the second switching layer may include a metal-oxygen material or a metal-nitrogen material. In one or more embodiments, the second switching layer may include the same material as the first switching layer, while in other embodiments, the second switching layer may be a different material than the first switching layer (e.g., a material different from the list provided above for the first switching material, or a completely different material in at least one embodiment). In at least one embodiment, the second switching layer may be formed of the same material as the first switching layer, but using a different deposition process resulting in a different relative atomic concentration of the same material. As an example, the second switching layer may be a non-stoichiometric AlO produced using a PVD process. y material, wherein y is a suitable non-stoichiometric relative concentration of oxygen atoms to aluminum atoms, and the first switching layer may be a stoichiometric AlO produced by an ALD process x material, where x is a suitable stoichiometric relative concentration of oxygen atoms to aluminum atoms. In one or more embodiments, the first switching layer or the second switching layer may be further doped with from about 0.5% to about 1.0% Si atoms by atomic percentage, or any suitable value or range therebetween. In one embodiment, the second switching layer is in direct physical contact with the top surface of the conductive layer exposed to the gap, but in other embodiments, a thin layer of the first switching layer (or a non-continuous island thereof) may remain between the second switching layer and the top surface of the conductive layer.

[0096] At 1910, method 1900 may include forming a top electrode-filament donor layer above the second switching layer, and filling the second gap. The top electrode-filament donor layer may include conductive particles that are at least partially permeable within the second switching layer. In one embodiment, the permeability of the conductive particles within the first switching layer is low (e.g., due to an increased density of stoichiometric materials for the first switching layer). In one or more embodiments, the top electrode-filament donor layer may be selected from materials that include (in one embodiment) or do not include (in another embodiment) the following: Al, non-stoichiometric AlN x , stoichiometric or non-stoichiometric AlNO x , TiN, Ti, W, etc., or appropriate combinations of the foregoing.

[0097] At 1912, method 1900 may include forming an optional barrier layer and forming a hard mask layer and a patterned photoresist above the top electrode-filament donor layer. The optional barrier layer may be a TiN, TaN, W or Ti material. The hard mask layer may be composed of SiO2, SiN, SiC, SiON, amorphous carbon, etc., or a suitable combination of the foregoing. At 1914, method 1900 may include etching a discrete resistance switching device and removing the patterned photoresist. The discrete resistance switching device produced by etching may include an etched hard mask, an optionally etched optional barrier layer, an etched top electrode-filament donor, an etched second switching layer, and a further etched first switching layer. In one embodiment, the conductive layer may also be etched as part of the discrete resistance switching device to form an etched conductive layer, but in other embodiments, the etching of the discrete resistance switching device may stop on the conductive layer.

[0098] In some embodiments, etching a discrete resistive switching device may include a two-etch process that etches a hard mask layer and forms an etched hard mask by a first etching process. Depending on the embodiment, the first etching process may stop on an optional barrier layer (if present) or may stop on a top electrode-filament donor layer. The second etching process of the two-etch process may form an etched top electrode-filament donor, an etched second switching layer, and a further etched first switching layer. In one embodiment, the second etching process may also form an etched conductive layer. In at least one embodiment, the second etching process that forms the etched top electrode-filament donor, the etched second switching layer, and the further etched first switching layer may include BCl3 or HBr wet etching chemicals.

[0099] In an alternative embodiment, etching a discrete resistive switching device may include a three-step process. The first etching step of the three-step process may etch the hard mask layer (and all of the optional barrier layer (if present) or a portion of the optional barrier layer). The second etching step may etch any remaining portion of the optional barrier layer (if present), as well as the top electrode-filament donor, the second switching layer, and the etched first switching layer. Then, the third etching of the three-step etching process may etch the conductive layer to form an etched conductive layer.

[0100] Fig. 20A flow chart of an example method 2000 for forming a resistive switching device according to an alternative or additional embodiment of the present disclosure is shown. At 2002, method 2000 may include forming a conductive layer covering a bottom electrode and a dielectric layer of a semiconductor device. In one embodiment, the conductive layer may be a conductive metal layer (e.g., W metal, Ti metal, or other suitable conductive metal). In various embodiments, the bottom electrode and the dielectric layer cover a substrate of the semiconductor device, and in at least one embodiment, the dielectric layer may be formed on a top surface of the substrate. In some embodiments, the conductive layer is in physical contact with the bottom electrode and the dielectric layer; while in other embodiments, one or more intermediate layers are disposed therebetween. Example intermediate layers may include an adhesion layer, a seed layer, a conductive layer, an ion conducting layer, a diffusion barrier layer, a passivation layer, etc., or a suitable combination of the foregoing.

[0101] At 2004, method 2000 may include forming a switching layer overlying the conductive layer. In various embodiments, the switching layer may have a first thickness and may include a resistance switching material that is at least partially permeable to conductive particles. In further embodiments, the switching layer may be in physical contact with the conductive layer, but in some embodiments, one or more intermediate layers may be present. At 2006, method 2000 may include forming a barrier layer overlying the switching layer. In one or more embodiments, the barrier layer may include a material within the barrier layer that resists penetration of conductive particles.

[0102] At 2008, method 2000 may include etching a gap in the barrier layer, exposing a portion of the switching layer to the gap. At 2010, method 2000 may include treating or controlling the etching of the portion of the switching layer exposed to the gap. In one or more embodiments, treating or controlling the etching may include etching the portion of the switching layer exposed to the gap in the barrier layer with a second etch, and causing the portion of the switching layer to have a second thickness less than the first thickness of the switching layer.

[0103] At 2012, method 2000 may include forming a top electrode covering the barrier layer and the treated switching layer. In one embodiment, the top electrode may be in physical contact with the barrier layer and with a portion of the resistance switching layer. In addition, the top electrode may be selected from a material that includes conductive particles and provides the conductive particles to the portion of the resistance switching layer in response to an electrical stimulus. At 2014, method 2000 may include etching a discrete resistance switching device including the top electrode, the barrier layer, and the switching layer using a third etch.

[0104] In at least one embodiment, the third etch further comprises etching the conductive metal layer when forming the discrete resistance switching device. In another embodiment, the method 2000 may further comprise forming a hard mask layer covering the top electrode. In such an embodiment, etching with the third etch may further comprise etching the hard mask layer when forming the discrete resistance switching device.

[0105] In further embodiments, method 2000 may include performing a cleaning process after the second etch. The cleaning process may be directed to the portion of the switching layer etched with the second etch. For example, the second etch and cleaning process may at least partially utilize a blocking material for the mask. In various embodiments, the cleaning process may include oxygen plasma or argon sputtering, and may further include removing etchant byproducts produced by the second etch from the top surface of the portion of the switching layer.

[0106] refer to Fig.21 , which depicts a method 2100 for manufacturing a resistive switching device according to yet another embodiment of the present disclosure. At 2102, the method 2100 may include forming a conductive layer above a bottom electrode within a dielectric layer located in a semiconductor substrate. At 2104, the method 2100 may include forming a switching layer covering the conductive layer and in physical contact with the conductive layer. In one or more embodiments, the switching layer may include a resistive material that is at least partially permeable to conductive particles. In addition, at 2106, the method 2100 may include forming a top electrode layer covering the switching layer and in physical contact with the switching layer. The top electrode may include a material that provides conductive particles that drift into the switching layer in response to an electrical stimulus applied to the bottom electrode and the top electrode.

[0107] At 2108, method 2100 may include forming a capping layer covering the top electrode layer. At 2110, method 2100 may include etching the capping layer, the top electrode layer, and the switching layer to form a discrete resistive switching device. In one or more embodiments, etching may include chemically etching at least the switching layer to produce a wet etched portion of the etched switching layer. At 2112, method 2100 may include passivating the periphery of the etched switching layer or the etched top electrode layer to a certain depth within the resistive switching device and forming a passivation shell around the core of the resistive switching device. In one embodiment, the passivation shell may have a higher resistance than the resistive material of the switching layer. In another embodiment, the passivation shell may have a lower permeability to conductive particles of the top electrode layer than the resistive material of the switching layer. In yet another embodiment, the passivation shell may have a higher resistance than the resistive material of the switching layer and have a lower permeability to conductive particles.

[0108] In at least one embodiment, passivating the perimeter of the etched switching layer may further include, after chemically etching at least the wet etched portion of the switching layer, oxidizing the perimeter of the etched switching layer to a value greater than of depth (from the periphery inwardly toward the core of the resistive switching device) to form a passivation shell. In one or more embodiments, the oxidized periphery can form a material for the passivation shell, the oxygen atomic weight of which is higher than the oxygen atomic weight of the resistive material. In further embodiments, the resistive material of the switching layer is an aluminum oxide material, and chemical etching of at least the wet etched portion of the switching layer forms porous voids within the aluminum oxide material from the periphery inwardly toward the core of the etched switching layer. In other embodiments, the oxidized periphery can further include using O2 ash, oxygen plasma, or a high temperature oxygen flow to promote oxidation of the periphery of the aluminum oxide material of the switching layer to greater than In one embodiment, the O2 ash, oxygen plasma, or high temperature oxygen flow may be implemented at a temperature of about 140 degrees Celsius to about 350 degrees Celsius, or any suitable value or range therebetween. In one or more embodiments, the oxidation further produces oxygen-rich aluminum oxide for the passivation shell, the atomic weight of oxygen of which is higher than the atomic weight of the resistive material.

[0109] In alternative or additional embodiments, method 2000 may include passivating the perimeter of the etched switching layer, and may further include, after chemically etching at least the wet etched portion of the switching layer, selectively removing the top electrode layer to a depth within the resistive switching device by selectively etching the top electrode layer with an etchant that etches the top electrode layer much faster than the switching layer. In addition, method 2000 may include conformally depositing a stoichiometric ALD oxide dielectric material on an exposed surface of the resistive switching device exposed by etching to form a discrete resistive switching device and exposed by selectively etching the top electrode layer to a depth within the resistive switching device. In one or more embodiments, the passivation shell is formed by an ALD oxide dielectric material of a core of a top electrode layer surrounding a material including the top electrode layer. In various additional embodiments, the top electrode layer material may be a non-stoichiometric aluminum-nitrogen material AlN formed by a PVD process. x The switching layer can be a non-stoichiometric aluminum-oxygen material AlO formed by a PVD process. y , or the etchant that selectively etches the top electrode layer is diluted ammonium hydroxide or diluted TMAH. In at least one embodiment, the diluted TMAH or diluted ammonium hydroxide can be diluted to a range of about 8000 parts of diluent to 1 part of TMAH or ammonium hydroxide to about 14000 parts of diluent to 1 part of TMAH or ammonium hydroxide, or any suitable value or range therebetween.

[0110] Example operating environment

[0111] Fig. 22A block diagram of an example operation and control environment 2200 for a memory array 2202 for a memory cell array according to various aspects of the subject disclosure is shown. In some embodiments, the control environment 2200 and the memory array 2202 can be formed within a single semiconductor die, but the disclosure is not limited thereto, and in other embodiments, some components of the control environment 2200 can be formed on separate semiconductor dies. In at least one aspect of the subject disclosure, the memory array 2202 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 2202 may include a two-terminal storage technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal storage technologies may include resistive switching memory, conductive bridging memory, phase change memory, organic memory, magnetoresistive memory, etc., or a suitable combination of the foregoing. In a further embodiment, the two-terminal storage technology may be a resistive storage technology formed by the process disclosed herein.

[0112] The column controller 2206 and the sense amplifier 2208 may be formed adjacent to the memory array 2202. In addition, the column controller 2206 may be configured to activate (or identify activation of) a subset of the bit lines of the memory array 2202. The column controller 2206 may utilize control signals provided by the reference and control signal generator 2218 to activate and operate on corresponding bit lines in the subset of bit lines, applying appropriate programming, erasing, or reading voltages to these bit lines. Inactivated bit lines may be maintained at an inhibit voltage (also applied by the reference and control signal generator 2218) to mitigate or avoid bit disturbance effects on these inactivated bit lines.

[0113] Additionally, the operating and control environment 2200 may include a row controller 2204. The row controller 2204 may be formed adjacent to and electrically connected to the word lines of the memory array 2202. Additionally, the row controller 2204 may select memory cells of a particular row with an appropriate select voltage using control signals from the reference and control signal generator 2218. Furthermore, the row controller 2204 may facilitate programming, erasing, or reading operations by applying an appropriate voltage on the selected word line.

[0114] The sense amplifier 2208 may read data from or write data to an activated memory cell of the memory array 2202 selected by the column control 2206 and the row control 2204. The data read from the memory array 2202 may be provided to the input / output buffer 2212. Likewise, the data to be written to the memory array 2202 may be received from the input / output buffer 2212 and written to the activated memory cell of the memory array 2202.

[0115] The clock source 2210 can provide individual clock pulses to facilitate the timing of read, write, and programming operations of the row controller 2204 and the column controller 2206. The clock source 2210 can further facilitate the selection of word lines or bit lines in response to external or internal commands received by the operating and control environment 2200. The input / output buffer 2212 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided via the command and address inputs, and data to be written to the memory array 2202 and data to be read from the memory array 2202 are transmitted on the bidirectional data inputs and outputs, facilitating connection to an external host device, such as a computer or other processing device (not depicted, but see, for example, below). Fig.23 computer 2302).

[0116] The input / output buffer 2212 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, receive address data and command data, and address data for each instruction. The address data may be transmitted to the row controller 2204 and the column controller 2206 via the address register 2214. In addition, the input data is transmitted to the memory array 2202 via the signal input line between the sense amplifier 2208 and the input / output buffer 2212, and the output data is received from the memory array 2202 via the signal output line from the sense amplifier 2208 to the input / output buffer 2212. The input data may be received from the host device, and the output data may be transmitted to the host device via the I / O bus.

[0117] The command received from the host device may be provided to the command interface 2216. The command interface 2216 may be configured to receive an external control signal from the host device and determine whether the data input to the input / output buffer 2212 is write data, a command, or an address. The input command may be transmitted to the state machine 2220.

[0118] The state machine 2220 can be configured to manage the programming and reprogramming of the memory array 2202 (and other memory banks of the multiple memory arrays). The instructions provided to the state machine 2220 are implemented according to the control logic configuration, enabling the state machine 2220 to manage reading, writing, erasing, data input, data output, and other functions associated with the memory cell array 2202. In some aspects, the state machine 2220 can send and receive confirmations and negative confirmations regarding the successful receipt or execution of various commands. In further embodiments, the state machine 2220 can decode and implement state-related commands, decode and implement configuration commands, etc.

[0119] To implement functions such as read, write, erase, input, output, etc., the state machine 2220 can control the clock source 2210 or the reference and control signal generator 2218. Control of the clock source 2210 can cause output pulses configured to facilitate the row controller 2204 and the column controller 2206 to implement specific functions. The output pulses can be transmitted to a selected bit line, for example, through the column controller 2206, or to a word line, for example, through the row controller 2204.

[0120] Combination Fig.23 , the systems, devices, and / or processes described herein may be implemented in hardware such as a single integrated circuit (IC) chip, multiple ICs, an application specific integrated circuit (ASIC), etc. In addition, the order in which some or all of the process boxes appear in each process should not be considered limiting. On the contrary, it should be understood that some process boxes may be performed in a variety of orders, not all of which are explicitly described herein.

[0121] refer to Fig.23 , a suitable environment 2300 for implementing various aspects of the claimed subject matter includes a computer 2302. The computer 2302 includes a processing unit 2304, a system memory 2310, a codec 2314, and a system bus 2308. The system bus 2308 couples system components including, but not limited to, the system memory 2310 to the processing unit 2304. The processing unit 2304 can be any of a variety of available processors. Dual microprocessors and other multi-processor architectures can also be used as the processing unit 2304.

[0122] The system bus 2308 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), card bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), FireWire (IEEE1394) and Small Computer System Interface (SCSI).

[0123] The system memory 2310 includes a volatile memory 2310A and a non-volatile memory 2310B. A basic input / output system (BIOS) (basic routines for transferring information between elements within the computer 2302, such as during startup) is stored in the non-volatile memory 2310B. In addition, according to the present invention, the codec 2314 may include at least one of an encoder or a decoder, wherein at least one of the encoder or the decoder may be composed of hardware, software, or a combination of hardware and software. Although the codec 2314 is depicted as a separate component, the codec 2314 may be included in the non-volatile memory 2310B. As an illustration and not limitation, the non-volatile memory 2310B may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory, a two-terminal memory, etc. The volatile memory 2310A includes a random access memory (RAM), and in some embodiments, may be implemented as a cache memory. By way of illustration and not limitation, RAM comes in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0124] The computer 2302 may also include removable / non-removable, volatile / non-volatile computer storage media. As an example, Fig.23Disk storage 2306 is shown. Disk storage 2306 includes, but is not limited to, devices such as disk drives, solid state disks (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. In addition, disk storage 2306 may include storage media alone or in combination with other storage media, including but not limited to compact disk drives (CD-ROMs), CD recordable drives (CD-R Drives), CD rewritable drives (CD-RW Drives), or digital versatile disk ROM drives (DVD-ROMs) such as high-density disk system storage. In order to facilitate the connection of disk storage 2306 to system bus 2308, removable or non-removable interfaces, such as storage interface 2312, are generally used. It is understood that storage 2306 can store information related to the user. Such information can be stored in or provided to a server or provided to an application running on a user device. In one embodiment, the user can be notified (e.g., through output device 2332) of the type of information stored in disk storage 2306 or transmitted to a server or application. The user may be provided an opportunity to opt-in or opt-out of such information being collected and / or shared with servers or applications (eg, via input from input device 2342).

[0125] It should be understood that Fig.23 Software is described that acts as an intermediary between the user and basic computer resources described in a suitable operating environment 2300. Such software includes an operating system 2306A. The operating system 2306A, which may be stored on disk storage 2306, is used to control and allocate the resources of the computer system 2302. Applications 2306C utilize the management of resources by the operating system 2306A through program modules 2306D, and program data 2306D stored in system memory 2310 or on disk storage 2306, such as startup / shutdown transaction tables, etc. It should be understood that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

[0126] The user inputs commands or information to the computer 2302 through input devices 2342. Input devices 2342 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game controller, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to the processing unit 2304 through the system bus 2308 via input ports 2340. Input ports 2340 include, for example, serial ports, parallel ports, game ports, and universal serial buses (USB). Output devices 2332 use some of the same types of ports as input devices 2342. Thus, for example, a USB port can be used to provide input to the computer 2302 and output information from the computer 2302 to the output device 2332. Output adapters 2330 are provided to illustrate that there are some output devices 2332 that require special adapters, such as monitors, speakers, and printers, among other output devices 2332. By way of illustration and not limitation, output adapters 2330 include video and sound cards that provide a means of connection between output devices 2332 and system bus 2308. It should be noted that other devices and / or device systems provide both input and output capabilities, such as remote computer 2338.

[0127] Computer 2302 can operate in a network environment using a logical connection with one or more remote computers (e.g., remote computer 2324). Remote computer 2324 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer device, smart phone, tablet computer or other network node, and generally includes many elements related to computer 2302. For the sake of simplicity, only memory storage device 2326 is shown with remote computer 2324. Remote computer 2324 is logically connected to computer 2302 through network 2322 and then connected through communication interface 2320. Network 2322 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs) and cellular networks. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks such as integrated services digital networks (ISDN) and their variants, packet switching networks, and digital subscriber lines (DSL).

[0128] The communication interface 2320 refers to the hardware / software used to connect the network 2322 to the bus 2308. Although the communication interface 2320 is shown as being internal to the computer 2302 for clarity of illustration, it may also be external to the computer 2302. The hardware / software required to connect to the network 2322 includes (for example purposes only) internal and external technologies such as modems (including conventional telephone grade modems, cable modems, and DSL modems), ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

[0129] The illustrated aspects of the present disclosure may also be practiced in a distributed computing environment, where certain tasks are performed by remote processing devices linked by a communications network. In a distributed computing environment, program modules or stored information, instructions, etc. may be located in local or remote memory storage devices.

[0130] In addition, it should be understood that the various components described herein may include circuits that may include components and circuit elements of appropriate values ​​to implement the embodiments disclosed in this topic. In addition, it should be understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a group of components may be implemented in a single IC chip. In other embodiments, one or more corresponding components may be manufactured or implemented on a separate IC chip.

[0131] With respect to the various functions performed by the above-described components, architectures, circuits, processes, etc., the terms used to describe these components (including references to "means") are intended to correspond to, unless otherwise specified, any components (e.g., functional equivalents) that perform the specified functions of the described components, even if not structurally equivalent to the disclosed structures, which perform the functions in the exemplary aspects of the embodiments shown herein. In this regard, it will also be recognized that the embodiments include systems and computer-readable media having computer-executable instructions for performing the actions and / or events of the various processes.

[0132] Furthermore, while a particular feature may be disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments as may be desirable and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes" and "comprising" and variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "comprising".

[0133] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from the context to direct to a singular form.

[0134] After reading this disclosure, one of ordinary skill in the art may envision further embodiments. For example, in various embodiments, erase operations may be initiated on multiple ReRAM devices (eg, 16, 32, etc.) simultaneously.

[0135] In other embodiments, combinations or sub-combinations of the above disclosed embodiments may be advantageously performed. For ease of understanding, the block diagrams and flow charts of the architecture are grouped. However, it should be understood that combinations of frames, additions of new frames, rearrangements of frames, etc. are contemplated in alternative embodiments of the present disclosure.

[0136] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes thereto will be suggested to those skilled in the art, and that the modifications or changes will be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A method for manufacturing a resistance switching device, comprising: providing a bottom electrode formed within a dielectric material overlying a substrate of the device; forming a conductive layer covering the bottom electrode and the dielectric layer and contacting the bottom electrode and the dielectric layer; forming a first resistance switching layer covering the conductive layer, wherein the first resistance switching layer is a resistive material; etching a gap in the first resistance-switching layer and exposing a portion of the conductive layer to the gap; depositing a second resistance-switching layer to create a second gap in the second resistance-switching layer, wherein the second resistance-switching layer conformally covers the first resistance-switching layer and a portion of the conductive layer exposed by the gap, wherein the second resistance-switching layer is configured to allow diffusion of conductive particles within the second resistance-switching layer; forming a top electrode covering the second resistance-switching layer and filling the second gap, wherein the top electrode includes the conductive particles and provides the conductive particles for diffusion within the second resistance-switching layer in response to an electrical stimulus applied to the resistance-switching device; forming an optional barrier layer overlying the top electrode and a hard mask material overlying the top electrode and optionally overlying the optional barrier layer; forming a resist covering the hard mask material and patterning the resist; as well as The hard mask, the optional barrier layer, the top electrode, the second resistance-switching layer, and the first resistance-switching layer are etched to form a discrete resistance-switching device.

2. The method according to claim 1, wherein: The first resistance-switching layer and the second resistance-switching layer are both formed of the resistance material.

3. The method according to claim 2, wherein: The resistor material is a metal-oxygen material or a metal-nitrogen material.

4. The method according to claim 3, wherein: The resistive material is an aluminum-oxygen material, and wherein forming the first resistive switching layer further comprises utilizing atomic layer deposition, wherein the atomic layer deposition produces a stoichiometric aluminum oxide material or a substantially stoichiometric aluminum oxide material for the first resistive switching layer, and wherein depositing the second resistive switching layer further comprises utilizing physical vapor deposition, i.e., PVD, wherein the physical vapor deposition produces a non-stoichiometric aluminum-oxygen material AlOx for the second resistive switching layer.

5. The method according to claim 3, wherein: The conductive layer is a W metal that makes physical contact with the metal-oxygen material or the metal-nitrogen material of the first resistance-switching layer, and makes physical contact with the second resistance-switching layer at the portion of the conductive layer exposed by the gap.

6. The method according to claim 1, wherein: The optional barrier layer is formed of a material including W, Ti, TiN or TaN.

7. The method according to claim 1, wherein: The etching further includes etching at least the top electrode, the second resistance-switching layer, and the first resistance-switching layer using a BCl 3 or HBr wet etch chemistry.

8. The method according to claim 1, wherein: The thickness of the first resistance switching layer is to and the second thickness of the second resistance switching layer is within the range of to within the range.

9. A method of forming a resistance switching device, comprising: forming a conductive metal layer, wherein the conductive metal layer covers and makes physical contact with a bottom electrode and a dielectric layer where the bottom electrode is located, wherein the bottom electrode and the dielectric layer cover a substrate; forming a switching layer having a first thickness over the conductive metal layer, wherein the switching layer comprises a resistance-switching material that is at least partially permeable to conductive particles; forming a barrier layer covering the switching layer, the barrier layer blocking the permeability of the conductive particles in the barrier layer; etching a gap in the barrier layer and exposing a portion of the switching layer to the gap; etching the portion of the switching layer exposed to the gap in the barrier layer with a second etch and causing the portion of the switching layer to have a second thickness less than the first thickness of the switching layer; forming a top electrode overlying and contacting the barrier layer and the portion of the resistance switching layer; as well as The top electrode, the barrier layer, and the switching layer are etched with a third etch to form a discrete resistive switching device.

10. The method according to claim 9, wherein: The third etch also includes etching the conductive metal layer while forming the discrete resistance switching device.

11. The method according to claim 10, wherein: The conductive metal layer includes tungsten (W) metal.

12. The method of claim 9, further comprising forming a hard mask layer overlying the top electrode, and wherein etching with the third etch further comprises etching the hard mask layer while forming the discrete resistive switching device.

13. The method of claim 9 , further comprising performing a cleaning process on the portion of the switching layer etched by the second etch, the cleaning process comprising oxygen plasma sputtering or argon sputtering, and further comprising removing etchant byproducts produced by the second etch from a top surface of the portion of the switching layer as part of the cleaning process.

14. The method according to claim 13, wherein: The second etch and the cleaning process utilize, at least in part, a barrier material for masking.

15. A method for manufacturing a resistance switching device, comprising: forming a conductive layer over a bottom electrode within a dielectric layer of a semiconductor substrate; forming a switching layer overlying and in physical contact with the conductive layer, wherein the switching layer comprises a resistive material that is at least partially permeable to conductive particles; forming a top electrode layer overlying and in physical contact with the switching layer, wherein the top electrode layer provides the conductive particles to drift into the switching layer in response to an electrical stimulus applied to the bottom electrode and the top electrode layer; forming a covering layer covering the top electrode layer; etching the capping layer, the top electrode layer, and the switching layer to form a discrete resistive switching device, wherein the etching comprises at least chemically etching the switching layer to produce an etched wet etched portion of the switching layer; as well as Passivating the periphery of the etched switching layer or the periphery of the etched top electrode layer to a certain depth within the resistive switching device and forming a passivation shell around the core of the resistive switching device, wherein the passivation shell has one or more of the following: higher than the resistance of the resistive material of the switching layer, lower permeability to said conductive particles than to said resistive material of said switching layer; or Both a higher resistance than the resistive material of the switching layer, and a lower permeability to the conductive particles than the resistive material of the switching layer.

16. The method according to claim 15, wherein: Passivating the perimeter of the etched switching layer further comprises, after chemically etching at least the wet etched portion of the switching layer, oxidizing the perimeter of the etched switching layer from the perimeter inwardly toward the core of the resistive switching device to a depth greater than 100°. to form the passivation shell, and wherein the periphery is oxidized to form a material for the passivation shell, wherein the material for the passivation shell has a higher oxygen atomic weight than the resistive material.

17. The method according to claim 16, wherein: The resistive material of the switching layer is an aluminum oxide material, and wherein chemically etching at least the wet etched portion of the switching layer forms porous voids in the aluminum oxide material from the periphery inwardly toward the core of the etched switching layer, and wherein oxidizing the periphery further comprises using O2 ash, oxygen plasma, or high temperature oxygen flow to promote oxidation of the periphery of the aluminum oxide material of the switching layer to a temperature greater than 100°. and produce an oxygen-rich aluminum oxide for the passivation shell, wherein the oxygen-rich aluminum oxide of the passivation shell has a higher oxygen atomic weight than the resistor material.

18. The method according to claim 15, wherein: Passivating the perimeter of the etched switching layer further comprises, after chemically etching at least the wet etched portion of the switching layer, selectively etching the top electrode layer to the depth within the resistive switching device with an etchant to selectively remove the top electrode layer to the depth within the resistive switching device, wherein the etchant etches the top electrode layer much faster than it etches the switching layer; as well as A stoichiometric ALD oxide dielectric material is conformally deposited above the exposed surface of the resistance switching device, wherein the passivation shell is formed by the ALD oxide dielectric material surrounding a core of the top electrode layer including material of the top electrode layer, wherein the exposed surface of the resistance switching device is exposed by etching to form the discrete resistance switching device and the exposed surface of the resistance switching device is exposed by selectively etching the top electrode layer to the certain depth within the resistance switching device.

19. The method according to claim 18, wherein: Have at least one of the following: The material of the top electrode layer is a non-stoichiometric aluminum-nitrogen material AlNx formed by a PVD process; The switching layer is a non-stoichiometric aluminum-oxygen material AlOy formed by a PVD process; or The etchant that selectively etches the top electrode layer is diluted ammonium hydroxide or diluted tetramethylammonium hydroxide (TMAH).

20. The method according to claim 19, wherein: The diluted TMAH or the diluted ammonium hydroxide is diluted to a range of 8000 parts of diluent to 1 part of TMAH or ammonium hydroxide to 14000 parts of diluent to 1 part of TMAH or ammonium hydroxide.

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