Driving circuit and driving chip

Abstract

The present disclosure provides a driving circuit and a driving chip. The driving circuit comprises a dead time control circuit, a conversion circuit, a bridge circuit and a pull-up circuit; the bridge circuit comprises a first switch tube located at an upper bridge arm and a second switch tube located at a lower bridge arm; the dead time control circuit is used for performing dead time control processing on a low-voltage driving control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal used for driving the second switch tube; the conversion circuit is used for converting the first low-voltage logic signal into a high-voltage logic signal used for driving the first switch tube; and the pull-up circuit is used for accelerating the pull-up speed of the high-voltage logic signal under the control of the first low-voltage logic signal.

Description

Technical Field

[0001] This disclosure relates to electronic circuits, and more specifically, to a driving circuit and a driving chip. Background Technology

[0002] In driver circuits, dead time is used to prevent shoot-through in the upper and lower arms of the bridge circuit. Dead time effectively avoids the situation where the upper and lower arms are simultaneously conducting due to the delay effect of IGBTs (Insulated Gate Transistors), improving the safety and reliability of the driver circuit. However, dead time has a significant impact on drive propagation delay, so it is necessary to provide a driver circuit that can reduce both dead time and drive propagation delay. Summary of the Invention

[0003] One object of this disclosure is to provide a new drive circuit and drive chip that can reduce dead time and drive transmission delay.

[0004] According to a first aspect of this disclosure, a driving circuit is provided. The driving circuit includes: a dead-time control circuit, a conversion circuit, a bridge circuit, and a pull-up circuit;

[0005] The bridge circuit includes a first switching transistor located in the upper bridge arm and a second switching transistor located in the lower bridge arm.

[0006] The dead-time control circuit is used to perform dead-time control processing on the low-voltage drive control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal for driving the second switch.

[0007] The conversion circuit is used to convert the first low-voltage logic signal into a high-voltage logic signal for driving the first switching transistor.

[0008] The pull-up circuit is used to accelerate the pull-up speed of the high-voltage logic signal under the control of the first low-voltage logic signal.

[0009] Optionally, the driving circuit further includes a first pre-stage driving circuit and a second pre-stage driving circuit;

[0010] The input terminal of the first pre-stage driving circuit is used to receive the high-voltage logic signal, the output terminal is connected to the gate of the first switching transistor, the power supply terminal is connected to the high-voltage power supply, and the ground terminal is connected to the high-voltage ground.

[0011] The input terminal of the second pre-stage driver circuit is used to receive the second low-voltage logic signal, the output terminal is connected to the gate of the second switching transistor, the power supply terminal is connected to the low-voltage power supply, and the ground terminal is connected to the low-voltage ground.

[0012] Optionally, the dead time control circuit outputs the first low-voltage logic signal through its first output terminal and the second low-voltage logic signal through its second output terminal.

[0013] The pull-up circuit includes a first resistor, a first capacitor, and a third switching transistor;

[0014] The first resistor is connected between the high-voltage power supply and the first potential point;

[0015] The first capacitor is connected between the first output terminal of the dead time control circuit and the first potential point;

[0016] The gate of the third switching transistor is connected to the first potential point, the source is connected to the high-voltage power supply, and the drain is connected to the output terminal of the conversion circuit.

[0017] Optionally, the pull-up circuit further includes a first Zener diode;

[0018] The positive terminal of the first Zener diode is connected to the first potential point, and the negative terminal is connected to the high-voltage power supply.

[0019] Optionally, the first and third switching transistors are PMOS transistors, and the second switching transistor is an NMOS transistor.

[0020] Optionally, the pull-up circuit includes a first resistor, a second resistor, a first capacitor, a third switch, a fourth switch, and a fifth switch.

[0021] The first resistor is connected between the high-voltage power supply and the first potential point;

[0022] The second resistor is connected between the high-voltage power supply and the second potential point;

[0023] The first capacitor is connected between the first potential point and the second potential point;

[0024] The gate of the third switch is connected to the first potential point, the source is connected to the high voltage power supply, and the drain is connected to the output terminal of the conversion circuit.

[0025] The gate of the fourth switch is connected to the high-voltage power supply, the source is connected to the second potential point, and the drain is connected to the drain of the fifth switch.

[0026] The gate of the fifth switching transistor is connected to the first output terminal of the dead time control circuit, and its source is connected to low-voltage ground.

[0027] Optionally, the pull-up circuit further includes a second Zener diode;

[0028] The gate of the fourth switching transistor is connected to the high-voltage power supply, including: the gate of the fourth switching transistor is connected to the high-voltage power supply through the second Zener diode, wherein the positive terminal of the second Zener diode is connected to the gate of the fourth switching transistor, and the negative terminal is connected to the high-voltage power supply.

[0029] Optionally, the pull-up circuit further includes a third resistor;

[0030] The third resistor is connected between the positive terminal of the second Zener diode and the low-voltage ground.

[0031] Optionally, the first, third, and fourth switching transistors are PMOS transistors, and the second and fifth switching transistors are NMOS transistors.

[0032] Optionally, the dead time control circuit outputs the first low-voltage logic signal through its first output terminal and the second low-voltage logic signal through its second output terminal.

[0033] The conversion circuit includes a fourth resistor, a fifth resistor, and a sixth switching transistor;

[0034] The fourth resistor is connected between the high-voltage power supply and the drain of the sixth switching transistor;

[0035] The fifth resistor is connected between the source of the sixth switch and the low-voltage ground.

[0036] The gate of the sixth switching transistor is connected to the first output terminal of the dead time control circuit, and the drain is the output terminal of the conversion circuit.

[0037] According to a second aspect of this disclosure, a driver chip is provided. The driver chip includes the driver circuitry described in any of the first aspects of this disclosure.

[0038] This disclosure provides a driving circuit including a dead-time control circuit, a conversion circuit, a bridge circuit, and a pull-up circuit. The dead-time control circuit performs dead-time control processing on a low-voltage drive control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal. The first low-voltage logic signal is processed by the conversion circuit to generate a drive signal for the upper bridge arm, and the second low-voltage logic signal is used to drive the lower bridge arm. The pull-up circuit accelerates the pull-up of the drive signal for the upper bridge arm under the control of the first low-voltage logic signal, thereby reducing the dead time and drive transmission delay.

[0039] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with their description, serve to explain the principles of the present disclosure.

[0041] Figure 1 This is a block diagram of the driving circuit provided in an embodiment of this disclosure;

[0042] Figure 2 This is a circuit diagram of the driving circuit provided in an embodiment of this disclosure;

[0043] Figure 3 yes Figure 2 The diagram shows the waveform of the drive circuit when the pull-up circuit is disconnected.

[0044] Figure 4 This is a circuit diagram of the first pull-up circuit provided in the embodiments of this disclosure;

[0045] Figure 5 This is a circuit diagram of the second pull-up circuit provided in the embodiments of this disclosure;

[0046] Figure 6 Is Figure 5 The waveform diagram of the drive circuit under the action of the pull-up circuit is shown. Detailed Implementation

[0047] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0048] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0049] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.

[0050] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0051] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0052] Explanation of English abbreviations:

[0053] MOS transistor: Metal Oxide Semiconductor. PMOS transistor: Positive channel Metal-Oxide-Semiconductor. NMOS transistor: Negative channel Metal-Oxide-Semiconductor. DMOS transistor: Double-diffusion Metal-Oxide-Semiconductor. CMOS transistor: Complementary Metal-Oxide-Semiconductor. HVMOS transistor: High Voltage Metal-Oxide-Semiconductor.

[0054] BCD process: Bipolar-CMOS-DMOS, a bipolar complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor process, is an integrated circuit manufacturing technology. CMOS transistors are typically implemented using the BCD process.

[0055] Compared to HVMOS transistors, DMOS transistors have lower equivalent internal resistance and stronger current carrying capacity for the same area, assuming the drain-source voltage range is the same. Therefore, using DMOS transistors helps reduce chip area and thus lower chip cost. However, the gate of a DMOS device cannot withstand high voltage from the substrate, generally only around 5V, which may cause some difficulties in chip design.

[0056] Latch-up: Latch-up is a parasitic effect unique to CMOS technology, which can lead to circuit failure or even burn out the chip.

[0057] See Figure 1 As shown, this embodiment of the present disclosure provides a driving circuit. The driving circuit includes a dead-time control circuit 100, a conversion circuit 200, a bridge circuit 500, and a pull-up circuit 600.

[0058] The bridge circuit 500 includes a first switching transistor located in the upper bridge arm and a second switching transistor located in the lower bridge arm.

[0059] The input terminal of the dead time control circuit 100 is used to receive the low-voltage drive control signal, and the drive output terminal OUT of the bridge circuit 500 is used to output the drive signal to drive the load.

[0060] The dead-time control circuit 100 is used to set the dead time to prevent the first and second switching transistors from conducting simultaneously, that is, to prevent shoot-through between the upper and lower bridge arms. Specifically, the dead-time control circuit 100 is used to perform dead-time control processing on the low-voltage drive control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal. In one example, one of the first and second low-voltage logic signals is obtained by delaying the low-voltage drive control signal on its rising edge according to the first dead time, and the other is obtained by delaying the low-voltage drive control signal on its falling edge according to the second dead time.

[0061] The conversion circuit 200 is used to convert the first low-voltage logic signal into a high-voltage logic signal.

[0062] The high-voltage logic signal is used to drive the first switching transistor, and the second low-voltage logic signal is used to drive the second switching transistor.

[0063] The pull-up circuit 600 is used to accelerate the pull-up speed of the high-voltage logic signal under the control of the first low-voltage logic signal.

[0064] This disclosure embodiment implements a driving circuit, which includes a dead-time control circuit, a conversion circuit, a bridge circuit, and a pull-up circuit. The dead-time control circuit is used to perform dead-time control processing on the low-voltage drive control signal to obtain a first low-voltage logic signal and a second low-voltage logic signal. The first low-voltage logic signal is processed by the conversion circuit to generate a drive signal for the upper bridge arm, and the second low-voltage logic signal is used to drive the lower bridge arm. The pull-up circuit is used to accelerate the pull-up of the drive signal for the upper bridge arm under the control of the first low-voltage logic signal, thereby speeding up the pull-up speed of the drive signal for the upper bridge arm and reducing the dead time and drive transmission delay.

[0065] In one example, the first switch can be a high-side driven transistor, which can be implemented using a PMOS transistor. The second switch can be a low-side driven transistor, which can be implemented using an NMOS transistor. For driver chips, the driver section is usually the main component of the chip area. Using BCD technology helps to reduce the chip area and thus reduce the chip cost. In another example, both the first and second switches can be DMOS devices, which helps to reduce the chip area and thus reduce the chip cost.

[0066] In one example, the driving circuit may further include a first pre-stage driving circuit for the first switching transistor and a second pre-stage driving circuit for the second switching transistor.

[0067] When the power supply voltage VDD and the drive output OUT of the drive circuit are medium to high voltage, since the gate of the DMOS transistor cannot withstand high voltage to the substrate, a power supply VSH that is 5V lower than the power supply voltage VDD and a power supply VCC that is 5V higher than the ground GND of the drive circuit can be introduced inside the drive circuit. The power supplies VSH and VCC can be obtained by stepping down the power supply voltage VDD. In this embodiment, the power supply voltage VDD of the drive circuit is used as the high-voltage power supply, and the power supply VSH that is 5V lower than the power supply voltage VDD is used as the high-voltage ground. The high-voltage power supply VDD and the high-voltage ground VSH form a high-voltage power supply domain. The power supply VCC that is 5V higher than the ground GND of the drive circuit is used as the low-voltage power supply, and the ground GND of the drive circuit is used as the low-voltage ground. The low-voltage power supply VCC and the low-voltage ground GND form a low-voltage power supply domain.

[0068] For the first pre-stage driver circuit, its operating power supply is a high-voltage power supply VDD. Specifically, the input terminal of the first pre-stage driver is connected to a high-voltage logic signal, the output terminal of the first pre-stage driver is connected to the gate of the first switching transistor to drive the first switching transistor, the power supply terminal of the first pre-stage driver is connected to the high-voltage power supply VDD, and the ground terminal of the first pre-stage driver circuit is connected to the high-voltage ground VSH. For the second pre-stage driver circuit, its operating power supply is a low-voltage power supply VCC. Specifically, the input terminal of the second pre-stage driver circuit is connected to a second low-voltage logic signal, the output terminal of the second pre-stage driver is connected to the gate of the second switching transistor to drive the second switching transistor, the power supply terminal of the second pre-stage driver is connected to the low-voltage power supply VCC, and the ground terminal of the second pre-stage driver circuit is connected to the low-voltage ground GND. In this way, the first and second switching transistors can be DMOS devices and can operate safely and reliably.

[0069] Based on the foregoing, see [link / reference]. Figure 2 As shown, this disclosure provides a driving circuit.

[0070] See Figure 2 As shown, the drive circuit includes: a dead time control circuit 100, a conversion circuit 200, a first pre-stage drive circuit 300, a second pre-stage drive circuit 400, a bridge circuit, and a pull-up circuit 600.

[0071] A bridge circuit includes a first switching transistor PM0 in the upper arm and a second switching transistor NM0 in the lower arm. The drive output terminal OUT of the bridge circuit outputs a drive signal to drive the load. In one example, the first switching transistor PM0 can be driven on the high side and can be implemented using a PMOS transistor. The second switching transistor NM0 can be driven on the low side and can be implemented using an NMOS transistor. The source of the first switching transistor PM0 is connected to the high-voltage power supply VDD, and its drain is connected to the drain of the second switching transistor NM0. The source of the second switching transistor NM0 is connected to the low-voltage ground, forming the bridge circuit.

[0072] The dead-time control circuit 100 receives the low-voltage drive control signal PUL at its input, outputs a first low-voltage logic signal PULH at its first output, and outputs a second low-voltage logic signal PULL at its second output. The dead-time control circuit 100 sets the dead time to prevent the first switch PM0 and the second switch NM0 from conducting simultaneously, thus preventing shoot-through between the upper and lower bridge arms. Specifically, the dead-time control circuit 100 performs dead-time control processing on the low-voltage drive control signal PUL to obtain the first low-voltage logic signal PULH and the second low-voltage logic signal PULL. In one example, the dead-time control circuit 100 performs rising-edge delay processing on the low-voltage drive control signal PUL to obtain the first low-voltage logic signal PULH, and falls-edge delay processing and inversion processing on the low-voltage drive control signal PUL to obtain the second low-voltage logic signal PULL.

[0073] The conversion circuit 200 converts the first low-voltage logic signal PULH into a high-voltage logic signal PDP, which is then provided to the first pre-amplifier driver circuit 300. For example, the voltage range of the first low-voltage logic signal PULH is 0V to 5V, and the voltage range of the converted high-voltage logic signal PDP is VSH to VDD. In one example, the conversion circuit 200 includes a fourth resistor R2, a fifth resistor R1, and a sixth switch NM1. The gate of the sixth switch NM1 is connected to the first output terminal of the dead-time control circuit, and its drain is connected to the input terminal of the first pre-amplifier driver circuit 300. The gate of the sixth switch NM1 is the input terminal of the conversion circuit 200, which receives the first low-voltage logic signal PULH. The drain of the sixth switch NM1 is the output terminal of the conversion circuit 200, providing the high-voltage logic signal PDP to the first pre-amplifier driver circuit 300. The fourth resistor R2 is connected between the high-voltage power supply VDD and the drain of the sixth switch NM1. The fifth resistor R1 is connected between the source of the sixth switch NM1 and the low-voltage ground. The sixth switch, NM1, can be implemented using an NMOS transistor.

[0074] The power supply terminal of the first pre-stage driver circuit 300 is connected to the high-voltage power supply VDD, and the ground terminal is connected to the high-voltage ground VSH. The first pre-stage driver circuit 300 may include multiple inverters connected in series to amplify the high-voltage logic signal PDP stage by stage to obtain the first drive signal PP. The input terminal of the first pre-stage driver circuit 300 is connected to the high-voltage logic signal PDP, and the output terminal is connected to the gate of the first switching transistor PM0 to provide the first drive signal PP to the first switching transistor PM0.

[0075] The power supply terminal of the second pre-stage driver circuit 400 is connected to the low-voltage power supply VCC, and the ground terminal is connected to the low-voltage ground GND. The second pre-stage driver circuit 400 may include multiple inverters connected in series to amplify the second low-voltage logic signal PULL stage by stage to obtain the second drive signal PN. The input terminal of the second pre-stage driver circuit 400 is connected to the second low-voltage logic signal PULL, and the output terminal is connected to the gate of the second switching transistor NM0 to provide the second drive signal PN for the second switching transistor NM0.

[0076] The pull-up circuit 600 is used to accelerate the pull-up speed of the high-voltage logic signal PDP under the control of the first low-voltage logic signal PULH. The operating power supply of the pull-up circuit is the high-voltage power supply VDD.

[0077] Figure 3 yes Figure 2 The diagram shown illustrates the waveform of the drive circuit when the pull-up circuit 600 is disconnected, i.e., without the pull-up circuit 600. Figure 2 The waveform diagram of the driving circuit is shown.

[0078] The dead-time control circuit 100 performs rising edge delay processing on the low-voltage drive control signal PUL to obtain the first low-voltage logic signal PULH, and performs falling edge delay processing and inversion processing on the low-voltage drive control signal PUL to obtain the second low-voltage logic signal PULL.

[0079] The conversion circuit 200 converts the first low-voltage logic signal PULH into a high-voltage logic signal PDP. The first pre-stage driver circuit 300 amplifies the high-voltage logic signal PDP stage by stage to obtain the first driver signal PP. The second pre-stage driver circuit 400 amplifies the second low-voltage logic signal PULL stage by stage to obtain the second driver signal PN.

[0080] The first switch PM0 is a PMOS transistor. When the first drive signal PP is '0', the first switch PM0 is turned on, and when the first drive signal PP is '1', the first switch PM0 is turned off. The second switch NM0 is an NMOS transistor. When the second drive signal PN is '1', the second switch NM0 is turned on, and when the second drive signal PN is '0', the second switch NM0 is turned off.

[0081] When the first low-voltage logic signal PULH is '0', the sixth switch NM1 is turned off. At this time, the high-voltage logic signal PDP is pulled up to the high-voltage power supply VDD by the fourth resistor R2, that is, the voltage relative to the high-voltage ground VSH is '1'.

[0082] When the first low-voltage logic signal PULH is '1', the sixth switch NM1 is turned on. Since the source voltage of the sixth switch NM1 (i.e., the voltage drop across the fifth resistor R1) is lower than its gate voltage (i.e., the low-voltage power supply VCC) by one turn-on threshold, by properly setting the ratio of the fifth resistor R1 to the fourth resistor R2, it can be ensured that the voltage drop across the fourth resistor R2 is approximately equal to the low-voltage power supply VCC. At this time, the high-voltage logic signal PDP is at a logic low level '0' relative to the high-voltage ground VSH.

[0083] Considering power consumption, the resistance values ​​of the fifth resistor R1 and the fourth resistor R2 cannot be too small, which limits the switching speed of the switching circuit 200. See also Figure 3 As shown, due to the parasitic capacitance between the gate and drain of the sixth switch NM1, the pull-up of the high-voltage logic signal PDP requires a relatively long time without the pull-up circuit 600. These factors will cause propagation delays on the falling and rising edges of the first low-voltage logic signal PULH. Assuming the pull-up delay of the high-voltage logic signal PDP (i.e., the time required to flip from "0" to "1") is td1, and the pull-down delay of the high-voltage logic signal PDP (i.e., the time required to flip from "1" to "0") is td2, then the propagation delay of the falling edge of the first low-voltage logic signal PULH is approximately td1, and the propagation delay of the rising edge of the first low-voltage logic signal PULH is approximately td2.

[0084] To avoid shoot-through between the first switch PM0 and the second switch NM0, which would cause additional losses or even overheating and burnout in the drive circuit, the dead time t1 of the first low-voltage logic signal PULH and the dead time t2 of the second low-voltage logic signal PULL must be set according to the transmission delay of the switching circuit.

[0085] For the rising edge of the low-voltage drive control signal PUL, due to the pull-down delay td2 of the high-voltage logic signal PDP, it can be ensured that the second switch NM0 is turned off first and the first switch PM0 is turned on later. Therefore, the corresponding dead time t1 can be very small, or even 0. The time delay for the rising edge of the low-voltage drive control signal PUL to reach the gate of the first switch PM0 is t3, t3≈t1+td2, and the propagation delay t5 of the rising edge of the low-voltage drive control signal PUL is approximately t3.

[0086] For the falling edge of the low-voltage drive control signal PUL, due to the pull-up delay td1 of the high-voltage logic signal PDP, the corresponding dead time t2 must be greater than or equal to td1 to ensure that the first switch PM0 turns off first and the second switch NM0 turns on later. Let t2 = td1 + t4, where t4 ≥ 0. For reliability, t4 is usually slightly greater than 0. The propagation delay t6 of the falling edge of the low-voltage drive control signal PUL is approximately equal to t2. It is evident that the pull-up delay of the high-voltage logic signal PDP directly determines the minimum value of the corresponding dead time t2. An excessively long pull-up delay of the high-voltage logic signal PDP results in an excessively long dead time and drive propagation delay.

[0087] and Figure 3 Unlike other circuits, the drive circuit, with a pull-up circuit 600 and operating normally, can accelerate the pull-up process of the high-voltage logic signal PDP, reducing the rise time of the high-voltage logic signal PDP. This reduces the propagation delay of the falling edge of the first low-voltage logic signal PULH, thereby reducing the corresponding dead time and the delay from the falling edge of the low-voltage drive control signal PUL to the drive output OUT. Specifically, the pull-up circuit 600, also controlled by the first low-voltage logic signal PULH, couples the falling edge of the first low-voltage logic signal PULH, causing the high-voltage logic signal PDP to be quickly pulled up the instant the first low-voltage logic signal PULH flips from "1" to "0". This reduces the propagation delay of the falling edge of the first low-voltage logic signal PULH. Under the premise that the first switch PM0 and the second switch NM0 do not shoot through, the corresponding dead time and the delay from the falling edge of the low-voltage drive control signal PUL to the drive output OUT can be significantly reduced.

[0088] See Figure 4 The diagram illustrates a pull-up circuit provided in one embodiment of this disclosure.

[0089] See Figure 4 As shown, the pull-up circuit includes a first resistor R4, a first capacitor C0, and a third switching transistor PM2. The first resistor R4 is connected between the high-voltage power supply VDD and the first potential point NET1. The first capacitor C0 is connected between the first output terminal of the dead-time control circuit and the first potential point NET1. The gate of the third switching transistor PM2 is connected to the first potential point NET1, its source is connected to the high-voltage power supply VDD, and its drain is connected to the output terminal of the switching circuit. The third switching transistor PM2 can be a PMOS transistor.

[0090] The pull-up circuit may also include a first Zener diode D0. The positive terminal of the first Zener diode D0 is connected to the first potential point NET1, and the negative terminal is connected to the high-voltage power supply VDD.

[0091] for Figure 4 In the pull-up circuit shown, when the first low-voltage logic signal PULH flips from '1' to '0', the sixth switch NM1 is turned off, and the fourth resistor R2 pulls up the high-voltage logic signal PDP. Since the voltage on the first capacitor C0 cannot change instantaneously, at the instant the first low-voltage logic signal PULH flips to '0', the voltage at the first potential point NET1 also drops to '0', thereby turning on the third switch PM2 to accelerate the pull-up of the high-voltage logic signal PDP. Afterwards, the first low-voltage logic signal PULH remains at '0', and the first resistor R4 charges the first capacitor C0 until the first potential point NET1 is pulled up to the high-voltage power supply VDD, at which point the third switch PM2 is turned off. The first Zener diode D0 is used to clamp the gate voltage of the third switch PM2, ensuring that the gate potential of the third switch PM2 does not exceed its withstand voltage value.

[0092] As can be seen, the pull-up circuit is controlled by the first low-voltage logic signal PULH. The first capacitor C0 is used to couple the falling edge signal of PULH, so that the high-voltage logic signal PDP is quickly pulled up at the moment when the first low-voltage logic signal PULH flips from "1" to "0". This reduces the transmission delay of the falling edge of the first low-voltage logic signal PULH. Under the premise that the first switch PM0 and the second switch NM0 do not shoot through, the corresponding dead time and the delay time from the falling edge of the low-voltage drive control signal PUL to the drive output OUT can be reduced to a large extent.

[0093] See Figure 5 The diagram illustrates a pull-up circuit provided in another embodiment of this disclosure.

[0094] See Figure 5 As shown, the pull-up circuit includes a first resistor R4, a second resistor R3, a first capacitor C0, a third switch PM2, a fourth switch PM1, and a fifth switch NM2. The first resistor R4 is connected between the high-voltage power supply VDD and the first potential point NET1. The second resistor R3 is connected between the high-voltage power supply VDD and the second potential point NET0. The first capacitor C0 is connected between the first potential point NET1 and the second potential point NET0. The gate of the third switch PM2 is connected to the first potential point NET1, its source is connected to the high-voltage power supply VDD, and its drain is connected to the output of the conversion circuit. The gate of the fourth switch PM1 is connected to the high-voltage power supply VDD, its source is connected to the second potential point NET0, and its drain is connected to the drain of the fifth switch NM2. The gate of the fifth switch NM2 is connected to the first output of the dead-time control circuit, and its source is connected to low-voltage ground.

[0095] In one example, see Figure 5As shown, the third switch PM2 and the fourth switch PM1 are PMOS transistors, and the fifth switch NM2 is an NMOS transistor. In this case, an inverter 601 is added between the gate of the fifth switch NM2 and the first output terminal of the dead time control circuit 100.

[0096] The pull-up circuit may also include a second Zener diode D2. The gate of the fourth switch PM1 is connected to the high-voltage power supply VDD. Specifically, the gate of the fourth switch PM1 is connected to the high-voltage power supply VDD through the second Zener diode D2, wherein the positive terminal of the second Zener diode D2 is connected to the gate of the fourth switch PM1, and the negative terminal is connected to the high-voltage power supply VDD.

[0097] In one example, the resistance of the second resistor R3 is very large, and a resistor in the Mohm (megaohm) range can be selected, which is beneficial to speed up the pull-up speed of the high-voltage logic signal PDP.

[0098] In one example, the pull-up circuit may also include a third resistor R5 connected between the positive terminal of the second Zener diode D2 and low-voltage ground. The third resistor R5 is used for current limiting, providing protection for the second Zener diode D2 and the fourth switching transistor PM1.

[0099] Figure 6 For use Figure 5 The waveform diagram of the pull-up circuit driver circuit shown below is combined with... Figure 6 As shown, for the use Figure 5 The driving circuit of the pull-up circuit shown will be further explained.

[0100] The second Zener diode D2 clamps the gate potential (i.e., the third potential point NET2) of the fourth switch PM1. The breakdown voltage of the second Zener diode D2 is V. D2-BV V D2-BV The voltage is approximately 5V, ensuring that the gate-substrate voltage difference of the fourth switch PM1 is within the safe operating range.

[0101] Assume the voltage at the third potential point NET2 is V. NET2 Therefore, we have:

[0102] V NET2 =VDD﹣V D2-BV

[0103] The turn-on threshold voltage V of the fourth switch PM1 TH0 It is a negative value. Assume the voltage at the second potential point NET0 is V. NET0 V NET0 Minimum value V NET0-MIN When the fifth switch NM2 is turned on, the gate-source voltage V of the fourth switch PM1 is... GS≈V TH0 Therefore, we have:

[0104] V NET2 -V NET0-MIN =V GS ≈V TH0

[0105] V NET0-MIN =V NET2 -V TH0 =VDD﹣V D2-BV -V TH0

[0106] VDD﹣V NET0-MIN =V D2-BV +V TH0

[0107] That is, the maximum voltage difference between the high-voltage power supply VDD and the second potential point NET0 is greater than the breakdown voltage V of the second Zener diode D2. D2-BV It should also be smaller than the absolute value of the threshold voltage of the fourth switch PM1, which can ensure that the voltage drop of the first capacitor C0 is not too large.

[0108] When the first low-voltage logic signal PULH flips from '1' to '0', the signal output by inverter 601 flips from '0' to '1', and the fifth switch NM2 turns on. Because the second resistor R3 has a very large resistance, the second potential point NET0 will be quickly pulled down to V. NET0-MIN Since the voltage across the first capacitor C0 cannot change instantaneously, the first potential point NET1 will also couple out a signal close to the level of the second potential point NET0, causing the third switch PM2 to conduct, thereby accelerating the pull-up of the high-voltage logic signal PDP. Afterwards, the first low-voltage logic signal PULH remains '0', and the branch of the fifth switch NM2 remains on, meaning the voltage at the second potential point NET0 remains at V. NET0-MIN The first resistor R4 slowly charges the first capacitor C0, pulling the voltage at the first potential point NET1 up to the high-voltage power supply VDD, and the third switch PM2 is completely turned off. At this time, the voltage drop across the first capacitor C0 will reach its maximum value V. C0-MAX ,

[0109] V C0-MAX =VDD﹣V NET0-MIN =V D2-BV +V TH0 ,

[0110] That is, the maximum voltage drop V across the first capacitor C0 C0-MAX The breakdown voltage V of the second Zener diode D2 D2-BV It also needs to be smaller than the absolute value of the threshold voltage of the fourth switch PM1 to ensure that the voltage drop of the first capacitor C0 is not too large.

[0111] From the above, we can see that, for Figure 5 The pull-up circuit shown does not have a large voltage drop across the first capacitor C0, so the requirement for the breakdown voltage of the first capacitor C0 is relatively low.

[0112] When the first low-voltage logic signal PULH flips from '0' to '1', the signal output by inverter 601 flips from '1' to '0', the fifth switch NM2 turns off, and the second resistor R3 pulls up the second potential point NET0. Because the resistance of the second resistor R3 is very large, the pull-up speed of the second potential point NET0 is very slow. The level of the first potential point NET1 at this time is basically unaffected by the second potential point NET0 and will remain at '1', preventing the risk of voltage coupling from the first capacitor C0 causing a latch-up in the drive circuit and drive chip.

[0113] It can be seen that, based on Figure 5 The provided pull-up circuit accelerates the pull-up speed of the high-voltage logic signal PDP during the transition of the first low-voltage logic signal PULH from '1' to '0', significantly reducing the corresponding dead time and the delay time from the falling edge of the low-voltage drive control signal PUL to the drive output OUT. During the transition of the first low-voltage logic signal PULH from '0' to '1', the pull-up circuit does not affect the high-voltage logic signal PDP.

[0114] Figure 5 The pull-up circuit shown has relatively few restrictions on the first capacitor C0 and can also prevent the risk of latch-up in the driver circuit and driver chip. Therefore, this type of pull-up circuit has relatively low requirements for process technology and layout design, which is conducive to reducing production costs and speeding up production.

[0115] In this embodiment of the disclosure, the first switch PM0, the second switch NM0, the third switch PM2, the fourth switch PM1, the fifth switch NM2, and the sixth switch NM1 can be DMOS devices. Using DMOS devices is beneficial for reducing the chip area and thus reducing the cost of the driver chip.

[0116] This disclosure also provides a driver chip. The driver chip includes the driver circuit provided in any of the foregoing embodiments.

[0117] The driving circuits and driving chips mentioned in this invention may include a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this invention. The various embodiments in this specification are described in a progressive manner, and similar or identical parts between embodiments can be referred to mutually. In some cases, the actions or steps described in the embodiments may be performed in a different order than those in the embodiments and still achieve the desired results. The computer-readable storage medium may be a tangible device capable of holding and storing instructions used by an instruction execution device.

[0118] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are customized by utilizing state information from computer-readable program instructions. These electronic circuits can execute computer-readable program instructions to implement various aspects of this invention.

[0119] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A driving circuit, characterized in that, include: Dead time control circuit, conversion circuit, bridge circuit and pull-up circuit; The bridge circuit includes a first switch (PM0) located in the upper bridge arm and a second switch (NM0) located in the lower bridge arm; The dead-time control circuit is used to perform dead-time control processing on the low-voltage drive control signal (PUL) to obtain a first low-voltage logic signal (PULH) and a second low-voltage logic signal (PULL) for driving the second switch (NMO). The conversion circuit is used to convert the first low-voltage logic signal (PULH) into a high-voltage logic signal (PDP) for driving the first switching transistor (PM0); The pull-up circuit is used to accelerate the pull-up speed of the high-voltage logic signal (PDP) under the control of the first low-voltage logic signal (PULH); The dead time control circuit outputs the first low-voltage logic signal (PULH) through its first output terminal and the second low-voltage logic signal (PULL) through its second output terminal. The pull-up circuit includes a first resistor (R4), a first capacitor (C0), and a third switching transistor (PM2); The first resistor (R4) is connected between the high voltage power supply (VDD) and the first potential point (NET1); The first capacitor (C0) is connected between the first output terminal of the dead time control circuit and the first potential point (NET1); The gate of the third switching transistor (PM2) is connected to the first potential point (NET1), the source is connected to the high voltage power supply (VDD), and the drain is connected to the output terminal of the conversion circuit.

2. The driving circuit according to claim 1, characterized in that, The driving circuit also includes a first pre-stage driving circuit and a second pre-stage driving circuit. The input terminal of the first pre-stage driver circuit is used to receive the high-voltage logic signal (PDP), the output terminal is connected to the gate of the first switching transistor (PM0), the power supply terminal is connected to the high-voltage power supply (VDD), and the ground terminal is connected to the high-voltage ground (VSH). The input terminal of the second pre-stage driver circuit is used to receive the second low-voltage logic signal (PULL), the output terminal is connected to the gate of the second switching transistor (NMO), the power supply terminal is connected to the low-voltage power supply (VCC), and the ground terminal is connected to the low-voltage ground.

3. The driving circuit according to claim 1, characterized in that, The pull-up circuit also includes a first Zener diode (D0); The positive terminal of the first Zener diode (D0) is connected to the first potential point (NET1), and the negative terminal is connected to the high voltage power supply (VDD).

4. The driving circuit according to claim 1, characterized in that, The first switch (PM0) and the third switch (PM2) are PMOS transistors, and the second switch (NM0) is an NMOS transistor.

5. The driving circuit according to claim 1, characterized in that, The dead time control circuit outputs the first low-voltage logic signal (PULH) through its first output terminal and the second low-voltage logic signal (PULL) through its second output terminal. The pull-up circuit includes a first resistor (R4), a second resistor (R3), a first capacitor (C0), a third switch (PM2), a fourth switch (PM1), and a fifth switch (NM2); The first resistor (R4) is connected between the high voltage power supply (VDD) and the first potential point (NET1); The second resistor (R3) is connected between the high voltage power supply (VDD) and the second potential point (NET0); The first capacitor (C0) is connected between the first potential point (NET1) and the second potential point (NET0); The gate of the third switching transistor (PM2) is connected to the first potential point (NET1), the source is connected to the high voltage power supply (VDD), and the drain is connected to the output terminal of the conversion circuit. The gate of the fourth switch (PM1) is connected to the high voltage power supply (VDD), the source is connected to the second potential point (NET0), and the drain is connected to the drain of the fifth switch (NM2). The gate of the fifth switching transistor (NM2) is connected to the first output terminal of the dead time control circuit, and its source is connected to low-voltage ground.

6. The driving circuit according to claim 5, characterized in that, The pull-up circuit also includes a second Zener diode (D2); The gate of the fourth switching transistor (PM1) is connected to the high-voltage power supply (VDD), including: the gate of the fourth switching transistor (PM1) is connected to the high-voltage power supply (VDD) through the second Zener diode (D2), wherein the positive terminal of the second Zener diode (D2) is connected to the gate of the fourth switching transistor (PM1), and the negative terminal is connected to the high-voltage power supply (VDD).

7. The driving circuit according to claim 6, characterized in that, The pull-up circuit also includes a third resistor (R5); The third resistor (R5) is connected between the positive terminal of the second Zener diode (D2) and the low-voltage ground.

8. The driving circuit according to claim 5, characterized in that, The first switch (PM0), the third switch (PM2), and the fourth switch (PM1) are PMOS transistors, and the second switch (NM0) and the fifth switch (NM2) are NMOS transistors. An inverter is provided between the gate of the fifth switch (NM2) and the first output terminal of the dead time control circuit.

9. The driving circuit according to any one of claims 2-8, characterized in that, The dead time control circuit outputs the first low-voltage logic signal (PULH) through its first output terminal and the second low-voltage logic signal (PULL) through its second output terminal. The conversion circuit includes a fourth resistor (R2), a fifth resistor (R1), and a sixth switch (NM1); The fourth resistor (R2) is connected between the high voltage power supply (VDD) and the drain of the sixth switching transistor (NM1); The fifth resistor (R1) is connected between the source of the sixth switch (NM1) and the low-voltage ground; The gate of the sixth switching transistor (NM1) is connected to the first output terminal of the dead time control circuit, and the drain is the output terminal of the conversion circuit.

10. A driver chip, characterized in that, Includes the drive circuit as described in any one of claims 1-9.

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