Circuit arrangement for regulating voltage, corresponding system and method

Abstract

The present disclosure relates to a circuit arrangement, a corresponding system and a method for regulating voltage. A configurable voltage regulation circuit includes first to fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sensing resistor network is coupled between an output node and an input of an error amplifier and is configured to provide a sensed output voltage. The error amplifier receives a reference voltage at another input and generates an error signal. A charging circuit supplies a charging current to the pump node and controls the value of the charging current according to the error signal. A switch command signal generator generates corresponding first, second, third and fourth switch signals to control a first switch, a second switch, a third switch and a fourth switch. Based on an input voltage being less than a first threshold or greater than a second threshold, the generator sets the configurable voltage regulation circuit as a charge pump or a linear regulator.

Description

Technical Field

[0001] The present disclosure is generally directed to circuit arrangements for regulating voltage, and more particularly to such circuit arrangements that may be used in conjunction with controlling a brushless DC motor. Background Art

[0002] The demands on automotive integrated circuits in terms of performance and reliability over time are very high: they should withstand extreme operating conditions due to the wide range of environmental conditions encountered by the vehicle during its service life (e.g. temperature, battery voltage, etc.). Circuit design that maintains performance over such a wide range is a big challenge.

[0003] Automotive requirements force the improvement of existing architectures to match environmental constraints. In particular, circuits directly connected to the battery should guarantee performance even when the battery is low.

[0004] Three-phase BLDC or brushless DC motors are fundamental in some automotive applications such as electronic power steering, transmissions, etc. The motor control usually includes three half-bridges, where each half-bridge consists of two N-channel FETs with the low side coupled between ground and the phase node, and the high side coupled between the battery voltage and the phase node.

[0005] These FETs are controlled by dedicated pre-drivers. A key parameter for motor control is the gate-source voltage VGS that the pre-driver can provide across the external FETs. The VGS voltage should be controlled because it has a direct impact on the FET drive performance (i.e., on-resistance) and if the value is too low, it may result in a degradation of the motor performance (speed, torque).

[0006] This voltage is generated by an on-chip power supply that must guarantee a gate-source voltage, VGS, typically in the range of 8 V and 12 V. The minimum value is important to allow the motor to be driven correctly, while the maximum value is necessary or desirable to avoid absolute maximum rating violations.

[0007] Even though the battery voltage can be lower or higher than the gate-source voltage VGS, this gate-source voltage VGS should be kept within a typical range. For example, when the battery is at a nominal state (12V, 24V, or 48V depending on the vehicle), the gate-source voltage VGS is lower than the battery voltage, while when the device is operating in a low-battery condition (as low as 4.5V), the gate-source voltage VGS is higher than the battery. Since the battery voltage is the input voltage of this power stage, regulating the output voltage must work even if the input voltage is higher or lower than the output voltage.

[0008] Given a certain input voltage (battery voltage), a power architecture that can generate an output voltage higher or lower than the input voltage is a cascade of a charge pump regulator and a linear regulator. The charge pump regulator can generate an output voltage higher than the input; the linear regulator can generate an output voltage lower than the input voltage.

[0009] exist Figure 1 An example of such a prior art arrangement is shown in .

[0010] The circuit 10, which may be an integrated circuit, comprises a charge pump regulator 11 which receives an input voltage VIN at an input node I of the circuit 10, which input voltage VIN may be in particular a battery voltage. The output voltage of the charge pump 11, an increased voltage VOUTH, which is ideally VOUTH=2xVIN, is supplied to the input of a linear regulator 12, whose output voltage VOUT is formed at an output node O, which is the output of the linear regulator and is introduced as a regulated supply voltage to a driver or pre-driver 20, whose output is coupled to the gate of a FET transistor 30. The output voltage VOUT is a regulated voltage, so that the driver 20 supplies a regulated gate-source voltage VGS to the FET 30. As mentioned, such a FET transistor 30 is one of the switches of a bridge or half-bridge circuit used to drive a motor. Another power supply terminal is coupled to the source of the FET 30. The driver 20 receives at its input a PWM signal from a PWM control circuit, neither of which is present in the circuit. Figure 1 Multiple pairs of driver 20 and FET transistor 30 may be coupled to the output node O, for example, three for driving three phases of a motor.

[0011] The use of two regulators, one connected in series to the other, requires a large amount of silicon area in the integrated circuit, thereby increasing the production cost of the integrated circuit.

[0012] However, current consumption is critical for many applications, so increasing the number of regulators means increasing the current consumption of the integrated circuit. Summary of the invention

[0013] Based on the foregoing description, a need or desire may be felt for a solution that overcomes one or more of the previously outlined disadvantages.

[0014] Embodiments of the present disclosure relate to a circuit arrangement for regulating voltage, which is configured to generate an output voltage higher than an input voltage and an output voltage lower than the input voltage.

[0015] Embodiments of the present disclosure relate particularly to a circuit arrangement for controlling a motor, comprising: a plurality of half-bridge circuits, wherein transistors are driven by corresponding drive circuits, a controlled gate-source voltage being provided to each of the transistors, the drive circuits being supplied with a regulated voltage via a voltage regulator that regulates an input voltage generated by an on-chip power supply.

[0016] According to one or more embodiments, technical benefits may be achieved by circuits having the features specifically set forth herein. Embodiments also relate to related systems and corresponding methods.

[0017] As mentioned previously, the present disclosure provides solutions for electronic circuits for regulating a voltage received at their input, comprising

[0018] Configurable voltage regulation circuitry including

[0019] a first switch coupled between the input node and a common mode node, a second switch coupled between the common mode node and a ground node,

[0020] A flying capacitor coupled between the common mode node and the pump node,

[0021] a third switch coupled between the input node and the pump node and a fourth switch coupled between the pump node and an output node of the circuit for regulating voltage,

[0022] The circuit also includes a sense resistor network, in particular a resistor divider, coupled between the output node and an input of an error amplifier to provide a sensed output voltage at the input, the error amplifier receiving a reference voltage at its other input and generating an error signal,

[0023] a charging circuit for supplying a charging current to the pump node, the charging circuit controlling a value of the charging current according to the error control signal,

[0024] a switch command signal generator configured to generate corresponding first, second, third and fourth switch signals to control the first switch, the second switch, the third switch and the fourth switch respectively, and if the input voltage is lower than a first threshold, the generator is configured to: set the configurable voltage regulation circuit as a charge pump by generating first and second switch signals driven by opposite phases of a clock signal to alternately couple a common mode to the input voltage and ground, and generating third and fourth switch signals driven by opposite phases of the clock signal to alternately couple a pump node to an output node and a charging circuit,

[0025] If the input voltage is greater than a second threshold, the generator is configured to set the configurable voltage regulating circuit as a linear regulator by generating a first switching signal to keep the first switch open and second, third and fourth switching signals to keep the second, third and fourth switches closed.

[0026] In a variant embodiment, the configurable regulating circuit includes a voltage monitoring circuit, which is configured to monitor the value of the input voltage and issue a corresponding first operation command or a second operation mode command to the switch command signal generator according to whether the value of the input voltage is lower than a first threshold or higher than a second threshold.

[0027] In an alternative embodiment, a tank capacitor is coupled between the output node and ground.

[0028] In a variant embodiment, the charging circuit is a controlled current generator

[0029] In a variant embodiment, the controlled current generator is coupled between the input node and the pump node.

[0030] In a variant embodiment, the controlled current generator is coupled between the pump node and the output node

[0031] In a variant embodiment, the charging circuit includes a PWM signal generator that generates a PWM signal proportional to the error signal, and the PWM signal drives the open and closed states of the third switch.

[0032] In a variant embodiment, the voltage monitor is configured as a voltage comparator with hysteresis having a first predefined threshold and a second predefined threshold greater than the first predefined threshold.

[0033] The present disclosure also provides a solution regarding a circuit arrangement for controlling an electric motor, the electric motor comprising a plurality of half-bridge circuits, wherein switching transistors are driven by corresponding driver circuits, providing a controlled gate-source voltage to each of the transistors, the driver circuits being supplied with a regulated voltage through a circuit arrangement according to any of the preceding embodiments.

[0034] The present disclosure also provides a solution for a method for regulating voltage, comprising a circuit according to any one of the aforementioned embodiments, comprising:

[0035] generating corresponding first, second, third and fourth switch signals to control the first switch, the second switch, the third switch and the fourth switch respectively,

[0036] If the input voltage is below a first threshold, configuring the configurable voltage regulating circuit as a charge pump by generating first and second switching signals driven by opposite phases of a clock signal to alternately couple the common mode to the input voltage and ground, and generating third and fourth switching signals driven by opposite phases of the clock signal to alternately couple the pump node to the output node and a charging circuit,

[0037] If the input voltage is greater than a second threshold, the generator sets the configurable voltage regulating circuit as a linear regulator by generating a first switching signal to keep the first switch open and second, third and fourth switching signals to keep the second, third and fourth switches closed.

[0038] In a variant embodiment, the method includes monitoring the value of the input voltage, and issuing a corresponding first operation command or a second operation mode command to the switch command signal generator according to whether the value of the input voltage is lower than a first threshold or higher than a second threshold.

[0039] In a variant embodiment, the second predefined threshold is greater than the first predefined threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting examples only, in which:

[0041] Figure 1 It has been described previously;

[0042] Figure 2 The circuit described herein is schematically shown;

[0043] Figure 3 A circuit diagram showing a first embodiment of the circuit described herein;

[0044] Figure 4 A circuit diagram showing a second embodiment of the circuit described herein;

[0045] Figure 5 A circuit diagram showing a third embodiment of the circuit described herein;

[0046] Figure 6 shows signals of the circuit according to the first embodiment during a first operating mode;

[0047] Figure 7 shows signals of the circuit according to the first embodiment during a second mode of operation;

[0048] Figure 8 A monitoring module of a circuit according to an embodiment is shown;

[0049] Fig. 9shows signals during transitions between operating modes of the circuit according to the first embodiment;

[0050] Fig.10 A circuit diagram showing a variant embodiment of the first embodiment of the circuit described herein;

[0051] Fig.11 A circuit diagram of a circuit for controlling a motor using the circuit described herein is shown. DETAILED DESCRIPTION

[0052] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or several of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0053] References throughout the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0055] Already referenced Figure 1 Figure parts, elements or components described are identified by the same reference numerals used previously in these figures; in order not to overburden this detailed description, the description of these previously described elements will not be repeated below.

[0056] A simple solution refers to a voltage regulator that is capable of or configured to generate output voltages both below and above the input voltage, obtained by combining a low dropout linear regulator and a Dickinson charge pump stage in a single circuit. The linear regulator is capable of providing an output voltage below its input voltage, while the charge pump can provide an output voltage above its input voltage. A switch network under the control of a voltage monitor sets the circuit to either a linear regulator configuration or a charge pump configuration depending on the input voltage.

[0057] In particular, the described circuit operates in two operating modes:

[0058] Linear mode: The voltage monitor constantly checks the input voltage value and if the value is greater than a predefined threshold, the linear mode is activated; and

[0059] Charge Pump Mode: The same voltage monitor activates the charge pump mode if the value of the input voltage falls below a predefined threshold.

[0060] A linear regulator and a charge pump are not different circuits, but rather a unique architecture where the power MOS, driver, regulation loop, and bias network are shared between the two operating modes.

[0061] exist Figure 2 , an embodiment of a circuit according to such a solution is schematically shown.

[0062] This circuit corresponds to Figure 1 The invention relates to a circuit of the present invention, but a voltage regulation circuit arrangement 51 is provided, which replaces the charge pump 11 and the linear regulator 12, and the arrangement 51 includes a configurable voltage regulator 52 which receives an input voltage VIN (in particular corresponding to a battery voltage VBAT) and is controlled in its operation by a voltage monitor 53, i.e. switches between a charge pump and a linear regulator configuration. The voltage monitor 53 also receives the input voltage VIN and generates a mode selection signal MODE SEL, which is supplied to control the configurable voltage regulator 52 so as to switch between a charge pump operation mode or configuration and a linear regulator operation mode or configuration.

[0063] exist Figure 3 In FIG. 5 , a first embodiment of a voltage regulating arrangement 51 is shown, which comprises a voltage monitor 53 coupled to an input node I to receive an input voltage VIN (which is in particular a battery voltage), and outputs a selection mode signal MODE SEL.

[0064] The configurable voltage regulator 52 includes a clock generation module 54, which receives the selection mode signal MODE SEL and generates four switch signals based on the content of the selection mode signal SEL, i.e., signals for controlling the open and closed states of switches (e.g., FET or MOSFET switches), wherein the first selection signal CLKNS1 controls the first switch S1, the second selection signal CLKS2 controls the second switch S2, the third selection signal CLKS3 controls the third switch S3, and the fourth selection signal CLKNS4 controls the fourth switch S4.

[0065] The configurable voltage regulator 52 then comprises a first pair of switches S1 and S2, such as MOSFET switches, the first switch S1 of the first pair being coupled between the input node I and a common node indicated by CM, the second switch S2 of the first pair being coupled between the common node CM and a ground node GND. The voltage regulator 52 then comprises a flying capacitor CFLY coupled between the common node CM and a pump node CP.

[0066] Then, the voltage regulator 52 includes a second pair of switches S3, S4, which includes a third switch S3 coupled between the input node I and the pump node CP and a fourth switch S4 coupled between the pump node CP and an output node O, with the output voltage VOUT formed at the output node O. The energy storage capacitor CTANK is then coupled between the output node O and the ground node GND.

[0067] The voltage regulator 52 also includes a sensing resistor network 55, which is embodied by a resistor divider, which includes a first resistor RREF1 coupled to the output node O and the inverting input of the error amplifier 54, and a second resistor RREF2 coupled between such inverting input and ground GND. Through the voltage divider 55, a sensed output voltage VOUT_DIV is introduced at such inverting input, that is, the ratio of the output voltage VOUT value divided by the voltage divider 55. The error amplifier 55 receives a reference voltage VREF at another input and supplies an error signal E at its output, which is proportional to the difference between the reference voltage VREF and the sensed output voltage VOUT_DIV. Therefore, the differential amplifier 54 operates as a comparator, comparing the inputs and outputting an error signal proportional to their difference.

[0068] The value of the error signal E drives the charging circuit 57, which in this embodiment is embodied by a current generator, coupled between the input node I and the pump node CP, and connected in series with a third switch S3, which is placed between the current generator 57 and the pump node CP. The current generator 57 injects a charging current ICTRL in the pump node CP, whose value is controlled, for example, in proportion to the error signal E.

[0069] When the fourth switch S4 is closed, this charging current ICTRL is supplied to the energy storage capacitor CTANK.

[0070] A load resistor RLOAD is shown in parallel with the energy storage capacitor CTANK to represent a load coupled to the output node OUT. This load is intended to be an internal load to the integrated circuit 50 due to the current consumption of the pre-driver 20 and the external FET 30.

[0071] The flying capacitor CFLY and the tank capacitor CTANK may be internal or external to the integrated circuit, depending on the implementation cost.

[0072] When the mode selection signal SEL MODE indicates the charge pump mode (VIN is below the nominal value), the clock generator 54 generates four selection signals based on two clock signals CLK and CLKN that are inverted (i.e., one is the inverted of the other). These clock signals CLK and CLKN are generated by the clock generator 54 starting from a master clock that is usually present in each integrated circuit. The clock signals CLK and CLKN have a dead time between them to avoid cross conduction from the input voltage VIN to the ground GND through the path S1-S2.

[0073] The first selection signal CLKNS1 is equal to the fourth selection signal CLKNS4, and the second selection signal CLKS2 is equal to the third selection signal CLKS3.

[0074] In the first clock CLK phase PH1, switches S2 and S3 are closed. S1 and S4 are open. The flying capacitor CFLY is charged between the ground GND and the input voltage VIN, and the current is determined by the charging current value of ICTRL. The output load, such as RLOAD, is fed by the energy storage capacitor CTANK.

[0075] In the second clock CLK phase PH2, switches S2 and S3 are open. S1 and S4 are closed. The common node CM rises to the input voltage VIN value, and the pump node CP is bootstrapped to a voltage higher than the input voltage VIN. The charging current ICTRL is turned OFF, and the output load is fed by the flying capacitor CFLY through the fourth switch S4.

[0076] exist Figure 6 The figure shows that Figure 3 0047] A timing diagram of the input voltage VIN, the output voltage VOUT, the clock signal CLK and its inverse CLKN as a function of time t in a charge pump mode in an embodiment of a circuit of FIG.

[0077] Initially, there is a power-up phase PU, in which the circuit 51 operates in linear mode, and then the charge pump mode starts.

[0078] As shown in the figure, the input voltage VIN here is 8 volts, so once the PU stage is terminated, the voltage monitor will signal through the SEL MODE signal to operate in the charge pump mode.

[0079] It can be seen that, as indicated above, at the beginning of the second phase PH2, the pump node CP is bootstrapped to a voltage higher than the input voltage VIN, and the output load is fed by the flying capacitor CFLY through the fourth switch S4, the output voltage OUT increases sharply, while during the first phase, the output node OUT was fed by the energy storage capacitor CTANK, as shown by the small drop in the output voltage when such capacitor is discharged.

[0080] When the mode selection signal SEL MODE indicates a linear mode (VIN exceeds a nominal value, for example, exceeds 12V), the switches S1, S2, S3, S4 are controlled differently, in particular independently. The first switch S1 is always open, and the other switches S2, S3, and S4 are always closed. In this configuration, the common node CM is connected to the ground GND, and the flying capacitor CFLY is connected in parallel with the energy storage capacitor CTANK (considering that the resistance of the switches S4 and S2 is negligible).

[0081] The desired output voltage VOUT in the linear mode and the charge pump mode is obtained by sensing the output voltage VOUT with the resistor divider 54 (i.e., resistors RREF1 and RREF2), comparing it with the reference voltage VREF, and controlling the charging current ICTRL accordingly based on the error E. The charging current ICTRL has a maximum value to limit the output current in the event of a fault, such as an output short to ground, a capacitor plate short, etc.

[0082] exist Figure 7 The figure shows that Figure 4 3 is a timing diagram of an input voltage VIN, an output voltage VOUT, a clock signal CLK and four switch selection signals CLKNS1 , CLKS2 , CLKS3 , CLKNS4 as a function of time t in a linear mode in an embodiment of a circuit of .

[0083] Initially, there is a power-up phase PU, in which the circuit 51 operates in the linear mode, and then it remains in the linear mode.

[0084] As shown in the figure, the input voltage VIN here is 14V, so the voltage monitor is signaled by the MODE SEL signal to operate in the linear mode.

[0085] In the example shown here, the value of the output voltage VOUT can be 12V, the input voltage VIN can be 8V, the reference voltage VREF can be 1.2V, the resistors RREF1 and RREF2 can be 900kΩ and 100kΩ respectively, the signal CLK main frequency can be 200kHz, the load resistor RLOAD can range between 500Ω and 1kΩ, the flying capacitor CFLY can be 1uF, and the energy storage capacitor CTANK can be 4.7uF. Usually the capacitors CFLY and CTANK are external components because the ripple requirements on the output voltage force the use of capacitors in the uF range.

[0086] exist Figure 4 In FIG. 6 , a second embodiment of the regulating circuit 61 is shown. In the following, a second embodiment of the proposed solution is reported.

[0087] This circuit corresponds to the circuit 51 except for the location of the current generator 57 embodying the charging circuit, which in this case is coupled between the pump node CP and the output node, upstream of the fourth switch S4, which then allows the charging current ICTRL to reach the output node O and charge the energy storage capacitor CTANK when it is closed. In other words, Figure 3 In the embodiment of the present invention, the current generator 57 is connected in series with the third switch S3, and Figure 4 In the embodiment of FIG. 5 , generator 57 is placed in series with switch S4.

[0088] exist Figure 5 , a third embodiment 71 of a regulating circuit is shown.

[0089] The difference between these embodiments still lies in the charging circuit, however, the charging circuit is indicated by reference numeral 67 and includes a PWM generator 67a, which receives the error signal E from the differential amplifier 56 and outputs a PWM output signal PWE, which directly drives the opening and closing of the third switch S3, rather than being driven by the generator 54. The third selection signal CLKS3 is introduced as an input of the PWM generator 67a, that is, the third switch S3 is controlled by the PWM generator 67a.

[0090] Therefore, the error signal E between the reference voltage VREF and the sensed output voltage VOUT_DIV is converted into a pulse signal PWE with a variable width. The pulse controls the on / off time of the third switch S3, thereby controlling the total current charging the energy storage capacitor CTANK and thus controlling the regulated voltage VOUT.

[0091] For example, if the sensed output voltage VOUT_DIV is lower than the reference voltage VREF, the PWM generator 67a reacts by increasing the on-time of the switch S3. On the other hand, if the sensed output voltage VOUT_DIV is higher than the reference voltage VREF, the PWM generator 67a reacts by reducing the on-time of the switch S3 until the switch S3 is completely turned off, which is a "pulse skipping" behavior.

[0092] As mentioned, the PWM generator 67a receives a clock signal, signal CLK S3, which in other embodiments controls S3 to be in charge pump mode and it is shielded from PWM modulation.

[0093] exist Figure 8, an embodiment of a voltage monitor 53 is schematically shown, which includes two input multiplexers 531, whose two inputs are coupled together through a hysteresis resistor RHYST, and one of the inputs is also coupled to an input node I through a monitoring resistor RMON2 and the other input is coupled to ground GND through another monitoring resistor RMON1. The output of the multiplexer 531 is one of the inputs of a comparator 532, which receives a reference voltage VREF at another input and outputs a mode selection signal MODE SEL, i.e. Fig. 9 The logic signal shown in , when logic high indicates the linear mode LM and when logic low indicates the charge pump mode.

[0094] The mode selection signal MODE SEL is introduced as a selection signal of the multiplexer 531 to generate hysteresis on the threshold value.

[0095] The selection of the operating mode - linear mode or charge pump mode - is performed by the voltage monitor 53 which senses the input VIN as follows:

[0096] If the input voltage VIN is lower than the first predefined threshold VTHHL, it means that the charge pump mode needs to be selected with MODE SEL to increase the output voltage until the desired value is reached;

[0097] Otherwise, if the input voltage VIN is above the predefined threshold VTHLH, it means that the linear mode is sufficient to guarantee the desired value of the output voltage while saving power consumption. In fact, in this case, the linear mode is preferred because the power consumed during the charge pump switching is not present in the linear mode.

[0098] The first threshold value VTHLH is greater than the second threshold value VTHH, in particular by a hysteresis voltage VTHYST.

[0099] The voltage monitor 53 is provided with a hysteresis obtained by a hysteresis resistor RHYST to prevent possible oscillations of the output regulated voltage during the transition from charge pump and linear mode and vice versa. Thus, the thresholds can be set with hysteresis, i.e., from low to high thresholds, e.g., VTHLH=10.5V, and from high to low thresholds, e.g., VTHHL=10V, VTHYST of 0.5V is hysteresis.

[0100] Once the values ​​of VREF, RMON1, RMON2, and RHYST are defined, the thresholds can be obtained using the known equations reported below. Typical values ​​for these parameters are VREF = 1.2V, RMON1 = 95kΩ, RMON2 = 730kΩ, and RHYST = 5kΩ.

[0101]

[0102]

[0103] VTH HysT =VTH LH -VTH HL =500mV

[0104] The voltage monitor in a variant embodiment may use a comparator without hysteresis, ie with a single threshold, in other words, the first voltage threshold and the second threshold have equal values.

[0105] Fig. 9 Shows Figure 3 Timing diagram of the circuit behavior when transitioning between linear mode and charge pump mode.

[0106] The time diagram shows Figure 7 and Figure 8 and a mode selection signal MODE SEL, which indicates a linear mode LM when logic high and a pump charging mode when logic low.

[0107] Under applicable conditions, the input voltage VIN may experience changes in its value due to transient load conditions or environmental conditions (i.e., low temperature operation). In this case, the voltage monitor 53 detects a low battery condition (in the figure, the input voltage VIN drops from 14V to below 10V, below VTHHL), and activates the charge pump mode CPM, which restores the output voltage VOUT to the desired value. It can also be observed in the figure that when the input voltage VIN exceeds 10.5V, exceeding VTHLH, the circuit 52 enters the linear mode.

[0108] exist Fig.10 It is shown in Figure 3 The implementation details of the circuit are shown in FIG. The switches S1, S2, S3, and S4 are implemented by high voltage (eg, high voltage MOSFET) switches and driven by corresponding drivers DRV1, DRV2, DRV3, and DRV4.

[0109] The third switch S3 consists of two switches S3A, S3B coupled in series between the input node I and the pump node CP: the switch S3A coupled to the input node I and receiving the error signal E at its control input is used to limit the current and to close the control loop regulating the output voltage VOUT. The switch S3B coupled to the pump node CP is driven by a driver DRV3, wherein one of the selection signals, namely CMD3, i.e. essentially the third switch signal, is used to prevent reverse current from flowing into the input voltage VIN when the charge pump mode is active in the bootstrap phase. In the linear mode, S3B is always active, i.e. closed.

[0110] The clock generator 54 generates commands CMD1 , CMD2 , CMD3 , and CMD4 for the pre-drivers DRV1 , DRV2 , DRV3 , DRV4 , which correspond in behavior to the switching signals CLKNS1 , CLKS2 , CLKS3 , CLKNS4 .

[0111] In charge pump mode, commands CMD1 and CMD4 are therefore in antiphase with CMD2 and CMD3, and there is a dead time between them. In linear mode, S3A, S3B, S4 and S2 are always on, while S1 remains off.

[0112] The low voltage drop control module 58 is inserted between the error signal E and the gate of the switch S3A and is configured to force the switch S3A to operate with a full or limited gate-source voltage VGS voltage according to the current required by the load.

[0113] The low voltage drop control module 58 consists of a comparator provided with a certain threshold and an analog circuit that controls the gate-source voltage of the switch S3A. The comparator senses the drain voltage of the switch S3A, and the analog circuit reacts by setting the gate-source voltage of S3A to a full range or a limited range. In the case where the load requires a high current, a high voltage drop occurs on the switch S3A, and therefore the drain voltage drops below the comparator threshold, so the low voltage drop control module limits the gate-source voltage of the switch S3A to limit the load current. Otherwise, if the load requires a low current, a low voltage drop occurs on the switch S3A, and therefore the drain voltage increases above the comparator threshold, so the low voltage drop control module forces the full gate-source voltage to reduce the on-resistance of the MOSFET switch S3A and keep the voltage drop of the switch S3A as low as possible. The reduced voltage drop on the switch S3A improves the system performance (i.e., the desired VOUT voltage and the gate-source voltage of the external FET).

[0114] Figure 4 , Figure 5 , Figure 6 A typical application of the circuit in the embodiments is to control a brushless DC three-phase motor drive.

[0115] In this case, the voltage regulator 51 is equipped with a flying capacitor CFLY1 and a storage capacitor CVPRE. Node CP1M corresponds to the common node CM, and node CP1P corresponds to the pump node CP. The circuit powered by the input voltage VIN indicated by VBP is responsible for powering the gate pre-driver 20 of the low-side and high-side external FETs 30. According to the application battery (depending on the vehicle 12V, 24V or 48V) voltage VBP is directly shorted to the battery voltage VBAT (i.e. 12V or 24V) or obtained by the battery voltage VBAT through a buck converter. Connect the decoupling capacitor CVBP to eliminate battery noise. In this case, reference numeral 30 indicates three half-bridge circuits of the three phases of the drive motor M, and includes three high-side FETs and three low-side FETs, and 20 indicates six corresponding pre-drivers. In this case, the low-side pre-driver gate voltage is powered by the output voltage VOUT of the circuit 51, and the high-side pre-driver voltage is powered by the bootstrap capacitor CBTx, which is coupled through the power supply terminal of the driver 20, and it is pre-charged by the voltage of the circuit 51.

[0116] 80 indicates a logic module that provides signals for driving three half-bridge circuits.

[0117] The second regulator 81 as a charge pump exists only to improve the performance of the system and can help provide charging current to turn off the high side FET 30 only when the motor control strategy calls for a high duty cycle.

[0118] The FET transistors in variant embodiments may be any type of field effect transistor used in bridge and half-bridge circuits, such as MOSFETs, in particular for driving electric motors.

[0119] The described solution thus has several advantages over prior art solutions.

[0120] The circuits described herein allow for providing a voltage regulator with an output that is higher or lower than the input voltage, wherein through the described architecture, only external capacitors are required or otherwise utilized, thereby avoiding the use of expensive external components such as inductors, FETs or diodes.

[0121] Of course, without prejudice to the principle of the present disclosure and without departing from the scope of the present disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example.

[0122] The electronic circuit (51) for regulating the voltage (VIN) received at its input can be summarized as comprising

[0123] A configurable voltage regulation circuit (52) comprising: a first switch (S1) coupled between an input node (I) and a common mode node (CM), a second switch (S2) coupled between the common mode node (CM) and a ground node (GND), a flying capacitor (CFLY) coupled between the common mode node (CM) and a pump node (CP), a third switch (S3) coupled between the input node (I) and the pump node (CP), a fourth switch coupled between the pump node (CP) and an output node (O) of a circuit (51) for regulating a voltage (VIN), the circuit further comprising: a sensing resistor network (55), in particular a resistor divider, coupled between the output node (O) and an input of an error amplifier (56) to provide a sensed output voltage (V DIV_OUT), the error amplifier (56) receives a reference voltage (VREF) at its other input and generates an error signal (E); a charging circuit (57; 67) for providing a charging current (ICTRL) to the pump node (CP), the charging circuit (ICTRL) controlling the value of the charging current (ICTRL) according to the error control signal (E); a switch command signal generator (54) configured to generate corresponding first, second, third and fourth switch signals to control the first switch (S1), the second switch (S2), the third switch (S3) and the fourth switch (S4), respectively, if the input voltage is lower than a first threshold, the generator (54) is configured to: generate a first (CLKN) driven by the opposite phase of the clock signal (CLK) The configurable voltage regulating circuit (52) is configured to be a charge pump by generating a first switching signal (CLKS1) and a second switching signal (CLKS2) to alternately couple the common mode to the input voltage and the ground and to generate a third (CLKS3) and a fourth switching signal (CLKNS4) driven by opposite phases of the clock signal (CLK) to alternately couple the pump node (CP) to the output node (O) and the charging circuit (57; 67), and if the input voltage is greater than a second threshold, the generator (54) is configured to set the configurable voltage regulating circuit (52) as a linear regulator by generating a first switching signal (CLKNS1) to keep the first switch (S1) open and second, third and fourth switching signals (CLKS2, CLKS3, CLKNS4) to keep the second (S2), third (S3) and fourth (S4) switches closed.

[0124] The configurable regulating circuit (52) may include a voltage monitoring circuit (53) configured to monitor the value of the input voltage (VIN) and, according to whether the value of the input voltage (VIN) is lower than a first threshold value (VTHHL) or higher than a second threshold value (VTHLH), issue a corresponding first (CMP) operation command or a second (LM) operation mode command (SEL MODE) to the switch command signal generator (54).

[0125] A storage capacitor (CTANK) may be coupled between the output node (O) and ground (GND).

[0126] The charging circuit may be a controlled current generator (57)

[0127] The controlled current generator (57) may be coupled between the input node and the pump node

[0128] The controlled current generator may be coupled between the pump node and the output node

[0129] The charging circuit may include a PWM signal generator (67) for generating a PWM signal (PWE) proportional to the error signal (E), the PWM signal (PWE) driving the open and closed states of the third switch (S3).

[0130] The voltage monitor (53) may be configured as a voltage comparator with hysteresis having a first predefined threshold (VTHHL) and a second predefined threshold (VTHLH) greater than the first predefined threshold (VTHHL).

[0131] A circuit arrangement for controlling an electric motor can be summarized as comprising a plurality of half-bridge circuits, wherein switching transistors (30) are driven by respective driver circuits (20) providing each of the transistors (30) with a controlled gate-source voltage, the driver circuits (20) being supplied with a regulated voltage through the circuit arrangement.

[0132] A method for regulating a voltage, comprising an electronic circuit (51) for regulating a voltage (VIN) received at its input, can be summarized as comprising: generating respective first, second, third and fourth switching signals to control the first switch (S1), the second switch (S2), the third switch (S3) and the fourth switch (S4), respectively, if the input voltage is below a first threshold, setting a configurable voltage regulating circuit (52) as a charge pump by generating first (CLKN S1) and second switching signals (CLK S2) driven by an inverse of a clock signal (CLK) to alternately couple a common mode to the input voltage and ground and generating third (CLK S3) and fourth switching signals (CLKN S4) driven by an inverse of the clock signal (CLK) to alternately couple a pump node (CP) to an output node (O) and a charging circuit (57; 67), if the input voltage is greater than a second threshold, the generator (54) switching the first switch (S1) to the charge pump by generating a first switching signal (CLKN S1) to keep the first switch (S1) open. S1) and second, third and fourth switch signals (CLK S2, CLK S3, CLK N S4) that keep the second (S2), third (S3) and fourth (S4) switches closed to set the configurable voltage regulation circuit (52) as a linear regulator.

[0133] The method may include monitoring the value of an input voltage (VIN), and issuing a corresponding first (CMP) operation command or a second (LM) operation mode command (SEL MODE) to the switch command signal generator (54) according to whether the value of the input voltage (VIN) is lower than a first threshold (VTHHL) or higher than a second threshold (VTHLH).

[0134] The second predefined threshold (VTHLH) may be greater than the first predefined threshold (VTHHL).

[0135] The various embodiments described above may be combined to provide additional embodiments. These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. An electronic circuit comprising: an input node configured to receive an input voltage; as well as Configurable voltage regulation circuitry including: a first switch coupled between the input node and a common mode node; a second switch coupled between the common mode node and a ground node; a flying capacitor coupled between the common mode node and a pump node; a third switch coupled between the input node and the pump node; a fourth switch coupled between the pump node and an output node; an error amplifier having a first input and a second input; a sense resistor network coupled between the output node and the first input of the error amplifier, the sense resistor network configured to provide a sensed output voltage at the first input of the error amplifier, the error amplifier receiving a reference voltage at the second input and configured to generate an error signal; a charging circuit configured to supply a charging current to the pump node, the charging circuit configured to control a value of the charging current according to the error signal; and a switch command signal generator configured to generate corresponding first switch signal, second switch signal, third switch signal and fourth switch signal to control the first switch, the second switch, the third switch and the fourth switch respectively, wherein if the input voltage is below a first threshold, the switch command signal generator is configured to set the configurable voltage regulating circuit as a charge pump by generating the first switch signal and the second switch signal driven by opposite phases of a clock signal to alternately couple the common mode node to the input voltage and the ground, and generating the third switch signal and the fourth switch signal driven by opposite phases of the clock signal to alternately couple the pump node to the output node and the charging circuit, and If the input voltage is greater than a second threshold, the switch command signal generator is configured to set the configurable voltage regulation circuit as a linear regulator by generating the first switch signal to keep the first switch open and the second switch signal, the third switch signal and the fourth switch signal to keep the second switch, the third switch and the fourth switch closed.

2. The circuit according to claim 1, wherein the configurable voltage regulation circuit comprises a voltage monitoring circuit, which is configured to monitor the value of the input voltage and issue a corresponding first operation command or a second operation mode command to the switch command signal generator according to whether the value of the input voltage is lower than a first threshold or higher than a second threshold.

3. The circuit of claim 1, wherein the configurable voltage regulation circuit comprises a storage capacitor coupled between the output node and the ground.

4. The circuit of claim 1, wherein the charging circuit is a controlled current generator.

5. The circuit of claim 4, wherein the controlled current generator is coupled between the input node and the pump node.

6. The circuit of claim 4, wherein the controlled current generator is coupled between the pump node and the output node.

7. The circuit according to claim 1, wherein the charging circuit comprises a pulse width modulation (PWM) signal generator, the pulse width modulation (PWM) signal generator being configured to generate a PWM signal proportional to the error signal, the PWM signal being configured to drive the operation of the third switch to an open state or a closed state.

8. The circuit of claim 2, wherein the voltage monitoring circuit is configured as a voltage comparator with hysteresis having a first predefined threshold and a second predefined threshold greater than the first predefined threshold.

9. A circuit for controlling a motor, comprising: a plurality of half-bridge circuits, each half-bridge circuit of the plurality of half-bridge circuits comprising a corresponding transistor; a plurality of driver circuits, each of the plurality of driver circuits being configured to: provide a controlled gate-source voltage to a corresponding transistor of a corresponding one of the plurality of half-bridge circuits; as well as A configurable voltage regulating circuit configured to supply a regulated voltage to the plurality of driving circuits, the configurable voltage regulating circuit comprising: a first switch coupled between the input node and the common mode node; a second switch coupled between the common mode node and a ground node; a flying capacitor coupled between the common mode node and a pump node; a third switch coupled between the input node and the pump node; a fourth switch coupled between the pump node and an output node; an error amplifier having a first input and a second input; a sense resistor network coupled between the output node and the first input of the error amplifier, the sense resistor network configured to provide a sensed output voltage at the first input of the error amplifier, the error amplifier receiving a reference voltage at the second input and configured to generate an error signal; a charging circuit configured to supply a charging current to the pump node, the charging circuit configured to control a value of the charging current according to the error signal; and a switch command signal generator configured to generate corresponding first switch signal, second switch signal, third switch signal and fourth switch signal to control the first switch, the second switch, the third switch and the fourth switch, respectively; wherein if the input voltage is below a first threshold, the switch command signal generator is configured to set the configurable voltage regulating circuit as a charge pump by generating the first switch signal and the second switch signal driven by opposite phases of a clock signal to alternately couple the common mode node to the input voltage and the ground, and generating the third switch signal and the fourth switch signal driven by opposite phases of the clock signal to alternately couple the pump node to the output node and the charging circuit, and If the input voltage is greater than a second threshold, the switch command signal generator is configured to set the configurable voltage regulation circuit as a linear regulator by generating the first switch signal to keep the first switch open and the second switch signal, the third switch signal and the fourth switch signal to keep the second switch, the third switch and the fourth switch closed.

10. The circuit according to claim 9, wherein the configurable voltage regulation circuit comprises a voltage monitoring circuit, which is configured to monitor the value of the input voltage and issue a corresponding first operation command or a second operation mode command to the switch command signal generator according to whether the value of the input voltage is lower than a first threshold or higher than a second threshold.

11. The circuit of claim 9, wherein the configurable voltage regulation circuit comprises a storage capacitor coupled between the output node and the ground.

12. The circuit of claim 9, wherein the charging circuit is a controlled current generator.

13. The circuit of claim 12, wherein the controlled current generator is coupled between the input node and the pump node.

14. The circuit of claim 12, wherein the controlled current generator is coupled between the pump node and the output node.

15. The circuit according to claim 9, wherein the charging circuit comprises a pulse width modulation (PWM) signal generator configured to generate a PWM signal proportional to the error signal, the PWM signal configured to drive the operation of the third switch to an open state or a closed state.

16. The circuit of claim 10, wherein the voltage monitoring circuit is configured as a voltage comparator with hysteresis having a first predefined threshold and a second predefined threshold greater than the first predefined threshold.

17. A method for regulating voltage, comprising: receiving an input voltage at an input node; Generate corresponding first switch signal, second switch signal, third switch signal and fourth switch signal to respectively control the first switch, second switch, third switch and fourth switch of the configurable voltage regulation circuit, the configurable voltage regulation circuit comprising: a flying capacitor coupled between a common mode node and a pump node; an error amplifier having a first input and a second input; a sensing resistor network coupled between an output node and the first input of the error amplifier, the sensing resistor network being configured to provide a sensed output voltage at the first input of the error amplifier, the error amplifier being configured to receive a reference voltage at the second input and generate an error signal; and a sensing resistor network being configured to supply a charge to the pump node. a charging circuit for a charging current, the charging circuit being configured to control a value of the charging current according to the error signal; and a switch command signal generator, the switch command signal generator being configured to generate corresponding first, second, third and fourth switch signals to control the first, second, third and fourth switches, respectively, wherein the first switch is coupled between the input node and the common mode node, the second switch is coupled between the common mode node and a ground node, the third switch is coupled between the input node and the pump node, and the fourth switch is coupled between the pump node and the output node; If the input voltage is below a first threshold, the configurable voltage regulating circuit is configured as a charge pump by generating the first switching signal and the second switching signal driven by opposite phases of a clock signal to alternately couple the common mode node to the input voltage and the ground, and generating the third switching signal and the fourth switching signal driven by opposite phases of the clock signal to alternately couple the pump node to the output node and the charging circuit, If the input voltage is greater than a second threshold, the switch command signal generator sets the configurable voltage regulation circuit as a linear regulator in the following manner: generating the first switch signal to keep the first switch open, and the second switch signal, the third switch signal, and the fourth switch signal to keep the second switch, the third switch, and the fourth switch closed.

18. The method according to claim 17, further comprising: The value of the input voltage is monitored, and according to whether the value of the input voltage is lower than a first threshold or higher than a second threshold, a corresponding first operation command or a second operation mode command is issued to the switch command signal generator. The method of claim 18 , wherein the second threshold is greater than the first threshold.

20. The method of claim 17, further comprising: Generating a PWM signal proportional to the error signal by a pulse width modulation (PWM) signal generator; as well as The operation of the third switch is driven to an open state or a closed state by the PWM signal.

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