An inductive boost five-level inverter and its control method

Abstract

The present invention discloses an inductance boost type five-level inverter and its control method. Among them, the five-level inverter includes a DC power supply, an inductor L, a capacitor C, a switching tube S1, a switching tube S2, a switching tube S3, a switching tube S4, a switching tube S5, and a switching tube S6. Compared with the existing five-level inverter, the five-level inverter of the present invention has 6 working modes, only requires 1 DC power supply, 1 inductor, 1 capacitor and 6 switching tubes, its structure and control are simpler, has fewer switching devices and energy storage elements, and lower total voltage stress of the switching devices, and has the ability of boost and capacitor voltage self-balancing.

Description

Technical Field

[0001] The present invention relates to the technical field of multilevel inverters, and particularly to an inductor-boost type five-level inverter and a control method thereof. Background Art

[0002] Compared with traditional two-level inverters, multilevel inverters have the advantages of low total harmonic distortion rate of output, less loss, and low electromagnetic interference because their output waveforms are closer to sine waves. In recent years, multilevel inverters have received extensive attention and have been successfully applied in fields such as motor drive, photovoltaic power generation, static compensators, and high-voltage direct current transmission.

[0003] Traditional multilevel inverter topologies include: diode-clamped type, flying-capacitor type, and cascaded H-bridge type. Diode-clamped type and flying-capacitor type multilevel inverters contain more switching devices and energy storage elements, and have poor self-balancing ability of capacitor voltages, and auxiliary circuits need to be added to achieve the balance of capacitor voltages. The cascaded H-bridge multilevel inverter realizes multilevel output through the series connection of the output terminals of multiple H-bridge inverters, has the advantages of simple control, high circuit reliability, easy modularization, etc., and has no capacitor voltage imbalance problem, but its disadvantage is that it requires multiple independent DC power supplies. In addition, the above traditional multilevel inverter topologies have no boosting ability, and their applications in low-voltage input occasions will be limited.

[0004] To solve the above problems existing in traditional multilevel inverters, researching new multilevel inverter topologies has become an important research issue in multilevel inverter technology.

[0005] The prior art discloses a five-level inverter and a leakage current control method thereof (publication number: CN103178735B), wherein, for the five-level inverter, a series-connected first switching tube and second switching tube are connected in parallel at both ends of the power supply as an additional bridge arm, the conduction states of the first switching tube and the second switching tube are controlled, and a certain control strategy is adopted to make the voltage between the first node of the five-level inverter and the negative terminal of the power supply smoothly transition at the zero crossing point, reduce the spike, and thus reduce the amplitude of the leakage current, but the number of switching tubes used in this invention is relatively large. Summary of the Invention

[0006] The present invention provides an inductor-boost type five-level inverter and a control method thereof to solve the problems existing in the existing five-level inverters, such as large number of components, high total voltage stress of switching devices, poor boosting and self-balancing ability of capacitor voltages, etc.

[0007] To solve the above technical problems, the technical solution of the present invention is as follows:

[0008] An inductor-boost type five-level inverter includes a DC power supply E, an inductor L, a capacitor C, a switching tube S 1 、a switching tube S2 and switching transistor S 3 and switching transistor S 4 and switching transistor S 5 and switching transistor S 6 ; switching transistor S 1 The second pole of switching transistor S, the first end of inductor L, and the first pole of switching transistor S 2 are connected to the first node. The first pole of switching transistor S 1 and the first pole of switching transistor S 5 are both connected to the first end of capacitor C. The second end of inductor L, the second end of capacitor C, and the first pole of switching transistor S 3 are all connected to the positive pole of DC power supply E. The second pole of switching transistor S 2 and the second pole of switching transistor S 6 are both connected to the negative pole of DC power supply E. The second pole of switching transistor S 3 is connected to the second pole of switching transistor S 4 . The first pole of switching transistor S 4 , the second pole of switching transistor S 5 , and the first pole of switching transistor S 6 are all connected to the second node. The first node is the negative voltage output terminal of this five-level inverter, and the second node is the positive voltage output terminal of this five-level inverter. The third pole of switching transistor S 1 , switching transistor S 2 , switching transistor S 3 , switching transistor S 4 , switching transistor S 5 , switching transistor S 6 is connected to the control signal.

[0009] Furthermore, switching transistor S 1 , switching transistor S 2 , switching transistor S 3 , switching transistor S 4 , switching transistor S 5 , switching transistor S 6 are all IGBT transistors. The first pole of switching transistor S 1 , switching transistor S 2 , switching transistor S 3 , switching transistor S 4 , switching transistor S 5 , switching transistor S 6 is the collector of the IGBT transistor, the second pole is the emitter of the IGBT transistor, and the third pole of the IGBT transistor is the gate.

[0010] Furthermore, switching transistor S 1 , switching transistor S 2 , switching transistor S 3 , switching transistor S 4 , switching transistor S 5 , switching transistor S6 are all MOS transistors; the switch transistor S 1 , the switch transistor S 2 , the switch transistor S 3 , the switch transistor S 4 , the switch transistor S 5 , the switch transistor S 6 's first pole is the drain of the MOS transistor, the second pole is the source of the MOS transistor, and the third pole of the MOS transistor is the gate.

[0011] A control method for an inductive boost five-level inverter, the control of the five-level inverter has the following 6 working modes, which are respectively:

[0012] Working mode 1, the switch transistors S 2 , the switch transistors S 4 and the switch transistor S 6 are in the on state, and the rest of the switch transistors are in the off state; the inductor L is connected in parallel across the DC power supply E through the switch transistor S 2 for energy storage, and i L increases linearly; the capacitor C is open; the output terminal of the inverter is short-circuited through the switch transistors S 2 and the switch transistor S 6 , so the output voltage u o = 0;

[0013] Working mode 2, the switch transistors S 2 , the switch transistors S 3 and the switch transistor S 4 are in the on state, and the rest of the switch transistors are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the capacitor C is still open; the DC power supply E supplies power to the load terminal alone, so the output voltage u o = U in ;

[0014] Working mode 3, the switch transistors switch transistors S 2 , the switch transistors S 3 and the switch transistor S 5 are in the on state, and the rest of the switch transistors are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the DC power supply E and the capacitor C are connected in series to supply power to the load terminal together, so the output voltage u o = 2U in ;

[0015] Working mode 4, the switch transistors S 1 , the switch transistors S 3 and the switch transistor S 5 are in the on state, and the rest of the switch transistors are in the off state; the inductor L is connected through the switch transistor S 1Parallel to both ends of the capacitor C for energy release and charging the capacitor, i L Linearly decreases; the output end of the inverter is short-circuited through the switching tube S 1 And the switching tube S 5 So the output voltage u of the inverter o = 0;

[0016] Operating mode 5, the switching tubes S 1 , the switching tube S 3 And the switching tube S 4 Are in the on state, and the rest of the switching tubes are in the off state; the inductor L continues to release energy, and i L Continues to linearly decrease; the capacitor C supplies power to the load end alone, so the output voltage u of the inverter o = -U in ;

[0017] Operating mode 6, the switching tubes S 1 , the switching tube S 4 And the switching tube S 6 Are in the on state, and the rest of the switching tubes are in the off state; the inductor L continues to release energy, and i L Continues to linearly decrease; the DC power supply E and the capacitor C are connected in series to jointly supply power to the load end, so the output voltage u of the inverter o = -2U in ;

[0018] u o And i o Are the output voltage and output current of the inverter respectively, and U in Is the voltage of the DC power supply E of the inverter, and i L Is the current flowing through the inductor L.

[0019] Furthermore, the switching tubes S 1 And the switching tube S 2 Complementary conduct and the duty cycle is 0.5 for both.

[0020] Furthermore, when the switching tube S 2 Is turned off, the switching tube S 1 Is turned on, and the inductor L stores energy, and the voltage across it is U in ; when the switching tube S 1 Is turned off, the switching tube S 2 Is turned on, and the inductor L releases energy, and the voltage across it is -U C ; in the steady state, according to the volt-second balance principle of the inductor, it can be obtained that

[0021]

[0022] In the formula, u C Is the voltage across the capacitor C, and T oFor the inverter output period, (1) the solution gives

[0023] U C = U in (9).

[0024] Furthermore, the five-level inverter adopts the lowest-level approximation modulation strategy.

[0025] Furthermore, the lowest-level approximation modulation strategy uses a sine wave u r with the same frequency and phase as the fundamental wave of the inverter output voltage as a reference, and makes the inverter output voltage waveform approximate the sine wave by controlling the duration of each level.

[0026] Furthermore, the Fourier series expansion of the inverter output voltage u o is performed, and the expression is as follows:

[0027]

[0028] In the formula, ω o is the inverter output angular frequency, ω o = 2π / T o ; θ 1 represents the phase of U in , θ 2 represents the phase of 2U in , and 0 ≤ θ 1 ≤ θ 2 ≤ π / 2.

[0029] Furthermore, the inverter provides energy for the load through the fundamental wave, then the fundamental wave amplitude expression of u o is:

[0030]

[0031] When both θ 1 and θ 2 are zero, the maximum fundamental wave amplitude of the inverter output voltage is:

[0032]

[0033] Then the modulation index M I of the inverter can be defined as:

[0034]

[0035] The THD of the inverter output voltage u o is:

[0036]

[0037] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0038] The inductive boost five-level inverter of the present invention only requires 1 DC power supply, 1 inductor, 1 capacitor and 6 switching devices. Compared with the existing five-level inverters, the structure and control are simpler, with fewer switching devices and energy storage elements and lower total voltage stress of the switching devices, and it has the capabilities of boosting and self-balancing of the capacitor voltage. Description of the Drawings

[0039] The drawings are only for illustrative purposes and should not be construed as a limitation of the present invention;

[0040] To better illustrate this embodiment, some components in the drawings are omitted, enlarged or reduced, and do not represent the dimensions of the actual product;

[0041] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0042] Figure 1 Schematic diagram of the inductive boost five-level inverter provided by the embodiment of the present invention;

[0043] Figures 2a - 2f Schematic diagrams of equivalent circuits of operating modes 1 - 6 corresponding to the five output levels of the inverter provided by the embodiment of the present invention;

[0044] Figure 3 Schematic diagram of the operating waveforms of the inverter provided by the embodiment of the present invention;

[0045] Figure 4 Schematic diagram of the nearest level approximation modulation provided by the embodiment of the present invention;

[0046] Figure 5 is the inverter switching tube S 1 - switching tube S 6 driving control signal waveform diagram;

[0047] Figure 6a and Figure 6b are respectively schematic diagrams of the output voltage and output current waveforms of the inverter with a resistive load provided by the embodiment of the present invention;

[0048] Figure 7a and Figure 7b are respectively schematic diagrams of the inductor current and capacitor voltage waveforms of the inverter provided by the embodiment of the present invention;

[0049] Figure 8a and Figure 8b are respectively schematic diagrams of the output voltage and output current waveforms of the inverter with an inductive load provided by the embodiment of the present invention. Detailed Embodiments

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of protection of the present invention.

[0051] Embodiment 1

[0052] For ease of understanding, please refer to Figure 1 , an embodiment of an inductor boost-type five-level inverter and its control method provided by the present invention. An inductor boost-type five-level inverter includes a DC power supply E, an inductor L, a capacitor C, and switching transistors S 1 , switching transistor S 2 , switching transistor S 3 , switching transistor S 4 , switching transistor S 5 , switching transistor S 6 ; the second pole of switching transistor S 1 , the first end of inductor L, and the first pole of switching transistor S 2 are connected to a first node. The first pole of switching transistor S 1 , and the first pole of switching transistor S 5 are both connected to the first end of capacitor C. The second end of inductor L, the second end of capacitor C, and the first pole of switching transistor S 3 are all connected to the positive pole of DC power supply E. The second pole of switching transistor S 2 , and the second pole of switching transistor S 6 are both connected to the negative pole of DC power supply E. The second pole of switching transistor S 3 is connected to the second pole of switching transistor S 4 . The first pole of switching transistor S 4 , the second pole of switching transistor S 5 , and the first pole of switching transistor S 6 are all connected to a second node. The first node is the negative voltage output terminal of this five-level inverter, and the second node is the positive voltage output terminal of this five-level inverter. The third poles of switching transistors S 1 , S 2 , S 3 , S 4 , S 5 , and S 6 are connected to control signals.

[0053] Compared with the existing five-level inverter, the present invention uses an inductor for boosting, and its structure and control are simpler, with fewer switching devices and energy storage elements and lower total voltage stress of the switching devices, and has the capabilities of boosting and capacitor voltage self-balancing.

[0054] Embodiment 2

[0055] Specifically, on the basis of Embodiment 1, the solution is described in combination with specific implementation examples to further reflect the technical effects of the present solution. Specifically:

[0056] The inductor-boosted five-level inverter is as Figure 1 shown. This topology consists of 1 DC power supply E, 1 inductor L, 1 capacitor C, and switching transistors S 1 -Switching transistor S 6 U in is the voltage of the inverter DC power supply E, and u o and i o are the output voltage and output current of the inverter respectively. The switching transistors S 1 and the switching transistor S 2 are complementarily turned on. When the switching transistor S 2 is turned on, the inductor L stores energy through the DC power supply E; when the switching transistor S 1 is turned on, the inductor L is connected in parallel with the capacitor C and releases energy to charge the capacitor C. By controlling the duty cycles of the switching transistors S 1 and the switching transistor S 2 to be equal, the capacitor voltage can be made equal to the voltage of the DC power supply E. Then, by controlling the on-logic states of all the switching transistors, a voltage gain of 2 times and five-level outputs with amplitudes of ±2U in , ±U in , 0 can be generated.

[0057] For simplified analysis, assume: (1) The inductor L and the capacitor C have no parasitic internal resistance, and the capacitance value is large enough, and the capacitor voltage u C has almost no ripple and its average value U C is equal to the DC power supply voltage U in ; (2) The switching actions of the switching transistors are completed instantaneously, and the on-resistance and on-voltage drop are both zero; the working modes and equivalent circuits corresponding to the five output levels of the inverter are shown in Figure 2, where u C is the voltage across the capacitor C, and i L is the current flowing through the inductor L; the working states of the switching transistors corresponding to each working mode are shown in Table 1.

[0058] Table 1 Working states of switching transistors corresponding to each working mode

[0059]

[0060] A control method for an inductive boost five-level inverter, where "1" and "0" of each switch represent its on and off states respectively, and "↑" and "↓" of the inductor L represent its energy storage and energy release states respectively; the working principles of each working mode are analyzed as follows:

[0061] 1) Working mode 1: As Figure 2a shown; the switch S 2 , the switch S 4 and the switch S 6 are in the on state, and the rest of the switches are in the off state; the inductor L is connected in parallel with the DC power supply E through the switch S 2 for energy storage, and i L increases linearly; the capacitor C is open; the output terminal of the inverter is short-circuited through the switch S 2 and the switch S 6 , so the output voltage u o of the inverter is 0;

[0062] 2) Working mode 2: As Figure 2b shown; the switch S 2 , the switch S 3 and the switch S 4 are in the on state, and the rest of the switches are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the capacitor C is still open; the DC power supply E supplies power to the load terminal alone, so the output voltage u o of the inverter is U in ;

[0063] 3) Working mode 3: As Figure 2c shown; the switch S 2 , the switch S 3 and the switch S 5 are in the on state, and the rest of the switches are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the DC power supply E and the capacitor C are connected in series to supply power to the load terminal together, so the output voltage u o of the inverter is 2U in ;

[0064] 4) Working mode 4: As Figure 2d shown; the switch S 1 , the switch S 3 and the switch S 5 are in the on state, and the rest of the switches are in the off state; the inductor L is connected in parallel with the capacitor C through the switch S 1 to release energy and charge the capacitor, and i L decreases linearly; the output terminal of the inverter is short-circuited through the switch S 1 and the switch S5 is short - circuited, so the output voltage u of the inverter o = 0;

[0065] 5) Operating mode 5: As Figure 2e shown; The switching transistors S 1 , switching transistor S 3 and switching transistor S 4 are in the on - state, and the rest of the switching transistors are in the off - state; The inductor L continues to release energy, and i L continues to decrease linearly; The capacitor C supplies power to the load terminal alone, so the output voltage u of the inverter o = -U in ;

[0066] 6) Operating mode 6: As Figure 2f shown; The switching transistors S 1 , switching transistor S 4 and switching transistor S 6 are in the on - state, and the rest of the switching transistors are in the off - state; The inductor L continues to release energy, and i L continues to decrease linearly; The DC power supply E and the capacitor C are connected in series to supply power to the load terminal together, so the output voltage u of the inverter o = -2U in .

[0067] According to Figures 2a - 2f and Table 1, combined with the symmetry of the positive and negative half - cycles of the inverter output AC voltage, it can be known that the switching transistors S 1 and S 2 conduct complementarily and the duty cycle of both is 0.5; When the switching transistor S 2 is off, the switching transistor S 1 is on, and the inductor L stores energy, and the voltage across it is U in ; When the switching transistor S 1 is off, the switching transistor S 2 is on, and the inductor L releases energy, and the voltage across it is -U C ; In the steady state, according to the volt - second balance principle of the inductor, we can get

[0068]

[0069] where T o is the output period of the inverter; Solving Equation (1) gives

[0070] U C = U in (16)

[0071] The above formula (2) shows that in the ideal case, the average value of the capacitor voltage U C is the same as the DC power supply voltage U inThey are equal, verifying the correctness of the aforementioned assumption, providing a basis for subsequent analysis, and also indicating that the inverter of the present invention has the characteristic of self - balancing capacitor voltage; in addition, according to Figures 2a - 2f it is obtained that the maximum voltage stress of the switching transistors S 1 , S 2 , S 5 and S 6 is 2U in , and the maximum voltage stress of the switching transistors S 3 and S 4 is U in .

[0072] Common modulation strategies for multilevel inverters include space vector modulation, carrier modulation, specific harmonic elimination, and nearest level approximation modulation, etc.; the switching frequencies of space vector modulation and carrier modulation are much higher than the inverter output frequency, with large switching losses, and they are more suitable for low - frequency output occasions; specific harmonic elimination and nearest level approximation modulation have lower switching frequencies and small switching losses, and are suitable for high - and low - frequency output occasions; specific harmonic elimination can eliminate specific harmonics of the inverter output voltage, but as the number of levels increases, the solution of each phase angle will become very difficult; nearest level approximation modulation makes the inverter output voltage waveform approximate a sine wave by controlling the duration of each level. Although it cannot guarantee the elimination of specific harmonics, it can eliminate more harmonic components, thus achieving a lower THD (Total Harmonic Distortion). The present invention adopts nearest level approximation as the modulation strategy for the inverter; the working waveform of the five - level inverter is as Figure 3 shown. In the figure, θ 1 represents the phase of U in , θ 2 represents the phase of 2U in , and 0 ≤ θ 1 ≤ θ 2 ≤ π / 2. As Figure 4 shown, the value of θ 1 should make the areas of the two gray - shaded regions equal, and the value of θ 2 should make the areas of the two line - filled regions equal; by changing the amplitude A r of the sine wave u r , a series of θ 1 and θ 2 can be calculated.

[0073] Embodiment 3

[0074] Specifically, on the basis of Embodiment 1, the solution is described in combination with specific implementation examples to further reflect the technical effects of the solution. Specifically:[[]]

[0075] To verify the feasibility and superiority of the five-level inverter proposed in the present invention, a simulation model of the five-level inverter was built on the Matlab / Simulink simulation platform for simulation verification; the simulation parameters are as follows: the DC power supply voltage U in = 100 V, the capacitor C = 470 μF, the inductor L = 30 mH, the output frequency f o of the inverter = 500 Hz, and the load of the inverter is a resistive-inductive load of 50 Ω + 10 mH;

[0076] Figure 5 Shown are the drive control signals of the switching tubes S 1 -S 6 ; it can be seen that S 1 and S 2 are complementary, S 3 and S 6 are complementary, S 4 and S 5 are complementary, which is consistent with the theoretical analysis; in addition, the duty cycles of S 1 and S 2 are 0.5, so the charging and discharging times of the inductor L are equal, making the capacitor voltage U C equal to the power supply voltage U in , which is consistent with the theoretical analysis;

[0077] Figure 6a And Figure 6b Shown are the output voltage and output current waveforms of the inverter with a resistive load (50 Ω); it can be seen that both the output voltage and current of the inverter are five-level waveforms with a frequency of 500 Hz, which is consistent with the theoretical values; in addition, the amplitude of the output voltage of the inverter is about 200 V, which is twice the voltage of the DC power supply E, verifying the boosting ability of the five-level inverter of the present invention;

[0078] Figure 7a And Figure 7b Shown are the inductor current and capacitor voltage waveforms of the inverter respectively; it can be seen that the inductor current is a triangular wave, and its measured average value is about 4.28 A and the ripple value is about 3.3 A; within the interval when S 2 is turned on, the inductor current rises linearly; within the interval when S 1 is turned on, the inductor current drops linearly, which is consistent with the theoretical analysis; in addition, the measured average value of the capacitor voltage is about 99.7 V, the ripple value is about 3.7 V, and the capacitor charging and discharging intervals within one output cycle of the inverter are consistent with the theoretical analysis, verifying the capacitor voltage self-balancing characteristic of the five-level inverter of the present invention;

[0079] Figure 8a And Figure 8bThe waveforms of the output voltage and output current of the inverter with an inductive load (50Ω - 10mH) are shown; it can be seen that the output voltage of the inverter is still a five-level waveform, while the output current becomes a sine wave under the filtering effect of the load inductor and lags behind the output voltage by a certain phase, indicating that the five-level inverter of the present invention can supply power to an inductive load.

[0080] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A control method for an inductor boost five-level inverter, characterized in that, It includes a boost-type five-level inverter, which includes a DC power supply E, an inductor L, a capacitor C, and switching tubes S 1 , switching tube S 2 , switching tube S 3 , switching tube S 4 , switching tube S 5 , switching tube S 6 ; The second pole of switching tube S 1 , the first end of inductor L, and the first pole of switching tube S 2 are connected to the first node. The first pole of switching tube S 1 , and the first pole of switching tube S 5 are both connected to the first end of capacitor C; The second end of inductor L, the second end of capacitor C, and the first pole of switching tube S 3 are all connected to the positive pole of DC power supply E. The second pole of switching tube S 2 , and the second pole of switching tube S 6 are both connected to the negative pole of DC power supply E. The second pole of switching tube S 3 is connected to the second pole of switching tube S 4 . The first pole of switching tube S 4 , the second pole of switching tube S 5 , and the first pole of switching tube S 6 are all connected to the second node; The first node is the negative voltage output terminal of this five-level inverter, and the second node is the positive voltage output terminal of this five-level inverter; The third poles of switching tubes S 1 , switching tubes S 2 , switching tubes S 3 , switching tubes S 4 , switching tubes S 5 , switching tubes S 6 are connected to control signals; The switching tubes S 1 , switching tubes S 2 , switching tubes S 3 , switching tubes S 4 , switching tubes S 5 , switching tubes S 6 are all IGBT tubes; The first poles of switching tubes S 1 , switching tubes S 2 , switching tubes S 3 , switching tubes S 4 , switching tubes S 5 , switching tubes S 6 are the collectors of IGBT tubes, the second poles are the emitters of IGBT tubes, and the third poles of IGBT tubes are the gates; The switching tubes S 1 , switching tubes S 2 , switching tubes S 3 , switching tubes S 4 , switching tubes S 5 , switch transistor S 6 are all MOS transistors; the first pole of switch transistor S 1 , switch transistor S 2 , switch transistor S 3 , switch transistor S 4 , switch transistor S 5 , switch transistor S 6 is the drain of the MOS transistor, the second pole is the source of the MOS transistor, and the third pole of the MOS transistor is the gate; the controlled five-level inverter has the following six operating modes, namely: Working mode 1, switch S 2 , switch S 4 and switch S 6 are in the on state, and the remaining switches are in the off state; Inductor L is connected in parallel across the DC power supply E through switch S 2 for energy storage, and i L increases linearly; Capacitor C is open-circuited; The output terminal of the inverter is short-circuited through the switching transistor S 2 and the switching transistor S 6 so the output voltage u o of the inverter is 0; Operating mode 2, switch S 2 , switch S 3 and switch S 4 are in the on state, and the remaining switches are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the capacitor C remains open; the DC power supply E supplies power to the load end alone, so the output voltage u o = U in ; Working mode 3, switching transistor S 2 , switching transistor S 3 and switching transistor S 5 are in the on state, and the remaining switching transistors are in the off state; the inductor L continues to store energy, and i L continues to increase linearly; the DC power supply E and the capacitor C are connected in series to supply power to the load terminal together, so the output voltage u o of the inverter = 2U in ; Working mode 4, switch S 1 , switch S 3 and switch S 5 are in the on state, and the remaining switches are in the off state; the inductor L is connected in parallel across the capacitor C through the switch S 1 to release energy and charge the capacitor, and i L decreases linearly; The output terminal of the inverter is short-circuited through the switching transistor S 1 and the switching transistor S 5 so that the output voltage u o of the inverter is equal to 0; Operating mode 5, switch S 1 , switch S 3 and switch S 4 are in the on state, and the remaining switches are in the off state; the inductor L continues to release energy, and i L continues to linearly decrease; the capacitor C supplies power to the load terminal alone, so the output voltage u o = -U in ; Working mode 6, switch S 1 , switch S 4 and switch S 6 are in the on state, and the remaining switches are in the off state; the inductor L continues to release energy, and i L continues to linearly decrease; the DC power supply E and the capacitor C are connected in series to jointly supply power to the load terminal, so the output voltage u o of the inverter = -2U in ; u o and i o are the output voltage and output current of the inverter, respectively. U in is the voltage of the DC power supply E of the inverter, and i L is the current flowing through the inductor L.

2. The control method for an inductor boost five-level inverter according to claim 1, characterized in that, Switching transistor S 1 and switching transistor S 2 Complementary conduction and the duty cycle is 0.5 for both.

3. The control method for an inductor boost five-level inverter according to claim 1, characterized in that, When the switch tube S 2 is turned off, the switch tube S 1 is turned on, and the inductor L stores energy. The voltage across its two ends is U in ; when the switch tube S 1 is turned off, the switch tube S 2 is turned on, and the inductor L releases energy. The voltage across its two ends is -U C ; in the steady state, according to the volt-second balance principle of the inductor, we have: where u C is the voltage across the capacitor C, T o is the output period of the inverter, and the solution is obtained as follows U C = U in (2).

4. The control method for an inductor boost five-level inverter according to claim 1, characterized in that, the five-level inverter adopts a lowest-level approximation modulation strategy.

5. The control method for an inductor boost five-level inverter according to claim 4, characterized in that, The minimum-level approximation modulation strategy uses a sine wave u with the same frequency and phase as the fundamental wave of the inverter output voltage r as a reference, and approximates the inverter output voltage waveform to a sine wave by controlling the duration of each level.

6. The control method for an inductor boost five-level inverter according to claim 5, characterized in that, For the output voltage u of a five-level inverter o perform Fourier series expansion to obtain the following expression: where ω o is the output angular frequency of the inverter, ω o = 2π / T o ; θ 1 represents the phase of U in , θ 2 represents the phase of 2U in , and 0 ≤ θ 1 ≤ θ 2 ≤ π / 2.

7. The control method for an inductor boost five-level inverter according to claim 6, characterized in that, The five-level inverter provides energy to the load through the fundamental wave, so the fundamental wave amplitude expression of u o is: When θ 1 and θ 2 are both zero, the maximum fundamental amplitude of the inverter output voltage is: Then the modulation index M of the inverter I can be defined as: The THD of the inverter output voltage u o is:

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