High-energy-efficiency mixed-precision charge domain in-memory computing architecture and working method thereof

Abstract

The invention belongs to the field of storage, and discloses a high-energy-efficiency mixed-precision charge domain in-storage computing architecture and a working method thereof. Comprising a single-slope analog-to-digital converter, a sparsity perception input alignment module, a multi-bit input accumulation module, a controller and an accumulation module, wherein the single-slope analog-to-digital converter consists of an index calculation array, a mantissa calculation array, a shared ramp voltage generator and a bidirectional counter. According to the invention, serial input binary coding based on capacitor voltage is suitable for floating point and integer multiply-accumulate operation with flexible bit width; according to the invention, a shared single-slope analog-to-digital converter (SS-ADC) is introduced to realize maximum index search and index difference calculation; according to the method, a sparsity perception calculation scheme is provided, low-importance input-weight pairs are filtered out through an adjustable threshold value, and invalid power consumption is reduced; according to the method, a multi-bit input accumulation method is further combined, and an ADC redundancy optimization quantization and normalization process is utilized, so that the overall energy efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of storage, and particularly relates to a high-efficiency charge domain high-efficiency in-memory computing architecture that supports floating-point / integer double-precision operations, and can support floating-point and integer multiplication and accumulation operations in the same macrocell. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence and large-scale deep neural networks (DNNs), the computing power requirements of computing systems have grown exponentially. Traditional von Neumann architectures, when handling large-scale matrix multiplication and accumulation operations, require frequent data movement between storage and computation units, forming a so-called "memory wall" bottleneck. This leads to a significant decrease in energy efficiency, making it difficult to meet the dual requirements of computing power and energy consumption in deep learning inference and training processes.

[0003] To address these issues, Computing-in-Memory (CiM) technology emerged. This technology avoids frequent data transfers between memory and processor by performing multiply-accumulate (MAC) operations directly within the memory array, thus exhibiting significant advantages in energy efficiency. Currently, in-memory computing chips based on novel devices such as SRAM, ReRAM, and FeFET have been extensively studied and have demonstrated high energy efficiency and high throughput in integer (INT) precision neural network inference tasks.

[0004] However, existing in-memory computing technologies still have the following shortcomings: 1. Precision Limitation: Most current analog in-memory computing architectures primarily support 8-bit or lower precision integer multiply-accumulate (INT-MAC). While low precision is sufficient for some inference tasks, it leads to significant model accuracy loss in applications requiring high precision (such as natural language processing, scientific computing, and training tasks).

[0005] 2. Insufficient Floating-Point Support: To meet high-precision requirements, some research has attempted to introduce floating-point multiply-accumulate (FP-MAC) into in-memory computation. However, floating-point numbers consist of a sign bit, an exponent bit, and a mantissa bit, requiring additional exponent alignment, normalization, and rounding operations. Traditional floating-point in-memory computation schemes often employ dedicated exponent processing circuits and complex data paths, leading to a significant increase in circuit area and power consumption, thus offsetting the energy efficiency advantages of in-memory computation.

[0006] 3. Insufficient Flexibility: Most existing floating-point in-memory computing architectures are optimized for only a single mode. For example, some architectures are fixed to support floating-point operations, but in scenarios requiring only integer operations, circuit resources cannot be fully utilized, resulting in wasted area and energy efficiency; other architectures only support integer operations and cannot meet the needs of applications requiring high floating-point precision. This lack of flexibility limits the application prospects of in-memory computing in general-purpose artificial intelligence accelerators.

[0007] 4. Trade-off between energy efficiency and accuracy: In floating-point calculations, exponent alignment is typically achieved through comparator trees and shifters, which not only increases latency but also incurs additional power consumption. Meanwhile, during mantissa accumulation, the analog-to-digital converter (ADC) is the main bottleneck for power consumption. Directly increasing the ADC resolution to support floating-point mantissa accumulation would inevitably lead to a significant reduction in energy efficiency.

[0008] 5. Insufficient utilization of sparsity: Neural network models generally exhibit sparse inputs, weights, or activations during operation. However, most existing in-memory computing architectures only perform intensive operations and fail to fully utilize sparsity to skip low-importance input-weight pairs, resulting in a large amount of wasted power consumption.

[0009] In summary, the existing technologies have the following pressing problems to be solved: how to support floating-point and integer operations simultaneously in the same computational macro to improve computational flexibility; how to reduce the energy consumption and latency of floating-point exponent processing and mantissa accumulation while ensuring high precision; how to introduce a sparsity-aware mechanism to reduce invalid computation; and how to optimize energy efficiency and avoid precision loss during ADC conversion.

[0010] Therefore, there is an urgent need for a new charge-domain in-memory computing architecture that is compatible with floating-point and integer multiplication-accumulation operations within the same array, and combines sparsity awareness and multi-bit input accumulation mechanisms to significantly improve energy efficiency while maintaining accuracy. This is precisely the core problem that this invention aims to solve. Summary of the Invention

[0011] The purpose of this invention is to address the problems of low energy efficiency, large area overhead, and insufficient computational flexibility in existing in-memory computing architectures when supporting high-precision floating-point operations. It proposes a charge-domain in-memory computing architecture based on a reconfigurable capacitor digital-to-analog converter (RCDAC) and its operating method. This architecture is compatible with both integer multiply-accumulate (INT-MAC) and floating-point multiply-accumulate (FP-MAC) within the same computational macro, and significantly improves energy efficiency through sparsity awareness and multi-bit input accumulation mechanisms.

[0012] The objective of this invention is achieved through the following technical solution: 1. Dual-array structure: The in-memory computation macro comprises two symmetrical arrays, each responsible for exponentiation and mantissa operations, respectively. The exponent array calculates the sum of the input exponent and the weighted exponent and performs exponent alignment; the mantissa array performs bitwise AND operations on the mantissa and partial accumulation. Through resource reuse, both arrays are used as integer in-memory computation macros during integer operations; during floating-point operations, the arrays perform their respective tasks, achieving dual-mode compatibility.

[0013] 2. Reconfigurable Capacitor Digital-to-Analog Converter (RCDAC): The RCDAC consists of four metal-oxide-metal (MOM) capacitors and several switches. Its core mechanism is charge sharing. In exponential mode, the input exponent and weighted exponent are encoded separately and the charge is accumulated to achieve exponential summation. In mantissa mode, the bitwise AND logic of the input and weights is executed through switch control to achieve mantissa partial product calculation. Compared with traditional capacitor encoders, this invention adds only a few switches, greatly improving computational flexibility. 3. Shared Single-Slope Analog-to-Digital Converter (SS-ADC): This invention employs a shared SS-ADC to perform exponential maximum detection and exponential difference calculation. The principle is as follows: the exponent is encoded as a charge voltage, compared with a uniform ramp voltage, and a time-domain signal is output by an inductive amplifier. The exponential difference is then obtained through a counter. This method avoids the area and power consumption overhead associated with traditional comparison trees and offset calculators. 4. Sparsity-Aware Index Processing: This invention proposes a sparsity-aware index processing scheme. Index calculation is divided into two stages: High-order sparsity detection stage: Based on the high-order part of the sum of the input index and the weight index, input-weight pairs are classified into four categories: "candidate," "potential," "observation," and "sparse." "Sparse" pairs are skipped in subsequent calculations to reduce invalid computation. Low-order difference calculation stage: Index difference calculation is performed only on candidate and potential pairs to further eliminate unimportant computations. This mechanism controls sparsity through thresholding, significantly improving energy efficiency while maintaining accuracy.

[0014] 5. Multi-bit Input Accumulation Method: In mantissa operations, this invention adopts a least-bit-first input method, merging multiple least significant bits before performing another ADC conversion. Combined with ADC redundancy, this reduces the number of conversions and addition operations during quantization and normalization, thereby reducing energy consumption and improving overall throughput.

[0015] Specifically as follows: A charge-domain in-memory computing architecture supporting both floating-point and integer modes includes: An exponent calculation array is used to encode the input exponent and the weighted exponent into charge voltages respectively through a reconfigurable capacitor digital-to-analog converter and perform charge-sharing accumulation to obtain the exponent sum; The mantissa calculation array is used to perform a bitwise AND operation between the input mantissa and the weighted mantissa through a reconfigurable capacitor digital-to-analog converter, and to perform partial accumulation in the charge domain; A single-slope analog-to-digital converter (SS-ADC) consisting of a shared ramp voltage generator and a bidirectional counter is used to detect the maximum value of the input-weighted exponent sum and calculate the exponent difference; A sparsity-aware input alignment module for skipping low-importance input-weight pairs based on an adjustable threshold; The multi-bit input accumulator module utilizes the quantization redundancy of the low-bit accumulation result in the multiply-accumulate operation to reduce the number of conversions in the successive approximation analog-to-digital converter and thus reduce quantization energy consumption. The controller and accumulation module manage the data flow, quantization and normalization operations of the exponent calculation array and the mantissa calculation array, and output the multiplication and accumulation results.

[0016] Furthermore, the reconfigurable capacitor digital-to-analog converter consists of four metal-oxide-metal (MOM) capacitors, and uses a charge-sharing method to achieve serial binary encoding. In exponential mode, the input exponent and the weight exponent are independently encoded and summed, while in mantissa mode, it is configured as a bitwise AND logic of the input and the weight.

[0017] Furthermore, the exponent calculation array and the mantissa calculation array have the same specifications, and can work simultaneously in integer mode to improve throughput, while in floating-point mode they respectively perform exponent and mantissa calculation functions.

[0018] Furthermore, the single-slope analog-to-digital converter simultaneously performs maximum exponent detection and exponent difference calculation of the input-weighted system under the same slope voltage, and obtains the exponent offset required for alignment through a bidirectional counter.

[0019] Furthermore, the sparsity-aware input alignment module includes a sparsity detection stage and a difference calculation stage. The sparsity detection stage classifies input-weight pairs into candidate, potential, observed, and sparse based on the high-order part of the exponent sum, and removes low-importance pairs. The difference calculation stage only performs exponential difference calculation on candidate and potential input-weight pairs, thereby reducing the amount of subsequent mantissa operations.

[0020] Furthermore, the multi-bit input accumulation module combines several least significant bit inputs in a least-bit-first input order before performing an ADC conversion, reducing the number of conversions and addition operations, thereby reducing quantization errors and improving energy efficiency.

[0021] Furthermore, the mantissa calculation array adopts a positive and negative split structure, accumulating the positive and negative partial products separately to avoid the additional energy consumption caused by sign expansion.

[0022] Furthermore, the controller in the accumulation module is further used to dynamically adjust the threshold of the sparsity sensing input alignment module, thereby balancing energy efficiency and computational accuracy under different accuracy requirements.

[0023] The present invention also provides a method for operating the charge domain in-memory computing architecture as described above, comprising: Step S1: After loading the weighted exponent into the exponent calculation array, serial binary encoding is achieved by using a reconfigurable capacitor digital-to-analog converter and floating-point input exponent, and charge accumulation is performed to obtain the exponent sum; Step S2: Detect the maximum exponent and calculate the exponent difference for each input-weight pair during the exponent calculation process using a single-slope analog-to-digital converter; Step S3: In the sparsity-aware input alignment module, based on the high-order classification of the exponent sum, the sparse input-weight pairs are directly skipped, and only candidate and potential pairs are retained to enter the next exponent difference calculation stage. During input alignment, based on the sparsity-aware mechanism, input-weight pairs with exponent differences higher than the threshold are used to improve the sparsity of computation. Step S4: The exponent-aligned input mantissa is sent to the mantissa calculation array, and the mantissa product is achieved by performing a bitwise AND operation through a reconfigurable capacitor digital-to-analog converter, and partial accumulation is performed in the charge domain; Step S5: Using a multi-bit input accumulation method, multiple least significant bits are combined and then ADC conversion is performed. The final floating-point or integer multiplication and accumulation result is output in conjunction with the normalization circuit.

[0024] Furthermore, the sparsity sensing mechanism in step S3 adopts a dynamically adjustable threshold to adjust the sparsity according to the application scenario, so as to balance energy efficiency and accuracy. The multi-bit input accumulation method in step S5 reduces rounding errors and energy consumption by delaying the ADC conversion of the low-order input and utilizing quantization redundancy.

[0025] The beneficial effects of this invention are as follows: The high-efficiency charge-domain in-memory computing architecture design in this invention supports floating-point / integer double-precision operations, improving computational energy efficiency and circuit utilization for multi-precision tasks. The proposed RCDAC circuit structure achieves compatibility with exponentiation and mantissa operations within the charge-domain in-memory computing architecture using minimal circuitry. Based on a shared single-slope voltage and a bidirectional counter, this computing architecture enables parallel maximum value lookup and difference calculation for the input-weighted exponent sum. It utilizes a sparsity-aware mechanism to improve input sparsity, thereby enhancing exponentiation processing efficiency and reducing computational power consumption and overall area overhead. This invention combines a multi-bit input accumulation method with ADC redundancy during computation to reduce quantization energy consumption. Attached Figure Description

[0026] Figure 1(a) is a schematic diagram of the in-memory computing architecture of the charge domain. Figure 1 (b) is a schematic diagram of the floating-point multiplication and accumulation operation process in the charge domain in-memory computing architecture. Figure 1 (c) represents the storage method for weight exponent and mantissa data in the charge domain in-memory computing architecture; Figure 2 (a) is a schematic diagram showing the connection between the reconfigurable capacitor digital-to-analog converter (RCDAC) and the static random access memory (SRAM) in the memory array. Figure 2 (b) is a schematic diagram of the RCDAC circuit. Figure 2 (c) is the input driver unit of the RCDAC. Figure 2 (d) is a waveform diagram of the exponential mode encoding of the RCDAC circuit; Figure 3 (a) is a circuit diagram for exponent calculation based on SS-ADC. Figure 3 (b) is a flowchart of the sparsity perception index calculation scheme. Figure 3 (c) is a schematic diagram of index calculation and labeling in the sparse perception stage. Figure 3 (d) is a schematic diagram of index calculation and labeling during the difference calculation stage; Figure 4 This is a schematic diagram of the mantissa alignment and input scheme based on the exponent difference; Figure 5 This is a schematic diagram of the SAR-ADC configuration scheme in floating-point and integer calculation modes in the charge domain in-memory computing architecture. Figure 6 This is a schematic diagram of multi-bit input accumulation and ADC redundancy utilization; Figure 7 Graph showing the linearity results for RCDAC exponential encoding; Figure 8 This is a diagram illustrating the relationship between calculation accuracy and SINAD test results; Figure 9 A comparison chart of energy efficiency and throughput under different floating-point formats; Figure 10 A graph showing the relationship between energy efficiency and input sparsity when deploying a ResNet20 network on a charge-domain in-memory computing architecture for the CIFAR-100 dataset. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0028] Please see Figure 1A charge-domain in-memory computing architecture supporting both floating-point and integer modes includes an exponent calculation array, a mantissa calculation array, a single-slope analog-to-digital converter (SS-ADC) composed of a shared ramp voltage generator and a bidirectional counter, a sparsity-aware input alignment module, a multi-bit input accumulation module, a controller, and an accumulation module. The sparsity-aware input alignment module, the multi-bit input accumulation module, and the controller and accumulation module are all included within... Figure 1 (a) The top controller and bidirectional calculator.

[0029] The exponent calculation array is used to encode the input exponent and the weighted exponent into charge voltages respectively through a reconfigurable capacitor digital-to-analog converter, and then perform charge-sharing accumulation to obtain the exponent sum.

[0030] The mantissa calculation array performs a bitwise AND operation between the input mantissa and the weighted mantissa using a reconfigurable capacitor digital-to-analog converter, and performs partial accumulation within the charge domain. The mantissa calculation array employs a positive-negative split-path structure, accumulating the positive and negative partial products separately to avoid additional power consumption caused by sign expansion. The exponent calculation array has the same specifications as the mantissa calculation array and can operate simultaneously in integer mode to improve throughput, while in floating-point mode it handles exponentiation and mantissa operations respectively.

[0031] A single-slope analog-to-digital converter (SS-ADC), consisting of a shared ramp voltage generator and a bidirectional counter, is used to detect the maximum value of the sum of the input-weighted exponents and calculate the exponent difference. The SS-ADC simultaneously performs maximum exponent detection and exponent difference calculation for the input-weighted exponents under the same ramp voltage, and obtains the required exponent offset for alignment via the bidirectional counter.

[0032] The sparsity-aware input alignment module is used to skip low-importance input-weight pairs based on an adjustable threshold. The module includes a sparsity detection stage and a difference calculation stage. The sparsity detection stage classifies input-weight pairs into candidate, potential, observed, and sparse categories based on the high-order part of the exponent sum, and eliminates low-importance pairs. The difference calculation stage only performs exponential difference calculations on candidate and potential input-weight pairs, thereby reducing the amount of subsequent mantissa computation.

[0033] The multi-bit input accumulator module utilizes the quantization redundancy of the low-significant bit accumulation result in the multiply-accumulate operation to reduce the number of conversions in the successive approximation analog-to-digital converter, thereby reducing quantization power consumption. By using a low-bit-first input order, the multi-bit input accumulator module combines several low-significant bit inputs before performing an ADC conversion, reducing the number of conversions and addition operations, thus reducing quantization errors and improving energy efficiency.

[0034] The controller and accumulation module manage the data flow, quantization, and normalization operations of the exponentiation and mantissa calculation arrays, and output the multiplication-accumulation result. The controller within the accumulation module further dynamically adjusts the threshold of the sparsity-aware input alignment module, thereby balancing energy efficiency and computational accuracy under different precision requirements.

[0035] The controller is included in Figure 1 (a) The top controller and bidirectional calculator, the cumulative module is included in Figure 1 (a) is in the post-processing and normalization module.

[0036] The aforementioned reconfigurable capacitor digital-to-analog converter consists of four metal-oxide-metal (MOM) capacitors. It uses a charge-sharing method to implement serial binary encoding. In exponential mode, the input exponent and the weight exponent are independently encoded and summed. In mantissa mode, it is configured as a bitwise AND logic of the input and the weight.

[0037] The present invention also provides a method for operating the charge domain in-memory computing architecture as described above, comprising: Step S1: After loading the weighted exponent into the exponent calculation array, serial binary encoding is achieved by using a reconfigurable capacitor digital-to-analog converter and floating-point input exponent, and charge accumulation is performed to obtain the exponent sum.

[0038] Step S2: Detect the maximum exponent and calculate the exponent difference of each input-weight pair during the exponent calculation process using a single-slope analog-to-digital converter.

[0039] Step S3: In the sparsity-aware input alignment module, based on the high-order classification of the exponent sum, the sparse input-weight pairs are directly skipped, and only candidate and potential pairs are retained to enter the next exponent difference calculation stage. During input alignment, based on the sparsity-aware mechanism, input-weight pairs with exponent differences higher than the threshold are used to improve the sparsity of computation.

[0040] The sparsity sensing mechanism employs a dynamically adjustable threshold, adjusting the sparsity according to the application scenario to balance energy efficiency and accuracy. Step S4: The exponent-aligned input mantissa is sent to the mantissa calculation array, and the mantissa product is achieved by performing a bitwise AND operation through a reconfigurable capacitor digital-to-analog converter, and partial accumulation is performed in the charge domain.

[0041] Step S5: Using a multi-bit input accumulation method, multiple least significant bits are combined and then ADC conversion is performed. The final floating-point or integer multiplication and accumulation result is output in conjunction with the normalization circuit.

[0042] The multi-bit input accumulation method reduces rounding errors and energy consumption by delaying the ADC conversion of the lower-order inputs and utilizing quantization redundancy. Example

[0043] like Figure 1 As shown in (a), this invention proposes an integer and floating-point dual-mode analog in-memory computing architecture based on MOM capacitors. This computing architecture includes two identical 64*128 charge domain in-memory computing arrays (north and south arrays), along with corresponding I / O ports, a SAR-ADC, a shared ramp voltage generator, 128 sense amplifiers (SAs), a bidirectional counter, a top-level control module, and other peripheral circuits. The north array is the exponentiation array, and the south array is the mantissa array. Figure 1 As shown in (b), the floating-point calculation process of this in-memory computing structure is as follows: 1) Perform exponential addition operation in the north array; 2) Perform maximum value lookup and difference calculation based on the shared ramp voltage generator circuit, sense amplifier, and bidirectional counter; 3) Perform mantissa multiplication and accumulation operation in the south array through the mantissa alignment input circuit of the sparsity sensing input alignment module. The mantissa alignment input circuit is included in... Figure 1 (c) In the sparsity sensing input alignment module; 4) Partial summation is read out via SAR-ADC and subsequent summation and regularization operations are performed in the post-processing and normalization module. For example... Figure 1 As shown in (c), this in-memory computation array adopts a local and global bit line structure, with each group consisting of 8 rows of SRAM. Local bit lines are used in conjunction with an RCDAC for computation. In exponential mode, data of the same weight is stored in the same group within the same column. In mantissa / integer mode, bits of the same weight are stored in different groups within the same column, meaning each group represents a different bit weight upon readout. Figure 2 As shown in (a), the eight SRAM cells within the group participate in the calculation of the reconfigurable capacitor digital-to-analog converter (RCDAC) through local bit lines and two inputs representing positive and negative values. Figure 2 As shown in (b), the reconfigurable capacitor digital-to-analog converter uses four MOM capacitors as the main computing units and implements configurable capacitor discharge logic through two transistors controlled by the addition mode. When the addition mode is set, capacitor discharge is controlled only by the weight (input), while when the addition mode is reset, capacitor discharge is controlled by the result of the AND operation between the weight and the input. Figure 2 As shown in (c), the inputs are assigned to positive and negative inputs by the sign bit and the addition mode control.

[0044] Exponential calculation array: The exponent calculation array adopts an RCDAC structure, which encodes the input exponent and the weighted exponent as charge voltages and accumulates the charges to obtain the exponent sum. Figure 2 (d) Taking two-digit exponent addition as an example, the waveform of the reconfigurable capacitor digital-to-analog converter is shown. The two computing capacitors encode the weights and the input respectively, and then the addition is performed to convert the exponent sum of the weights and the input into the capacitor voltage.

[0045] Sparsity-aware exponential processing: like Figure 3 As shown in (a), the exponent and voltage are compared with the shared ramp voltage, and the comparison result is used by the top-level controller to calculate the exponent difference through a bidirectional counter. Figure 3 As shown in (b), this scheme performs two-stage processing (sparseness detection stage and difference calculation stage) on the high and low four bits of the exponent respectively. Figure 3 (c) shows a schematic diagram of the sparsity detection stage. The input-weight pairs are classified according to the high 4 bits of their exponent sum: those with the same exponent as the maximum are marked as "candidates"; those with an exponent 1 lower than the maximum are marked as "potentials"; those with an exponent 2 lower than the maximum are marked as "observations"; and the rest are marked as "sparse" and are directly masked in subsequent operations. Figure 3 (d) illustrates the operation of the difference calculation stage. In the low-order difference stage, candidate and potential pairs continue to calculate the difference value through counters, ultimately obtaining the difference with the maximum exponent. By adjusting the threshold, the sparsity of the input-weight pairs participating in subsequent mantissa operations can be dynamically changed to balance energy efficiency and accuracy.

[0046] Input mantissa shift alignment: like Figure 4 As shown, based on the exponential differences of each input-weight pair obtained from the aforementioned operations, the input mantissa is shifted to align with the exponent of subsequent mantissa products. The aligned mantissas are input in little-endian order. The adjustable threshold mentioned above will be used here to set all input mantissas to zero, thereby skipping the subsequent mantissa calculation stage and improving computational efficiency.

[0047] SAR-ADC dual-mode configuration In this dual-mode in-memory computing architecture, both the north and south arrays possess their own successive approximation ADCs (SAR-ADC). For example... Figure 5 As shown, in floating-point calculation mode, a positive and negative branching structure is adopted to accumulate positive and negative results separately, avoiding the increased energy consumption caused by sign expansion and frequent bit flipping during partial addition. In the integer calculation stage, since the parameters participate in the calculation as unsigned numbers, the north and south arrays simultaneously perform integer multiplication and accumulation operations. The capacitor voltage is converted into a digital quantity by the SAR-ADC and sent to the post-processing and normalization module for accumulation.

[0048] Multiple inputs accumulated and read out: The mantissa input is injected into the array bit by bit in least-bit priority order. In traditional designs, an ADC conversion is required for each input bit, resulting in high power consumption. Figure 6 As shown, this invention combines multiple least significant bits and delays their ADC conversion, utilizing quantization redundancy to avoid low-bit rounding errors, thereby reducing the number of ADC conversions and the workload of the adder, and improving throughput and energy efficiency.

[0049] The functions and effects of this invention are further illustrated and demonstrated through the following simulation experiments: 1. Simulation platform and experimental conditions The experiment was based on UMC 40nm process. The in-memory array, SS-ADC and read / write driver circuit were implemented in a fully custom manner. The controller was synthesized and implemented in the back end using a standard cell library.

[0050] During simulation, the SPECTRE AMS simulator was used to simulate the in-memory calculation design of the charge domain. The applicant also compared the results with non-patent literature 1 (H. Zhang, S. He, X. Lu, X. Guo, S. Wang, Y. Du, and L. Du, “SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MACComputation for CNN Edge Inference,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4357–4368, 2023-11) and non-patent literature 2 (F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin, “A 28nm 29.2TFLOPS / W BF16 and 36.5TOPS / W INT8 Reconfigurable Digital CIM Processor with Unified FP / INT)). Pipeline and Bitwise In-MemoryBooth Multiplication for Cloud Deep Learning Acceleration,” in 2022 IEEEInternational Solid-State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022-02), Non-Patent Document 3 (P.-C. Wu, J.-W. Su, L.-Y. Hong, J.-S. Ren, C.-H. Chien, H.-Y. Chen, C.-E. Ke, H.-M. Hsiao, S.-H. Li, S.-S. Sheu, W.-C. Lo, S.-C.Chang, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, and M.-F.The computational energy efficiency of the in-memory computing design in Chang's article, "A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips," published in the IEEE Journal of Solid-State Circuits, vol. 59, no. 1, pp. 196–207, 2024-01, was compared.

[0051] 2. Simulation Results 1) Element Nonlinear Analysis The applicant first conducted coded simulations of all possible input and weight combinations to evaluate the nonlinearity of the RCDAC. For example... Figure 7 As shown, the maximum INL of RCDAC encoding does not exceed 0.2 LSB and the maximum DNL does not exceed 0.07 LSB, exhibiting good linearity and symmetry.

[0052] 2) Linearity Analysis Then, the applicant performed 10k floating-point multiplication-accumulation operations under the charge domain in-memory computing architecture to simulate the computational error, using a normal distribution. For example... Figure 8 As shown, the 1-σ error of the calculation results of this architecture is 0.12%, and its equivalent SINAD is 58dB, which demonstrates good calculation accuracy and linearity.

[0053] 3) Calculate energy efficiency analysis In terms of calculating energy efficiency, such as Figure 9 As shown, the applicant evaluated the energy efficiency and throughput improvements of the described in-memory computing architecture under different data accuracies. It can be seen that computational energy efficiency and throughput increase as the data bit width decreases. Furthermore, to evaluate the energy efficiency improvement of the sparsity exponential processing scheme, the applicant conducted ablation experiments on 18 convolutional layers of the ResNet20 model based on the CIFAR-100 dataset. Figure 10 As shown, the in-memory computing architecture improves input sparsity and computational efficiency by introducing a sparsity-aware processing scheme.

[0054] 4) Performance Comparison The table below compares the high-efficiency charge domain in-memory computing design of this invention with other in-memory computing designs. To ensure a relatively fair comparison of energy efficiency, all designs are scaled to the 40nm process node.

[0055]

[0056] As shown in the table above, the high-energy-efficiency charge-domain in-memory computing architecture of this invention, which supports floating-point / integer double-precision operations, achieves ideal computational energy efficiency under INT8 and weighted precision, and can support flexible computational precision. Specifically, the computational energy efficiency of floating-point multiply-accumulate operations of the charge-domain in-memory computing architecture of this invention is 1.34 times and 1.37 times higher than that of digital domain operation (Non-Patent Document 2) and mixed-signal scheme (Non-Patent Document 3). This is mainly attributed to the sparsity-aware processing scheme and multi-bit input accumulation readout strategy of this invention, which achieves a good balance between precision and energy efficiency.

[0057] The results above show that this invention not only has high computational efficiency, but also supports flexible computational accuracy.

[0058] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A charge domain in-memory computing architecture supporting floating point and integer dual mode, characterized in that, The application comprises: an index calculation array for encoding input indices and weight indices into charge-voltage respectively by reconfigurable capacitor digital-to-analog converters and performing charge-sharing accumulation to obtain index sums; a mantissa calculation array for performing bit-by-bit AND operation between input mantissas and weight mantissas by reconfigurable capacitor digital-to-analog converters and performing partial accumulation in the charge domain; a single-slope analog-to-digital converter composed of a shared slope voltage generator and a bidirectional counter for detecting the maximum value of input-weight index sums and calculating index differences; a sparsity-aware input alignment module for skipping low-importance input-weight pairs based on an adjustable threshold; a multi-bit input accumulation module for reducing the number of successive approximation analog-to-digital converter conversions to reduce quantization energy consumption by utilizing the quantization redundancy of low-bit accumulation results in multiply-accumulate operations; a controller and accumulation module for managing the data flow, quantization and normalization operations of the index calculation array and the mantissa calculation array and outputting multiply-accumulate results.

2. The charge domain in-memory computing architecture of claim 1, wherein, The reconfigurable capacitor digital-to-analog converter is composed of four metal-oxide-metal capacitors, realizes serial binary encoding in a charge-sharing manner, independently encodes input indices and weight indices in an index mode and sums them, and is configured as a bit-by-bit AND logic between input and weight in a mantissa mode.

3. The charge domain in-memory computing architecture of claim 1, wherein, The index calculation array and the mantissa calculation array have the same specifications, can work simultaneously in an integer mode to improve throughput, and can respectively undertake index and mantissa operation functions in a floating-point mode.

4. The charge domain in-memory computing architecture of claim 1, wherein, The single-slope analog-to-digital converter simultaneously performs input-weight maximum index detection and index difference calculation under the same slope voltage, and obtains the index offset required for alignment through a bidirectional counter.

5. The charge domain in-memory computing architecture of claim 1, wherein, The sparsity-aware input alignment module comprises a sparsity detection stage and a difference calculation stage, the sparsity detection stage classifies input-weight pairs into candidate, potential, observed and sparse according to the high-bit part of the index sum and eliminates low-importance pairs, and the difference calculation stage only performs index difference calculation on candidate and potential input-weight pairs.

6. The charge domain in-memory computing architecture of claim 1, wherein, The multi-bit input accumulation module reduces the number of conversions and addition operations by merging several low-significant-bit inputs in a low-to-high input order and then performing an ADC conversion.

7. The charge domain in-memory computing architecture of claim 1, wherein, The mantissa calculation array adopts a positive-negative branching structure to accumulate positive and negative partial products respectively.

8. The charge domain in-memory computing architecture of claim 1, wherein, The controller in the controller and accumulation module is further used for dynamically adjusting the threshold of the sparsity-aware input alignment module, thereby balancing energy efficiency and calculation accuracy under different accuracy requirements.

9. A method of operating a charge domain in-memory computing architecture as claimed in any one of claims 1 to 8, wherein, The application comprises: Step S1: loading weight indices to the index calculation array, realizing serial binary encoding by reconfigurable capacitor digital-to-analog converters and input floating-point indices and performing charge accumulation to obtain index sums; Step S2: detecting the maximum index and calculating the index difference of each input-weight pair in the index calculation process by a single-slope analog-to-digital converter; Step S3: in the sparsity-aware input alignment module, based on the high-bit classification of the index sum, directly skipping sparse input-weight pairs, only retaining candidate and potential pairs to enter the next index difference calculation stage, and based on the sparsity-aware mechanism in input alignment, input-weight pairs with an index difference higher than a threshold are improved in sparsity. Step S4: the input mantissa after index alignment is sent to the mantissa calculation array, and the bit-by-bit "and" operation is performed by the reconfigurable capacitor digital-to-analog converter to realize the mantissa product and perform partial accumulation in the charge domain; Step S5: a multi-bit input accumulation method is used to combine multiple low significant bits and then perform ADC conversion, and a normalization circuit is combined to output the final floating point or integer multiplication and accumulation result.

10. The method of working according to claim 9, characterized in that, The sparsity sensing mechanism in step S3 adopts a dynamic adjustable threshold, and adjusts the sparsity according to the application scenario; The multi-bit input accumulation method in step S5 delays the ADC conversion of the low bits, reduces the rounding error by using the quantization redundancy, and reduces the energy consumption.

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