A high-isolation switch chip topology based on coupled lines

Abstract

The present invention proposes a high-isolation on-chip switch topology based on coupling lines, which includes a main coupling line, a first sub-coupling line and a second sub-coupling line, an auxiliary coupling line, a matching capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor, a first resistor, a second resistor, a third resistor and a fourth resistor, a first bias voltage, a second bias voltage, an RF input port, a first RF output port and a second RF output port. When the first bias voltage is low and the second bias voltage is high, the RF input port and the first RF output port are connected, and the RF input port and the second RF output port are disconnected. The auxiliary coupling line can significantly enhance the isolation between the first RF output port and the second RF output port while reducing the insertion loss. The present invention solves the key problem of low isolation of on-chip RF switches while reducing the chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-isolation switch chip topology structure based on coupled lines. Background Art

[0002] In half-duplex transceiver circuits in communication systems, switching technology is often used to enable the transmit and receive channels to share a single antenna, reducing circuit size and redundancy. RF switches are components used to control the transmission path and signal strength of RF signals, and are widely used in wireless communications, phased array systems, and other fields. With the advancement of modern wireless communication technology, communication systems have placed higher demands on the insertion loss, isolation, power capacity, and integration of transceiver switches.

[0003] Currently, on-chip RF switch circuit topologies are primarily divided into two categories: the traditional circuit topology based on quarter-wavelength transmission lines and the coupled-line topology. For on-chip RF switches, the traditional quarter-wavelength transmission line topology requires a large amount of layout area to implement the quarter-wavelength impedance transformation line, hindering large-scale system integration. While coupled-line topologies can effectively reduce chip area, they suffer from low isolation. Summary of the Invention

[0004] Technical problem: In order to solve the problem of low port isolation in the above-mentioned RF switch topology based on coupled lines, a new coupled line structure is proposed, which can significantly improve the port isolation while maintaining low insertion loss.

[0005] Technical solution: In order to solve the above problems, the present invention proposes a high-isolation on-chip switch topology based on coupling lines, which includes an input module, an isolation enhancement module and an output module; the input module includes a main coupling line and a matching capacitor; one end of the matching capacitor is respectively connected to the RF input port and one end of the main coupling line, and the other end of the matching capacitor is grounded, and the other end of the main coupling line is grounded. Mutual inductance is formed between the input module, the isolation enhancement module and the output module through the coupling line.

[0006] Furthermore, the isolation enhancement module includes an auxiliary coupling line, a third transistor and a fourth transistor, one end of the auxiliary coupling line is grounded, the other end of the auxiliary coupling line is connected to the drains of the third transistor and the fourth transistor, the gate of the third transistor is connected to the third resistor to the second bias voltage, and the gate of the fourth transistor is connected to the fourth resistor to the first bias voltage; the sources of the third transistor and the fourth transistor are respectively connected to the first RF output port and the second RF output port.

[0007] Furthermore, the output module includes a first secondary coupling line, a second secondary coupling line, a first transistor, and a second transistor; one end of the first secondary coupling line is simultaneously connected to the first RF output port, the drain of the first transistor, and the source of the third transistor, and the other end is grounded, the source of the first transistor is grounded, and the gate is connected to the first bias voltage through a first resistor; one end of the second secondary coupling line is simultaneously connected to the second RF output port, the drain of the second transistor, and the source of the fourth transistor, and the other end is grounded, the source of the second transistor is grounded, and the gate is connected to the second bias voltage through a second resistor.

[0008] There is mutual coupling between any two lines among the main coupling line and the first secondary coupling line, the second secondary coupling line, and the auxiliary coupling line. The strength of the coupling depends on the spacing between the coupling lines and the length of the coupling lines.

[0009] The main coupling coil, the first secondary coupling line, the second secondary coupling line, and the auxiliary line are all realized by mutual coupling of metal lines in an integrated circuit process.

[0010] Since layered metal structures are often used in integrated circuit processes, the main coupling line is constructed by a layer of metal in the integrated circuit process, and the first secondary coupling line, the second secondary coupling line and the auxiliary line are constructed by the same layer of metal as the metal layer other than the main coupling line.

[0011] The first transistor and the fourth transistor are both controlled by a first bias voltage, the second transistor and the third transistor are both controlled by a second bias voltage, and the impedance values ​​of the first resistor, the second resistor, the third resistor and the fourth resistor connected to the gate are between 5K and 50K ohms.

[0012] The first transistor and the second transistor have the same transistor size, the third transistor and the fourth transistor have the same transistor size, and the gate widths of the first transistor and the second transistor are smaller than the gate widths of the third transistor and the fourth transistor.

[0013] For the above circuit, when the first bias voltage is at a low level and the second bias voltage is at a high level, the RF input terminal and the first RF output terminal are connected, and the RF input terminal and the second RF output terminal are disconnected; when the first bias voltage is at a high level and the second bias voltage is at a low level, the RF input terminal and the first RF output terminal are disconnected, and the RF input terminal and the second RF output terminal are connected.

[0014] Beneficial effects: Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0015] The advantage of the present invention is that it provides a new type of high-isolation on-chip switch topology based on coupled lines. On the one hand, the switch topology structure in the form of coupled lines can effectively reduce the chip size. On the other hand, the port isolation between the first RF output terminal and the second RF output terminal is improved by adding auxiliary coupled lines. When the switch is operating normally, the third transistor and the fourth transistor respectively operate in different working states, namely, on and off; the RF output port (first RF output terminal or second RF output terminal) connected to the on-state transistor (the third transistor or the fourth transistor) is electromagnetically coupled to the main coupling line through the auxiliary coupling line (the first auxiliary coupling line or the second auxiliary coupling line) and the auxiliary coil, thereby enhancing its own induced current and reducing insertion loss; and the RF output port (first RF output terminal or second RF output terminal) connected to the off-state transistor (the third transistor or the fourth transistor) forms a series resonance with the ground due to the inductance of the auxiliary coil itself and the equivalent parasitic capacitance of the transistor when the high frequency is cut off, further short-circuiting the RF signal to the ground and achieving high isolation. Compared to conventional circuit topologies based on quarter-wavelength transmission lines, this structure significantly reduces chip area and manufacturing costs. Furthermore, compared to conventional coupled-line circuit topologies, this structure significantly improves port isolation while maintaining low insertion loss. Targeting half-duplex transceiver RF circuits in communication systems, this invention addresses the issues of low isolation between the low-noise amplifier (LNA) and power amplifier (PA), as well as the large chip area of ​​conventional on-chip RF switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit diagram of a high-isolation on-chip switch topology structure based on coupled lines in the present invention;

[0017] Figure 2 Schematic diagram of four coupled lines in the high-isolation on-chip switch topology based on coupled lines of the present invention;

[0018] Figure 3 This is a circuit diagram of a conventional on-chip switch topology based on a quarter-wavelength transmission line;

[0019] Figure 4 Schematic diagram of two quarter-wavelength transmission lines in a conventional on-chip switch topology based on a quarter-wavelength transmission line;

[0020] Figure 5 A circuit diagram of an on-chip switch topology in the form of a common coupled line;

[0021] Figure 6 A schematic diagram of three coupled lines in an on-chip switch topology in the form of a common coupled line;

[0022] Figure 7 The insertion loss performance comparison of the high isolation on-chip switch topology based on coupled lines in the present invention with and without auxiliary coupled lines is shown;

[0023] Figure 8 The isolation performance comparison of the high isolation on-chip switch topology based on coupled lines in the present invention with and without auxiliary coupled lines is shown;

[0024] Figure 9 Comparison of insertion loss performance between the high-isolation on-chip switch topology based on coupled lines in the present invention and the conventional on-chip switch topology in the form of coupled lines;

[0025] Figure 10 The isolation performance comparison between the high isolation on-chip switch topology based on coupled lines in the present invention and the conventional on-chip switch topology in the form of coupled lines is shown;

[0026] Figure 1 There are: main coupling line M1, first coupling line V2 and second coupling line V3, auxiliary coupling line A4, matching capacitor C1, first transistor FET_1, second transistor FET_2, third transistor FET_3, fourth transistor FET_4; first resistor RG_1, second resistor RG_2, third resistor RG_3, fourth resistor RG_4; first bias voltage VDD, second bias voltage VCC; radio frequency input terminal RF in , the first RF output terminal RF out1 , the second RF output terminal RF out2 . DETAILED DESCRIPTION

[0027] The present invention will be further explained below with reference to the accompanying drawings and examples. The embodiments of the present invention include but are not limited to the following examples.

[0028] The present invention proposes a high-isolation on-chip switch topology structure based on a coupling line, which includes an input module, an isolation enhancement module and an output module; the input module includes a main coupling line (M1) and a matching capacitor (C1); one end of the matching capacitor (C1) is connected to a radio frequency input port (RF in ) is connected to one end of the main coupling line (M1), and the other end of the matching capacitor (C1) is grounded. The other end of the main coupling line (M1) is grounded, and mutual inductance is formed between the input module, the isolation enhancement module and the output module through the coupling line.

[0029] The isolation enhancement module comprises an auxiliary coupling line (A4), a third transistor (FET_3) and a fourth transistor (FET_4); one end of the auxiliary coupling line (A4) is grounded, and the other end of the auxiliary coupling line (A4) is connected to the drains of the third transistor (FET_3) and the fourth transistor (FET_4); the gate of the third transistor (FET_3) is connected to the third resistor (RG_3) to the second bias voltage (VCC), and the gate of the fourth transistor (FET_4) is connected to the fourth resistor (RG_4) to the first bias voltage (VDD); the sources of the third transistor (FET_3) and the fourth transistor (FET_4) are respectively connected to the first radio frequency output port (RF out1 ) and the second RF output port (RF out2 ).

[0030] The output module comprises a first secondary coupling line (V2), a second secondary coupling line (V3), a first transistor (FET_1), and a second transistor (FET_2); one end of the first secondary coupling line (V2) is simultaneously connected to a first radio frequency output port (RF out1 ), the drain of the first transistor (FET_1), and the source of the third transistor (FET_3), the other end of which is grounded, the source of the first transistor (FET_1) is grounded, and the gate is connected to the first bias voltage (VDD) through the first resistor (RG_1); one end of the second secondary coupling line (V3) is also connected to the second RF output port (RF out2 ), the drain of the second transistor (FET_2), and the source of the fourth transistor (FET_4), the other end of which is grounded, the source of the second transistor (FET_2) is grounded, and the gate is connected to the second bias voltage (VCC) through the second resistor (RG_2).

[0031] When the control voltage VCC is high and VDD is low, the RF input terminal RF in and RF output terminal RF out1 The RF input terminal RF in and RF output terminal RF out2 The two terminals are turned off, transistors FET_1 and FET_4 are in the cut-off state, and FET_2 and FET_3 are in the on state. At this time, FET_1 in the cut-off state and the auxiliary coupling line V2 form a parallel resonant cavity, inducing the energy from the main coupling line M1 to realize the transmission of the RF signal. Because the transistor FET_3 connected to the auxiliary coupling line V2 is turned on, FET_3 can be equivalent to a small on-resistance for the RF signal, so the auxiliary coupling line V2 is connected in series with the auxiliary coupling line A4 through the small resistance equivalent to FET_3. The coupling currents of these two coupling lines are in the same direction, and the currents are superimposed and transmitted to the output terminal RF out1 , reduce insertion loss; for the shutdown port RFout2 At this time, the transistor FET_2 is in the on state, which is equivalent to a small on-resistance connected to the ground, short-circuiting the current coupled from the main coupling line to the ground. The transistor FET_4 is in the off state, and is connected in series with the auxiliary coupling line A4 to form a series resonant network connected to the ground. Since the auxiliary line A4 is physically located between the two auxiliary coupling lines V2 and V3, it can effectively reduce the mutual coupling between the auxiliary coupling lines V2 and V3, realizing RF out1 and RF out2 Conversely, when the control voltage VCC is low and VDD is high, the RF input terminal RF in and RF output terminal RF out1 Shut down, RF input terminal RF in and RF output terminal RF out2 There is conduction between them.

[0032] Based on the above working principle, this embodiment designs and simulates the above circuit based on a 40nm CMOS process, verifying the practicality of the present invention.

[0033] like Figure 2 The figure shows the coupled line structure in the above-mentioned high isolation on-chip switch topology based on coupled lines. The grounding capacitor C1 of the main coupled line M1 and the transistors FET_1, FET_2, FET_3, and FET_4 are not shown. The network area is 100um×15um=0.0015mm 2 . Figure 3 The figure shows the circuit structure of a traditional on-chip switch topology based on a quarter-wavelength transmission line, which includes two quarter-wavelength transmission lines and two SPST cells (Single-Pole-Single-Throw cells). The mainstream implementation of the SPST cell is a π-type matching network or an L-type matching network composed of transistors and inductors, which will not be described in detail here. Figure 5 The figure shows a circuit structure diagram of an on-chip switch topology structure in the form of a common coupled line, which mainly includes three coupled lines. Because these three coupled lines are the same layer of metal in the integrated circuit, the length, width and height of these three coupled lines are the same, and this structure does not have the auxiliary coupling line in the present invention. The switching principle is similar to that of the present invention and will not be elaborated here. Figure 4 and Figure 6 Schematic diagrams of a quarter-wavelength transmission line in a conventional on-chip switch topology based on a quarter-wavelength transmission line and a coupled line diagram of an on-chip switch topology in the form of a common coupled line. The network area of ​​the conventional quarter-wavelength structure is 170um×100um=0.017mm 2The network area of ​​the common coupled line structure is 110um×18um=0.00198mm 2 By comparison, it can be seen that the high-isolation on-chip switch topology based on coupled lines adopted by the present invention can significantly reduce the chip area compared with the traditional quarter-wavelength transmission line structure while maintaining a network area similar to that of the ordinary coupled line structure.

[0034] Figure 7 and Figure 8 The insertion loss and isolation of the high-isolation on-chip switch topology based on the coupling line of the present invention are compared when the auxiliary coupling line A4 is present and removed. It can be seen that when the auxiliary coupling line is present, the insertion loss is within 3.5dB in the range of 130-160GHz, and the isolation is greater than 30dB. At the series resonance point of the auxiliary line A4 inductance and the equivalent parasitic capacitance of the transistor (FET_3 or FET_4) at the end time, the isolation is at most 46dB. When the auxiliary line does not exist, the insertion loss increases to 4.5dB, and the port 2 (RF out1 ) and port 3 (RF out2 ) is reduced to 17dB.

[0035] Figure 9 and Figure 10 The insertion loss and isolation results of the high-isolation on-chip switch topology based on coupled lines and the ordinary coupled-line on-chip switch topology are compared. It can be seen that the difference in insertion loss between the two is within 0.2dB in the frequency range of 120-160GHz, and the isolation between port 2 and port 3 of the high-isolation on-chip switch topology based on coupled lines is significantly improved compared with the ordinary coupled-line on-chip switch topology.

[0036] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A high-isolation on-chip switch topology based on coupled lines, characterized in that: The structure includes an input module, an isolation enhancement module and an output module; the input module includes a main coupling line (M1) and a matching capacitor (C1); one end of the matching capacitor (C1) is connected to a radio frequency input port (RF in ) is connected to one end of the main coupling line (M1), and the other end of the matching capacitor (C1) is grounded, the other end of the main coupling line (M1) is grounded, and mutual inductance is formed between the input module, the isolation enhancement module and the output module through the coupling line; The isolation enhancement module comprises an auxiliary coupling line (A4), a third transistor (FET_3) and a fourth transistor (FET_4); one end of the auxiliary coupling line (A4) is grounded, and the other end of the auxiliary coupling line (A4) is connected to the drains of the third transistor (FET_3) and the fourth transistor (FET_4); the gate of the third transistor (FET_3) is connected to the third resistor (RG_3) to the second bias voltage (VCC), and the gate of the fourth transistor (FET_4) is connected to the fourth resistor (RG_4) to the first bias voltage (VDD); the sources of the third transistor (FET_3) and the fourth transistor (FET_4) are respectively connected to the first radio frequency output port (RF out1 ) and the second RF output port (RF out2 ).

2. The high-isolation on-chip switch topology structure based on coupled lines according to claim 1, characterized in that: The output module includes a first secondary coupling line (V2), a second secondary coupling line (V3), a first transistor (FET_1), and a second transistor (FET_2); one end of the first secondary coupling line (V2) is simultaneously connected to a first radio frequency output port (RF out ), the drain of the first transistor (FET_1) and the source of the third transistor (FET_3), the other end of which is grounded, the source of the first transistor (FET_1) is grounded, and the gate is connected to the first bias voltage (VDD) through the first resistor (RG_1); one end of the second secondary coupling line (V3) is also connected to the second RF output port (RF out2 ), the drain of the second transistor (FET_2) and the source of the fourth transistor (FET_4), the other end of which is grounded, the source of the second transistor (FET_2) is grounded, and the gate is connected to the second bias voltage (VCC) through the second resistor (RG_2).

3. The high-isolation on-chip switch topology structure based on coupled lines according to claim 2, characterized in that: The main coupling line (M1), the first secondary coupling line (V2), the second secondary coupling line (V3) and the auxiliary coupling line (A4) are all realized by mutual coupling of metal lines in an integrated circuit process.

4. A high-isolation on-chip switch topology structure based on coupled lines according to claim 2 or 3, characterized in that: The lengths and widths of the main coupling line (M1), the first secondary coupling line (V2), the second secondary coupling line (V3) and the auxiliary coupling line (A4), as well as the spacing between the coupling lines, are not fixed.

5. A high-isolation on-chip switch topology structure based on coupled lines according to claim 2 or 3, characterized in that: The first transistor (FET_1) and the fourth transistor (FET_4) are both controlled by a first bias voltage (VDD), and the second transistor (FET_2) and the third transistor (FET_3) are both controlled by a second bias voltage (VCC).

6. A high-isolation on-chip switch topology structure based on coupled lines according to claim 2 or 3, characterized in that: The resistance values ​​of the first resistor (RG_1), the second resistor (RG_2), the third resistor (RG_3) and the fourth resistor (RG_4) are between 5K and 50K ohms.

7. A high-isolation on-chip switch topology structure based on coupled lines according to claim 2 or 3, characterized in that: The first transistor (FET_1) and the second transistor (FET_2) are of the same transistor size, and the third transistor (FET_3) and the fourth transistor (FET_4) are of the same transistor size.

8. The high-isolation on-chip switch topology structure based on coupled lines according to claim 2 or 3, characterized in that: The gate widths of the first transistor (FET_1) and the second transistor (FET_2) are smaller than the gate widths of the third transistor (FET_3) and the fourth transistor (FET_4).

9. A method for implementing the high isolation on-chip switch topology structure according to claims 1-8, characterized in that: The above switch topology is realized using CMOS technology.

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