Current-mode cycle analog-to-digital converter and analog-to-digital conversion method

Abstract

The present invention discloses a current-mode circulating analog-to-digital converter and an analog-to-digital conversion method, belonging to the field of integrated circuit technology. The analog-to-digital converter includes: a sampling and holding circuit, a sensitive amplifier, a selection circuit, an operation circuit, and a logic control circuit. The present invention adopts a current-sensitive amplifier as a comparison circuit to convert the difference between the current to be measured and the reference current into a voltage and then amplify it, thereby improving the sensitivity of the comparison circuit to weak signals and improving the comparison accuracy; the current-sensitive amplifier adopts a differential input structure to improve the anti-interference ability of the circuit, while achieving two-bit output per cycle, reducing the offset error caused by the traditional dual comparator circuit structure and reducing the circuit power consumption. Compared with the existing current-mode circulating analog-to-digital converter, the present invention effectively improves the conversion accuracy and reduces the circuit power consumption.

Description

Technical Field

[0001] The present invention relates to a current-mode circulation analog-to-digital converter and an analog-to-digital conversion method, and belongs to the technical field of integrated circuits. Background Art

[0002] In analog circuit design, voltage-mode circuits are predominantly used. With continuous technological advancements and the widespread demand for low-power systems, circuit supply voltages are continuously decreasing, and the shortcomings of voltage-mode circuits are becoming increasingly apparent. Current-mode circuits, on the other hand, are not limited by low supply voltages and offer advantages such as simple circuit structure, high speed, and wide bandwidth. They hold great potential in applications such as image sensors.

[0003] Analog-to-digital converters (ADCs), as a crucial component of signal processing systems, significantly impact overall circuit power consumption and area. In typical circuit design, analog current signals must first be converted to analog voltage signals using an I / V converter circuit, and then converted to digital signals using a voltage-mode ADC. This inevitably increases circuit power consumption and area, and can also easily introduce errors, affecting conversion accuracy. Therefore, current-mode ADCs have become a significant research area.

[0004] Current-mode ADCs primarily include flash ADCs, cyclic ADCs, SAR ADCs, pipeline ADCs, and folding and interpolation ADCs. Cyclic ADCs, or cyclic analog-to-digital converters, have the simplest circuit structure. The overall circuit is similar to the first stage of a pipeline ADC, reusing the same circuitry to produce one bit of output per cycle. Conversion accuracy is achieved by controlling the number of cycles.

[0005] The working process of the current mode cycle type analog-to-digital converter includes: the input signal I IN The sample / hold circuit samples and holds the signal D, which is first amplified by the operation circuit to signal 2D. The comparator compares the signal D with the reference current I REF Compare and quantize it into digital value B. If the signal value D is greater than the reference current I REF If the reference current is greater than 2D, the output B is high level 1, and then the reference current is subtracted from the signal 2D to obtain the value of the residual current; otherwise, B is low level 0, and the signal value 2D remains unchanged. Combining the above two cases, the value of the residual current can be summarized as 2D-B×I REF The remaining current is fed back to the input terminal, and the above operation is repeated again to obtain the next bit, and this cycle is repeated until the preset conversion accuracy is achieved.

[0006] Traditional current-mode cyclic analog-to-digital converters are affected by the offset error of the current comparator, and the residual current may exceed the range, resulting in missing codes.

[0007] The redundant sign bit (RSD) algorithm is often used in designs to address this issue. This method requires two reference currents and two current comparators. Each cycle produces only three quantization results: 00, 01, and 10. The input signal for each cycle is the redundant current from the previous cycle, and the current cycle's quantization result is used to correct the previous cycle. This correction algorithm is implemented by adding the results of each cycle together.

[0008] Furthermore, the traditional CMOS current comparator design used in the above solution is based on a current mirror. It first detects the input current at a low-impedance input node, then amplifies the current and ultimately converts it into a large voltage change at the output. This inevitably introduces input current offset due to current mirror error, significantly reducing comparator accuracy. Implementing the RSD algorithm requires two traditional current comparators to simultaneously determine the input current. The mismatch between the two comparators also reduces comparator accuracy, thereby reducing the conversion accuracy of the current-mode loop-type analog-to-digital converter. Furthermore, the two current comparators also consume significant power. Summary of the Invention

[0009] In order to solve the problems of poor precision and high power consumption of the existing current-mode circulating analog-to-digital converter, the present invention provides a current-mode circulating analog-to-digital converter and an analog-to-digital conversion method.

[0010] A first object of the present invention is to provide a current-mode circulating analog-to-digital converter, comprising:

[0011] A sample-and-hold circuit, configured to store the input current and the residual current, and convert the residual current into the input current of the next comparison cycle;

[0012] A sense amplifier is used to compare the magnitude relationship between the input current and the sense amplifier reference current and output the comparison result;

[0013] A selection circuit, configured to select a corresponding selection reference current according to a comparison result output by the sense amplifier;

[0014] an operation circuit, configured to operate on the input current and the selected reference current to obtain the residual current;

[0015] The logic control circuit is used to control the number of cycles, that is, to achieve different resolutions of the analog-to-digital converter, and to stagger and add the comparison results of the sense amplifier in each comparison cycle as the final digital output.

[0016] Optionally, the sense amplifier is a 2-bit current sense amplifier, comprising: a first current sampling and subtraction circuit, a second current sampling and subtraction circuit, a latching and amplifying circuit, and a decision circuit;

[0017] The first and second current sampling and subtraction circuits include: a current sampling branch, a current subtraction branch, and a current storage circuit; the current sampling branch is turned on during the sampling phase to store a reference current or input current in the current storage circuit; the current subtraction branch is turned on during the comparison phase to subtract the reference current or input current from the current stored in the current storage circuit; the current storage circuit includes a MOS transistor and an energy storage element; the MOS transistor converts the drain current into a gate-source voltage and stores it in the energy storage element; similarly, when current needs to be released, the energy storage element provides the MOS transistor with the same gate-source voltage difference, thereby generating a corresponding drain current;

[0018] The latch amplification circuit adds a coupling capacitor to the input MOS transistor, wherein the coupling capacitor stores the threshold voltage of the input MOS transistor of the latch amplification circuit during the current sampling phase, and converts the positive and negative relationship of the current difference into a change in the gate voltage of the input MOS transistor during the current subtraction phase, thereby improving the sensitivity of the latch amplification circuit; the latch amplification circuit amplifies the tiny voltage difference of the gate of the input MOS transistor and outputs it to the decision circuit;

[0019] The decision circuit is implemented by a combinational logic circuit, which converts the output of the lock and storage amplification circuit into high and low level signals that can be recognized by the digital circuit. At the same time, the output digital code value meets the requirements of the RSD algorithm and is directly used by subsequent circuits, thereby simplifying the circuit design.

[0020] Optionally, the operational circuit includes: a multiplication by two circuit and a subtraction circuit, wherein the multiplication by two circuit is used to convert the input current and the residual current generated by each conversion into twice the original current, thereby ensuring that the residual current output by the operational circuit does not exceed the measuring range; the subtraction circuit is used to realize the subtraction of the output current of the multiplication by two circuit and the selection circuit to generate the residual current for each conversion cycle.

[0021] Optionally, the selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier, and the selection reference current includes: a first selection reference current I L , the second selected reference current I (L+H) / 2 and the third selected reference current I H ;

[0022] Wherein, the first selected reference current I L is the minimum current that the current-mode cyclic analog-to-digital converter can convert, and the third selected reference current I His the maximum current that the current-mode cyclic analog-to-digital converter can convert, and the second selected reference current I (L+H) / 2 =(I L +I H ) / 2.

[0023] Optionally, the logic control circuit stores the comparison result output by the sensitive amplifier during each conversion cycle, controls the residual current to be stored in the sampling and holding circuit, and implements the staggered addition of the output results of multiple cycles to generate the final N-bit output of the analog-to-digital converter.

[0024] A second object of the present invention is to provide a current-mode circulating analog-to-digital conversion method, the method being implemented based on the current-mode circulating analog-to-digital converter according to claim 5, comprising:

[0025] Step 1: Sample and hold circuit for input current I IN Sampling and converting the input current I IN Input sense amplifier;

[0026] Step 2: The sense amplifier compares the input current with a sense amplifier reference current and outputs a comparison result;

[0027] Step 3: The selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier;

[0028] Step 4: The input current I IN After the multiplication circuit, it becomes 2I IN , the residual current I of this cycle is obtained by subtracting the selected reference current through the operation circuit. RES ;

[0029] Step 5: The residual current I RES The current is sampled by the sample-and-hold circuit and used as the input current for the next cycle, and steps 1-4 are repeated;

[0030] Step 6: The logic control circuit controls the number of cycles N, processes the output result of each cycle, and outputs the final analog-to-digital conversion result.

[0031] Optionally, the working process of the sense amplifier includes:

[0032] Sense amplifier input current I SAIN After being sampled by the sampling and holding circuit, the first reference current I REF_L , the second reference current I REF_H For comparison, if the input current I SAIN is less than the first reference current I REF_L, then the output D[1:0]=00; if the input current I SAIN Greater than the first reference current I REF_L At the same time, it is smaller than the second reference current I REF_H Then the output D[1:0]=01; if the input current I SAIN Greater than the second reference current I REF_H Then the output D[1:0]=10;

[0033] The first reference current I REF_L =I (L+H) / 2 -1 / 8(I H -I L ); the second reference current I REF_H =I (L+H) / 2 +1 / 8(I H -I L ).

[0034] Optionally, the operation process of the selection circuit includes: selecting a corresponding reference current according to the value of D[1:0] output by the sense amplifier and transmitting it to the operation circuit, and D[1:0]=00 selects the first selected reference current I L , D[1:0]=01 selects the second selection reference current I (L+H) / 2 , D[1:0]=10 selects the third selected reference current I H .

[0035] Optionally, the logic control circuit adds the obtained N groups of comparison results D[1:0] in a staggered manner and discards the last bit to obtain an N-bit analog-to-digital conversion result.

[0036] The beneficial effects of the present invention are:

[0037] The current-mode cyclic analog-to-digital converter and analog-to-digital conversion method of the present invention use a current-sensing amplifier as a comparison circuit to convert the difference between the current to be measured and the reference current into a voltage and then amplify it, thereby improving the sensitivity of the comparison circuit to weak signals and enhancing comparison accuracy. The 2-bit current-sensing amplifier adopts a differential input structure to enhance the circuit's anti-interference capability while achieving two-bit output per cycle, thereby reducing the offset error caused by the traditional dual-comparator circuit structure and lowering circuit power consumption.

[0038] The sensitive amplifier of the present invention combines current sampling and current subtraction circuits, first sampling the current and converting it into voltage storage, and then performing current subtraction, thereby avoiding the precision error caused by the current mirror copy in the traditional structure. By introducing a coupling capacitor, the threshold voltage of the input MOS tube can be stored in the current sampling stage, thereby improving the sensitivity of the latch and amplification circuit to the tiny voltage output by the previous stage sampling and subtraction circuit, and improving the comparison accuracy. The structure and control timing of the decision circuit are simpler, realizing the control of the subsequent stage selection circuit and completing the decoding of the 2-bit output.

[0039] Therefore, compared with the existing current-mode circulating analog-to-digital converter, the present invention effectively improves conversion accuracy and reduces circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 FIG. 4 is a circuit diagram of a 2-bit current-sensing amplifier according to an embodiment of the present invention.

[0042] Figure 2 4 is a control timing diagram of a 2-bit current-sensing amplifier according to an embodiment of the present invention.

[0043] Figure 3 This is a circuit diagram of a current-mode circulating analog-to-digital converter according to an embodiment of the present invention.

[0044] Figure 4 This is a structural block diagram of a current-mode circulating analog-to-digital converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0046] First, the basic theoretical knowledge involved in this application is introduced as follows:

[0047] Sense amplifiers are commonly used in storage circuits and are categorized as voltage- and current-sensing amplifiers. Voltage-mode sense amplifiers convert current into voltage for comparison. The measured current and reference current are converted to corresponding voltages via current-to-voltage conversion circuits, and then a voltage comparator circuit performs a judgment. Current-mode sense amplifiers directly compare the measured current with a reference current, converting the current difference into a voltage. This voltage difference is then compared with the inverter's flip-flop voltage or a reference voltage to generate an output.

[0048] Example 1:

[0049] This embodiment provides a current-mode circulating analog-to-digital converter, such as Figure 4 As shown, including:

[0050] A sample-and-hold circuit, configured to store the input current and the residual current, and convert the residual current into the input current of the next comparison cycle;

[0051] A sense amplifier is used to compare the magnitude relationship between the input current and the sense amplifier reference current and output the comparison result;

[0052] A selection circuit, configured to select a corresponding selection reference current according to a comparison result output by the sense amplifier;

[0053] an operation circuit, configured to operate on the input current and the selected reference current to obtain the residual current;

[0054] The logic control circuit is used to control the number of cycles, that is, to achieve different resolutions of the analog-to-digital converter, and to stagger and add the comparison results of the sense amplifier in each comparison cycle as the final digital output.

[0055] Example 2:

[0056] This embodiment provides a current-mode cyclic analog-to-digital converter. Figure 3 ,include:

[0057] A sample-and-hold circuit is used to store the input current and the residual current and convert the residual current into the input current of the next comparison cycle;

[0058] The sample-and-hold circuit of this embodiment includes: a sampling PMOS transistor P1, a sampling capacitor C1, and a sampling switch S2. One end of the sampling switch S2 is connected to the drain of the sampling PMOS transistor P1, and the other end is respectively connected to the sampling capacitor C1 and the gate of the sampling PMOS transistor P1. The source of the sampling PMOS transistor P1 is connected to the end of the sampling capacitor C1 that is not connected to the gate of the sampling PMOS transistor P1.

[0059] 2-bit sense amplifier, used to compare the input current with the reference current and output the comparison result;

[0060] Figure 1 A circuit diagram of a 2-bit current sensing amplifier of this embodiment includes: a first current sampling and subtraction circuit, a second current sampling and subtraction circuit, a latching and amplifying circuit, and a decision circuit;

[0061] The first sampling and subtraction circuit includes: a fifth switch NMOS transistor NM5, a sixth switch NMOS transistor NM6, a first sampling PMOS transistor PM0, a first sampling capacitor CP0, and a first sampling switch SW0; the source electrodes of the fifth switch NMOS transistor NM5 and the sixth switch NMOS transistor NM6 are respectively connected to the reference current I REF_L and the sense amplifier input current I SAIN The input terminal of the first sampling PMOS transistor is connected to the gate of the fifth switching NMOS transistor NM5, the gate of the sixth switching NMOS transistor NM6 is connected to the control signal PRE, the drains of the fifth switching NMOS transistor NM5 and the sixth switching NMOS transistor NM6 are connected and connected to the connection point of the first sampling PMOS transistor PM0 and the first switch SW0, and serve as the Q1 node of the first output pair; one end of the first sampling switch SW0 is connected to the drain of the first sampling PMOS transistor PM0, and the other end is respectively connected to the first sampling capacitor CP0 and the gate of the first sampling PMOS transistor PM0; the source of the first sampling PMOS transistor PM0 is connected to the end of the first sampling capacitor CP0 that is not connected to the gate of the first sampling PMOS transistor PM0;

[0062] The second sampling and subtraction circuit includes: a seventh switch NMOS transistor NM7, an eighth switch NMOS transistor NM8, a second sampling PMOS transistor PM1, a second sampling capacitor CP1, and a second sampling switch SW1; the sources of the seventh switch NMOS transistor NM7 and the eighth switch NMOS transistor NM8 are respectively connected to the sense amplifier input current I SAIN and reference current I REF_H The gate of the seventh switch NMOS transistor NM7 is connected to the control signal SG2, the gate of the eighth switch NMOS transistor NM8 is connected to the control signal PRE, the drains of the seventh switch NMOS transistor NM7 and the eighth switch NMOS transistor NM8 are connected and connected to the connection point between the second sampling PMOS transistor PM1 and the second sampling switch SW1 and serve as the QB1 node of the first output pair; one end of the second sampling switch SW1 is connected to the drain of the second sampling PMOS transistor PM1, and the other end is respectively connected to the second sampling capacitor CP1 and the gate of the second sampling PMOS transistor PM1; the source of the second sampling PMOS transistor PM1 is connected to the end of the second sampling capacitor CP1 that is not connected to the gate of the second sampling PMOS transistor PM1;

[0063] The latch amplification circuit includes: a second coupling capacitor CP2, a third coupling capacitor CP3, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a zeroth NMOS transistor NM0, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4; the source of the fourth PMOS transistor PM4 is connected to a power supply voltage, the gate is connected to a control signal SG1, and the drain is connected to the sources of the PMOS transistors PM2 and PM3; one end of the second coupling capacitor CP2 is connected to the Q1 node of the first output pair, one end is connected to the second switch SW2 and the gate of the second PMOS transistor PM2, and the other end of the second switch SW2 is connected to the drain of the second PMOS transistor PM2 as the Q2 node of the second output pair; one end of the third coupling capacitor CP3 is connected to the QB1 node of the first output pair, one end is connected to the third switch SW3 and the gate of the third PMOS transistor PM3, and the third switch The other end of SW3 is connected to the drain of the third PMOS transistor PM3 as the QB2 node of the second output pair; one end of the fourth switch SW4 is connected to the Q1 node of the first output pair, one end is connected to the drain of the zeroth NMOS transistor NM0 and the Q2 node of the second output pair, the gate of the zeroth NMOS transistor NM0 is connected to the control signal SG1, and the source is connected to the ground; one end of the fifth switch SW5 is connected to the QB1 node of the first output pair, one end is connected to the drain of the first NMOS transistor NM1 and the QB2 node of the second output pair, the first NMOS transistor NM0 is connected to the QB1 node of the first output pair, The gate of the MOS transistor NM1 is connected to the control signal SG1, and the source is connected to ground; the drain of the second NMOS transistor NM2 is connected to the Q2 node of the second output pair and the gate of the third NMOS transistor NM3, the drain of the third NMOS transistor NM3 is connected to the QB2 node of the second output pair and the gate of the second NMOS transistor NM2, the sources of the second NMOS transistor NM2 and the third NMOS transistor NM3 are connected to the drain of the fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is connected to the control signal EN, and the source is connected to ground;

[0064] The decision circuit includes: a first inverter INV1, a second inverter INV2, a third inverter INV3 and an AND gate AND1; the input end of the first inverter INV1 is connected to the QB2 node of the second output pair, the input end of the second inverter INV2 is connected to the Q2 node of the second output pair, and the control ends of the first inverter INV1 and the second inverter INV2 are connected to the control signal EN; the input end of the third inverter INV3 is connected to the output end A2 of the first inverter INV1, and the output end serves as D[1]; one input end of the AND gate AND1 is connected to the output end A2 of the first inverter INV1, and the other input end is connected to the output end A1 of the second inverter INV2, and the output end serves as D[0].

[0065] The working principle of the 2-bit sense amplifier of this embodiment is as follows: wherein the control signals SG2 and SG2N are opposite signals to each other.

[0066] Standby mode: When sampling signal PRE is low, the corresponding NMOS transistors NM6 and NM7 are turned off. When control signal SG1 is high, the corresponding switches SW4 and SW5 are turned on, NMOS transistors NM0 and NM1 are turned on, and PMOS transistor PM4 is turned off. When control signal SG2 is low, the corresponding NMOS transistors NM5 and NM7 are turned off. When control signal SG2N is high, the corresponding switches SW0, SW1, SW2, and SW3 are turned on. When control signal EN is low, the corresponding NMOS transistor NM4 is turned off, and the corresponding inverters INV1 and INV2 are disabled. The nodes of the first output pair Q1 and QB1 and the second output pair Q2 and QB2 are discharged to a low level.

[0067] Phase 1: The sampling signal PRE is high, and the corresponding NMOS transistors NM6 and NM7 are turned on; the control signal SG1 is low, and the corresponding switches SW4 and SW5 are turned off, the NMOS transistors NM0 and NM1 are turned off, and the PMOS transistor PM4 is turned on; the control signal SG2 is low, and the corresponding NMOS transistors NM5 and NM7 are turned off; the control signal SG2N is high, and the corresponding switches SW0, SW1, SW2, and SW3 are turned on; the control signal EN is low, and the corresponding NMOS transistor NM4 is turned off, and the corresponding inverters INV1 and INV2 do not work. Sense amplifier input current I SAIN and reference current I REF_H It is stored in the form of gate-source voltage on CP0 and CP1, and the threshold voltage Vth of the differential input PMOS transistors PM2 and PM3 is stored on the plates of capacitors CP2 and CP3 connected to the gates of PM2 and PM3 respectively.

[0068] Phase 2: The sampling signal PRE is at a low level, and the corresponding NMOS transistors NM6 and NM7 are turned off; the control signal SG1 is at a low level, and the corresponding switches SW4 and SW5 are turned off, the NMOS transistors NM0 and NM1 are turned off, and the PMOS transistor PM4 is turned on; the control signal SG2 is at a high level, and the corresponding NMOS transistors NM5 and NM7 are turned on; the control signal SG2N is at a low level, and the corresponding switches SW0, SW1, SW2, and SW3 are turned off; the control signal EN is at a low level, and the corresponding NMOS transistor NM4 is turned off, and the corresponding inverters INV1 and INV2 do not work. The voltage change value of the first output pair Q1 and QB1 nodes in this phase is ΔVQ1=[(I SAIN -I REF_L )×T PH2 ] / CP2, the voltage change value of QB1 point ΔVQB1=[(I REF_H -I SAIN )×TPH2 ] / CP3, where T PH2 The time of the second phase is CP2 = CP3. If ΔVQ1 and ΔVQB1 are greater than zero, the voltage at the node of the second output pair Q2 and QB2 does not fluctuate; if ΔVQ1 and ΔVQB1 are less than zero, the voltage at the node of the second output pair Q2 and QB2 increases.

[0069] Phase 3: The sampling signal PRE is at a low level, and the corresponding NMOS transistors NM6 and NM7 are turned off; the control signal SG1 is at a low level, and the corresponding switches SW4 and SW5 are turned off, the NMOS transistors NM0 and NM1 are turned off, and the PMOS transistor PM4 is turned on; the control signal SG2 is at a high level, and the corresponding NMOS transistors NM5 and NM7 are turned on; the control signal SG2N is at a low level, and the corresponding switches SW0, SW1, SW2, and SW3 are turned off; the control signal EN is at a high level, and the corresponding NMOS transistor NM4 is turned on, and the corresponding inverters INV1 and INV2 are working. In this phase, a decision is made based on the voltage value at the second output pair Q2 and QB2 nodes. When the voltage at the second output pair Q2 and QB2 nodes is less than the inverter's reverse voltage, A1 and A2 are 1; when the voltage at the second output pair Q2 and QB2 nodes is greater than the inverter's reverse voltage, A1 and A2 are 0. Therefore, A1 and A2 will have three situations, namely: the sense amplifier input current I SAIN REF_L REF_H When A1=0, A2=1; the input current of the sensitive amplifier I REF_L SAIN REF_H When A1=1, A2=1; the input current of the sensitive amplifier I REF_L REF_H SAIN When A1=1, A2=0, the corresponding output D[1:0] is 00, 01 and 10.

[0070] Figure 2 This is the control timing diagram of the above 2-bit current-sensing amplifier.

[0071] A selection circuit, configured to select a corresponding reference current according to a comparison result output by the sense amplifier;

[0072] The selection circuit of this embodiment includes: a fifth selection PMOS transistor P5, a sixth selection PMOS transistor P6, a seventh selection PMOS transistor P7, an eighth selection PMOS transistor P8, a fourth selection NMOS transistor N4, and a fifth selection NMOS transistor N5;

[0073] The gate of the fifth selection PMOS transistor P5 and the sixth selection PMOS transistor P6 are connected to the output end of the sense amplifier;

[0074] ​​​​​​The gates of the fifth selection PMOS transistor P5, the fourth selection NMOS transistor N4, and the eighth selection PMOS transistor P8 are connected in sequence; the gates of the sixth selection PMOS transistor P6, the seventh selection PMOS transistor P7, and the fifth selection NMOS transistor N5 are connected in sequence;

[0075] The drain of the fifth selection PMOS transistor P5 is connected to the source of the sixth selection PMOS transistor P6, and the drain of the sixth selection PMOS transistor P6 is externally connected to the first selection reference current I L ;

[0076] The drain of the fourth selection NMOS transistor N4 is connected to the drain of the seventh selection PMOS transistor P7, and the source of the seventh selection PMOS transistor P7 is externally connected to the second selection reference current I (L+H) / 2 ;

[0077] The drain of the eighth selection PMOS transistor P8 is connected to the drain of the fifth selection NMOS transistor N5, and the source of the fifth selection NMOS transistor N5 is externally connected to the third selection reference current I H ;

[0078] The operation circuit is used to operate the input current, and includes: a second operation PMOS tube P2, a third operation PMOS tube P3 and a fourth operation PMOS tube P4 forming a double current mirror.

[0079] The logic control circuit is used to control the number of cycles, that is, to achieve different resolutions of the analog-to-digital converter, and to stagger and add the comparison results of the sensitive amplifier in each comparison cycle as the final digital output.

[0080] The working process of the current-mode circulating analog-to-digital converter of this embodiment is as follows:

[0081] Sample / hold phase: switch S1 is connected to the input signal I IN , switch S2 is closed, input current I IN It is stored on C1 in the form of gate-source voltage.

[0082] Conversion stage 1: switch S1 is connected to N1, S2 is disconnected, and the current stored on C1 is copied to the input of the current sense amplifier through the current mirror composed of N1 and N2, and is combined with the two reference currents I REF_H and I REF_L The current stored on C1 is copied by the double current mirror composed of P2 to P4 and becomes 2I IN The selection circuit composed of P5~P8, N4, and N5 is turned on according to the value of D[1:0], and the corresponding reference current I L , I H , I (L+H) / 2 Copy to the left path, and add it to the above 2I INSubtract the current to get the residual current I RES1 .

[0083] Conversion stage 2: switch S1 is connected to N6, S2 is closed, and the residual current I obtained in conversion stage 1 is RES1 It is stored on C1 in the form of gate-source voltage. Then switch S1 is connected to N1, S2 is disconnected, and the current stored on C1 is copied to the input of the current sense amplifier through the current mirror composed of N1 and N2, and is combined with the two reference currents I REF_H and I REF_L The current stored on C1 is copied by the double current mirror composed of P2 to P4 and becomes 2I RES1 , subtracted from the reference current output by the selection circuit to obtain the residual current I RES2 .

[0084] Conversion phases 3 to N: Same as conversion phase 2.

[0085] After N cycles are completed, the obtained N groups of D[1:0] are staggered and added by the logic control circuit, and the last bit is discarded to obtain the N-bit conversion result.

[0086] The current-mode cyclic analog-to-digital converter of this embodiment uses a current-sensing amplifier as a comparison circuit to convert the difference between the measured current and the reference current into a voltage for amplification, thereby increasing the comparison circuit's sensitivity to weak signals and improving comparison accuracy. The 2-bit current-sensing amplifier uses a differential input structure to enhance the circuit's anti-interference capability while generating two outputs per cycle, reducing the offset error introduced by the traditional dual-comparator circuit structure and lowering circuit power consumption.

[0087] The sense amplifier in this embodiment combines current sampling and current subtraction circuits. Current sampling is first performed and converted into voltage storage before current subtraction is performed, thus avoiding the precision error caused by the current mirror copy in the traditional structure. By introducing coupling capacitors CP2 and CP3, the threshold voltage of the input PMOS transistors PM2 and PM3 is stored during the current sampling stage, thereby improving the sensitivity of the latch and amplification circuit to the tiny voltage output by the previous stage sampling and subtraction circuit, thereby improving comparison accuracy. The structure and control timing of the decision circuit are simpler, realizing control of the subsequent stage selection circuit and completing decoding of the 2-bit output.

[0088] Example 3:

[0089] This embodiment provides a current-mode circulating analog-to-digital conversion method, which is implemented using the current-mode circulating analog-to-digital converter described in the first or second embodiment, including:

[0090] Step 1: Sample and hold circuit for input current I IN Sampling and converting the input current IIN Input sense amplifier;

[0091] Step 2: The sense amplifier compares the input current with a sense amplifier reference current and outputs a comparison result;

[0092] Step 3: The selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier;

[0093] Step 4: The input current I IN After the multiplication circuit, it becomes 2I IN , the residual current I of this cycle is obtained by subtracting the selected reference current through the operation circuit. RES ;

[0094] Step 5: The residual current I RES The current is sampled by the sample-and-hold circuit and used as the input current for the next cycle, and steps 1-4 are repeated;

[0095] Step 6: The logic control circuit controls the number of cycles N, processes the output result of each cycle, and outputs the final analog-to-digital conversion result.

[0096] Example 4:

[0097] This embodiment provides a current-mode circulating analog-to-digital conversion method, which is implemented using the current-mode circulating analog-to-digital converter described in the second embodiment, including:

[0098] Step 1: Sample and hold circuit for input current I IN Sampling is performed and the input current is input to the sense amplifier;

[0099] The switch S1 is connected to N1, S2 is disconnected, and the current stored on C1 is copied to the input end of the current sense amplifier through the current mirror composed of N1 and N2.

[0100] Step 2: The sense amplifier compares the input current with the amplifier reference current and outputs the comparison result;

[0101] Sense amplifier input current I SAIN After being sampled by the sample and hold circuit, it is compared with the first reference current I REF_L , the second reference current I REF_H For comparison, if the input current I SAIN Less than the first reference current I REF_L , then the output D[1:0]=00; if the input current I SAIN Greater than the first reference current I REF_L At the same time, it is less than the second reference current I REF_H Then the output D[1:0]=01; if the input current I SAINGreater than the second reference current I REF_H Then the output D[1:0]=10;

[0102] The first reference current I REF_L =I (L+H) / 2 -1 / 8(I H -I L ); the second reference current I REF_H =I (L+H) / 2 +1 / 8(I H -I L ).

[0103] Step 3: The selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier;

[0104] According to the value of D[1:0] output by the sense amplifier, the corresponding reference current is selected and transmitted to the operation circuit. When D[1:0]=00, the first selected reference current I L , D[1:0]=01 selects the second selection reference current I (L+H) / 2 , D[1:0]=10 selects the third selected reference current I H .

[0105] Step 4: The input current I IN After the multiplication circuit, it becomes 2I IN , the residual current I of this cycle is obtained by subtracting the selected reference current through the operation circuit. RES1 ;

[0106] Step 5: The residual current I RES1 The current is sampled by the sample-and-hold circuit and used as the input current for the next cycle, and steps 1-4 are repeated;

[0107] Switch S1 is connected to N6, S2 is closed, and the residual current I obtained in the first cycle RES1 It is stored on C1 in the form of gate-source voltage. Then switch S1 is connected to N1, S2 is disconnected, and the current stored on C1 is copied to the input of the current sense amplifier through the current mirror composed of N1 and N2, and is combined with the two reference currents I REF_H and I REF_L The current stored on C1 is copied by the double current mirror composed of P2 to P4 and becomes 2I RES1 , subtracted from the reference current output by the selection circuit to obtain the residual current I RES2 .

[0108] Continue the cyclic comparison according to the above steps and complete the preset number of cycles.

[0109] Step 6: The logic control circuit controls the number of cycles N, and adds the N groups of comparison results D[1:0] obtained by staggering and discarding the last bit to obtain the N-bit analog-to-digital conversion result.

[0110] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A current-mode circulating analog-to-digital converter, characterized in that: include: A sample-and-hold circuit, configured to store the input current and the residual current, and convert the residual current into the input current of the next comparison cycle; A sense amplifier is used to compare the magnitude relationship between the input current and the sense amplifier reference current and output the comparison result; A selection circuit, configured to select a corresponding selection reference current according to a comparison result output by the sense amplifier; an operation circuit, configured to operate on the input current and the selected reference current to obtain the residual current; A logic control circuit for controlling the number of cycles, i.e., achieving different resolutions of the analog-to-digital converter, and performing staggered addition of the comparison results of the sense amplifier in each comparison cycle as a final digital output; The sensitive amplifier is a 2-bit current sensitive amplifier, comprising: a first current sampling and subtraction circuit, a second current sampling and subtraction circuit, a latching and amplifying circuit, and a decision circuit; The first and second current sampling and subtraction circuits include: a current sampling branch, a current subtraction branch, and a current storage circuit; the current sampling branch is turned on during the sampling phase to store a reference current or input current in the current storage circuit; the current subtraction branch is turned on during the comparison phase to subtract the reference current or input current from the current stored in the current storage circuit; the current storage circuit includes a MOS transistor and an energy storage element; the MOS transistor converts the drain current into a gate-source voltage and stores it in the energy storage element; similarly, when current needs to be released, the energy storage element provides the MOS transistor with the same gate-source voltage difference, thereby generating a corresponding drain current; The latch amplification circuit adds a coupling capacitor to the input MOS transistor, wherein the coupling capacitor stores the threshold voltage of the input MOS transistor of the latch amplification circuit during the current sampling phase, and converts the positive and negative relationship of the current difference into a change in the gate voltage of the input MOS transistor during the current subtraction phase, thereby improving the sensitivity of the latch amplification circuit; the latch amplification circuit amplifies the tiny voltage difference of the gate of the input MOS transistor and outputs it to the decision circuit; The decision circuit is implemented by a combinational logic circuit, which converts the output of the lock and storage amplification circuit into high and low level signals that can be recognized by the digital circuit. At the same time, the output digital code value meets the requirements of the RSD algorithm and is directly used by subsequent circuits, thereby simplifying the circuit design.

2. The current-mode circulating analog-to-digital converter according to claim 1, wherein: The arithmetic circuit includes: a multiplication by two circuit and a subtraction circuit, wherein the multiplication by two circuit is used to convert the input current and the residual current generated by each conversion into twice the original current, thereby ensuring that the residual current output by the arithmetic circuit does not exceed the range; the subtraction circuit is used to realize the subtraction of the output current of the multiplication by two circuit and the selection circuit to generate the residual current of each conversion cycle.

3. The current-mode circulating analog-to-digital converter according to claim 2, wherein: The selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier, and the selection reference current includes: a first selection reference current I L , the second selected reference current I (L+H) / 2 and the third selected reference current I H ; Wherein, the first selected reference current I L is the minimum current that the current-mode cyclic analog-to-digital converter can convert, and the third selected reference current I H is the maximum current that the current-mode cyclic analog-to-digital converter can convert, and the second selected reference current I (L+H) / 2 =(I L +I H ) / 2.

4. The current-mode circulating analog-to-digital converter according to claim 3, wherein: The logic control circuit stores the comparison result output by the sense amplifier during each conversion cycle, controls the residual current to be stored in the sample and hold circuit, and implements the staggered addition of the output results of multiple cycles to generate the final N-bit output of the analog-to-digital converter.

5. A current mode cycle type analog-to-digital conversion method, characterized in that: The method is implemented based on the current-mode circulating analog-to-digital converter according to claim 4, comprising: Step 1: Sample and hold circuit for input current I IN Sampling and converting the input current I IN Input sense amplifier; Step 2: The sense amplifier compares the input current with a sense amplifier reference current and outputs a comparison result; Step 3: The selection circuit selects a corresponding selection reference current according to the comparison result output by the sense amplifier; Step 4: The input current I IN After the multiplication circuit, it becomes 2I IN , the residual current I of this cycle is obtained by subtracting the selected reference current through the operation circuit. RES ; Step 5: The residual current I RES The current is sampled by the sample-and-hold circuit and used as the input current for the next cycle, and steps 1-4 are repeated; Step 6: The logic control circuit controls the number of cycles N, processes the output result of each cycle, and outputs the final analog-to-digital conversion result.

6. The current mode cycle type analog-to-digital conversion method according to claim 5, characterized in that: The working process of the sense amplifier includes: Sense amplifier input current I SAIN After being sampled by the sampling and holding circuit, the first reference current I REF_L , the second reference current I REF_H For comparison, if the input current I SAIN is less than the first reference current I REF_L , then the output D[1:0]=00; if the input current I SAIN Greater than the first reference current I REF_L At the same time, it is smaller than the second reference current I REF_H Then the output D[1:0]=01; if the input current I SAIN Greater than the second reference current I REF_H Then the output D[1:0]=10; The first reference current I REF_L =I (L+H) / 2 -1 / 8(I H -I L ); the second reference current I REF_H =I (L+H) / 2 +1 / 8(I H -I L ).

7. The current mode cycle type analog-to-digital conversion method according to claim 6, characterized in that: The working process of the selection circuit includes: selecting the corresponding reference current according to the value of D[1:0] output by the sense amplifier and transmitting it to the operation circuit, and D[1:0]=00 selects the first selected reference current I L , D[1:0]=01 selects the second selection reference current I (L+H) / 2 , D[1:0]=10 selects the third selected reference current I H .

8. The current mode cycle type analog-to-digital conversion method according to claim 7, characterized in that: The logic control circuit adds the obtained N groups of comparison results D[1:0] in a staggered manner and discards the last bit to obtain an N-bit analog-to-digital conversion result.

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