A method for generating large-bandwidth linear frequency modulation signals based on high-speed DAC and FPGA

Abstract

The present invention provides a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and an FPGA, comprising: determining the parameters of a DDS IP core by using the parameters of a high-speed DAC; calculating the phase control words k0 and Δk by using the bandwidth B and duration τ of the LFM signal; inputting k0 and Δk into the FPGA, and the FPGA calculating the phase offset k according to k0 and Δk. off (m), initial phase increment k inc (m,0), the change in phase increment dk inc , and then according to dk inc Calculate the input phase control word increment k inc (m,i); configure M DDS IP cores and set k off (m) and k inc (m,i) is fed into M DDS IP cores, which output M complex signals. A high-speed DAC is configured to upconvert these M complex signals, which then output a wide-bandwidth LFM signal. This method can generate wideband LFM signals with arbitrary frequency modulation slopes, provided the signal bandwidth is less than or equal to the DAC sampling bandwidth. This method offers high flexibility and minimizes bandwidth accumulation errors due to precision.

Description

Technical Field

[0001] The present invention relates to the technical field of radar signal processing, and in particular to a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and an FPGA. Background Art

[0002] Wideband linear frequency modulation (LFM) signals are widely used in remote sensing satellite signal processing systems. They are a common signal in remote sensing payloads such as ground-based radars, spaceborne SAR (SAR), and scatterometers. Wideband radar signals possess higher spatial resolution than narrowband radar signals, increasing the system's information storage capacity and providing more frequency-domain information about the target, providing a more robust basis for target identification. Furthermore, wideband radar signals can reduce the effects of multipath and enhance the radar's anti-interference capabilities. Radar detection range is related to transmitted signal power: longer ranges require greater transmit power, but transmit power is limited by the transmitter and feed system. Due to frequency resolution, wideband radar signals typically have large pulse widths, and wide pulses can enhance radar signal transmit power.

[0003] Due to the limitations of the Nyquist sampling rate, broadband signal generation currently mostly relies on controlling DDS chips. However, high-performance DDS chips are expensive and are primarily used in the RF modules of radar systems. Domestic literature describes using multipliers and accumulators to generate phase control words, and then using a multi-path lookup table to generate broadband LFM signals. This method is inflexible, and the wider the LFM bandwidth, the greater the accumulated error, causing the actual bandwidth to differ from the required bandwidth. Furthermore, the bandwidth of the generated linear frequency modulation signal is limited by the processing clock rate, placing stringent requirements on timing control. Summary of the Invention

[0004] The present invention aims to provide a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and FPGA to solve the above-mentioned problems.

[0005] The present invention provides a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and an FPGA, comprising the following steps:

[0006] Step 1: Use half the sampling rate f of the high-speed DAC s The DDS IP core processing clock rate f is calculated based on the number of channels M. DDS , determine the phase control word quantization bit number q of the DDS IP core, and determine the DDS IP core output data bit width based on the high-speed DAC working data bit width;

[0007] Step 2: Pre-calculate the DDS phase control word k0 corresponding to the starting frequency f0 and the DDS phase control word Δk corresponding to the frequency increment Δf using the bandwidth B and duration τ of the LFM signal;

[0008] Step 3: Use the phase control word k0 and Δk as the input signal of FPGA. FPGA calculates the phase offset k of each DDS IP core based on the phase control word k0 and Δk. off (m) and the initial phase increment k inc (m,0);

[0009] Step 4: FPGA calculates the phase increment change dk of each DDS IP core based on the phase control word k0 and Δk inc , and then according to the change in phase increment dk inc Iteratively calculate the input phase control word increment k of each DDS IP core at time i inc (m,i);

[0010] Step 5: Configure M DDS IP cores and set the phase offset to k off (m) and the phase control word increment k inc (m,i) are fed into M DDS IP cores respectively, and M multiplexed signals are output;

[0011] Step 6: Configure a high-speed DAC and send the M-channel multiplexed signals to the high-speed DAC for up-conversion. The high-speed DAC outputs a large-bandwidth LFM signal.

[0012] Furthermore, step 2 includes the following sub-steps:

[0013] Step 2-1, the expression of LFM signal is:

[0014]

[0015] Where f0 is the starting frequency; Indicates the frequency modulation slope of the signal; t is time;

[0016] Step 2-2, the phase expression of the LFM signal is:

[0017]

[0018] Step 2-3: Discretize time t to obtain the phase expression:

[0019]

[0020] Among them, T s =1 / f s is the sampling period of the complex signal; N = f s τ, represents the number of sampling points within the duration of the LFM signal;

[0021] Step 2-4, make Represents the frequency step of each sampling point, and the phase expression is further expressed as:

[0022]

[0023] Step 2-5: quantize the phase of the LFM signal to 2π by q bits. The quantized phase is expressed as:

[0024]

[0025] Step 2-6: Extract the phase of step 2-5 into M paths. The phase of the mth path is expressed as:

[0026]

[0027] in, represents the i-th time point of the m-th road;

[0028] make Indicates the DDS phase control word k0 corresponding to the starting frequency f0 in each DDS IP core;

[0029] make Indicates the DDS phase control word Δk corresponding to the frequency increment Δf in each DDS IP core.

[0030] Furthermore, the phase of the m-th DDS IP core based on the phase control word k0 and Δk is expressed as:

[0031]

[0032] Furthermore, the phase offset k of the m-th DDS IP core in step 3 is off (m) is expressed as:

[0033]

[0034] Furthermore, the initial phase increment k of the m-th DDS IP core in step 3 is inc (m,0) is expressed as:

[0035]

[0036] Furthermore, the phase increment change dk of the m-th DDS IP core in step 4 is inc Expressed as:

[0037]

[0038] Furthermore, in step 4, the input phase control word increment k of the m-th DDS IP core at time i inc (m,i) is expressed as:

[0039]

[0040] Furthermore, step 5 is specifically as follows:

[0041] Configure the DDS IP core operating mode to Phase Generator and SIN COS LUT, the phase control word width to q, and the operating clock to f DDS , configure the DDS IP core output data width to be consistent with the high-speed DAC working data width, and set the phase offset of the m-th DDS IP core to k off (m) Connect to the CHAN_0_POFF interface of the DDS IP core and increment the input phase control word of the m-th DDS IP core at time i by k inc (m,i) is connected to the CHAN_0_PINC interface of the DDS IP core, and the DDS IP core outputs M-channel multiplexed signals.

[0042] Furthermore, step 6 is specifically as follows:

[0043] Configure the high-speed DAC to have a center frequency of f c , send the M-channel multiplexed signal to the high-speed DAC module to complete the up-conversion, and send the analog signal output by the high-speed DAC to the center frequency f c , an analog filter with a bandwidth of B; the output center frequency of the analog filter is f c , a large-bandwidth LFM signal with a bandwidth of B.

[0044] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0045] 1. The present invention can generate a broadband LFM signal with any frequency modulation slope under the condition that the signal bandwidth is less than or equal to the DAC sampling bandwidth, with high flexibility and small bandwidth accumulation error caused by precision.

[0046] 2. The present invention adopts a multi-channel data parallel processing method, which greatly reduces the FPGA's requirements for the processing clock rate and timing risks, and solves the limitation of generating broadband LFM signals with the help of a dedicated DDS chip.

[0047] 3. The present invention has a clear principle and a simple structure, and is easy to implement in FPGA hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly introduced below. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 This is a flow chart of a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and FPGA in an embodiment of the present invention.

[0050] Figure 2 This is a spectrum diagram after integrating multi-channel DDS data in an embodiment of the present invention.

[0051] Figure 3 1 is a waveform spectrum diagram of the DAC output of the hardware platform in an embodiment of the present invention.

[0052] Figure 4 4 is a waveform spectrum diagram of the analog filter output of the hardware platform in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0055] Example

[0056] like Figure 1 As shown, this embodiment proposes a method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and an FPGA, comprising the following steps:

[0057] Step 1: Use half the sampling rate f of the high-speed DAC s The DDS IP core processing clock rate f is calculated based on the number of channels M. DDS , determine the phase control word quantization bit number q of the DDS IP core, and determine the DDS IP core output data bit width based on the high-speed DAC working data bit width;

[0058] Step 2: Pre-calculate the DDS phase control word k0 corresponding to the starting frequency f0 and the DDS phase control word Δk corresponding to the frequency increment Δf using the bandwidth B and duration τ of the LFM signal (linear frequency modulation signal):

[0059] Step 2-1, the expression of LFM signal is:

[0060]

[0061] Where f0 is the starting frequency; Indicates the frequency modulation slope of the signal; t is time;

[0062] Step 2-2, the phase expression of the LFM signal is:

[0063]

[0064] Step 2-3: Discretize time t to obtain the phase expression:

[0065]

[0066] Among them, T s =1 / f s is the sampling period of the complex signal; N = f s τ, represents the number of sampling points within the duration of the LFM signal;

[0067] Step 2-4, make Represents the frequency step of each sampling point, and the phase expression is further expressed as:

[0068]

[0069] Step 2-5: quantize the phase of the LFM signal to 2π by q bits. The quantized phase is expressed as:

[0070]

[0071] Step 2-6: Extract the phase of step 2-5 into M paths. The phase of the mth path is expressed as:

[0072]

[0073] in, represents the i-th time point of the m-th road;

[0074] make Indicates the DDS phase control word k0 corresponding to the starting frequency f0 in each DDS IP core;

[0075] make Indicates the DDS phase control word Δk corresponding to the frequency increment Δf in each DDS IP core;

[0076] The phase of the m-th DDS IP core is expressed as:

[0077]

[0078] Step 3: Use the phase control word k0 and Δk as the input signal of FPGA. FPGA calculates the phase offset k of each DDS IP core based on the phase control word k0 and Δk. off (m) and the initial phase increment k inc (m,0):

[0079] Step 3-1: Phase offset k of the m-th DDS IP core off (m) is expressed as:

[0080]

[0081] Step 3-2: Initial phase increment k of the m-th DDS IP core inc (m,0) is expressed as:

[0082]

[0083] Step 4: FPGA calculates the phase increment change dk of each DDS IP core based on the phase control word k0 and Δk inc , and then according to the change in phase increment dk inc Iteratively calculate the input phase control word increment k of each DDS IP core at time i inc (m,i):

[0084] Step 4-1: The change in phase increment dk of the m-th DDS IP core inc Expressed as:

[0085]

[0086] Step 4-2: The input phase control word increment k of the m-th DDS IP core at time i inc (m,i) is expressed as:

[0087]

[0088] From steps 2-4, we can see that when f0>f DDS When the phase control word k0 is used, the binary representation of the number of bits is greater than q bits, resulting in data overflow. However, due to the periodicity of trigonometric functions about 2π, when the phase control word k0 is used to calculate the phase increment k(m,i), the lower q bits can be directly taken. When the phase control word k0 is used to calculate the phase offset k off When Then take the lower q bits of the result. At the same time, the FPGA division operation requires a divider. Due to the influence of the divider accuracy, the phase error will accumulate. Therefore, try to select M as an integer power of 2. In this way, the division operation can be replaced by a shift operation, and the error will be very small. It can also be pre-calculated in the software and The value is converted into binary and used as the input signal of FPGA, and then multiplication and addition operations are performed in FPGA. Similarly, the phase control word data overflow caused by multiplication and addition operations can be directly taken as its low q bits.

[0089] Step 5: Configure M DDS IP cores and set the phase offset to k off (m) and the phase control word increment k inc (m,i) are fed into M DDS IP cores respectively, and M multiplexed signals are output:

[0090] Configure the DDS IP core operating mode to Phase Generator and SIN COS LUT, the phase control word width to q, and the operating clock to f DDS , configure the DDS IP core output data width to be consistent with the high-speed DAC working data width, and set the phase offset of the m-th DDS IP core to k off (m) Connect to the CHAN_0_POFF interface of the DDS IP core and increment the input phase control word of the m-th DDS IP core at time i by k inc (m,i) is connected to the CHAN_0_PINC interface of the DDS IP core, and the DDS IP core outputs M-channel multiplexed signals.

[0091] Step 6. Configure the high-speed DAC and send the M-channel multiplexed signal to the high-speed DAC for up-conversion. The high-speed DAC outputs a large-bandwidth LFM signal:

[0092] Configure the high-speed DAC to have a center frequency of f c , send the M-channel multiplexed signal to the high-speed DAC module to complete the up-conversion, and send the analog signal output by the high-speed DAC to the center frequency f c , an analog filter with a bandwidth of B; the output center frequency of the analog filter is f c , a large-bandwidth LFM signal with a bandwidth of B.

[0093] Example:

[0094] (1) High-speed DAC operating parameters: The high-speed DAC chip model is AD9164, which supports 2.4GHz sampling, sampling bandwidth is 1GHz, working data bit width is 16bit, and center frequency is 1.8GHz, thus determining the half sampling rate f s =1.2GHz, number of channels M=8, calculate the DDS IP core processing clock rate f DDS =150MHz.

[0095] (2) DDS IP core configuration parameters: Phase control word quantization bit number q = 32 bits, DDS IP core output data bit width is determined to be 16 bits according to the high-speed DAC working data bit width, phase offset and phase increment are selected as Programmable mode, and output is selected as Sine and Cosine mode.

[0096] (3) LFM signal parameters: bandwidth B = 1 GHz, duration τ = 1 ms, starting frequency f0 = -500 MHz, corresponding DDS phase control word k0 = 0xCAAAAAAAB, frequency increment Δf = 8.33 MHz, corresponding phase control word Δk = 0x5D34.

[0097] (4) The phase control word k0 and Δk are used as the input signal of FPGA. FPGA calculates the change dk of the phase control word increment of each DDS IP core based on the phase control word k0 and Δk. inc =M·Δk=0x2E9A0, and the phase offset k of each DDSIP core off (m), initial phase increment k inc (m,0).

[0098] (5) Figure 2 The digital signal output by the DDS shown in the figure is sent to the high-speed DAC interface module, and the analog signal spectrum output by the high-speed DAC is as follows: Figure 3 As shown, it can be seen that the spectrum not only has a 1 GHz bandwidth signal at 1.8 GHz, but also has a 1 GHz bandwidth periodic image component at 0.6 GHz.

[0099] (6) After the signal output by the high-speed DAC is up-converted, it is input into the analog filter. The center frequency of the analog filter output is configured to be 3 GHz and the bandwidth is 1 GHz. The final output is an LFM signal with a center frequency of 3 GHz and a bandwidth of 1 GHz, such as Figure 4 shown.

[0100] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and an FPGA, characterized in that: The following steps are involved: Step 1: Half the sampling rate of a high-speed DAC and number of channels M Calculate and determine the DDS IP core processing clock rate , determine the number of quantization bits of the phase control word of the DDS IP core , and determine the DDS IP core output data bit width based on the high-speed DAC working data bit width; Step 2: Bandwidth of the LFM signal and duration Pre-calculate the starting frequency The corresponding DDS phase control word , and the frequency increment The corresponding DDS phase control word ; Step 3: Set the phase control word and As the input signal of FPGA, FPGA controls the phase of the signal. and Calculate the phase offset of each DDS IP core and the initial phase increment ; Step 4: FPGA controls the phase of the and Calculate the phase increment change of each DDS IP core , and then according to the change of phase increment Iteratively calculate the input phase control word increment of each DDS IP core at time i ; Step 5. Configuration M A DDS IP core, the phase offset and phase control word increment Send in separately M DDS IP core, output M The specific steps of step 5 are as follows: configure the DDS IP core working mode to Phase Generator and SIN COS LUT, and the phase control word width is q , the working clock is , configure the DDS IP core output data width to be consistent with the high-speed DAC working data width, and offset the phase of the m-th DDS IP core Connect to the CHAN_0_POFF interface of the DDS IP core and increment the input phase control word of the mth DDS IP core at time i Connect to the CHAN_0_PINC interface of the DDS IP core, and the DDS IP core outputs M-channel multiplexed signals; Step 6: Configure the high-speed DAC. M The multiplexed signal is sent to a high-speed DAC for up-conversion, and the high-speed DAC outputs a large-bandwidth LFM signal; Step 2 includes the following sub-steps: Step 2-1, the expression of LFM signal is: in, is the starting frequency; , represents the frequency modulation slope of the signal; For time; Step 2-2, the phase expression of the LFM signal is: Step 2-3: Discretize time t to obtain the phase expression: ， in, is the sampling period of the complex signal; , represents the number of sampling points within the duration of the LFM signal; Step 2-4, make , represents the frequency step of each sampling point, then the phase expression is further expressed as: Step 2-5: Align the phase of the LFM signal conduct Bit quantization, the quantized phase is expressed as: Step 2-6, the phase of step 2-5 M If the mth path is extracted, the phase of the mth path is expressed as: in, , represents the i-th time point of the m-th road; make , indicating the starting frequency of each DDS IP core The corresponding DDS phase control word ; make , which indicates the frequency increment in each DDS IP core The corresponding DDS phase control word ; Based on phase control word and The phase of the m-th DDS IP core is expressed as: ； Phase offset of the m-th DDS IP core in step 3 Expressed as: ； The initial phase increment of the m-th DDS IP core in step 3 Expressed as: ； The change in phase increment of the m-th DDS IP core in step 4 Expressed as: ； The input phase control word increment of the m-th DDS IP core at time i in step 4 Expressed as: 。 2. The method for generating a large-bandwidth linear frequency modulation signal based on a high-speed DAC and FPGA according to claim 1, wherein: Step 6 is as follows: Configure the high-speed DAC center frequency to ,Will M The multiplexed signal is sent to the high-speed DAC module for up-conversion, and the analog signal output by the high-speed DAC is sent to the , bandwidth is B Analog filter; The analog filter output center frequency is , bandwidth is B Large bandwidth LFM signal.

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