Pcie device clock retention apparatus, method, and readable storage medium

Abstract

The application discloses a PCIE device clock maintaining device, method and readable storage medium, wherein the device comprises: a PCIE switching chip, which is used for acquiring board clock data in real time; a delay circuit, which is used for maintaining transmission data of the PCIE switching chip within a preset time; a clock extraction circuit, which is used for recovering clock data from the transmission data to complete clock extraction; a clock locking circuit, which is used for locking the clock data; a clock selection circuit, which is used for selecting the clock data as a board available clock; and a clock driving circuit, which is used for providing a board service clock based on the board available clock. The application can provide a system maintaining clock function for a short time when a board system clock fails, and avoid the occurrence of a system failure caused by the interruption of all service channels due to the loss of the system clock.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit control, and more particularly, to a PCIE device clock maintaining device, method and readable storage medium. BACKGROUND

[0002] PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth, do not share bus bandwidth, mainly supports active power management, error reporting, end-to-end reliable transmission, hot plug and quality of service (QOS) and the like.

[0003] Since the PCIE device is a device running high-speed services, however, the system clock is an essential component unit for the normal operation of the entire running device, when the system clock is lost due to failure, the entire system will immediately stop all services, and therefore, if the system can obtain the clock through internal processing, it will greatly reduce the loss caused by the system stopping all services. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a PCIE device clock maintaining device, method and readable storage medium, which can provide the function of maintaining the clock of the system for a short time when the system clock of the board fails, and avoid the occurrence of system failure caused by the loss of system clock.

[0005] The first aspect of the present application provides a PCIE device clock maintaining device, the device comprising:

[0006] a PCIE exchange chip, the PCIE exchange chip being configured to obtain real-time board clock data;

[0007] a delay circuit, the delay circuit being configured to retain transmission data of the PCIE exchange chip for a preset time, wherein the transmission data is transmitted from a transmission end of the PCIE exchange chip;

[0008] a clock extraction circuit, the clock extraction circuit being configured to recover clock data from the transmission data to complete clock extraction;

[0009] a clock locking circuit, the clock locking circuit being configured to lock the clock data;

[0010] a clock selection circuit, the clock selection circuit being configured to select the clock data as a board available clock;

[0011] a clock driving circuit configured to provide an on-board service clock based on the on-board available clock;

[0012] The input end of the delay circuit is electrically connected with the transmitting end of the PCIE exchange chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE exchange chip; the input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit; the output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit; the output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit; and the output end of the clock driving circuit is electrically connected with the input end of the PCIE exchange chip.

[0013] In the scheme, the device further comprises a clock generator configured to provide the on-board available clock, wherein the output end of the clock generator is electrically connected with the input end of the clock selection circuit.

[0014] In the scheme, the input end of the clock selection circuit is further electrically connected with an external clock input unit configured to acquire external clock input data.

[0015] In the scheme, the delay circuit sends the transmitting data back to the receiving end of the PCIE exchange chip, and the transmitting end and the receiving end of the PCIE exchange chip are further processed.

[0016] The second aspect of the application further provides a PCIE device clock maintaining method, which comprises the following steps:

[0017] monitoring the state of an on-board system clock, wherein,

[0018] when the on-board system clock is monitored to be faulty, the following method steps are performed:

[0019] acquiring on-board clock data and sending the on-board clock data from a transmitting end of a PCIE exchange chip;

[0020] keeping transmitting data of the PCIE exchange chip within a preset time;

[0021] recovering clock data from the transmitting data to complete clock extraction;

[0022] locking the clock data;

[0023] selecting the clock data as an on-board available clock;

[0024] providing an on-board service clock based on the on-board available clock

[0025] In the scheme, when it is monitored that the on-board system clock does not fail, selection data of a clock selection circuit is acquired to switch different on-board service clocks.

[0026] In the scheme, when it is monitored that the on-board system clock does not fail, the method further comprises acquiring on-board available clock data provided by a clock generator or acquiring external clock input data.

[0027] In the scheme, the method further comprises extracting the on-board clock data from one of the PCIE exchange chip's downlink service channels.

[0028] In the scheme, the method further comprises extracting the current system clock as the on-board service clock after the on-board system clock fails and is repaired.

[0029] The third aspect of the application provides a computer readable storage medium, wherein the computer readable storage medium comprises a PCIE device clock maintaining method program of a machine, and the PCIE device clock maintaining method program is executed by a processor to realize the steps of the PCIE device clock maintaining method according to any one of the above aspects.

[0030] The PCIE device clock maintaining device, method and readable storage medium disclosed by the application can provide the function of maintaining the clock of the system for a short time when the on-board system clock fails, and avoid the system failure caused by the interruption of all service channels due to the loss of the system clock. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The structure schematic diagram of the PCIE device clock maintaining device in one embodiment of the application is shown.

[0032] Figure 2 The structure schematic diagram of the PCIE device clock maintaining device in another embodiment of the application is shown.

[0033] Figure 3 The step flow chart of the PCIE device clock maintaining method in one embodiment of the application is shown. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned purposes, features and advantages of the application, the application is further described in detail below in combination with the drawings and specific embodiments. It should be noted that the embodiments of the application and the features in the embodiments can be combined with each other without conflict.

[0035] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be recognized by one skilled in the art that the present application can be practiced without the specific details, or with other methods, components, materials, etc. In other instances, well-known structures are not described in detail in order to avoid obscuring the present application.

[0036] Figure 1 A structural schematic diagram of a PCIE device clock maintaining device is shown.

[0037] As Figure 1 shown, the present application discloses a PCIE device clock maintaining device, which comprises:

[0038] a PCIE switching chip, which is used to acquire the board clock data in real time;

[0039] a delay circuit, which is used to retain the transmission data of the PCIE switching chip within a preset time, wherein the transmission data is sent from the transmission end of the PCIE switching chip;

[0040] a clock extraction circuit, which is used to recover the clock data from the transmission data to complete clock extraction;

[0041] a clock locking circuit, which is used to lock the clock data;

[0042] a clock selection circuit, which is used to select the clock data as the board available clock;

[0043] a clock driving circuit, which is used to provide the board service clock based on the board available clock;

[0044] Wherein, the input end of the delay circuit is electrically connected with the transmission end of the PCIE switching chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE switching chip; the input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit; the output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit; the output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit; and the output end of the clock driving circuit is electrically connected with the input end of the PCIE switching chip.

[0045] It should be noted that, as Figure 1 shown, when the system clock fails, neither the clock generator 7 nor the external clock 8 can normally input the system clock, at this time, the board clock data acquired by the PCIE switching chip 1 is used as the board service clock to provide stable clock, wherein, based on Figure 1It can be known that the input end of the delay circuit 2 is electrically connected with the transmitting end TX of the PCIE exchange chip 1, the output end of the delay circuit 2 is electrically connected with the receiving end RX of the PCIE exchange chip 1 and the input end of the clock extraction circuit 3, the delay circuit 2 is used for retaining the transmitting data of the PCIE exchange chip in a preset time, wherein the preset time is generally two minutes, and the preset time can be adjusted according to actual application, then the clock extraction circuit 3 can recover the clock data from the transmitting data to complete clock extraction, correspondingly, the output end of the clock extraction circuit 3 is electrically connected with the input end of the clock locking circuit 4, so that the clock locking circuit 4 can lock the corresponding clock data after obtaining the clock data, wherein the locking time can be 24 hours, and the locking time can be adjusted according to actual application, the output end of the clock locking circuit 4 is electrically connected with the input end of the clock selection circuit 5, so that the clock selection circuit 5 can select the clock data as the available clock of the board and output the available clock, since the output end of the clock selection circuit 5 is electrically connected with the input end of the clock driving circuit 6, so that the clock driving circuit 6 can obtain the available clock of the board and provide the service clock of the board based on the available clock of the board, so as to complete the short-time clock supply of the board system and avoid the problem of service channel interruption caused by losing the system clock.

[0046] According to the embodiment of the application, the device further comprises a clock generator, wherein the output end of the clock generator is electrically connected with the input end of the clock selection circuit.

[0047] It should be noted that, as shown in the figure, Figure 2 when the system clock of the board is normal, that is, the output data of the clock locking circuit 4 is not needed, that is, the circuit in the dashed box is not used temporarily, and the input clock of the clock generator 7 is used, the clock selection circuit 5 selects the clock input by the clock generator 7 and outputs the clock input by the clock generator 7 as the available clock of the board.

[0048] According to the embodiment of the application, the input end of the clock selection circuit is further electrically connected with an external clock input unit, for obtaining external clock input data.

[0049] It should be noted that, as shown in the figure, Figure 2 when the system clock of the board is normal, that is, the output data of the clock locking circuit 4 is not needed, that is, the circuit in the dashed box is not used temporarily, and the clock input by the external clock 8 is used, and the clock selection circuit 5 selects the clock input by the external clock 8 as the available clock of the board and outputs the clock.

[0050] According to the embodiment of the application, the delay circuit sends the transmitting data back to the receiving end of the PCIE switching chip, and the transmitting end and the receiving end of the PCIE switching chip perform a back-and-forth process.

[0051] It should be noted that while the delay circuit 2 sends the transmitting data back to the receiving end RX of the PCIE switching chip 1, the transmitting end TX and the receiving end RX inside the PCIE switching chip 1 perform a back-and-forth process to form a closed loop, so as to more effectively maintain the continuity of the data sent into the delay circuit 2.

[0052] Figure 3 A step schematic diagram of a PCIE device clock maintaining method is shown.

[0053] As shown in Figure 3 The application discloses a PCIE device clock maintaining method, and the method comprises the following steps:

[0054] Step S302, monitoring the state of the on-board system clock, wherein when it is monitored that the on-board system clock is faulty, the following method steps are performed:

[0055] Step S304, obtaining on-board clock data and sending the on-board clock data from the transmitting end of the PCIE switching chip;

[0056] Step S306, reserving transmitting data of the PCIE switching chip within a preset time;

[0057] Step S308, recovering clock data from the transmitting data to complete clock extraction;

[0058] Step S310, locking the clock data;

[0059] Step S312, selecting the clock data as on-board available clock;

[0060] Step S314, providing on-board service clock based on the on-board available clock.

[0061] It should be noted that firstly, the state of the system clock of the board is monitored, when the system clock fails, that is, the input source of the current system clock cannot provide normal system clock, the current board clock data running on the board is acquired and sent from the transmitting end of the PCIE switching chip, the delay circuit is used to retain the transmitting data of the PCIE switching chip in the preset time, wherein the transmitting data includes the board clock data transmitted by the transmitting end of the PCIE switching chip, and the preset time can be set to "2" minutes, which can be adjusted according to actual needs in specific application, then the clock extraction circuit is used to recover the clock data based on the retained transmitting data to complete corresponding clock extraction, and then the clock locking circuit is used to lock the extracted clock data, so as to output the locked clock data to the clock selection circuit as the available clock of the board, and then the clock driving circuit can provide the board service clock based on the available clock of the board for the system running on the board, so as to avoid the problem that the system service stops due to the loss of the system clock. It is worth mentioning that before the clock data is locked, it is difficult to maintain high-precision clock extraction for a long time, so the accuracy of long-time running cannot be guaranteed, therefore, the time length of locking the clock data is generally "24" hours, and an alarm is sent at the same time when the system clock is lost to remind manual maintenance.

[0062] It is worth mentioning that the system clock represents the clock signal currently running on the board, and the service clock represents the clock signal currently available on the board, when the service clock is used as the clock signal running on the board, the clock signal becomes the system clock.

[0063] According to the embodiment of the application, when it is monitored that the system clock of the board does not fail, the selection data of the clock selection circuit is acquired to switch different service clocks of the board.

[0064] It should be noted that the system clock is required when the PCIE device normally runs, when it is monitored that the system clock of the board does not fail, the selection data of the clock selection circuit is acquired and output, and then different service clocks of the board can be switched based on different clock data, wherein the source of the system clock of the selection data includes a clock generator or external clock input.

[0065] According to the embodiment of the application, when it is monitored that the system clock of the board does not fail, the method further includes acquiring the available clock data of the board provided by the clock generator.

[0066] It should be noted that when the system clock of the board normally runs, the data input by the clock generator can be used as the available clock data of the board.

[0067] According to the embodiment of the present application, when it is monitored that the local system clock is not malfunctioning, the method further comprises obtaining external clock input data.

[0068] It should be noted that when the local system clock is operating normally, the data input by the external clock can be used as the local available clock data.

[0069] According to the embodiment of the present application, the method further comprises extracting the local clock data from one of the downstream service channels of the PCIE switching chip.

[0070] It should be noted that the above embodiment describes that the PCIE switching chip, the delay circuit, the clock extraction circuit and the clock locking circuit are used to extract the local service clock, and in the present embodiment, one of the downstream service channels of the PCIE switching chip is set as a channel specially used for clock extraction to extract the local clock data.

[0071] According to the embodiment of the present application, the method further comprises extracting the current system clock as the local service clock after the local system clock is malfunctioning and is repaired.

[0072] It should be noted that the above embodiment describes that the PCIE switching chip and the peripheral circuit are used to complete the clock delay and extraction recovery after the local system clock is malfunctioning, but this content can only provide short-term system clock maintaining function, and an alarm is also sent after the system clock is malfunctioning, so after the local system clock is malfunctioning and is repaired, the clock recovery through the PCIE switching chip and the peripheral circuit is not needed, and the current recovered normal system clock can be directly used as the local service clock, wherein the local service clock comprises the input data of the clock generator or the input data of the external clock.

[0073] The third aspect of the present application provides a computer readable storage medium, wherein the computer readable storage medium comprises a PCIE device clock maintaining method program of a machine, and when the PCIE device clock maintaining method program is executed by a processor, the steps of the PCIE device clock maintaining method according to any one of the above embodiments are implemented.

[0074] The PCIE device clock maintaining device, method and readable storage medium disclosed by the present application can provide short-term system clock maintaining function when the local system clock is malfunctioning, and can avoid the system failure caused by the interruption of all service channels due to the loss of the system clock.

[0075] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The described device embodiments are merely illustrative. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices, or units, and can be electrical, mechanical, or in other forms.

[0076] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place, or distributed on multiple network units; and some or all of the units can be selected as needed to achieve the purposes of the embodiments.

[0077] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; and the integrated unit can be implemented in the form of hardware or hardware plus software functional units.

[0078] Those of ordinary skill in the art can understand that all or part of the steps of the above-described method embodiments can be completed by a program instructing related hardware, and the foregoing program can be stored in a computer readable storage medium, and when the program is executed, the steps of the method embodiments are executed; and the foregoing storage medium includes mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks or optical disks, and various media that can store program codes.

[0079] Alternatively, the integrated units of the present application, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes: mobile storage devices, ROMs, RAMs, magnetic disks or optical disks, and various media that can store program codes.

Claims

1. A PCIE device clock holding apparatus, characterized by, Specifically comprising: PCIE exchange chip, the PCIE exchange chip is used to obtain the board clock data in real time; Delay circuit, the delay circuit is used to retain the PCIE exchange chip transmission data in the preset time, wherein the transmission data is sent from the transmission end of the PCIE exchange chip; Clock extraction circuit, the clock extraction circuit is used to recover clock data from the transmission data to complete clock extraction; Clock locking circuit, the clock locking circuit is used to lock the clock data; Clock selection circuit, the clock selection circuit is used to select the clock data as the board available clock; Clock driving circuit, the clock driving circuit is used to provide the board service clock based on the board available clock; Wherein, the input end of the delay circuit is electrically connected with the transmission end of the PCIE exchange chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE exchange chip;The input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit;The output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit;The output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit;The output end of the clock driving circuit is electrically connected with the input end of the PCIE exchange chip; Further comprising clock generator, the clock generator is used to provide the board available clock, wherein the output end of the clock generator is electrically connected with the input end of the clock selection circuit.

2. The PCIE device clock holding apparatus according to claim 1, wherein, The input end of the clock selection circuit is also electrically connected with an external clock input unit for obtaining external clock input data.

3. The PCIE device clock holding apparatus according to claim 1, wherein The delay circuit sends the transmission data back to the receiving end of the PCIE exchange chip, and the transmission end and the receiving end of the PCIE exchange chip are also processed.

4. A PCIE device clock holding method, characterized in that, The method is as follows: Monitoring the state of the board system clock, wherein, When it is monitored that the board system clock fails, the following method steps are executed: Obtain the board clock data and send it from the transmission end of the PCIE exchange chip; Retain the transmission data of the PCIE exchange chip in the preset time; Recover the clock data from the transmission data to complete clock extraction; Lock the clock data; Select the clock data as the board available clock; Provide the board service clock based on the board available clock; Further comprising: When it is monitored that the board system clock does not fail, the method further comprises obtaining the board available clock data provided by the clock generator or obtaining the external clock input data.

5. The PCIE device clock holding method of claim 4, wherein, When it is monitored that the board system clock does not fail, obtain the selection data of the clock selection circuit to switch different board service clock.

6. The PCIE device clock holding method of claim 4, wherein, The method further comprises extracting the board clock data from one of the PCIE exchange chip downstream service channels.

7. The PCIE device clock holding method of claim 4, wherein, The method further comprises extracting the current system clock as the board service clock after the board system clock fails and is repaired.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a PCIE device clock maintaining method program, and the PCIE device clock maintaining method program is executed by the processor to realize the steps of the PCIE device clock maintaining method in any one of claims 4 to 7.

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