Memory internal power supply circuit
By introducing first and second mirror circuits into the power generation circuit inside the memory, a control voltage is generated to stabilize the gate voltage of the drive transistor, thus solving the problem of drive voltage drop and improving the drive capability of the power generation circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-06-28
- Publication Date
- 2026-05-29
AI Technical Summary
In the prior art, in the internal power generation circuit of 95nm SONOS type electrically erasable programmable read-only memory, the driving voltage drops rapidly due to peak pull-down current, affecting the driving capability.
The first and second mirror circuits are used to generate the first and second control voltages respectively. The source terminal of the second driving transistor is connected to the gate terminal of the first driving transistor to stabilize the gate terminal voltage of the first driving transistor and prevent the driving voltage from continuously decreasing.
It effectively restores and stabilizes the drive voltage, improving the driving capability of the internal power generation circuit of the memory.
Smart Images
Figure CN115171759B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a power generation circuit for an internal memory. Background Technology
[0002] For a 95nm SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) electrically erasable programmable read-only memory (EEPROM), the external power supply VDDA has a voltage range of 1.7V to 5.5V, and an internal power supply VDDI needs to be generated to provide power to the internal circuitry of the EEPROM.
[0003] Figure 1 A schematic diagram of an internal power generation circuit for a memory provided by related technologies is shown. This power generation circuit includes a current source generation circuit composed of PMOS transistors P01, PMOS transistor P11, NMOS transistors N01 and N11, and resistor R01. The current from this current source generation circuit is mirrored to PMOS transistor P21, and then flows through PMOS transistors P31 and NMOS transistor N21 to ground GND. This process determines the gate voltage IB of the driving transistor Z11.
[0004] The drain of the driver transistor Z11 is connected to the power supply terminal VDD, and the source voltage of the driver transistor Z11 is V. When entering the working state, the source terminal of the driver transistor Z11 will generate a spike pull-down current in the milliampere level, which causes the source voltage V of the driver transistor Z11 to drop rapidly. In addition, the driver transistor Z11 is usually a large-size driver transistor, and there is a large coupling capacitance between its source and gate terminals. This coupling will reduce the gate voltage IB1 of the driver transistor Z11, and further reduce the source voltage V of the driver transistor Z11, which is detrimental to the driving capability of the internal power generation circuit of the memory. Summary of the Invention
[0005] This application provides a power generation circuit for an internal memory, which can solve the problem of driving voltage drop in related technologies.
[0006] In order to solve the technical problems described in the background art, this application provides a memory internal power generation circuit, which includes: a current source generation circuit, a first mirror circuit and a first driving transistor.
[0007] The first mirror circuit is connected between the current source generating circuit and the first driving transistor. It generates a first mirror current based on the current source generating circuit and generates a first control voltage based on the first mirror current to provide to the gate terminal of the first driving transistor.
[0008] The drain of the first driving transistor is connected to the power supply, and the source outputs the driving voltage.
[0009] The internal power generation circuit of the memory also includes: a second mirror circuit and a second driving transistor;
[0010] The second mirror circuit is connected between the current source generating circuit and the second driving transistor, and generates a second mirror current from the current source generating circuit, and generates a second control voltage based on the second mirror current and provides it to the gate terminal of the second driving transistor.
[0011] The drain of the second driving transistor is connected to the power supply, and the source is connected to the gate of the first driving transistor.
[0012] Optionally, the value of the driving voltage is calculated using the following formula: VDDI=IB_VDDI-Vth(Z1)-∆V(Z1); where IB_VDDI=VGA-Vth(Z2);
[0013] VDDI is the driving voltage, IB_VDDI is the first control voltage, Vth(Z1) is the threshold voltage of the first driving transistor, and ∆V(Z1) is the voltage drop of the first driving transistor caused by the current flowing through it; VGA is the second control voltage, and Vth(Z2) is the threshold voltage of the second driving transistor.
[0014] Optionally, the potential value of the second control voltage is the same as the potential value of the first control voltage.
[0015] Optionally, a voltage-regulating capacitor is connected between the ground terminal and the gate terminal of the first driving transistor. The voltage-regulating capacitor reduces the coupling between the source terminal and the gate terminal of the first driving transistor and stabilizes the driving voltage.
[0016] Optionally, NMOS transistor N3 can be used as the voltage regulator capacitor;
[0017] The gate terminal of the NMOS transistor N3 is connected to the gate terminal of the first driving transistor. The source terminal, the drain terminal, and the substrate terminal of the NMOS transistor N3 are connected and grounded.
[0018] Optionally, the current source generating circuit includes PMOS transistor P0, PMOS transistor P1, NMOS transistor N0, NMOS transistor N1 and resistor R0;
[0019] The gate of PMOS transistor P0 is connected to the gate of PMOS transistor P1 and is also connected to the drain of PMOS transistor P1. The source of PMOS transistor P0 and the source of PMOS transistor P1 are both connected to the power supply.
[0020] The gate of NMOS transistor N0 is connected to the gate of NMOS transistor N1 and to the drain of NMOS transistor N0. The drain of NMOS transistor N0 is also connected to the drain of PMOS transistor P0. The drain of NMOS transistor N1 is connected to the drain of PMOS transistor P1. The source of NMOS transistor N0 is connected to ground. The source of NMOS transistor N1 is connected to one end of resistor R0. The other end of resistor R0 is connected to ground.
[0021] Optionally, the first mirror circuit includes PMOS transistor P2, PMOS transistor P3 and NMOS transistor N2;
[0022] The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P1, the source of PMOS transistor P2 is connected to the power supply, and the drain is connected to the source of PMOS transistor P3.
[0023] The gate of the PMOS transistor P3 is connected to the gate of the NMOS transistor N2, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2, and the connection node between the gate of the PMOS transistor P3 and the gate of the NMOS transistor N2 is connected to the connection node between the drain of the PMOS transistor P3 and the drain of the NMOS transistor N2.
[0024] The source of the NMOS transistor N2 is connected to ground.
[0025] Optionally, the connection node between the drain of P2 and the source of P3 in the first mirror circuit is connected to the gate of the first driving transistor to generate the first control voltage and provide it to the gate of the first driving transistor.
[0026] Optionally, the second mirror circuit includes PMOS transistor P5, PMOS transistor P4 and NMOS transistor N4;
[0027] The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P1, the source of PMOS transistor P5 is connected to the power supply, and the drain is connected to the source of PMOS transistor P4.
[0028] The gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N4, the drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N4, and the connection node between the gate of the PMOS transistor P4 and the gate of the NMOS transistor N4 is connected to the connection node between the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4.
[0029] The source of the NMOS transistor N4 is connected to ground.
[0030] Optionally, in the second mirror circuit, the drain of PMOS transistor P5 is connected to the connection node of the source of PMOS transistor P4, and is connected to the gate of the second driving transistor, so as to generate the second control voltage and provide it to the gate of the second driving transistor.
[0031] The technical solution of this application includes at least the following advantages: a second control voltage is generated based on the second mirror current by the second mirror circuit and applied to the gate terminal of the second driving transistor. The source terminal of the second driving transistor is then connected to the gate terminal of the first driving transistor. This allows the second driving transistor to pull back the gate terminal voltage of the first driving transistor when the gate terminal voltage (i.e., the first control voltage) of the first driving transistor shows a downward trend due to the gate-source coupling capacitance of the first driving transistor. This enables the driving voltage to recover quickly and stably, avoids the driving voltage from continuously dropping, and improves the driving capability of the power generation circuit inside the memory. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0033] Figure 1 A schematic diagram of the internal power generation circuit of a memory provided by related technologies is shown.
[0034] Figure 2 A circuit diagram of an internal power generation circuit for a memory provided in an embodiment of this application is shown. Detailed Implementation
[0035] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0038] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0039] Figure 2 This application shows a circuit schematic diagram of an internal power generation circuit for a memory according to an embodiment of the present application. Figure 2 As can be seen from the diagram, the internal power generation circuit of the memory includes: a current source generation circuit 110, a first mirror circuit 121, a first driving transistor Z1, a second mirror circuit 122, and a second driving transistor Z2.
[0040] The first mirror circuit 121 is connected between the current source generating circuit 110 and the first driving transistor Z1. It can generate a first mirror current based on the current source generating circuit 110, generate a first control voltage IB_VDDI based on the first mirror current, and provide the first control voltage IB_VDDI to the gate terminal of the first driving transistor Z1.
[0041] The drain of the first driving transistor Z1 is connected to the power supply VDDA, and the source of the first driving transistor Z1 outputs the driving voltage VDDI.
[0042] The second mirror circuit 122 is connected between the current source generating circuit 110 and the second driving transistor Z2. It can generate a second mirror current based on the current source generating circuit 110, generate a second control voltage VGA based on the second mirror current, and provide the second control voltage VGA to the gate terminal of the second driving transistor Z2.
[0043] The drain of the second driving transistor Z2 is connected to the power supply VDDA, and the source of the second driving transistor Z2 is connected to the gate of the first driving transistor Z1.
[0044] In this embodiment, a second control voltage is generated based on the second mirror current through a second mirror circuit and applied to the gate terminal of the second driving transistor. The source terminal of the second driving transistor is then connected to the gate terminal of the first driving transistor. This allows the second driving transistor to pull back the gate terminal voltage of the first driving transistor when the gate terminal voltage (i.e., the first control voltage) of the first driving transistor shows a downward trend due to the gate-source coupling capacitance of the first driving transistor. This enables the driving voltage to quickly recover and stabilize, preventing the driving voltage from continuously dropping and improving the driving capability of the power generation circuit inside the memory.
[0045] Continue to refer to Figure 2 The current source generating circuit 110 includes PMOS transistors P0, PMOS transistor P1, NMOS transistors N0 and NMOS transistors N1, and resistor R0.
[0046] The gate of PMOS transistor P0 is connected to the gate of PMOS transistor P1 and also to the drain of PMOS transistor P1. The sources of both PMOS transistor P0 and PMOS transistor P1 are connected to the power supply VDDA. The gate of NMOS transistor N0 is connected to the gate of NMOS transistor N1 and also to the drain of NMOS transistor N0. The drain of NMOS transistor N0 is also connected to the drain of PMOS transistor P0. The drain of NMOS transistor N1 is connected to the drain of PMOS transistor P1. The source of NMOS transistor N0 is connected to ground GNDA. The source of NMOS transistor N1 is connected to one end of resistor R0, and the other end of resistor R0 is connected to ground GNDA.
[0047] The first mirror circuit 121 includes PMOS transistor P2, PMOS transistor P3 and NMOS transistor N2.
[0048] The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P1 in the current source generating circuit 110. The source of PMOS transistor P2 is connected to power supply VDDA, and its drain is connected to the source of PMOS transistor P3. The gate of PMOS transistor P3 is connected to the gate of NMOS transistor N2, and the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N2. The connection node between the gate of PMOS transistor P3 and the gate of NMOS transistor N2 is connected to the connection node between the drain of PMOS transistor P3 and the drain of NMOS transistor N2. The source of NMOS transistor N2 is connected to ground GNDA.
[0049] Continue to refer to Figure 2 The connection node between the drain of PMOS transistor P2 and the source of PMOS transistor P3 in the first mirror circuit 121 is connected to the gate terminal of the first driving transistor Z1 in the internal power generation circuit of the memory, and is used to generate the first control voltage IB_VDDI to be provided to the gate terminal of the first driving transistor Z1.
[0050] The second mirror circuit 122 includes PMOS transistor P5, PMOS transistor P4 and NMOS transistor N4.
[0051] The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P1 in the current source generating circuit 110. The source of PMOS transistor P5 is connected to power supply VDDA, and its drain is connected to the source of PMOS transistor P4. The gate of PMOS transistor P4 is connected to the gate of NMOS transistor N4, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4. The connection node between the gate of PMOS transistor P4 and the gate of NMOS transistor N4 is connected to the connection node between the drain of PMOS transistor P4 and the drain of NMOS transistor N4. The source of NMOS transistor N4 is connected to ground GNDA.
[0052] Continue to refer to Figure 2 In the second mirror circuit 122, the drain of PMOS transistor P5 is connected to the source of PMOS transistor P4 at the same node, which is connected to the gate of the second driving transistor Z2 in the internal power generation circuit of the memory. This is used to generate a second control voltage VGA to be supplied to the gate of the second driving transistor Z2. The source of the second driving transistor Z2 is connected to the gate of the first driving transistor Z1.
[0053] To further reduce the coupling between the gate and source terminals of the first driving transistor Z1, a voltage stabilizing capacitor can be connected between the gate terminal and ground terminal GNDA of the first driving transistor Z1. The voltage stabilizing capacitor reduces the coupling between the source and gate terminals of the first driving transistor Z1 and stabilizes the driving voltage VDDI output by the first driving transistor Z1.
[0054] Optionally, an NMOS transistor N3 can be used as the voltage regulator capacitor; the gate terminal of the NMOS transistor N3 is connected to the gate terminal of the first driving transistor Z1, and the source terminal, drain terminal, and substrate terminal of the NMOS transistor N3 are connected to the ground terminal GNDA.
[0055] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A power generation circuit for an internal memory, characterized in that, The internal power generation circuit of the memory includes: a current source generation circuit, a first mirror circuit, and a first driving transistor; The first mirror circuit is connected between the current source generating circuit and the first driving transistor. It generates a first mirror current based on the current source generating circuit and generates a first control voltage based on the first mirror current to provide to the gate terminal of the first driving transistor. The drain of the first driving transistor is connected to the power supply, and the source outputs the driving voltage. The internal power generation circuit of the memory also includes: a second mirror circuit and a second driving transistor; The second mirror circuit is connected between the current source generating circuit and the second driving transistor, and generates a second mirror current from the current source generating circuit, and generates a second control voltage based on the second mirror current and provides it to the gate terminal of the second driving transistor. The drain of the second driving transistor is connected to the power supply, and the source is connected to the gate of the first driving transistor.
2. The memory internal power generation circuit as described in claim 1, characterized in that, The formula for calculating the value of the driving voltage is: VDDI=IB_VDDI-Vth(Z1)-∆V(Z1); where IB_VDDI=VGA-Vth(Z2); VDDI is the driving voltage, IB_VDDI is the first control voltage, Vth(Z1) is the threshold voltage of the first driving transistor, and ∆V(Z1) is the voltage drop of the first driving transistor caused by the current flowing through it; VGA is the second control voltage, and Vth(Z2) is the threshold voltage of the second driving transistor.
3. The memory internal power generation circuit as described in claim 1, characterized in that, The potential value of the second control voltage is the same as the potential value of the first control voltage.
4. The memory internal power generation circuit as described in claim 1, characterized in that, A voltage-regulating capacitor is connected between the ground terminal and the gate terminal of the first driving transistor. The voltage-regulating capacitor reduces the coupling between the source terminal and the gate terminal of the first driving transistor and stabilizes the driving voltage.
5. The memory internal power generation circuit as described in claim 4, characterized in that, The voltage regulator capacitor is N3, which is an NMOS transistor. The gate terminal of the NMOS transistor N3 is connected to the gate terminal of the first driving transistor. The source terminal, the drain terminal, and the substrate terminal of the NMOS transistor N3 are connected and grounded.
6. The memory internal power generation circuit as described in claim 1, characterized in that, The current source generating circuit includes PMOS transistor P0, PMOS transistor P1, NMOS transistor N0, NMOS transistor N1 and resistor R0; The gate of PMOS transistor P0 is connected to the gate of PMOS transistor P1 and is also connected to the drain of PMOS transistor P1. The source of PMOS transistor P0 and the source of PMOS transistor P1 are both connected to the power supply. The gate of NMOS transistor N0 is connected to the gate of NMOS transistor N1 and to the drain of NMOS transistor N0. The drain of NMOS transistor N0 is also connected to the drain of PMOS transistor P0. The drain of NMOS transistor N1 is connected to the drain of PMOS transistor P1. The source of NMOS transistor N0 is connected to ground. The source of NMOS transistor N1 is connected to one end of resistor R0. The other end of resistor R0 is connected to ground.
7. The memory internal power generation circuit as described in claim 6, characterized in that, The first mirror circuit includes PMOS transistor P2, PMOS transistor P3 and NMOS transistor N2; The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P1, the source of PMOS transistor P2 is connected to the power supply, and the drain is connected to the source of PMOS transistor P3. The gate of the PMOS transistor P3 is connected to the gate of the NMOS transistor N2, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2, and the connection node between the gate of the PMOS transistor P3 and the gate of the NMOS transistor N2 is connected to the connection node between the drain of the PMOS transistor P3 and the drain of the NMOS transistor N2. The source of the NMOS transistor N2 is connected to ground.
8. The memory internal power generation circuit as described in claim 7, characterized in that, The connection node between the drain of P2 and the source of P3 in the first mirror circuit is connected to the gate of the first driving transistor, which is used to generate the first control voltage and provide it to the gate of the first driving transistor.
9. The internal power generation circuit of the memory as described in claim 6, characterized in that, The second mirror circuit includes PMOS transistor P5, PMOS transistor P4 and NMOS transistor N4; The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P1, the source of PMOS transistor P5 is connected to the power supply, and the drain is connected to the source of PMOS transistor P4. The gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N4, the drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N4, and the connection node between the gate of the PMOS transistor P4 and the gate of the NMOS transistor N4 is connected to the connection node between the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4. The source of the NMOS transistor N4 is connected to ground.
10. The memory internal power generation circuit as described in claim 9, characterized in that, In the second mirror circuit, the drain of PMOS transistor P5 is connected to the connection node of the source of PMOS transistor P4, which is connected to the gate of the second driving transistor to generate the second control voltage and provide it to the gate of the second driving transistor.