Silicon-based beam lead schottky barrier diode glass frame forming method

Abstract

The application discloses a forming method of a silicon-based beam lead Schottky barrier diode glass frame, which comprises the following steps: preparing a wafer, growing a composite medium, first L-shaped groove photolithography, etching the medium, second L-shaped groove photolithography, ICP etching, anisotropic etching, glass passivation, glass photolithography, and glass etching. The application realizes the forming of the glass frame through three-layer composite medium passivation, anisotropic etching of L-shaped right trapezoidal mesa, and multiple glass passivation and etching. The right trapezoidal mesa has good glass filling effect, and the formed glass frame can provide excellent support and peripheral protection for a beam lead T-shaped series connection of a diode chip, and can be expanded to a beam lead single tube, a ring-shaped 4-tube stack or other beam lead integrated structures by changing a photolithography layout. The glass frame forming process formed by the method has the advantages of accurate and controllable pattern, high consistency, strong expandability and the like, and the process is simple and easy to implement.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a method for forming a glass frame, in particular to a method for forming a glass frame of a silicon-based beam-type lead Schottky barrier diode. Background Art

[0002] The glass frame supports the entire chip, so glass frame molding technology is one of the key technologies for silicon-based beam-lead Schottky barrier diode T-type series-pair transistor chips. Currently, silicon-based beam-lead Schottky barrier diode glass frame molding technology mainly includes two difficulties:

[0003] 1. Selection of surface protection medium. Although the conventional SiO2 / Si3N4 composite dielectric layer can take into account the good passivation effect of SiO2 and the waterproof effect of Si3N4, it is easy to cause "bubbling" when covering the Si3N4 with glass due to the different materials.

[0004] 2. In terms of table top forming, the best choice is a regular trapezoidal table top. Compared with vertical table tops, regular trapezoidal table tops have better glass coverage, especially the edge coverage is much higher than that of vertical table tops. However, how to form a regular trapezoidal table top is a major difficulty. If a single dry etching method is used, this method has extremely high requirements for equipment. When etching deep tables (table height difference ≥ 50μm) and requiring a large positive bevel angle, it is often accompanied by a "grass-growing" phenomenon. The morphology is difficult to accurately control and is accompanied by etching damage. If a single anisotropic wet etching method is used, due to the long etching time, it is impossible to take into account the surface pattern. Summary of the Invention

[0005] Technical Problem Solved: To address the aforementioned challenges in this field, a method for forming a glass frame is achieved by combining dry etching and anisotropic etching, through the combined design of the secondary photolithography pattern size and etching depth. The method features a simple process, high efficiency, good consistency, and low equipment requirements. Furthermore, the present invention utilizes a three-layer SiO2 / Si3N4 / SiO2 composite dielectric film as a dielectric mask, which not only reaps the advantages of SiO2 / Si3N4 but also avoids the "bubbling" problem between the topmost SiO2 film and the subsequent glass material. In light of this, the present invention provides a method for forming a glass frame for a silicon-based beam-lead Schottky barrier diode.

[0006] Technical solution: A method for forming a glass frame for a silicon-based beam-lead Schottky barrier diode, the method comprising the following steps:

[0007] S1, preparation wafer: select commercially available silicon wafers and pre-treat them with aqua regia for 15 minutes;

[0008] S2. Growth of composite dielectric layer: A composite dielectric layer is grown on the surface of the silicon wafer using LPCVD or PECVD technology. The composite dielectric layer is a three-layer film structure of SiO2 / Si3N4 / SiO2, where the middle layer is Si3N4 and the remaining layers are SiO2. The thickness of the three layers of SiO2 / Si3N4 / SiO2 is and

[0009] S3, the first L-shaped groove lithography: the L-shaped dielectric etching pattern is lithographically produced, and the cross-sectional size of the layout is L2;

[0010] S4, dielectric etching: removing the composite dielectric layer exposed after S3 photolithography;

[0011] S5, second L-shaped groove lithography: lithography out the ICP etching pattern, the cross-sectional size of the layout is L1;

[0012] S6, ICP etching: Use vertical etching process to etch a vertical mesa structure in the groove after S5 photolithography, and the etching depth is h;

[0013] S7, anisotropic etching: anisotropically etching the silicon wafer after etching in S6 to reach the target depth H, forming a regular trapezoidal mesa structure;

[0014] S8, glass passivation: glass passivation is performed on the silicon wafer to fill the positive trapezoidal terraces;

[0015] S9, photolithography glass: perform photolithography on the silicon island area in the Lv-shaped groove;

[0016] S10, etching glass: Etching the exposed silicon island table to remove the glass on its surface and complete the glass frame forming; wherein L1, L2, h, and H satisfy the following relationship, and θ is the angle between the waist of the regular trapezoidal table and the vertical direction:

[0017]

[0018] L2=L1+2h×tanθ.

[0019] The above two formulas allow for an error of ±10%, and this error does not affect the final result.

[0020] Preferably, the silicon wafer in S1 has a crystal orientation of <100> .

[0021] Preferably, the thickness of the three-layer SiO2 / Si3N4 / SiO2 film in S2 is and

[0022] Preferably, θ is 35.26°.

[0023] Preferably, in S7, a TMAH solution with a volume concentration of 10% to 15% is used to perform anisotropic etching on the silicon wafer at a temperature of 60-80°C.

[0024] Preferably, in S8, the glass scraping method is used for scraping 3-6 times.

[0025] The principle behind the molding method described in this invention is that SiO2 exhibits excellent stress matching at both silicon and glass interfaces, making it an excellent passivation dielectric. However, its moisture resistance is inferior to that of Si3N4. Therefore, a three-layer SiO2 / Si3N4 / SiO2 composite dielectric film achieves both moisture resistance and stress matching. Furthermore, the etching rates of silicon in different crystal orientations vary significantly when using a specific etching solution. Therefore, a specific etching solution can be combined with a specific crystal orientation to produce an etching profile with a specific angle.

[0026] Beneficial effects: (1) The present invention adopts a three-layer SiO2 / Si3N4 / SiO2 composite dielectric film as a dielectric mask, which can obtain the advantages of SiO2 / Si3N4 and avoid the "bubbling" problem between the top SiO2 film and the subsequent glass material; (2) The present invention combines dry etching and anisotropic corrosion, and finally realizes a beam-type lead glass frame forming technology with simple operation process, high efficiency, good consistency and low equipment requirements through the combined design of the secondary photolithography pattern size and etching depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the beam-lead T-type series-connected glass frame structure of the present invention;

[0028] Figure 2 This is a process flow chart of the beam-lead T-type series-connected glass frame forming technology of the present invention;

[0029] Figure 3 is a schematic diagram of a glass frame structure formed by the method described in Example 1;

[0030] Figure 4 This is a schematic diagram of the glass frame structure formed by the method described in Example 2. DETAILED DESCRIPTION

[0031] The following examples further illustrate the present invention but are not to be construed as limiting the present invention. Modifications and substitutions made to the methods, steps, or conditions of the present invention without departing from the spirit and substance of the present invention are intended to fall within the scope of the present invention. Unless otherwise specified, the techniques used in the examples are conventional means well known to those skilled in the art.

[0032] Example 1

[0033] Silicon-based beam-lead Schottky barrier diode glass frame forming method, process flow as follows Figure 2 As shown, the method includes the following steps:

[0034] (1) Preparation wafer: silicon wafer, the crystal orientation of the silicon wafer is <100> ;

[0035] (2) Growth of composite dielectric layer: LPCVD or PECVD is used to grow a three-layer composite (SiO2 / Si3N4 / SiO2) dielectric layer with thicknesses of 5000 / 2000 / 5000 respectively;

[0036] (3) First L2-shaped groove lithography: The L2-shaped dielectric etching pattern is etched. Taking the glass groove size as an example, the width of L2 is 115 μm.

[0037] (4) Dielectric etching: removing the exposed composite dielectric layer after photolithography and stripping the adhesive;

[0038] (5) Second L1-shaped groove lithography: The ICP-etched pattern is etched. Taking the glass groove size as an example, the L1 width is 80 μm.

[0039] (6) ICP etching: vertical mesa structure is etched using vertical etching process, with an etching depth h of 25 μm, and then the resin is removed;

[0040] (7) Anisotropic etching: The silicon wafer is anisotropically etched. The anisotropic etching solution is a TMAH solution with a volume concentration of 10%. The etching temperature is 70°C. The final target depth H is 50 μm, forming a regular trapezoidal terrace structure with a θ of approximately 35.26°.

[0041] (8) Glass passivation: Glass passivate the silicon wafer by scraping 3-6 times to fill the trapezoidal table;

[0042] (9) Photolithography glass: Photolithography of the silicon island area in the Lu-shaped groove;

[0043] (10) Etching glass: Etching the exposed silicon island glass area to remove the glass on the surface of the silicon island and complete the glass frame forming. Figure 3 shown.

[0044] Example 2

[0045] Silicon-based beam-lead Schottky barrier diode glass frame forming method, process flow as follows Figure 2 As shown, the method includes the following steps:

[0046] (1) Preparation wafer: silicon wafer, the crystal orientation of the silicon wafer is <100> ;

[0047] (2) Growth of composite dielectric layer: LPCVD or PECVD is used to grow a three-layer composite (SiO2 / Si3N4 / SiO2) dielectric layer with thicknesses of 5000 / 2000 / 5000 respectively;

[0048] (3) First L2-shaped groove lithography: The L2-shaped dielectric etching pattern is etched. Taking the glass groove size as an example, the L2 width is 80 μm;

[0049] (4) Dielectric etching: removing the exposed composite dielectric layer after photolithography and stripping the adhesive;

[0050] (5) Second L1-shaped groove lithography: Lithography of the ICP-etched pattern. Taking the glass groove size as an example, the L1 width is 40 μm;

[0051] (6) ICP etching: vertical mesa structure is etched using vertical etching process, with an etching depth h of 25 μm, and then the resin is removed;

[0052] (7) Anisotropic etching: The silicon wafer is anisotropically etched. The anisotropic etching solution is a 12% volume concentration TMAH solution. The etching temperature is 75°C. The final target depth H is 50 μm, forming a regular trapezoidal terrace structure with a θ of approximately 35.26°.

[0053] (8) Glass passivation: Glass passivate the silicon wafer by scraping 3-6 times to fill the trapezoidal table;

[0054] (9) Photolithography glass: Photolithography of the silicon island area in the Lu-shaped groove;

[0055] (10) Etching glass: Etching the exposed silicon island glass area to remove the glass on the surface of the silicon island and complete the glass frame forming.

Claims

1. A method for forming a glass frame for a silicon-based beam-lead Schottky barrier diode, characterized in that: The method comprises the following steps: S1, preparation wafer: select commercially available silicon wafers and pre-treat them with aqua regia for 15 minutes; S2. Growth of composite dielectric layer: A composite dielectric layer is grown on the surface of the silicon wafer using LPCVD or PECVD technology. The composite dielectric layer is a three-layer film structure of SiO2 / Si3N4 / SiO2, where the middle layer is Si3N4 and the remaining layers are SiO2. The thickness of the three layers of SiO2 / Si3N4 / SiO2 is and S3, the first L-shaped groove lithography: the L-shaped dielectric etching pattern is lithographically produced, and the cross-sectional size of the layout is L2; S4, dielectric etching: removing the composite dielectric layer exposed after S3 photolithography; S5, second L-shaped groove lithography: lithography out the ICP etching pattern, the cross-sectional size of the layout is L1; S6, ICP etching: Use vertical etching process to etch a vertical mesa structure in the groove after S5 photolithography, and the etching depth is h; S7, anisotropic etching: anisotropically etching the silicon wafer after etching in S6 to reach the target depth H, forming a regular trapezoidal mesa structure; S8, glass passivation: glass passivation is performed on the silicon wafer to fill the positive trapezoidal terraces; S9, photolithography glass: perform photolithography on the silicon island area in the Lv-shaped groove; S10, etching glass: Etching the exposed silicon island table to remove the glass on its surface and complete the glass frame forming; wherein L1, L2, h, and H satisfy the following relationship, and θ is the angle between the waist of the regular trapezoidal table and the vertical direction: L2=L1+2h×tanθ; The crystal orientation of the silicon wafer in S1 is <100> ; In S7, a TMAH solution with a volume concentration of 10% to 15% is used to anisotropically etch the silicon wafer at a temperature of 60-80°C.

2. The method for forming a glass frame of a silicon-based beam-lead Schottky barrier diode according to claim 1, wherein: The thickness of the three-layer SiO2 / Si3N4 / SiO2 film in S2 is and 3. The method for forming a glass frame of a silicon-based beam-lead Schottky barrier diode according to claim 1, wherein: θ is 35.26°.

4. The method for forming a glass frame of a silicon-based beam-lead Schottky barrier diode according to claim 1, wherein: In S8, the glass scraping method is used for 3-6 times.

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