Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate comprising a plurality of discrete active regions, the plurality of active regions being arranged along a first direction and parallel to a second direction, the first direction being perpendicular to the second direction; forming a plurality of first grooves in the substrate, the plurality of first grooves being arranged along the second direction and extending through the plurality of active regions along the first direction; forming an initial wordline gate structure within the first grooves, the initial wordline gate structure comprising opposing first and second side regions; removing the first side regions and portions of the active regions adjacent to the first side regions to form a wordline gate structure, and forming a second groove between the wordline gate structure and the active regions; forming a first isolation structure within the second grooves; forming a plurality of capacitor structures on the first side of each active region; and forming a plurality of bitline structures on the second side of the substrate, the plurality of bitline structures being arranged along the first direction and parallel to the second direction. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] The basic memory cell of a dynamic random access memory (DRAM) consists of a transistor and a storage capacitor, while the memory array is composed of multiple memory cells. Therefore, the size of the memory chip is determined by the area of ​​the basic memory cell.

[0004] Existing dynamic random access memories still need to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of a dynamic random access memory.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a plurality of mutually discrete active areas, the plurality of active areas being arranged along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other; forming a plurality of first grooves in the substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged along the second direction, and the first grooves penetrating the plurality of active areas along the first direction; forming an initial word line gate structure in the first groove, the initial word line gate structure comprising a first side region and a second side region opposite to each other, the first side region and the second side region respectively being adjacent to the active area; removing the first side region and a portion of the active area adjacent to the first side region to form a word line gate structure, and forming a second groove between the word line gate structure and the active area; forming a first isolation structure in the second groove; forming a plurality of capacitor structures on the first surface of each of the active areas; and forming a plurality of bit line structures on the second surface of the substrate, the plurality of bit line structures being arranged along the first direction and parallel to the second direction.

[0007] Optionally, the word line gate structure includes a gate dielectric layer located on the sidewall surfaces and the bottom surface of the first groove and a gate layer located on the surface of the gate dielectric layer.

[0008] Optionally, a bottom plane of the first isolation structure in a direction toward the second surface of the substrate is lower than half of the height of the gate layer.

[0009] Optionally, the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.

[0010] Optionally, the gate layer includes a first portion located at the bottom of the first groove and a second portion located on the first portion, and the first portion and the second portion are made of different materials.

[0011] Optionally, the ratio of the height of the second section to the height of the first section is in a range of 1:4 to 4:1.

[0012] Optionally, the material of the first section includes metal, the metal includes tungsten, and the material of the second section includes polysilicon; the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than the bottom plane of the second section in the direction toward the second surface of the substrate.

[0013] Optionally, the material of the first section includes polysilicon, the material of the second section includes metal, and the metal includes tungsten; the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than the bottom plane of the first section in the direction toward the second surface of the substrate.

[0014] Optionally, the method for forming the word line gate structure includes: forming an initial gate dielectric material layer on the side wall surface and bottom surface of the first groove and the top surface of the active area of ​​the first side of the substrate; forming an initial first section on the initial gate dielectric material layer; etching back the initial first section until the top surface of the initial first section is lower than the top surface of the active area of ​​the first side of the substrate and a portion of the initial gate dielectric material layer on the side wall of the first groove is exposed to form a first section; forming an initial second section on the first section; flattening the initial second section and the initial gate dielectric material layer on the top of the active area of ​​the first side of the substrate until the top surface of the active area of ​​the first side of the substrate is exposed to form a gate dielectric layer and a transitional second section; etching back the transitional second section to form the second section.

[0015] Optionally, there is a second isolation structure between adjacent active areas; the method for forming a plurality of bit line structures on the second surface of the substrate includes: thinning the second surface of the substrate until the surface of the second isolation structure is exposed; performing ion implantation on the second surface of the thinned active area to form a second doped area in the active area; forming a plurality of bit line structures on the second doped area, each bit line structure being electrically connected to the second doped area in an active area respectively.

[0016] Optionally, before forming a plurality of bit line structures on the second doping region, the method further includes: forming a bit line plug on the second doping region, wherein the bit line plug electrically connects the bit line structure and the second doping region.

[0017] Optionally, after ion implantation is performed on the second surface of the thinned active area and before forming a plurality of bit line structures on the second doped area, the method further includes: removing a portion of the active area at the bottom of the word line gate structure until the surface of the gate dielectric layer is exposed.

[0018] Optionally, the method for forming the bit line structure includes: forming a first dielectric layer on the active area on the second side of the substrate and the second isolation structure, the first dielectric layer having a plurality of third grooves, the third grooves exposing the second side surface of the active area; and forming the bit line structure in the third grooves.

[0019] Optionally, the bit line structure includes a barrier layer located on the sidewall surfaces and the bottom surface of the third groove, and a bit line layer located on the barrier layer.

[0020] Optionally, the material of the second isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

[0021] Optionally, the method for forming a capacitor structure includes: forming a second dielectric layer on the first isolation structure and the first surface of the active area; forming a fourth groove in the second dielectric layer, wherein the fourth groove exposes a portion of the first surface of the active area; and forming a capacitor structure in the fourth groove.

[0022] Optionally, the method for thinning the second surface of the substrate includes: providing a base, wherein a surface of the base is bonded to a surface of the second dielectric layer; and flipping the base and the substrate to thin the second surface of the substrate.

[0023] Optionally, the process of thinning the second surface of the substrate includes a chemical mechanical polishing process.

[0024] Optionally, after forming the initial word line gate structure, before removing the first side region and the portion of the active region adjacent to the first side region, it also includes: ion implantation into the first surface of the active region to form a first doped region in the active region; and each capacitor structure is electrically connected to a first doped region respectively.

[0025] Optionally, a projection of the capacitor structure on the first surface of the active region at least overlaps with a portion of the first doped region.

[0026] Optionally, after forming the first isolation structure and before forming a plurality of capacitor structures on the first surface of each active region, the method further includes: forming a capacitor plug on the first doped region, wherein the capacitor plug electrically connects the capacitor structure and the first doped region.

[0027] Optionally, a top surface of the word line gate structure facing the first surface of the substrate is lower than a bottom plane of the first doped region facing the second surface of the substrate.

[0028] Optionally, the process of removing the first side region and a portion of the active region adjacent to the first side region includes a dry etching process.

[0029] Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

[0030] Optionally, the capacitor structure includes: a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer.

[0031] Optionally, the shape of the dielectric layer includes: planar or "U" shape.

[0032] Optionally, each of the capacitor structures is located on an active area adjacent to the second side area.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] The technical solution of the present invention forms a new semiconductor structure. On the one hand, the capacitor structure is located on the first surface of the substrate, and the bitline structure is located on the second surface of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process. On the other hand, the wordline gate structure is located within the substrate, thereby saving space in a direction perpendicular to the substrate surface and increasing the density of memory array cells. On the other hand, a first isolation structure is provided between the wordline gate structure and the active area. The second side region of the wordline gate structure is adjacent to the active area, so that the first isolation structure can isolate the first side region of the wordline gate structure from the active area, preventing the wordline gate structure from contacting the active areas on both adjacent sides simultaneously, thereby generating two channels and forming a parasitic device, making it difficult to turn off the transistor. This can reduce leakage current and improve the performance of the semiconductor structure.

[0035] Furthermore, the material of the gate layer includes polysilicon or tungsten, and the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than half the height of the gate layer, thereby ensuring that the channel in the first side region of the word line gate structure can be completely turned off.

[0036] Furthermore, the gate layer includes a first subsection and a second subsection located above the first subsection. The first subsection is made of a metal including tungsten, and the second subsection is made of polysilicon. The bottom plane of the first isolation structure facing the second surface of the substrate is lower than the bottom plane of the second subsection facing the second surface of the substrate. Therefore, the bottom plane of the first isolation structure only needs to be lower than the bottom plane of the second subsection to achieve the effect of shutting off the channel in the first side region of the wordline gate structure.

[0037] Furthermore, a capacitor plug is formed on the first doped region on the first surface of the active region, and the capacitor structure is electrically connected to the first doped region through the capacitor plug, thereby increasing the process window for forming the capacitor structure and the capacitor plug.

[0038] Furthermore, after ion implantation is performed on the second surface of the thinned active region and before forming a plurality of bit line structures on the second doped region, the method further includes removing a portion of the active region at the bottom of the word line gate structure until the surface of the gate dielectric layer is exposed. In this case, the second surfaces of the active region are separated from each other, thereby reducing the capacitance generated after the bit line structures are formed on the second surfaces of the active region.

[0039] Furthermore, the top surface of the wordline gate structure facing the first surface of the substrate is lower than the bottom surface of the first doped region facing the second surface of the substrate. This prevents the channel subsequently formed by the wordline gate structure in the active area from overlapping with the first doped region, thereby preventing the performance of the first doped region from being affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0041] Figures 2 to 24 is a structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention;

[0042] Figures 25 to 27 is a structural schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention;

[0043] Figures 28 to 30 It is a structural schematic diagram of the semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0044] As described in the background art, existing dynamic random access memories still need to be improved. This will now be analyzed and explained in conjunction with specific embodiments.

[0045] Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor structure in one embodiment.

[0046] Please refer to Figure 1, including: a substrate 100; a word line gate structure 101 located in the substrate 100; a source doped region 103 and a drain doped region 102 located in the substrate 100 on both sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 through a source plug 104; and a capacitor structure 107 electrically connected to the drain doped region 102 through a capacitor plug 106.

[0047] The formation process of the semiconductor structure is as follows: first, a source doping region 103 and a drain doping region 102 are formed, then a word line gate structure 101 is formed in the substrate 100, then a source plug 104 and a bit line structure 105 are formed, then a capacitor plug 106 is formed, and finally a capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, with the source doping region 103 and the drain doping region 102 on both horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor and are both located above the substrate in terms of processing technology. The capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105, which makes the overall process more complex and places extremely high requirements on the photolithography process and alignment.

[0048] In order to solve the above problems, the technical solution of the present invention forms a new semiconductor structure. On the one hand, the capacitor structure is located on the first surface of the substrate, and the bit line structure is located on the second surface of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; on the other hand, the word line gate structure is located within the substrate, thereby saving space in the direction perpendicular to the substrate surface and increasing the density of the memory array unit; on the other hand, a first isolation structure is provided between the word line gate structure and the active area, the second side area of ​​the word line gate structure is adjacent to the active area, and the first side area of ​​the word line gate structure is adjacent to the first isolation structure, so that the first isolation structure can isolate the first side area of ​​the word line gate structure from the active area, avoiding the situation where the word line gate structure contacts the active areas on both adjacent sides at the same time to generate two channels to form a parasitic device, making it difficult to turn off the transistor. This can reduce leakage current and improve the performance of the semiconductor structure.

[0049] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figures 2 to 24 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0051] Please refer to Figure 2 and Figure 3 , Figure 3 for Figure 2 A top view of the first surface 300 of the substrate, Figure 2 for Figure 3A schematic cross-sectional structure diagram along section line AA1 is provided, wherein a substrate 200 is provided, wherein the substrate includes a first surface 300 and a second surface 400 opposite to each other, and the substrate includes a plurality of mutually discrete active regions 201, wherein the plurality of active regions 201 are arranged along a first direction X and parallel to a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0052] In this embodiment, the substrate 200 is made of silicon.

[0053] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0054] In this embodiment, a second isolation structure 202 is provided between adjacent active regions 201 .

[0055] The material of the second isolation structure 202 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride.

[0056] In this embodiment, the material of the second isolation structure 202 includes silicon oxide.

[0057] Please refer to Figure 4 、 Figure 5 and Figure 6 , Figure 6 for Figure 5 and Figure 4 A top view of the first surface 300 of the substrate, Figure 4 for Figure 6 Schematic diagram of the cross-section structure along the section line BB1, Figure 5 for Figure 6 A schematic diagram of the cross-sectional structure along the section line CC1 shows that a plurality of first grooves 203 are formed in the substrate 200, and the first grooves 203 extend from the first surface 300 to the second surface 400. The plurality of first grooves 203 are arranged along the second direction Y, and the first grooves 203 pass through the plurality of active areas 201 along the first direction X.

[0058] The method for forming the first groove 203 includes: forming a patterned mask layer (not shown) on the first surface 300 of the substrate, wherein the patterned mask layer exposes a portion of the surface of the active area 201; etching the active area 201 using the patterned mask layer as a mask to form the first groove 203 in the substrate.

[0059] In this embodiment, the bottom plane of the first groove 203 facing the second substrate surface 400 is higher than the bottom plane of the second isolation structure 202 facing the second substrate surface 400, leaving physical space for subsequent formation of the second doped region on the second substrate surface 400.

[0060] Please refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 A top view of the first surface 300 of the substrate, Figure 7 for Figure 8 Schematic diagram of the cross-sectional structure along the section line DD1, an initial word line gate structure is formed in the first groove 203, and the initial word line gate structure includes a first side region (not marked) and a second side region (not marked) relative to each other, and the first side region and the second side region are respectively adjacent to the active area 201.

[0061] The initial word line gate structure includes an initial gate dielectric layer 204 located on the sidewall surfaces and the bottom surface of the first groove 203 and an initial gate layer 205 located on the surface of the initial gate dielectric layer 204 .

[0062] The top surface of the initial word line gate structure facing the first surface 300 of the substrate is lower than the surface of the first surface 300 of the active region 201 , providing physical space for subsequent formation of a first doped region on the first surface 300 of the active region 201 .

[0063] The method for forming the initial word line gate structure includes: forming a gate dielectric material layer (not shown) on the sidewall surfaces and bottom surface of the first groove 203 and the surface of the first surface 300 of the active area 201; forming a gate material layer (not shown) on the gate dielectric material layer; planarizing the gate material layer and the gate dielectric material layer until the surface of the active area 201 is exposed to form a transitional initial word line gate structure; and etching back the transitional initial word line gate structure until a portion of the first groove 203 sidewall is exposed to form the initial word line gate structure.

[0064] In this embodiment, the material of the initial gate dielectric layer 204 includes silicon oxide or a low-K (K less than 3.9) material; the material of the initial gate layer 205 includes polysilicon.

[0065] In another embodiment, the material of the initial gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the initial gate layer includes a metal, and the metal includes tungsten.

[0066] In another embodiment, the initial word line gate structure further includes an initial work function layer, the initial work function layer being located between the initial gate dielectric layer and the initial gate layer. The material of the initial work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0067] In other embodiments, the initial gate layer includes a first portion located at the bottom of the first groove and a second portion located above the first portion, and the first portion and the second portion are made of different materials.

[0068] Please refer to Figure 9 and Figure 10 , Figure 10 for Figure 9 A top view of the first surface 300 of the substrate, Figure 9 for Figure 10 As shown in the cross-sectional structural diagram along the section line EE1 , after the initial word line gate structure is formed, ion implantation is performed on the surface of the first surface 300 of the active region 201 to form a first doped region 206 in the active region 201 .

[0069] The top surface of the initial word line gate structure facing the first substrate surface 300 is lower than the bottom surface of the first doped region 206 facing the second substrate surface 400. Therefore, the channel formed by the subsequent word line gate structure in the active area 201 will not overlap with the first doped region 206, thereby preventing the performance of the first doped region 206 from being affected.

[0070] The first doping region 206 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0071] Please refer to Figure 11 , Figure 11 For Figure 9 Based on the structural diagram, the first side region and a portion of the active region 201 adjacent to the first side region are removed to form a word line gate structure, and a second groove 207 is formed between the word line gate structure and the active region 201.

[0072] The wordline gate structure includes a gate dielectric layer 208 located on a portion of the sidewall surfaces and the bottom surface of the first groove 203, and a gate layer 209 located on the surface of the gate dielectric layer 208. The wordline gate structure is located within the substrate, thereby saving space in a direction perpendicular to the substrate surface and increasing the density of the memory array cells.

[0073] The first side region and a portion of the active region 201 adjacent to the first side region are removed, so that only the second side of the word line gate structure is in contact with the active region 201, thereby generating a channel during operation, so that the transistor meets performance requirements, and is easy to control when turned on and off, thereby reducing leakage current.

[0074] In this embodiment, the bottom plane of the second groove 207 in the direction toward the second surface 400 of the substrate is lower than half the height of the gate layer 209. This ensures that the isolation effect of the first isolation structure subsequently formed in the second groove 207 completely shuts off the channel in the first side region of the word line gate structure, thereby reducing leakage current.

[0075] In this embodiment, the process of removing the first side region and a portion of the active region 201 adjacent to the first side region includes a dry etching process, which can easily control the depth and dimensional accuracy of the formed second groove 207 .

[0076] Please refer to Figure 12 and Figure 13 , Figure 13 for Figure 12 A top view of Figure 12 for Figure 13 A schematic cross-sectional structural diagram along the section line FF1 shows that a first isolation structure 210 is formed in the second groove 207 .

[0077] The first isolation structure 210 is also located on the top surface of the word line gate structure.

[0078] The first isolation structure 210 is located between the word line gate structure and the active area 201. The second side area of ​​the word line gate structure is adjacent to the active area 201. Thus, the first isolation structure 210 can isolate the first side area of ​​the word line gate structure from the active area 201, thereby preventing the word line gate structure from contacting the active areas 201 on both adjacent sides at the same time to generate two channels to form a parasitic device, making it difficult to turn off the transistor, thereby reducing leakage current.

[0079] The method for forming the first isolation structure 210 includes: forming an isolation material layer (not shown) in the second groove 207, on the top of the word line gate structure and on the surface of the active area 201; and planarizing the isolation material layer until the surface of the active area 201 is exposed to form the first isolation structure 210.

[0080] The material of the first isolation structure 210 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0081] In this embodiment, the material of the first isolation structure 210 includes silicon oxide.

[0082] In this embodiment, the bottom plane of the first isolation structure 210 in the direction toward the second substrate surface 400 is lower than half the height of the gate layer 209. Therefore, the isolation effect of the first isolation structure 210 allows the channel in the first side region of the word line gate structure to be completely shut off, thereby reducing leakage current.

[0083] Please refer to Figure 14 and Figure 15 , Figure 15 for Figure 14 A top view of the first surface 300 of the substrate, Figure 14 for Figure 15 As shown in the cross-sectional structural diagram along the section line GG1 , a plurality of capacitor structures 212 are formed on the first surface of each active region 201 , and each capacitor structure 212 is electrically connected to one first doped region 206 .

[0084] Each of the capacitor structures 212 is located on the active area 201 adjacent to the second side area, and a projection of the capacitor structure 212 on the first surface of the active area 201 at least overlaps with a portion of the first doped area 206 .

[0085] In this embodiment, the method further includes forming a capacitor plug 211 on the first doping region 206 , wherein the capacitor plug 211 electrically connects the capacitor structure 212 and the first doping region 206 .

[0086] The method for forming the capacitor plug 211 and the capacitor structure 212 includes: forming a second dielectric layer (not shown) on the first isolation structure 210 and the first surface 300 of the active region 201; forming a fourth groove (not shown) in the second dielectric layer; forming an opening (not shown) in the fourth groove, wherein the opening exposes a portion of the surface of the first doped region 206; forming the capacitor plug 211 in the opening, and forming the capacitor structure 212 in the fourth groove.

[0087] The method for forming the capacitor plug 211 and the capacitor structure 212 includes forming a fourth groove in the second dielectric layer, forming an opening in the fourth groove, forming the capacitor plug in the opening, and finally forming the capacitor structure in the fourth groove. This method has a large process window, a simple process, and can improve production efficiency.

[0088] The capacitor structure 212 includes a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0089] The shape of the dielectric layer includes: planar or "U" shape.

[0090] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0091] When the dielectric layer is in a "U" shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0092] The material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes: a combination of one or more of tantalum nitride and titanium nitride.

[0093] The material of the capacitor plug 211 includes metal or metal nitride. The metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum. The metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0094] In another embodiment, the capacitor plug may not be formed, and the capacitor structure is directly in contact and electrically connected to the first doped region.

[0095] The method for forming the capacitor structure includes: forming a second dielectric layer on the first isolation structure and the first surface of the active area; forming a fourth groove in the second dielectric layer, wherein the fourth groove exposes a portion of the surface of the first doped area; and forming a capacitor structure in the fourth groove.

[0096] Next, a plurality of bit line structures 215 are formed on the second surface 400 of the substrate. The plurality of bit line structures 215 are arranged along the first direction X and parallel to the second direction Y. The formation process of the bit line structures 215 is shown in FIG. Figures 16 to 24 .

[0097] Please refer to Figure 16 、 Figure 17 and Figure 18 , Figure 18 for Figure 16 and Figure 17 A top view of the second surface 400 of the substrate, Figure 16 for Figure 18 Schematic diagram of the cross-section structure along the section line HH1, Figure 17 for Figure 18 The schematic cross-sectional structure diagram along the section line JJ1 shows that the second surface 400 of the substrate is thinned until the surface of the second isolation structure 202 is exposed.

[0098] The method for thinning the second surface 400 of the substrate includes: providing a base (not shown), bonding the surface of the base to the surface of the second dielectric layer; turning the base and the substrate over, and thinning the second surface 400 of the substrate.

[0099] The process of thinning the second surface 400 of the substrate includes a chemical mechanical polishing process.

[0100] Please refer to Figure 19 、 Figure 20 and Figure 21 , Figure 21 for Figure 19 and Figure 20 A top view of the second surface 400 of the substrate, Figure 19 for Figure 21 Schematic diagram of the cross-section structure along the section line KK1, Figure 20 for Figure 21 As shown in the cross-sectional structural diagram along the section line LL1 , ion implantation is performed on the second surface 400 of the thinned active region to form a second doped region 213 in the active region 201 .

[0101] The second doping region 213 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0102] In this embodiment, the conductivity type of the doped ions in the second doped region 213 is the same as the conductivity type of the doped ions in the first doped region 206 .

[0103] Please refer to Figure 22 、 Figure 23 and Figure 24 , Figure 24 for Figure 22 and Figure 23 A top view of the second surface 400 of the substrate, Figure 22 for Figure 24 Schematic diagram of the cross-section structure along the section line MM1, Figure 23 for Figure 24 As shown in the cross-sectional structural diagram along the section line NN1 , a plurality of bit line structures 215 are formed on the second doped region 213 . Each bit line structure is electrically connected to the second doped region 213 in one active region 201 .

[0104] The method for forming the bit line structure 215 includes: forming a first dielectric layer 214 on the active area 201 on the second surface 400 of the substrate and on the second isolation structure 202, wherein the first dielectric layer 214 has a plurality of third grooves (not shown), and the third grooves expose the surface of the second doped region 213; and forming the bit line structure 215 in the third grooves.

[0105] The bit line structure 215 includes a barrier layer (not shown) located on the sidewall surfaces and the bottom surface of the third groove, and a bit line layer (not shown) located on the barrier layer.

[0106] The material of the barrier layer includes metal nitride; the material of the bit line layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0107] In another embodiment, the method further includes forming a bit line plug on the second doping region, wherein the bit line plug electrically connects the bit line structure and the second doping region.

[0108] Thus, the semiconductor structure formed has, on the one hand, the capacitor structure 212 located on the first surface 300 of the substrate, and the bitline structure 215 located on the second surface 400 of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process; on the other hand, the wordline gate structure is located within the substrate, thereby saving space in a direction perpendicular to the substrate surface and increasing the density of the memory array cells; on the other hand, a first isolation structure 210 is provided between the wordline gate structure and the active area 201, and the second side region of the wordline gate structure is adjacent to the active area 201, so that the first isolation structure 210 can isolate the first side region of the wordline gate structure from the active area 201, preventing the wordline gate structure from contacting the active areas 201 on both sides simultaneously, thereby generating two channels and forming parasitic devices, making it difficult to turn off the transistor. This can reduce leakage current and improve the performance of the semiconductor structure.

[0109] Figures 25 to 27 It is a structural schematic diagram of the semiconductor structure forming process in another embodiment of the present invention.

[0110] Please refer to Figure 25 and Figure 26 , Figure 25 For Figure 19 The structural diagram of the foundation, Figure 26 For Figure 21 The structural diagram of the foundation, Figure 26 for Figure 25 A top view of the second surface 400 of the substrate, Figure 25 for Figure 26 The schematic diagram of the cross-sectional structure along the section line OO1 shows that part of the active area 201 at the bottom of the word line gate structure is removed until the surface of the gate dielectric layer 208 is exposed, a fifth groove 301 is formed in the active area 201, and several discrete second doped regions 313 are formed on the second surface 400 of the active area 201.

[0111] Please refer to Figure 27 , Figure 27 For Figure 25Based on the structural schematic diagram, a first dielectric layer 314 is formed in the fifth groove 301, on the active area 201 on the second surface 400 of the substrate and on the second isolation structure 202, and the first dielectric layer 314 has a plurality of third grooves (not shown), and the third grooves expose the surface of the second doped region 313; a bit line structure 315 is formed in the third grooves.

[0112] The second surfaces 400 of the active region 201 are separated from each other, so that after the bit line structure 315 is formed on the second doping region 313 , the capacitance generated is reduced.

[0113] Figures 28 to 30 It is a structural schematic diagram of the semiconductor structure forming process in another embodiment of the present invention.

[0114] Please refer to Figure 28 , Figure 28 For Figure 4 Based on the structural schematic diagram, an initial word line gate structure is formed in the first groove 203, and the initial word line gate structure includes a first side region (not marked) and a second side region (not marked) relative to each other, and the first side region and the second side region are respectively adjacent to the active area 201.

[0115] The initial word line gate structure includes an initial gate dielectric layer 404 located on the sidewall surfaces and the bottom surface of the first groove 203 and an initial gate layer located on the surface of the initial gate dielectric layer 404 .

[0116] In this embodiment, the initial gate layer includes a first sub-portion 405 located at the bottom of the first groove 203 and a second sub-portion 406 located above the first sub-portion 405 . The first sub-portion 405 and the second sub-portion 406 are made of different materials.

[0117] In this embodiment, the material of the first section 405 includes metal or polysilicon, and the material of the second section 406 includes metal or polysilicon, and the metal includes tungsten.

[0118] The ratio of the height of the second sub-portion 406 to the height of the first sub-portion 405 is in a range of 1:4 to 4:1, thereby ensuring that the resistance reduction and leakage current reduction effects of the subsequently formed word line gate structure are balanced.

[0119] The method for forming the initial word line gate structure includes: forming an initial gate dielectric material layer (not shown) on the sidewall surface and bottom surface of the first groove 203 and the top surface of the active area 201 of the first surface 300 of the substrate; forming an initial first subdivision (not shown) on the initial gate dielectric layer; etching back the initial first subdivision until the top surface of the initial first subdivision is lower than the top surface of the active area 201 of the first surface 300 of the substrate and a portion of the initial gate dielectric material layer on the sidewall of the first groove 201 is exposed, thereby forming a first subdivision 405; forming an initial second subdivision (not shown) on the first subdivision 405; planarizing the initial second subdivision and the initial gate dielectric material layer on the top of the active area 201 of the first surface 300 of the substrate until the top surface of the active area 201 of the first surface 300 of the substrate is exposed, thereby forming an initial gate dielectric layer 404 and a transitional second subdivision (not shown); and etching back the transitional second subdivision to form a second subdivision 406.

[0120] Please refer to Figure 29 and Figure 30 , remove the first side region and a portion of the active region 201 adjacent to the first side region to form a word line gate structure, and form a second groove (not shown) between the word line gate structure and the active region 201; and form a first isolation structure 410 in the second groove.

[0121] Please refer to Figure 29 The material of the first section 405 includes metal, the metal includes tungsten, the material of the second section 406 includes polysilicon, and the bottom plane of the first isolation structure 410 in the direction toward the second surface 400 of the substrate is lower than the bottom plane of the second section 406 in the direction toward the second surface 400 of the substrate.

[0122] Therefore, the bottom plane of the first isolation structure 410 only needs to be ensured to be lower than the bottom plane of the second sub-portion 406 to achieve the effect of turning off the channel in the first side region of the word line gate structure.

[0123] The formation process of the first isolation structure 410 can be referred to Figure 11 and Figure 12 , I will not go into details here.

[0124] Please refer to Figure 30 The first subsection 405 is made of polysilicon, and the second subsection 406 is made of a metal including tungsten. The bottom plane of the first isolation structure 410 in the direction toward the second substrate surface 400 is lower than the bottom plane of the first subsection 406 in the direction toward the second substrate surface 400. This ensures that the first isolation structure 410 can completely isolate the first side region of the word line gate structure from the active area 201, thereby achieving the effect of shutting off the channel in the first side region of the word line gate structure.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a plurality of mutually separated active regions, the plurality of active regions being arranged along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other; forming a plurality of first grooves in the substrate, wherein the first grooves extend from the first surface to the second surface, the plurality of first grooves are arranged along the second direction, and the first grooves penetrate the plurality of active regions along the first direction; forming an initial word line gate structure in the first groove, wherein the initial word line gate structure includes a first side region and a second side region opposite to each other, wherein the first side region and the second side region are respectively adjacent to the active region; removing the first side region and a portion of the active region adjacent to the first side region to form a word line gate structure, and forming a second groove between the word line gate structure and the active region; forming a first isolation structure in the second groove; forming a plurality of capacitor structures on the first surface of each active area; A plurality of bit line structures are formed on the second surface of the substrate. The plurality of bit line structures are arranged along a first direction and are parallel to a second direction.

2. The method for forming a semiconductor structure according to claim 1, wherein: The word line gate structure includes a gate dielectric layer located on the sidewall surface and the bottom surface of the first groove and a gate layer located on the surface of the gate dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: A bottom plane of the first isolation structure in a direction toward the second surface of the substrate is lower than half of the height of the gate layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The gate layer is made of polysilicon or metal, and the metal includes tungsten.

5. The method for forming a semiconductor structure according to claim 2, wherein: The gate layer includes a first portion located at the bottom of the first groove and a second portion located on the first portion. The first portion and the second portion are made of different materials.

6. The method for forming a semiconductor structure according to claim 5, wherein: The ratio of the height of the second section to the height of the first section is in a range of 1:4 to 4:

1.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first section includes metal including tungsten, and the material of the second section includes polysilicon; the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than the bottom plane of the second section in the direction toward the second surface of the substrate.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first section includes polysilicon, the material of the second section includes metal, and the metal includes tungsten; the bottom plane of the first isolation structure in the direction toward the second surface of the substrate is lower than the bottom plane of the first section in the direction toward the second surface of the substrate.

9. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the word line gate structure includes: forming an initial gate dielectric material layer on the side wall surface and bottom surface of the first groove and the top surface of the active area of ​​the first side of the substrate; forming an initial first section on the initial gate dielectric material layer; etching back the initial first section until the top surface of the initial first section is lower than the top surface of the active area of ​​the first side of the substrate and a portion of the initial gate dielectric material layer on the side wall of the first groove is exposed to form a first section; forming an initial second section on the first section; flattening the initial second section and the initial gate dielectric material layer on the top of the active area of ​​the first side of the substrate until the top surface of the active area of ​​the first side of the substrate is exposed to form a gate dielectric layer and a transitional second section; etching back the transitional second section to form the second section.

10. The method for forming a semiconductor structure according to claim 2, wherein: A second isolation structure is provided between adjacent active areas; and a method for forming a plurality of bit line structures on the second surface of the substrate comprises: thinning the second surface of the substrate until the surface of the second isolation structure is exposed; ion implanting the second surface of the thinned active area to form a second doped area within the active area; and forming a plurality of bit line structures on the second doped area, wherein each bit line structure is electrically connected to the second doped area within an active area.

11. The method for forming a semiconductor structure according to claim 10, wherein: Before forming a plurality of bit line structures on the second doping region, the method further includes: forming a bit line plug on the second doping region, wherein the bit line plug electrically connects the bit line structure and the second doping region.

12. The method for forming a semiconductor structure according to claim 10, wherein: After ion implantation is performed on the second surface of the thinned active area and before a plurality of bit line structures are formed on the second doped area, the method further includes: removing a portion of the active area at the bottom of the word line gate structure until the surface of the gate dielectric layer is exposed.

13. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the bit line structure includes: forming a first dielectric layer on the active area on the second side of the substrate and on the second isolation structure, wherein the first dielectric layer has a plurality of third grooves, and the third grooves expose the second side surface of the active area; forming the bit line structure in the third grooves.

14. The method for forming a semiconductor structure according to claim 13, wherein: The bit line structure includes a barrier layer located on the sidewall surface and the bottom surface of the third groove, and a bit line layer located on the barrier layer.

15. The method for forming a semiconductor structure according to claim 10, wherein: The material of the second isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

16. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming a capacitor structure includes: forming a second dielectric layer on the first isolation structure and the first surface of the active area; forming a fourth groove in the second dielectric layer, wherein the fourth groove exposes a portion of the first surface of the active area; and forming a capacitor structure in the fourth groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for thinning the second surface of the substrate includes: providing a base, wherein the surface of the base is bonded to the surface of the second dielectric layer; turning over the base and the substrate, and thinning the second surface of the substrate.

18. The method for forming a semiconductor structure according to claim 10, wherein: The process of thinning the second surface of the substrate includes a chemical mechanical polishing process.

19. The method for forming a semiconductor structure according to claim 1, wherein: After forming the initial word line gate structure, before removing the first side region and the portion of the active region adjacent to the first side region, the method further includes: performing ion implantation on the first surface of the active region to form a first doped region in the active region; and each capacitor structure is electrically connected to a first doped region.

20. The method for forming a semiconductor structure according to claim 19, wherein: A projection of the capacitor structure on the first surface of the active region at least overlaps with a portion of the first doped region.

21. The method for forming a semiconductor structure according to claim 19, wherein: After forming the first isolation structure and before forming a plurality of capacitor structures on the first surface of each active region, the method further includes: forming a capacitor plug on the first doped region, wherein the capacitor plug electrically connects the capacitor structure and the first doped region.

22. The method for forming a semiconductor structure according to claim 19, wherein: A top surface of the word line gate structure facing the first surface of the substrate is lower than a bottom plane of the first doped region facing the second surface of the substrate.

23. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first side region and a portion of the active region adjacent to the first side region includes a dry etching process.

24. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

25. The method for forming a semiconductor structure according to claim 1, wherein: The capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer.

26. The method for forming a semiconductor structure according to claim 25, wherein: The shape of the dielectric layer includes: planar or "U" shape.

27. The method for forming a semiconductor structure according to claim 1, wherein: Each of the capacitor structures is located on the active area adjacent to the second side area.

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