Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method comprises: forming a plurality of first recesses in a first substrate, the first recesses extending from a first surface to a second surface, the first recesses being arranged along a second direction, the first recesses penetrating a plurality of active regions along a first direction, and a distance from a bottom of the first recess to the first surface being less than a thickness of an isolation layer; forming a word line gate structure in the first recess; thinning the first substrate from the second surface until a surface of the isolation layer is exposed; and forming a bit line on the second surface after the thinning, the bit line being arranged along the first direction and being parallel to the second direction, one active region being electrically interconnected with one bit line, without forming a bit line contact, reducing a difficulty of a process manufacturing, improving a process window of forming the bit line, and saving a production cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] Memory typically includes storage capacitors and storage transistors connected to them. Storage capacitors store electrical charge representing stored information, while storage transistors act as switches controlling the inflow and outflow of charge from the capacitors. These transistors are also connected to internal circuitry within the memory and receive control signals from it. Each storage transistor contains an active region, a drain region, and a gate. The gate controls the current flow between the source and drain regions and is connected to the word line. The drain region forms a bit line contact region to connect to the bit line. The source region forms a memory node contact region to connect to the storage capacitor.

[0004] The development of dynamic random access memory (DRAM) has placed higher demands on the stability of its fabrication process. In existing technologies, bit lines are formed using photolithography. Because the photolithography process requires precise alignment between bit lines, the alignment requirements are high, increasing the difficulty of manufacturing.

[0005] In summary, the existing bit line fabrication process has a small window, resulting in poor performance stability of the formed memory. The existing bit line fabrication process needs further improvement. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the bit line formation process window and improve the performance stability of the memory.

[0007] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a first substrate having a first surface and a second surface opposite to each other; the first substrate including a plurality of mutually discrete active regions, an isolation layer between adjacent active regions, the plurality of active regions being arranged along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other, and the first surface exposing the isolation layer; a plurality of first grooves located within the first substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged along the second direction and penetrating through the plurality of active regions along the first direction, and the distance from the bottom of the first groove to the first surface being less than the thickness of the isolation layer; a word line gate structure located within the first grooves; the second surface exposing the isolation layer; and bit lines located on the second surface, the bit lines being arranged along the first direction and parallel to the second direction, with one active region electrically interconnected with one bit line.

[0008] Optionally, the surface of the isolation layer protrudes from the second surface, and the isolation layers have a second groove that exposes the second surface, the second groove being parallel to the second direction and arranged along the first direction; the bit line is located within the second groove.

[0009] Optionally, it further includes: a dielectric layer located on the second surface, the dielectric layer having a second groove exposing the surface of the active region, the second groove being parallel to a second direction and arranged along a first direction; the bit line being located within the second groove.

[0010] Optionally, it may also include: a plurality of second source / drain regions located within each of the active regions, the second source / drain regions extending from the first surface to the second surface.

[0011] Optionally, it may also include: a plurality of capacitors located on the first surface, each of the capacitors being electrically interconnected with a second source-drain region.

[0012] Optionally, it also includes: a first source / drain region located within the active region, the first source / drain region extending from the bottom of the second groove toward the first surface.

[0013] Accordingly, the present invention also provides a method for forming the above-mentioned semiconductor structure, comprising: providing a first substrate having a first surface and a second surface opposite to each other, the first substrate including a plurality of mutually discrete active regions, an isolation layer between adjacent active regions, the plurality of active regions being arranged along a first direction and parallel to a second direction, the first direction and the second direction being perpendicular to each other, and the first surface exposing the isolation layer; forming a plurality of first grooves in the first substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged along the second direction, and the first grooves penetrating the plurality of active regions along the first direction, and the distance from the bottom of the first groove to the first surface being less than the thickness of the isolation layer; forming a word line gate structure in the first grooves; thinning the first substrate from the second surface until the surface of the isolation layer is exposed; after the thinning process, forming bit lines on the second surface, the bit lines being arranged along the first direction and parallel to the second direction, and an active region being electrically interconnected with a bit line.

[0014] Optionally, the bit line formation method includes: after the thinning process, etching the first substrate from the second surface to form a second groove between adjacent isolation layers; and forming a bit line in the second groove.

[0015] Optionally, after forming the second groove and before forming the bit line, the method further includes: forming a first source / drain region in the active region, the first source / drain region having a first doped ion, and the first source / drain region extending from the bottom of the second groove toward the first surface.

[0016] Optionally, the method for forming the first source / drain region includes: implanting a first doped ion into the active region at the bottom of the second groove, the first doped ion including N-type or P-type ions; and annealing the first substrate.

[0017] Optionally, the bit line includes an electrode layer; the method of forming the bit line includes: depositing an electrode material layer from the second surface into the surface of the isolation layer and into the second groove; planarizing the electrode material layer until the surface of the isolation layer is exposed.

[0018] Optionally, the bit line may further include a barrier layer between the electrode layer and the second groove.

[0019] Optionally, after forming the second groove and before forming the bit line, the method further includes: performing surface treatment on the second groove to form a contact layer on the surface of the second groove.

[0020] Optionally, the material of the contact layer includes metal silicides.

[0021] Optionally, after forming the word line gate structure, the method further includes: implanting a second doped ion into the active region from the first surface, the second doped ion including N-type or P-type ions, and the conductivity type of the second doped ion being the same as that of the first doped ion, thereby forming a plurality of second source / drain regions on each active region.

[0022] Optionally, after forming the second source / drain region and before the thinning process, the method further includes: forming a plurality of capacitors on the first surface, each of the capacitors being electrically interconnected with a second source / drain region.

[0023] Optionally, the word line gate structure includes a first sidewall and a second sidewall opposite to each other in a second direction; after forming the word line gate structure and before forming the capacitor, the structure further includes: forming an insulating trench between each active region and the adjacent first sidewall, the insulating trench extending from the first surface to the second surface and penetrating the active region along the first direction; and forming an insulating layer in the insulating trench.

[0024] Optionally, after forming the second source / drain region and before forming the capacitor, the method further includes: forming a capacitor contact on the first surface, wherein the capacitor and the second source / drain region are electrically interconnected through the capacitor contact.

[0025] Optionally, the bit line may be made of metal.

[0026] Optionally, it further includes: providing a second substrate; and bonding the first substrate and the second substrate together with the first surface facing the second substrate after the isolation layer is formed and before the thinning process.

[0027] Optionally, the bit line formation method includes: after the thinning process, forming a dielectric material layer on the second surface; forming a first patterned layer on the surface of the dielectric material layer, the first patterned layer exposing the dielectric material layer on the active region; using the first patterned layer as a mask, etching the dielectric material layer until the surface of the active region is exposed, forming a dielectric layer and a second groove located in the dielectric layer; and forming a bit line in the second groove.

[0028] Optionally, the word line gate structure includes a gate dielectric layer located on the sidewall and bottom surface of the first recess, and a gate layer located on the gate dielectric layer.

[0029] Optionally, the gate layer may be made of metal; the gate dielectric layer may be made of oxide.

[0030] Optionally, the method for forming the first groove includes: forming a second patterned layer on the first surface, the second patterned layer exposing a portion of the active region and a portion of the isolation layer surface; and using the second patterned layer as a mask to etch the active region and the isolation layer.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] In the semiconductor structure formation method provided by the present invention, a word line gate structure is formed in the first groove, and the first substrate is thinned from the second surface until the surface of the isolation layer is exposed. After the thinning process, a bit line is formed on the second surface. The bit lines are arranged along a first direction and are parallel to a second direction. An active region is electrically interconnected with a bit line, and the bit line is in direct contact with the active region. It is not necessary to prepare bit line contacts. Therefore, the bit line does not need to be aligned with bit line contacts during bit line preparation, which reduces the difficulty of the manufacturing process, increases the bit line formation process window, and saves production costs.

[0033] Furthermore, the bit lines are formed without photolithography, but using a self-aligned method, that is, the position of the bit lines is defined by the position of the isolation layer, which saves the use of photomasks and reduces the manufacturing cost. Attached Figure Description

[0034] Figures 1 to 18 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0035] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0036] As described in the background section, the existing word line formation process has a small window, resulting in poor performance stability of the formed memory. The existing word line formation process needs further improvement.

[0037] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. A word line gate structure is formed within a first groove. The first substrate is thinned from a second surface until the surface of the isolation layer is exposed. After the thinning process, bit lines are formed on the second surface. The bit lines are arranged along a first direction and are parallel to a second direction. An active region is electrically interconnected with a bit line, and the bit line is in direct contact with the active region. No bit line contact preparation is required. Therefore, during bit line preparation, the bit lines do not need to be aligned with bit line contacts, reducing the difficulty of the manufacturing process, increasing the bit line formation process window, and saving production costs.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 1 to 18This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 Top view structural diagram, Figure 2 yes Figure 1 A cross-sectional view along the DD' direction shows a first substrate 101 with opposing first surfaces 101a and second surfaces 101b. The first substrate 101 includes a plurality of mutually discrete active regions 102, with an isolation layer 103 between adjacent active regions 102. The plurality of active regions 102 are arranged along a first direction X and are parallel to a second direction Y. The first direction X and the second direction Y are perpendicular to each other. The first surface 101a exposes the isolation layer 103.

[0041] In this embodiment, the first substrate 101 is made of silicon. In other embodiments, the first substrate may be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements may include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] The active region 102 is used to form the source / drain region and the channel region of the device.

[0043] The isolation layer 103 is formed using a chemical vapor deposition process. The isolation layer 103 is used for electrical insulation between different electrical components.

[0044] The isolation layer 103 has a thickness m, where the thickness m refers to the dimension of the isolation layer 103 in the direction perpendicular to the surface of the first substrate 101.

[0045] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Top view structural diagram, Figure 4 yes Figure 3 A cross-sectional view along the EE' direction shows that a plurality of first grooves (not shown) are formed in the first substrate 101. The first grooves extend from the first surface 101a to the second surface 101b. The plurality of first grooves are arranged along the second direction Y, and the first grooves penetrate the plurality of active regions 102 along the first direction X. The distance n from the bottom of the first groove to the first surface 101a is less than the thickness m of the isolation layer 103. A word line gate structure 104 is formed in the first groove.

[0046] In this embodiment, the isolation layer 103 is subsequently used to define the position of the bit line.

[0047] The method for forming the first groove includes: forming a second patterned layer (not shown in the figure) on the first surface 101a, the second patterned layer exposing a portion of the active region 102 and a portion of the isolation layer 103 surface; using the second patterned layer as a mask, etching the active region 102 and the isolation layer 103.

[0048] The word line gate structure 104 includes a gate dielectric layer (not shown in the figure) located on the sidewall and bottom surface of the first recess, and a gate layer (not shown in the figure) located on the gate dielectric layer.

[0049] The gate layer is made of metal; the gate dielectric layer is made of oxide.

[0050] The word line gate structure 104 includes a first sidewall 104c and a second sidewall 104d opposite each other in the second direction Y.

[0051] In this embodiment, the top surface of the word line gate structure 104 is lower than the top surface of the active region 102. This lower surface provides physical space for the subsequent implantation of second doped ions into the active region 102 from the first surface 101a, forming several second source / drain regions.

[0052] Subsequently, after forming the word line gate structure, a plurality of second source / drain regions are formed on each active region 102; the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 is exposed; after forming the second source / drain regions but before the thinning process, a plurality of capacitors are formed on the first surface 101a, each capacitor being electrically interconnected with a second source / drain region. In this embodiment, after forming the word line gate structure 104 but before forming the capacitors, an insulating layer is formed between each active region 102 and the adjacent first sidewall 104c. The method for forming the insulating layer is described in [reference needed]. Figures 5 to 6 .

[0053] Please refer to Figures 5 to 6 , Figure 5 yes Figure 6 Top view structural diagram, Figure 6 yes Figure 5 A cross-sectional structural diagram along the EE' direction shows that an insulating trench (not shown in the figure) is formed between each active region 102 and the adjacent first sidewall 104c. The insulating trench extends from the first surface 101a to the second surface 101b and penetrates the active region 102 along the first direction X. An insulating layer 105 is formed in the insulating trench.

[0054] The process for forming the insulating trench includes a dry etching process. The dry etching process is beneficial for forming a better morphology of the insulating trench.

[0055] In this embodiment, the insulating trench portion is also located within the word line gate structure 104.

[0056] In this embodiment, the bottom of the insulating trench is lower than half the height of the word line gate structure 104. This ensures the isolation effect of the insulating layer 105, prevents the word line gate structure 104 from controlling the active region 102 channel adjacent to the first sidewall 104c, and reduces leakage current.

[0057] In this embodiment, the insulating layer 105 is also located on the top surface of the word line gate structure 104.

[0058] The insulating layer 105 is located between the second sidewall 104c of the word line gate structure 104 and the active region 102. The second sidewall 104d of the word line gate structure 104 is adjacent to the active region 102. Thus, the insulating layer 105 can isolate the first sidewall 104c and the active region 102, avoiding the situation where the word line gate structure 104 simultaneously contacts the active regions 102 on both adjacent sides, resulting in two channels forming parasitic devices and making it difficult for the transistor to be turned off, thereby reducing leakage current.

[0059] The method for forming the insulating layer 105 includes: forming a dielectric material layer (not shown in the figure) in the insulating trench, on the top of the word line gate structure 104 and on the surface of the active region 102; planarizing the dielectric material layer until the surface of the active region 102 is exposed.

[0060] The insulating layer 105 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0061] In this embodiment, the insulating layer 105 is made of silicon oxide.

[0062] Please continue to refer to this. Figure 5 and Figure 6 After forming the word line gate structure 104, second doped ions are injected into the active region 102 from the first surface 101a. The second doped ions include N-type or P-type ions, and a plurality of second source / drain regions 106 are formed on each active region 102.

[0063] In this embodiment, the second dopant ion is an N-type ion, used to form an NMOS device. In other embodiments, the second dopant ion is a P-type ion, used to form a PMOS device.

[0064] Subsequently, the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 is exposed. Before the thinning process after the formation of the second source / drain region 106, the process further includes forming a plurality of capacitors on the first surface 101a, each of the capacitors being electrically interconnected with one of the second source / drain regions 106.

[0065] In this embodiment, the insulating layer 105 is formed after the word line gate structure 104 is formed and before the capacitor is formed. Specifically, the insulating layer 105 is formed before the second source / drain region 106 is formed. In other embodiments, the insulating layer 105 may be formed before the capacitor and after the second source / drain region 106 is formed.

[0066] Please refer to the method for forming the capacitor. Figures 7 to 9 .

[0067] Please refer to Figures 7 to 9 , Figure 7 yes Figure 8 and Figure 9 Top view structural diagram, Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure along the DD' direction. Figure 9 yes Figure 7 A cross-sectional view along the EE' direction shows that a plurality of capacitors 107 are formed on the first surface 101a, and each capacitor 107 is electrically interconnected with a second source-drain region 106.

[0068] After the second source / drain region 106 is formed and before the capacitor 107 is formed, a capacitor contact 108 is also formed on the first surface 101a. The capacitor 107 and the second source / drain region 106 are electrically interconnected through the capacitor contact 108.

[0069] In this embodiment, a dielectric material layer 109 is also formed on the first surface 101a, and the capacitor 107 and the capacitor contact 108 are located within the dielectric material layer 109.

[0070] The method for forming the capacitor contact 108 and the capacitor 107 includes: forming a third groove (not shown) within the dielectric material layer 109; forming a fourth groove (not shown) within the third groove, wherein the opening of the fourth groove exposes a portion of the surface of the second source / drain region 106; forming the capacitor contact 108 within the fourth groove; and forming the capacitor 107 within the third groove. The method for forming the capacitor contact 108 and the capacitor 107 has a large process window, is relatively simple, and can improve production efficiency.

[0071] The capacitor 107 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0072] The dielectric layer can be planar or U-shaped.

[0073] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0074] When the dielectric layer is U-shaped, the surface of the first electrode layer is uneven, and the surface of the second electrode layer is uneven; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0075] The material of the first electrode layer includes: a metal or a metal nitride; the material of the second electrode layer includes: a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0076] The material of the capacitive contact 108 includes: metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0077] In another embodiment, the capacitor plug can be omitted, and the capacitor structure is directly electrically connected to the first doped region.

[0078] In this embodiment, a second substrate is also provided. After the isolation layer 103 is formed and before the thinning process, the first surface 101a is made to face the second substrate, and the first substrate 101 and the second substrate are bonded together.

[0079] Please refer to Figures 10 to 12 , Figure 10 yes Figure 11 and Figure 12 Top view structural diagram, Figure 11 yes Figure 10 A schematic diagram of the cross-sectional structure along the M1M2 direction. Figure 12 yes Figure 10 A cross-sectional view along the N1N2 direction shows a second substrate 201; the first surface 101a faces the second substrate 201, and the first substrate 101 and the second substrate 201 are bonded; the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 is exposed.

[0080] The second substrate 201 is made of silicon. In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0081] Specifically, after the capacitor 107 is formed, the first substrate 101 and the second substrate 201 are bonded together.

[0082] In this embodiment, after the first substrate 101 and the second substrate 201 are bonded together, the first surface 101a and the second surface 101b of the first substrate 101 are inverted, that is, the second substrate 201 is located below the first substrate 101, and the second substrate 201 is used as a substrate to facilitate subsequent operations.

[0083] The thinning process includes chemical mechanical polishing.

[0084] Subsequently, after the thinning process, bit lines are formed on the second surface 101b. The bit lines are arranged along the first direction X and are parallel to the second direction Y. An active region 102 is electrically interconnected with a bit line. In the memory structure formed by this method, the memory capacitor 107 and bit lines are located on both sides of the transistor (active region 102). Unlike memory structures where the bit lines and capacitors are located on the same side above the transistor, where the contact lines of the capacitors must pass through the bit lines but cannot contact them, this method effectively reduces the area occupied by the memory and increases the level of memory integration.

[0085] In this embodiment, please refer to the method of forming the bit line. Figures 13 to 18 .

[0086] Please refer to Figures 13 to 15 , Figure 13 yes Figure 14 and Figure 15 Top view structural diagram, Figure 14 yes Figure 13 A cross-sectional view along the M1M2 direction. Figure 15 yes Figure 13 A cross-sectional view along the N1N2 direction is shown. After the thinning process, the first substrate 101 is etched from the second surface 101b to form a second groove 110 between adjacent isolation layers 103.

[0087] In this embodiment, after the second groove 110 is formed and before the bit line is formed, a first source / drain region 111 is formed in the active region 102. The first source / drain region 111 contains a first doped ion. The conductivity type of the first doped ion is the same as that of the second doped ion. The first source / drain region 111 extends from the bottom of the second groove 110 toward the first surface 101a.

[0088] The method for forming the first source / drain region 111 includes: implanting a first doped ion into the active region 102 at the bottom of the second groove 110, the first doped ion including N-type or P-type ions; and annealing the first substrate 101.

[0089] A channel region of the device is formed between the first source / drain region 111 and the second source / drain region 106. The channel region forms a vertical channel device structure along a direction perpendicular to the surface of the first substrate 101.

[0090] In this embodiment, the first dopant ion is an N-type ion, used to form an NMOS device. In other embodiments, the first dopant ion is a P-type ion, used to form a PMOS device.

[0091] refer to Figures 16 to 18 , Figure 16 yes Figure 17 and Figure 18 Top view structural diagram, Figure 17 yes Figure 16 A schematic diagram of the cross-sectional structure along the M1M2 direction. Figure 18 yes Figure 16 A cross-sectional view along the N1N2 direction shows that a bit line 112 is formed within the second groove 110.

[0092] The bit line 112 includes an electrode layer (not shown in the figure).

[0093] The bit line 112 is made of metal. In this embodiment, the metal is copper. In other embodiments, the metal can be tungsten, aluminum, etc.

[0094] The bit line 112 is in direct contact with the active region 102, so there is no need to prepare bit line contacts. Therefore, the bit line does not need to be aligned with bit line contacts during bit line preparation, which reduces the difficulty of the manufacturing process, increases the bit line formation process window, and saves production costs.

[0095] In this embodiment, the position of the bit line 112 is defined by the isolation layer 103 and formed by a self-alignment method. Therefore, the formation process of the bit line 112 does not require photolithography, which saves the use of photomasks and reduces the manufacturing cost.

[0096] The method for forming the bit line 112 includes: depositing an electrode material layer (not shown in the figure) from the second surface 101b onto the surface of the isolation layer 103 and into the second groove 110; planarizing the electrode material layer until the surface of the isolation layer 103 is exposed.

[0097] The bit line 112 also includes a barrier layer (not shown in the figure) between the electrode layer and the second groove 110. The barrier layer is used to block the diffusion of ions in the active region 102 into the electrode layer, which helps to improve the stability of device performance.

[0098] In this embodiment, after the second groove 110 is formed and before the bit line 112 is formed, the second groove 110 is further surface-treated to form a contact layer on the surface of the second groove 110 (not shown in the figure).

[0099] The formation process of the contact layer includes a self-aligned metal silicide process.

[0100] The contact layer is made of a metal silicide. In this embodiment, the metal silicide is titanium silicide. The contact layer is used to reduce the contact resistance between the bit line 112 and the active region 102.

[0101] In other embodiments, the bit line formation method includes: after the thinning process, forming a dielectric material layer on the second surface; forming a first patterned layer on the surface of the dielectric material layer, the first patterned layer exposing the dielectric material layer on the active region; using the first patterned layer as a mask, etching the dielectric material layer until the surface of the active region is exposed, forming a dielectric layer and a second groove located within the dielectric layer; and forming a bit line within the second groove. The bit line is in direct contact with the active region, eliminating the need to prepare bit line contacts. Therefore, during bit line preparation, the bit line does not need to be aligned with bit line contacts, reducing the difficulty of the manufacturing process, increasing the bit line formation process window, and saving production costs.

[0102] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [further details]. Figures 16 to 18The system includes: a first substrate 101 having opposing first surfaces 101a and second surfaces 101b; the first substrate 101 including a plurality of mutually discrete active regions 102; an isolation layer 103 between adjacent active regions 102; the plurality of active regions 102 arranged along a first direction X and parallel to a second direction Y; the first direction X and the second direction Y being perpendicular to each other; and the first surface 101a exposing the isolation layer 103; and a plurality of first grooves (not shown in the figure) located within the first substrate 101, the first grooves extending from the first surface 101... A surface 101a extends toward a second surface 101b, a plurality of first grooves are arranged along a second direction Y, and the first grooves penetrate a plurality of active regions 102 along a first direction X, and the distance from the bottom of the first groove to the first surface 101a is less than the thickness of the isolation layer 103; a word line gate structure 104 is located in the first groove; the second surface 101b exposes the isolation layer 103; a bit line 112 is located on the second surface 101b, the bit line 112 is arranged along the first direction X, and the bit line 112 is parallel to the second direction Y, and an active region 102 is electrically interconnected with a bit line 112.

[0103] In this embodiment, the surface of the isolation layer 103 protrudes from the second surface 101b, and the isolation layers 103 have second grooves 110 that expose the second surface 101b. The second grooves 110 are parallel to the second direction Y and arranged along the first direction X; the bit line 112 is located within the second groove 110. On one hand, the bit line 112 is in direct contact with the active region 102, eliminating the need to prepare bit line contacts. Therefore, the bit line does not need to be aligned with bit line contacts during bit line preparation, reducing the difficulty of the manufacturing process, increasing the bit line formation process window, and saving production costs. On the other hand, the position of the bit line 112 is defined by the isolation layer 103 and formed using a self-alignment method. Therefore, the formation process of the bit line 112 does not require photolithography, saving the use of photomasks and reducing manufacturing costs.

[0104] In other embodiments, the method further includes: a dielectric layer located on the second surface, the dielectric layer having a second groove exposing the surface of the active region, the second groove being parallel to a second direction and arranged along a first direction; the bit line being located within the second groove. The bit line is in direct contact with the active region, eliminating the need for bit line contact fabrication. Therefore, during bit line fabrication, the bit line does not need to be aligned with the bit line contact, reducing the difficulty of the manufacturing process, increasing the bit line formation process window, and saving production costs.

[0105] In this embodiment, the semiconductor structure further includes a plurality of second source / drain regions 106 located within each of the active regions 102, the second source / drain regions 106 extending from the first surface 101a to the second surface 101b.

[0106] In this embodiment, the semiconductor structure further includes a plurality of capacitors 107 located on the first surface 101a, each of the capacitors 107 being electrically interconnected with a second source / drain region 106.

[0107] In this embodiment, the semiconductor structure further includes: a first source / drain region 111 located within the active region 102, the first source / drain region 111 extending from the second recess 110 (e.g., Figure 12 (As shown) The bottom extends toward the first surface 101a.

[0108] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: A first substrate having a first surface and a second surface opposite to each other, the first substrate including a plurality of mutually discrete active regions, an isolation layer between adjacent active regions, the plurality of active regions being arranged along a first direction and the plurality of active regions being parallel to a second direction, the first direction and the second direction being perpendicular to each other, and the first surface exposing the isolation layer. A plurality of first grooves are located within the first substrate, the first grooves extend from a first surface to a second surface, the plurality of first grooves are arranged along a second direction, and the first grooves penetrate the plurality of active regions along a first direction, and the distance from the bottom of the first groove to the first surface is less than the thickness of the isolation layer. The word line gate structure located within the first recess; The second surface exposes the insulating layer, and the surface of the insulating layer protrudes or is flush with the second surface; The bit lines located on the second surface are arranged along the first direction and are parallel to the second direction, and an active region is electrically interconnected with a bit line.

2. The semiconductor structure of claim 1, wherein, The surface of the isolation layer protrudes from the second surface, and the isolation layers have a second groove that exposes the second surface. The second groove is parallel to the second direction and arranged along the first direction; the bit line is located within the second groove.

3. The semiconductor structure of claim 1, wherein, Also includes: A dielectric layer located on the second surface, the dielectric layer having a second groove exposing the surface of the active region, the second groove being parallel to a second direction and arranged along a first direction; The bit line is located within the second groove.

4. The semiconductor structure of claim 1, wherein, Also includes: A plurality of second source-drain regions are located within each of the active regions, the second source-drain regions extending from the first surface to the second surface.

5. The semiconductor structure of claim 4, wherein, Also includes: A plurality of capacitors are located on the first surface, each of the capacitors being electrically interconnected with a second source-drain region.

6. The semiconductor structure of claim 2, wherein, Also includes: The first source / drain region is located within the active region and extends from the bottom of the second groove toward the first surface.

7. A method of forming a semiconductor structure, comprising: include: A first substrate is provided, the first substrate having a first surface and a second surface opposite to each other, the first substrate including a plurality of mutually discrete active regions, an isolation layer between adjacent active regions, the plurality of active regions being arranged along a first direction and the plurality of active regions being parallel to a second direction, the first direction and the second direction being perpendicular to each other, and the first surface exposing the isolation layer. A plurality of first grooves are formed in the first substrate. The first grooves extend from the first surface to the second surface. The plurality of first grooves are arranged along the second direction. The first grooves penetrate the plurality of active regions along the first direction. The distance from the bottom of the first groove to the first surface is less than the thickness of the isolation layer. A word line gate structure is formed within the first groove; The second surface is thinned from the first substrate until the surface of the isolation layer is exposed; After the thinning process, bit lines are formed on the second surface, the bit lines are arranged along the first direction and parallel to the second direction, an active region is electrically interconnected with a bit line, and the surface of the isolation layer is made to bulge or be flush with the second surface.

8. The method of forming a semiconductor structure of claim 7, wherein, The method for forming the bit line includes: after the thinning process, etching the first substrate from the second surface to form a second groove between adjacent isolation layers; and forming a bit line in the second groove.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the second groove and before forming the bit line, the method further includes: forming a first source / drain region in the active region, the first source / drain region having a first doped ion, and the first source / drain region extending from the bottom of the second groove toward the first surface.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first source / drain region includes: implanting a first doped ion into the active region at the bottom of the second groove, the first doped ion including N-type or P-type ions; and annealing the first substrate.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The bit line includes an electrode layer; the method of forming the bit line includes: depositing an electrode material layer from the second surface into the surface of the isolation layer and into the second groove; planarizing the electrode material layer until the surface of the isolation layer is exposed.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The bit line also includes a barrier layer between the electrode layer and the second groove.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the second groove and before forming the bit line, the method further includes: performing surface treatment on the second groove to form a contact layer on the surface of the second groove.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The material of the contact layer includes metal silicides.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the word line gate structure, the method further includes: implanting a second doped ion into the active region from the first surface, wherein the second doped ion includes an N-type or a P-type ion, and the conductivity type of the second doped ion is the same as that of the first doped ion, thereby forming a plurality of second source / drain regions on each active region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After the second source / drain region is formed, before the thinning process, the method further includes: forming a plurality of capacitors on the first surface, each of the capacitors being electrically interconnected with a second source / drain region.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The word line gate structure includes a first sidewall and a second sidewall opposite each other in a second direction; After forming the word line gate structure and before forming the capacitor, the method further includes: forming an insulating trench between each active region and an adjacent first sidewall, wherein the insulating trench extends from the first surface to the second surface and penetrates the active region along the first direction; An insulating layer is formed within the insulating trench.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, After forming the second source / drain region and before forming the capacitor, the method further includes: forming a capacitor contact on the first surface, wherein the capacitor and the second source / drain region are electrically interconnected through the capacitor contact.

19. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the bit line includes metal.

20. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: A second substrate is provided; after the isolation layer is formed and before the thinning process, the first surface is oriented toward the second substrate, and the first substrate and the second substrate are bonded together.

21. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the bit line includes: after the thinning process, forming a dielectric material layer on the second surface; forming a first patterned layer on the surface of the dielectric material layer, the first patterned layer exposing the dielectric material layer on the active region; using the first patterned layer as a mask, etching the dielectric material layer until the surface of the active region is exposed, forming a dielectric layer and a second groove located in the dielectric layer; and forming a bit line in the second groove.

22. The method for forming a semiconductor structure as described in claim 7, characterized in that, The word line gate structure includes a gate dielectric layer located on the sidewall and bottom surface of the first recess, and a gate layer located on the gate dielectric layer.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The gate layer is made of metal; the gate dielectric layer is made of oxide.

24. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the first groove includes: forming a second patterned layer on the first surface, the second patterned layer exposing a portion of the active region and a portion of the isolation layer surface; and using the second patterned layer as a mask to etch the active region and the isolation layer.

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