Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the method comprises: forming a plurality of first recesses in the first region, the first recesses extending from the first surface to the second surface, the first recesses being arranged along a second direction, and the first recesses penetrating a plurality of active regions along a first direction, and a distance from the bottom of the first recess to the first surface being less than the thickness of the isolation layer; forming a plurality of openings in the second region, the openings extending from the first surface to the second surface, a distance from the bottom of the opening to the first surface being greater than the distance from the bottom of the first recess to the first surface, and the openings being in communication with the first recesses; forming a word line gate structure in the first recesses and the openings, the word line gate structure comprising a word line in the first recess and a word line contact in the opening. The semiconductor structure forming method reduces the difficulty of process manufacturing, improves the forming process window of the word line contact, and saves production costs.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the rapid development of today's technology, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a volatile memory, and for applications that store a large amount of data, dynamic random access memory is the most commonly used solution.

[0003] The memory generally includes a storage capacitor and a storage transistor connected to the storage capacitor, the storage capacitor is used to store the charge representing the storage information, the storage transistor is a switch that controls the charge inflow and discharge of the storage capacitor, and the storage transistor is also connected to the internal circuit in the storage to receive the control signal of the internal circuit. Among them, the storage transistor is formed with a source region, a drain region and a gate, the gate is used to control the current flow between the source region and the drain region, and is connected to the word line, the drain region is used to form a bit line contact area to be connected to the bit line, and the source region is used to form a storage node contact area to be connected to the storage capacitor.

[0004] The development of dynamic random access memory puts higher requirements on the stability of its forming process. In the prior art, the word line is buried in the silicon substrate, and a separate photolithography process is required to manufacture the word line contact for leading out the word line and interconnecting with external circuits. In the photolithography process, the word line contact needs to be aligned with the buried word line, so the alignment process of photolithography is relatively high, which increases the difficulty of process manufacturing, and the additional photolithography also increases the cost of process manufacturing.

[0005] In summary, the existing forming process of the word line contact has a small process window, the performance stability of the formed memory is poor, and the existing forming process of the word line needs to be further improved. SUMMARY

[0006] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the forming process window of the word line contact and improve the performance stability of the memory.

[0007] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a first substrate, the first substrate comprising adjacent first and second regions, the first substrate having opposite first and second faces, the first region comprising a plurality of mutually discrete active regions, the adjacent active regions having an isolation layer therebetween, the plurality of active regions being arranged along a first direction and being parallel to a second direction, the first direction being perpendicular to the second direction, the first face exposing the isolation layer; a plurality of first recesses in the first region, the first recesses extending from the first face to the second face, the plurality of first recesses being arranged along the second direction and the first recesses penetrating the plurality of active regions along the first direction, and the distance from the bottom of the first recess to the first face being less than the thickness of the isolation layer; a plurality of openings in the second region, the openings penetrating the first substrate and the openings being in communication with the first recesses; a word line gate structure in the first recesses and the openings, the word line gate structure comprising a word line in the first recesses and a word line contact in the openings; the second face exposing the isolation layer; bit lines on the second face, the bit lines being arranged along the first direction and being parallel to the second direction, one active region being electrically interconnected with one bit line.

[0008] Optionally, the isolation layer surface protrudes from the second face, the isolation layer having second recesses exposing the second face therebetween, the second recesses being parallel to the second direction and being arranged along the first direction; the bit lines being in the second recesses.

[0009] Optionally, further comprising: a dielectric layer on the second face, the dielectric layer having second recesses exposing the active regions and the surfaces of the word line contacts, the second recesses being parallel to the second direction and being arranged along the first direction; a conductive layer in the second recesses, the conductive layer comprising the bit lines in the second recesses exposing the active regions and word line lead layers in the second recesses exposing the surfaces of the word line contacts.

[0010] Optionally, further comprising: a plurality of second source / drain regions in each of the active regions, the second source / drain regions extending from the first face to the second face.

[0011] Optionally, further comprising: a plurality of capacitors on the first face, each of the capacitors being electrically interconnected with one of the second source / drain regions.

[0012] Optionally, further comprising: first source / drain regions in the active regions, the first source / drain regions extending from the second face to the first face.

[0013] Correspondingly, the technical scheme of the present application also provides a forming method of the semiconductor structure, comprising: providing a first substrate, the first substrate comprising a first region and a second region adjacent to each other, the first substrate having opposite first and second surfaces, the first region comprising a plurality of active regions separated from each other by isolation layers, the plurality of active regions being arranged along a first direction and being parallel to a second direction, the first direction being perpendicular to the second direction, the first surface exposing the isolation layers; forming a plurality of first recesses in the first region, the first recesses extending from the first surface to the second surface, the plurality of first recesses being arranged along the second direction and penetrating the plurality of active regions along the first direction, the first recesses having a bottom-to-first-surface distance smaller than a thickness of the isolation layers; forming a plurality of openings in the second region, the openings extending from the first surface to the second surface, the openings having a bottom-to-first-surface distance greater than the bottom-to-first-surface distance of the first recesses, and the openings being in communication with the first recesses; forming a word line gate structure in the first recesses and the openings, the word line gate structure comprising word lines in the first recesses and word line contacts in the openings; performing a thinning process on the first substrate from the second surface until the surfaces of the isolation layers and the surfaces of the word line contacts are exposed; after the thinning process, forming bit lines on the second surface, the bit lines being arranged along the first direction and being parallel to the second direction, one active region being electrically interconnected with one bit line.

[0014] Optionally, the forming method of the bit lines comprises: after the thinning process, etching the first substrate from the second surface to form second recesses between the adjacent isolation layers; and forming the bit lines in the second recesses.

[0015] Optionally, after the second recesses are formed and before the bit lines are formed, the forming method further comprises: forming first source / drain regions in the active regions, the first source / drain regions having first doping ions therein, and the first source / drain regions extending from the second surface to the first surface.

[0016] Optionally, the forming method of the first source / drain regions comprises: implanting the first doping ions into the active regions at the bottoms of the second recesses, the first doping ions comprising N-type or P-type ions; and performing an annealing process on the substrate.

[0017] Optionally, the bit lines comprise electrode layers, and the forming method of the bit lines comprises: depositing an electrode material layer in the second recesses and on the surfaces of the isolation layers from the second surface; and planarizing the electrode material layer until the surfaces of the isolation layers are exposed.

[0018] Optionally, the bit lines further comprise barrier layers between the electrode layers and the second recesses.

[0019] Optionally, after forming the second recess, before forming the bit line, the method further comprises: performing surface treatment on the second recess to form a contact layer on the surface of the second recess.

[0020] Optionally, the material of the contact layer comprises metal silicide.

[0021] Optionally, after forming the word line gate structure, the method further comprises: implanting second doping ions from the first surface into the active region, the second doping ions comprising N-type or P-type ions, and the second doping ions having the same conductivity type as the first doping ions, to form a plurality of second source / drain regions on each active region.

[0022] Optionally, after forming the second source / drain regions, before the thinning process, the method further comprises: forming a plurality of capacitors on the first surface, each of the capacitors being electrically interconnected with one of the second source / drain regions.

[0023] Optionally, the word line comprises a first sidewall and a second sidewall opposite to each other in the second direction; after forming the word line gate structure, before forming the capacitor, the method further comprises: forming an insulating trench between each active region and the adjacent first sidewall, the insulating trench extending from the first surface to the second surface, and the insulating trench penetrating the active region in the first direction; and forming an insulating layer in the insulating trench.

[0024] Optionally, after forming the first source / drain regions, before forming the capacitors, the method further comprises: forming a capacitor contact on the first surface, the capacitors being electrically interconnected with the first source / drain regions through the capacitor contact.

[0025] Optionally, the material of the bit line comprises metal.

[0026] Optionally, the method further comprises: providing a second substrate; after forming the isolation layer, before the thinning process, bonding the first substrate to the second substrate with the first surface facing the second substrate.

[0027] Optionally, the method of forming the bit line comprises: after the thinning process, forming a dielectric material layer on the second surface; forming a first patterned layer on the surface of the dielectric material layer, the first patterned layer exposing the dielectric material layer on the active region; using the first patterned layer as a mask, etching the dielectric material layer until the active region and the word line contact surface are exposed, to form a dielectric layer and a second recess in the dielectric layer; and forming a conductive layer in the second recess, the conductive layer in the second recess exposed by the active region being a bit line, and the conductive layer in the second recess exposed by the word line contact surface being a word line lead-out layer.

[0028] Optionally, the word line comprises a gate dielectric layer on the sidewall and bottom surface of the first recess, and a gate layer on the gate dielectric layer.

[0029] Optionally, the material of the gate layer comprises metal, and the material of the gate dielectric layer comprises oxide.

[0030] Optionally, the forming method of the first recess and the opening comprises: forming a second patterned layer on the first surface, the second patterned layer exposing part of the active region and part of the surface of the isolation layer; and etching the first substrate with the second patterned layer as a mask.

[0031] Optionally, the forming process of the first recess and the opening comprises a dry etching process.

[0032] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0033] In the forming method of the semiconductor structure provided by the technical scheme, a plurality of openings are formed in the second region, the openings extend from the first surface to the second surface, the distance from the bottom of the opening to the first surface is greater than the distance from the bottom of the first recess to the first surface, and the opening is in communication with the first recess. A word line gate structure is formed in the first recess and the opening, the word line gate structure comprises a word line in the first recess and a word line contact in the opening, the word line and the word line contact can be formed in the same process, and a separate photolithography process is not required to form a word line contact for interconnecting the word line with external circuits, thereby reducing the difficulty of process manufacturing, improving the process window of forming the word line contact, and saving production cost.

[0034] Further, a conductive layer is formed in the second recess, the conductive layer in the second recess exposing the active region is a bit line, and the conductive layer in the second recess exposing the surface of the word line contact is a word line lead-out layer. The bit line is formed at the same time as the word line lead-out layer, which is used for interconnecting the word line with external circuits, and a separate process is not required to lead out the word line, thereby saving the production process and reducing production cost.

[0035] Further, the forming method of the bit line comprises: etching the first substrate from the second surface to form a second recess between adjacent isolation layers; and forming a bit line in the second recess. On the one hand, the formation of the bit line does not require a photolithography process, but a self-alignment method is used to define the position of the bit line, thereby saving the use of a mask and reducing the cost of process manufacturing; on the other hand, the word line contact is still exposed on the surface of the first substrate after the formation of the bit line, and the word line contact can be directly interconnected with external circuits, and a separate process is not required to lead out the word line, thereby saving the generation process and reducing production cost.

[0036] The semiconductor structure provided by the technical scheme of the present application is characterized in that the word line gate structure in the first groove includes the word line and the word line contact, and the word line and the word line contact are formed in the same process, without the need of using a separate photolithography process to form the word line contact for interconnecting the word line with external circuits, thus reducing the difficulty of process manufacturing, improving the process window of forming the word line contact, and saving production cost. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figures 1-23 is a structural schematic diagram of each step in a forming method of a semiconductor structure of an embodiment of the present application;

[0038] Figures 24-26 is a structural schematic diagram of each step in a forming method of a semiconductor structure of another embodiment of the present application. DETAILED DESCRIPTION

[0039] It should be noted that the "surface", "upper", and the like in the present specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0040] As described in the background, the existing process window of forming the word line contact is small, and the performance stability of the formed memory is poor, and the existing process of forming the word line contact needs to be further improved.

[0041] To solve the above technical problems, the technical scheme of the present application provides a forming method of a semiconductor structure, which is characterized in that: a plurality of openings are formed in the second region, the openings extend from the first surface to the second surface, the distance from the bottom of the opening to the first surface is greater than the distance from the bottom of the first groove to the first surface, and the opening is in communication with the first groove; a word line gate structure is formed in the first groove and the opening, the word line gate structure includes a word line in the first groove and a word line contact in the opening, and the word line and the word line contact can be formed in the same process, without the need of using a separate photolithography process to form the word line contact for interconnecting the word line with external circuits, thus reducing the difficulty of process manufacturing, improving the process window of forming the word line contact, and saving production cost.

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0043] Figures 1-23 is a structural schematic diagram of each step in a forming method of a semiconductor structure of an embodiment of the present application;

[0044] Reference should be made to Figures 1-2 , Figure 1 isFigure 2 a top view structural schematic diagram of the first substrate 101, Figure 2 is Figure 1 a cross-sectional structural schematic diagram of the first substrate 101 along the direction of DD' in the first embodiment, a first substrate 101 is provided, the first substrate 101 comprises adjacent first region I and second region II, the first substrate 101 has opposite first face 101a and second face 101b, the first region I comprises a plurality of mutually separate active regions 102, the adjacent active regions 102 have isolation layers 103, the plurality of active regions 102 are arranged along a first direction X, and the plurality of active regions 102 are parallel to a second direction Y, the first direction X and the second direction Y are perpendicular to each other, and the first face 101a exposes the isolation layers 103.

[0045] In the embodiment, the material of the first substrate 101 is silicon. In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] The active region 102 is used to form the source-drain region and channel region of the device.

[0047] The formation process of the isolation layer 103 includes a chemical vapor deposition process. The isolation layer 103 is used for electrical insulation between different electrical devices.

[0048] The isolation layer 103 has a thickness m, which refers to the dimension of the isolation layer 103 in the direction perpendicular to the surface of the first substrate 101.

[0049] The first region I is used to form MOS devices, and the second region II is used to form word line contacts.

[0050] Subsequently, a plurality of first recesses are formed in the first region I, the first recesses extend from the first face 101a to the second face 101b, a plurality of the first recesses are arranged along the second direction Y, and the first recesses penetrate a plurality of the active regions 102 along the first direction X, and the distance from the bottom of the first recess to the first face 101a is less than the thickness m of the isolation layer; a plurality of openings are formed in the second region II, the openings extend from the first face 101a to the second face 101b, the distance from the bottom of the opening to the first face 101a is greater than the distance from the bottom of the first recess to the first face 101a, and the opening communicates with the first recess. In the embodiment, the formation method of the first recess and the opening, please refer to Figures 3-5 .

[0051] Please refer to Figures 3-5 , Figure 3is Figure 4 and Figure 5 a top view structural schematic diagram of, Figure 4 is Figure 3 a cross-sectional structural schematic diagram along the direction of DD' in, Figure 5 is Figure 3 a cross-sectional structural schematic diagram along the direction of EE' in, a second patterning layer (not labeled in the figure) is formed on the first surface 101a, the second patterning layer exposes part of the active region 102 and part of the surface of the isolation layer 103; taking the second patterning layer as a mask, etching the first substrate 101 to form a first recess 201 and an opening 202.

[0052] The forming process of the first recess 201 and the opening 202 includes a dry etching process.

[0053] The distance h from the bottom of the opening 202 to the first surface 101a is greater than the distance n from the bottom of the first recess 201 to the first surface 101a; the distance n from the bottom of the first recess 201 to the first surface 101a is less than the thickness m of the isolation layer 103. In this embodiment, the distance h from the bottom of the opening 202 to the first surface 101a is greater than the thickness m of the isolation layer 103. In other embodiments, the distance h from the bottom of the opening 202 to the first surface 101a can be less than or equal to the thickness m of the isolation layer 103.

[0054] The proportion of the area of the second region II exposed by the second patterning layer to the area of the second region II is greater than the proportion of the area of the first region I exposed by the second patterning layer to the area of the first region I, so that under the loading effect of the etching process, the distance h from the bottom of the opening 202 formed in the second region II to the first surface 101a is greater than the distance n from the bottom of the first recess 201 formed in the first region I to the first surface 101a. The second patterning layer as a mask forms the first recess 201 and the opening 202, which is used to facilitate the loading effect of the etching process, and at the same time, the opening 202 is deeper than the first recess 201. Therefore, the shape of the second patterning layer is not limited to the shape described in this embodiment.

[0055] The first recess 201 is used to form a word line, and the opening 202 is used to form a word line contact for interconnecting the semiconductor structure with external circuits. The opening 202 and the first recess 201 are formed in the same photolithography process, without the need to use a separate photolithography process to manufacture the recess required for the word line contact, thereby reducing the difficulty of process manufacturing and improving the process window for forming the word line contact.

[0056] Please refer to Figures 6-8 , Figure 6 is Figure 7 andFigure 8 Top view structural diagram, Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along the DD' direction. Figure 8 yes Figure 6 A cross-sectional view along the EE' direction shows that a word line gate structure is formed in the first groove 201 and the opening 202. The word line gate structure includes a word line 104 located in the first groove 201 and a word line contact 105 located in the opening 202.

[0057] The word line 104 includes a gate dielectric layer (not shown in the figure) located on the sidewall and bottom surface of the first groove, and a gate layer (not shown in the figure) located on the gate dielectric layer.

[0058] The gate layer is made of metal; the gate dielectric layer is made of oxide.

[0059] The word line 104 includes a first sidewall 104c and a second sidewall 104d opposite each other in the second direction Y.

[0060] The character line 104 and the character line contact 105 are formed in the same process, saving steps and reducing production costs.

[0061] In this embodiment, the top surface of the word line 104 is lower than the top surface of the active region 102. This lower surface provides physical space for the subsequent implantation of second doped ions into the active region 102 from the first surface 101a, forming several second source / drain regions. Specifically, in this embodiment, the top surface of the word line contact 105 is flush with the top surface of the word line 104, making the surface of the word line gate structure flat and ensuring the uniformity of the word line gate structure's performance.

[0062] The method for forming the word line gate structure includes: forming a gate material layer on the surface of the first substrate 101, the surface of the isolation layer 103, the first groove 201, and the opening 202; planarizing the gate material layer until the surfaces of the first substrate 101 and the isolation layer 103 are exposed; and after the planarization process, etching back the gate material layer to form the word line gate structure.

[0063] Subsequently, after forming the word line gate structure, a plurality of second source / drain regions are formed on each active region 102; the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 and the surface of the word line contact 105 are exposed; after forming the second source / drain regions, a plurality of capacitors are formed on the first surface 101a, each of the capacitors being electrically interconnected with one of the second source / drain regions. In this embodiment, after forming the word line gate structure, before forming the capacitors, an insulating layer is formed between each active region 102 and the adjacent first sidewall 104c. The forming method of the insulating layer is described with reference to Figures 9-11 .

[0064] Please refer to Figures 9-11 , Figure 9 is Figure 10 and Figure 11 is a top view structural schematic diagram, Figure 10 is Figure 9 is a sectional view structural schematic diagram along the direction of DD', and Figure 11 is Figure 9 is a sectional view structural schematic diagram along the direction of EE', an insulating trench (not labeled in the figure) is formed between each active region 102 and the adjacent first sidewall 104c, the insulating trench extends from the first surface 101a to the second surface 101b, and the insulating trench penetrates the active region 102 along the first direction X; an insulating layer 106 is formed in the insulating trench.

[0065] The forming process of the insulating trench includes a dry etching process. The dry etching process is beneficial to forming a better insulating trench morphology.

[0066] In this embodiment, the insulating trench part is also located in the word line 104.

[0067] In this embodiment, the bottom of the insulating trench is lower than one half of the height of the word line 104. Thus, the isolation effect of the insulating layer 106 can be ensured, the control effect of the word line 104 on the channel of the active region 102 adjacent to the first sidewall 104c can be avoided, and the leakage current can be reduced.

[0068] In this embodiment, the insulating layer 106 is also located on the top surface of the word line 104. Specifically, the insulating layer 106 is also located on the top surface of the word line gate structure.

[0069] The insulating layer 106 is located between the first sidewall 104c of the word line 104 and the active region 102, and the second sidewall 104d of the word line 104 is adjacent to the active region 102, so that the insulating layer 106 can isolate the first sidewall 104c and the active region 102, avoid the word line 104 contacting the active regions 102 on both sides to form two channels and form a parasitic device, so that the transistor is not easy to turn off, thereby reducing the leakage current.

[0070] The forming method of the insulating layer 106 includes: forming a dielectric material layer (not labeled in the figure) in the insulating trench, on the top of the word line gate structure, and on the surface of the active region 102; and planarizing the dielectric material layer until the surface of the active region 102 is exposed.

[0071] The material of the insulating layer 106 includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0072] In the embodiment, the material of the insulating layer 106 includes silicon oxide.

[0073] Please continue to refer to Figures 9-11 , after forming the word line gate structure, second doping ions are injected into the active region 102 from the first surface 101a, and the second doping ions include N-type or P-type ions, and a plurality of second source / drain regions 107 are formed on each active region 102.

[0074] In the embodiment, the second doping ions are N-type ions, and are used to form an NMOS device. In other embodiments, the second doping ions are P-type ions, and are used to form a PMOS device.

[0075] Subsequently, the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 is exposed. After the second source / drain region 107 is formed, the thinning process further includes: forming a plurality of capacitors on the first surface 101a, and each capacitor is electrically interconnected with one second source / drain region 107.

[0076] In the embodiment, the insulating layer 106 is formed after the word line gate structure is formed and before the capacitor is formed. Specifically, the insulating layer 106 is formed before the second source / drain region 107 is formed. In other embodiments, the insulating layer 106 can be formed before the capacitor and after the second source / drain region 107 is formed.

[0077] The forming method of the capacitor is described in detail in Figures 12-14 .

[0078] Please refer toFigures 12-14 , Figure 12 is Figure 13 and Figure 14 is a top view structural schematic diagram, Figure 13 is Figure 12 is a cross-sectional structural schematic diagram along the direction of DD', Figure 14 is Figure 12 is a cross-sectional structural schematic diagram along the direction of EE', a plurality of capacitors 108 are formed on the first surface 101a, and each of the capacitors 108 is electrically interconnected with one of the second source-drain regions 107.

[0079] After the second source-drain regions 107 are formed, before the capacitors 108 are formed, a capacitor contact 109 is also formed on the first surface 101a, and the capacitors 108 are electrically interconnected with the second source-drain regions 107 through the capacitor contact 109.

[0080] In the embodiment, a dielectric material layer 110 is also formed on the first surface 101a, and the capacitors 108 and the capacitor contact 109 are located in the dielectric material layer 110.

[0081] The forming method of the capacitor contact 109 and the capacitors 108 includes: forming a connected third recess (not shown) and a fourth recess (not shown) in the dielectric material layer 110, and exposing part of the surface of the second source-drain region 107 at the bottom of the fourth recess; forming the capacitor contact 109 in the fourth recess and forming the capacitors 108 in the third recess. The forming method of the capacitor contact 109 and the capacitors 108 has a larger process window and a simpler process, and can improve production efficiency.

[0082] The capacitors 108 include: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0083] The shape of the dielectric layer includes: a planar type or a "U" type.

[0084] When the shape of the dielectric layer is the planar type, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0085] When the shape of the dielectric layer is the "U" type, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0086] The material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0087] The material of the capacitive contact 109 includes: metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0088] In another embodiment, the capacitive plug can not be formed, and the capacitive structure is directly in contact with the first doped region.

[0089] In this embodiment, a second substrate is also provided, and after the isolation layer 103 is formed, the first surface 101a is made to face the second substrate, and the first substrate 101 and the second substrate are bonded, as shown in FIG. 4. Figures 15-17 .

[0090] Please refer to Figures 15-17 , Figure 15 is Figure 16 and Figure 17 is a top view structural schematic diagram of Figure 16 is Figure 15 is a sectional view structural schematic diagram along the MM' direction in Figure 17 is Figure 15 is a sectional view structural schematic diagram along the NN' direction in A second substrate 300 is provided; the first surface 101a is made to face the second substrate 300, and the first substrate 101 and the second substrate 300 are bonded; and the first substrate 101 is thinned from the second surface 101b until the surface of the isolation layer 103 is exposed.

[0091] The material of the second substrate 300 is silicon. In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0092] Specifically, after the capacitor 108 is formed, the first substrate 101 and the second substrate 300 are bonded.

[0093] In this embodiment, after the first substrate 101 and the second substrate 300 are bonded, the first substrate 101 is inverted upside down, i.e., the second substrate 300 is located below the first substrate 101, so that the second substrate 300 serves as a base, facilitating subsequent operations.

[0094] The thinning process includes a chemical mechanical polishing process.

[0095] Subsequently, after the thinning process, bit lines are formed on the second surface 101b, the bit lines are arranged along the first direction X, and the bit lines are parallel to the second direction Y. One active region 102 is electrically interconnected with one bit line. The memory structure formed by the method is different from the memory structure in which the bit lines and the capacitors are located on the same side of the transistor, and the contact line of the capacitor must pass through the bit line but cannot be in contact with the bit line. The memory structure can effectively reduce the area occupied by the memory and increase the integration level of the memory.

[0096] In this embodiment, the formation of the bit lines will be described below with reference to Figures 18-23 .

[0097] Please refer to Figures 18-20 , Figure 18 is Figure 19 and Figure 20 is a top view structural schematic diagram of Figure 19 is Figure 18 is a cross-sectional view along the MM' direction in Figure 20 is Figure 18 is a cross-sectional view along the NN' direction in

[0098] In this embodiment, after the second recess 111 is formed, the first source / drain region 112 is formed in the active region 102 before the bit lines are formed. The first source / drain region 112 has first doped ions, the conduction type of the first doped ions is the same as that of the second doped ions, and the first source / drain region 112 extends from the bottom of the second surface 101b to the first surface 101a.

[0099] The method for forming the first source / drain region 112 includes: injecting first doped ions into the active region 102 at the bottom of the second recess 111, the first doped ions including N-type or P-type ions; and performing an annealing process on the first substrate 101.

[0100] The first source-drain region 112 and the second source-drain region 107 form a channel region of a device. The channel region is perpendicular to the surface of the first substrate 101, and is used to form a vertical channel device.

[0101] In this embodiment, the first doping ions are N-type ions, and are used to form an NMOS device. In other embodiments, the first doping ions are P-type ions, and are used to form a PMOS device.

[0102] Reference is made to Figures 21-23 , Figure 21 is a top view structural schematic diagram of Figure 22 and Figure 23 is a cross-sectional structural schematic diagram of Figure 22 is a cross-sectional structural schematic diagram of Figure 21 in the direction of MM' in Figure 23 is a cross-sectional structural schematic diagram of Figure 21 in the direction of NN' in

[0103] The bit line 113 includes an electrode layer (not shown in the figure).

[0104] The material of the bit line 113 includes a metal. In this embodiment, the metal is copper. In other embodiments, the metal can be aluminum, tungsten, etc.

[0105] The bit line 113 is in direct contact with the active region 102, and does not need to be prepared as a bit line contact. Therefore, the bit line does not need to be aligned with the bit line contact in the bit line preparation, which reduces the difficulty of process manufacturing, improves the process window of the bit line formation, and saves production costs.

[0106] In this embodiment, the position of the bit line 113 is defined by the isolation layer 103, and is formed by a self-alignment method. Therefore, the formation process of the bit line 113 does not need to use a photolithography process, which saves the use of a photomask and reduces the process manufacturing cost.

[0107] The formation method of the bit line 113 includes: depositing an electrode material layer (not shown in the figure) on the surface of the isolation layer 103 and in the second recess 111 from the second surface 101b; and planarizing the electrode material layer until the surface of the isolation layer 103 is exposed.

[0108] The bit line 113 further includes a barrier layer (not shown in the figure) between the electrode layer and the second recess 111. The barrier layer is used to block the diffusion of ions in the active region 102 into the electrode layer, which is beneficial to improve the stability of the device performance.

[0109] In this embodiment, after forming the second recess 111, before forming the bit line 113, the second recess 111 is further subjected to surface treatment to form a contact layer (not shown in the figure) on the surface of the second recess 111.

[0110] The forming process of the contact layer includes a self-aligned metal silicide process.

[0111] The material of the contact layer includes metal silicide. In this embodiment, the metal silicide is titanium silicide. The contact layer is used to reduce the contact resistance between the bit line 113 and the active region 102.

[0112] Correspondingly, an embodiment of the present application further provides a semiconductor structure formed by the above method, please continue to refer to Figures 21-23 , which comprises a first substrate 101, the first substrate 101 comprises adjacent first region I and second region II, the first substrate 101 has opposite first surface 101a and second surface 101b, the first region I comprises a plurality of mutually separated active regions 102, the adjacent active regions 102 have an isolation layer 103, the plurality of active regions 102 are arranged along a first direction X, and the plurality of active regions are parallel to a second direction Y, the first direction X and the second direction Y are perpendicular to each other, and the first surface 101a exposes the isolation layer 103; a plurality of first recesses 201 (as shown in Figure 3 ) located in the first region I, the first recesses 201 extend from the first surface 101a to the second surface 101b, the plurality of first recesses 201 are arranged along the second direction Y, and the first recesses 201 penetrate the plurality of active regions 102 along the first direction X, and the distance n from the bottom of the first recess 201 to the first surface 101a is less than the thickness m of the isolation layer 103; a plurality of openings (not shown in the figure) located in the second region II, the openings penetrate the first substrate 101, and the openings communicate with the first recesses 201; a word line gate structure located in the first recesses 201 and the openings, the word line gate structure comprises a word line 104 located in the first recess 201, and a word line contact 105 located in the opening; the second surface 101b exposes the isolation layer 103; a bit line 113 located on the second surface 101b, the bit line 113 is arranged along the first direction X, and the bit line 113 is parallel to the second direction Y, and one active region 102 is electrically interconnected with one bit line 113.

[0113] In this embodiment, the surface of the isolation layer 103 protrudes from the second surface 101b, and the second recess 111 (as shown in Figure 19 ) exposing the second surface 101b is formed between the isolation layers 103, the second recess 111 is parallel to the second direction Y and arranged along the first direction X; and the bit line 113 is located in the second recess 111.

[0114] In this embodiment, the semiconductor structure further comprises: a plurality of second source-drain regions 107 in each of the active regions 102, the second source-drain regions 107 extending from the first surface 101a to the second surface 101b.

[0115] The semiconductor structure further comprises: a plurality of capacitors 108 on the first surface 101a, each of the capacitors 108 being electrically interconnected with one of the second source-drain regions 107.

[0116] The semiconductor structure further comprises: a first source-drain region 112 in the active region 102, the first source-drain region 112 extending from the bottom of the second recess 111 to the first surface 101a.

[0117] Figures 24-26 is a structural schematic diagram of each step in the forming method of the semiconductor structure of another embodiment of the present application.

[0118] In this embodiment, another forming method of a bit line is provided, please continue to refer to Figures 15-17 , Figures 24-26 , Figure 24 is a top view structural schematic diagram of Figure 25 and Figure 26 , Figure 25 is a cross-sectional structural schematic diagram along the direction of MM' in Figure 24 , Figure 26 is a cross-sectional structural schematic diagram along the direction of NN' in Figure 24 , after the thinning process, a dielectric material layer (not labeled in the figure) is formed on the second surface 101b; a first patterned layer (not labeled in the figure) is formed on the surface of the dielectric material layer, the first patterned layer exposes the dielectric material layer on the active region 102; taking the first patterned layer as a mask, etching the dielectric material layer until the surface of the active region 102 and the word line contact 105 is exposed, forming a dielectric layer 401 and a second recess (not labeled in the figure) in the dielectric layer 401; forming a conductive layer in the second recess, taking the conductive layer in the second recess of the active region 102 as a bit line 402, and taking the conductive layer in the second recess exposing the surface of the word line contact 105 as a word line lead-out layer 403.

[0119] In one aspect, the word line lead-out layer 403 and the word line contact 105 are used to electrically connect the word line lead-out to the outside world, the word line lead-out layer 403 is formed in the same process as the bit line 402, and the word line contact 105 is formed in the same process as the word line 104, without the need for a separate process to lead out the word line, saving the production process and reducing production costs. In another aspect, the bit line 402 is in direct contact with the active area 102, without the need to prepare a bit line contact, so that the bit line does not need to be aligned with the bit line contact in the bit line preparation, reducing the difficulty of process manufacturing, improving the process window of the bit line formation, and saving production costs.

[0120] Before the bit line 402 is formed, a first source-drain region 404 is also formed in the active area 102, the first source-drain region 404 has first doping ions therein, and the first source-drain region 404 extends from the second surface 101b to the first surface 101a.

[0121] In this embodiment, the method for forming the first source-drain region 404 includes: before the dielectric material layer is formed, first doping ions are implanted into the active area 102 from the second surface 101b, the first doping ions include N-type or P-type ions.

[0122] The bit line 402 includes an electrode layer (not labeled in the figure).

[0123] The material of the bit line 402 includes metal. In this embodiment, the metal is copper. In other embodiments, the metal can be tungsten, aluminum, etc.

[0124] After the second recess is formed, before the bit line 402 is formed, the second recess is also subjected to surface treatment to form a contact layer (not labeled in the figure) on the surface of the second recess.

[0125] The formation process of the contact layer includes a self-aligned metal silicide process.

[0126] The material of the contact layer includes metal silicide. In this embodiment, the metal silicide is titanium silicide. The contact layer is used to reduce the contact resistance between the bit line 402 and the active area 102.

[0127] Correspondingly, another embodiment of the present application also provides a semiconductor structure formed by the above method, please continue to refer to Figures 24-26, including: a first substrate 101, the first substrate 101 including adjacent first region I and second region II, the first substrate 101 having opposite first face 101a and second face 101b, the first region I including a plurality of mutually separated active regions 102, the adjacent active regions 102 having isolation layer 103 therebetween, the plurality of active regions 102 being arranged along a first direction X, and the plurality of active regions being parallel to a second direction Y, the first direction X and the second direction Y being perpendicular to each other, the first face 101a exposing the isolation layer 103; a plurality of first recesses 201 (as shown in Figure 3 FIG. 1) located in the first region I, the first recesses 201 extending from the first face 101a to the second face 101b, the plurality of first recesses 201 being arranged along the second direction Y, and the first recesses 201 penetrating the plurality of active regions 102 along the first direction X, and the distance n from the bottom of the first recess 201 to the first face 101a being less than the thickness m of the isolation layer 103; a plurality of openings (not labeled in the figure) located in the second region II, the openings penetrating the first substrate 101, and the openings being in communication with the first recesses 201; a word line gate structure located in the first recesses 201 and the openings, the word line gate structure including word lines 104 located in the first recesses 201, and word line contacts 105 located in the openings; the second face 101b exposing the isolation layer 103; bit lines 402 located on the second face 101b, the bit lines 402 being arranged along the first direction X, and the bit lines 402 being parallel to the second direction Y, one active region 102 being electrically interconnected with one bit line 402.

[0128] In the embodiment, the semiconductor structure further includes: a dielectric layer 401 located on the second face 101b, the dielectric layer 401 having second recesses (not labeled in the figure) exposing surfaces of the active regions 102 and the word line contacts 105 located therein, the second recesses being parallel to the second direction Y and arranged along the first direction X; a conductive layer located in the second recesses, the conductive layer including the bit lines 402 located in the second recesses exposing the active regions, and word line lead-out layers 403 located in the second recesses exposing surfaces of the word line contacts 105.

[0129] In the embodiment, the semiconductor structure further includes: a plurality of second source / drain regions 107 located in each of the active regions 102, the second source / drain regions 107 extending from the first face 101a to the second face 101b.

[0130] The semiconductor structure further includes: a plurality of capacitors 108 located on the first face 101a, each of the capacitors 108 being electrically interconnected with one of the second source / drain regions 107.

[0131] The semiconductor structure further includes a first source / drain region 404 located within the active region 102, the first source / drain region 404 extending from the second face 101b to the first face 101a.

[0132] Although the present application has been disclosed with reference to the above embodiments, the above embodiments are not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The first substrate includes a first region and a second region adjacent to each other, the first substrate has opposite first and second surfaces, the first region includes a plurality of active regions separated from each other by isolation layers, the plurality of active regions are arranged along a first direction, and the plurality of active regions are parallel to a second direction, the first direction is perpendicular to the second direction, and the first surface exposes the isolation layers; a plurality of first recesses in the first region, the first recesses extend from the first surface to the second surface, the plurality of first recesses are arranged along the second direction, and the first recesses extend through the plurality of active regions along the first direction, and the distance from the bottom of the first recess to the first surface is less than the thickness of the isolation layers; a plurality of openings in the second region, the openings extend through the first substrate, and the openings are in communication with the first recesses; a word line gate structure in the first recesses and the openings, the word line gate structure includes word lines in the first recesses, and word line contacts in the openings; the second surface exposes the isolation layers; bit lines on the second surface, the bit lines are arranged along the first direction, and the bit lines are parallel to the second direction, one active region is electrically interconnected with one bit line. the isolation layers protrude from the second surface, the isolation layers have second recesses exposing the second surface therebetween, the second recesses are parallel to the second direction and arranged along the first direction; and the bit lines are in the second recesses.

2. The semiconductor structure of claim 1, wherein, Further comprising:

3. The semiconductor structure of claim 1, wherein, a dielectric layer on the second surface, the dielectric layer has second recesses exposing the surfaces of the active regions and the word line contacts, the second recesses are parallel to the second direction and arranged along the first direction; a conductive layer in the second recesses, the conductive layer includes the bit lines in the second recesses exposing the active regions, and word line lead layers in the second recesses exposing the surfaces of the word line contacts. Further comprising:

4. The semiconductor structure of claim 1, wherein, a plurality of second source / drain regions in each of the active regions, the second source / drain regions extend from the first surface to the second surface. Further comprising:

5. The semiconductor structure of claim 4, wherein, a plurality of capacitors on the first surface, each of the capacitors is electrically interconnected with one of the second source / drain regions. Further comprising:

6. The semiconductor structure of claim 1, wherein, a first source / drain region in the active region, the first source / drain region extends from the second surface to the first surface. The first substrate includes a first region and a second region adjacent to each other, the first substrate has opposite first and second surfaces, the first region includes a plurality of active regions separated from each other by isolation layers, the plurality of active regions are arranged along a first direction, and the plurality of active regions are parallel to a second direction, the first direction is perpendicular to the second direction, and the first surface exposes the isolation layers; 7. A method of forming a semiconductor structure, comprising: a plurality of first recesses in the first region, the first recesses extend from the first surface to the second surface, the plurality of first recesses are arranged along the second direction, and the first recesses extend through the plurality of active regions along the first direction, and the distance from the bottom of the first recess to the first surface is less than the thickness of the isolation layers; ​ ​ forming a plurality of openings in the second region, the openings extending from the first surface to the second surface, the openings having a bottom-to-first surface distance greater than the first recess bottom-to-first surface distance, and the openings being in communication with the first recesses; forming a word line gate structure in the first recesses and the openings, the word line gate structure including a word line in the first recesses and a word line contact in the openings; thinning the first substrate from the second surface until the isolation layer surface and the word line contact surface are exposed; after the thinning, forming bit lines in the second surface, the bit lines being arranged in a first direction and being parallel to a second direction, and one active region being electrically interconnected with one bit line.

8. The method of forming a semiconductor structure of claim 7, wherein, The method of forming the bit lines includes, after the thinning, etching the first substrate from the second surface to form second recesses between adjacent isolation layers; and forming the bit lines in the second recesses.

9. The method of forming a semiconductor structure of claim 8, wherein, After the second recesses are formed and before the bit lines are formed, the method further includes forming first source / drain regions in the active regions, the first source / drain regions having first dopant ions therein, and the first source / drain regions extending from the second surface to the first surface.

10. The method of forming a semiconductor structure of claim 9, wherein, The method of forming the first source / drain regions includes implanting first dopant ions into the active regions at the bottom of the second recesses, the first dopant ions including N-type or P-type ions; and annealing the substrate.

11. The method of forming a semiconductor structure of claim 8, wherein, The bit lines include an electrode layer, and the method of forming the bit lines includes depositing an electrode material layer from the second surface to the isolation layer surface and into the second recesses; and planarizing the electrode material layer until the isolation layer surface is exposed.

12. The method of forming a semiconductor structure of claim 11, wherein, The bit lines further include a barrier layer between the electrode layer and the second recesses.

13. The method of forming a semiconductor structure of claim 11, wherein, After the second recesses are formed and before the bit lines are formed, the method further includes surface treating the second recesses to form a contact layer on the surfaces of the second recesses.

14. The method of forming a semiconductor structure of claim 13, wherein, The material of the contact layer includes a metal silicide.

15. The method of forming a semiconductor structure of claim 9, wherein, After the word line gate structure is formed, the method further includes implanting second dopant ions into the active regions from the first surface, the second dopant ions including N-type or P-type ions, and the second dopant ions having a same conductivity type as the first dopant ions to form a plurality of second source / drain regions on each active region.

16. The method of forming a semiconductor structure of claim 15, wherein, After the second source / drain regions are formed and before the thinning, the method further includes forming a plurality of capacitors on the first surface, each of the capacitors being electrically interconnected with one of the second source / drain regions.

17. The method of forming a semiconductor structure of claim 16, wherein The word lines include first and second sidewalls opposite in the second direction; After the word line gate structure is formed and before the capacitors are formed, the method further includes forming an insulating trench between each active region and an adjacent first sidewall, the insulating trench extending from the first surface to the second surface and penetrating the active region in the first direction; forming an insulating layer in the insulating trench.

18. The method of forming a semiconductor structure of claim 16, wherein, After the first source / drain regions are formed and before the capacitors are formed, the method further includes forming a capacitor contact on the first surface, the capacitor being electrically interconnected with the first source / drain region through the capacitor contact.

19. The method of forming a semiconductor structure of claim 7, wherein, The material of the bit lines includes a metal.

20. The method of forming a semiconductor structure of claim 7, wherein, The method further includes: A second substrate is provided; after forming the isolation layer, before the thinning process, the first surface is made to face the second substrate, and the first substrate and the second substrate are bonded.

21. The method of forming a semiconductor structure of claim 7, wherein, The method for forming the bit line comprises: after the thinning process, forming a dielectric material layer on the second surface; forming a first patterning layer on the surface of the dielectric material layer, the first patterning layer exposing the dielectric material layer on the active region; taking the first patterning layer as a mask, etching the dielectric material layer until the active region and the word line contact surface are exposed, forming a dielectric layer and a second recess in the dielectric layer; forming a conductive layer in the second recess, the conductive layer in the second recess exposing the active region being a bit line, and the conductive layer in the second recess exposing the word line contact surface being a word line lead-out layer.

22. The method of forming a semiconductor structure of claim 7, wherein, The word line comprises a gate dielectric layer on the sidewall and bottom surface of the first recess, and a gate layer on the gate dielectric layer.

23. The method of forming a semiconductor structure of claim 22, wherein, The material of the gate layer comprises metal, and the material of the gate dielectric layer comprises oxide.

24. The method of forming a semiconductor structure of claim 7, wherein, The method for forming the first recess and the opening comprises: forming a second patterning layer on the first surface, the second patterning layer exposing part of the active region and part of the surface of the isolation layer; taking the second patterning layer as a mask, etching the first substrate.

25. The method of forming a semiconductor structure of claim 7, wherein, The forming process of the first recess and the opening comprises a dry etching process.

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