A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor, which is used for making the first ring gate transistor and the second ring gate transistor included in the semiconductor device both have good conductive performance. The semiconductor device comprises a substrate, a first ring gate transistor and a second ring gate transistor. Along the length direction of a first channel included in the first ring gate transistor, the first channel comprises a first channel region and second channel regions located on both sides of the first channel region. A first gate stack is arranged around the outer periphery of the first channel region. The first channel has a thickness of a part of each layer of nanosheets located in the second channel region greater than that of a part located in the first channel region. The first channel has a material different from that of a second channel included in the second ring gate transistor. Along the thickness direction of the substrate, any layer of nanosheets of the second channel is arranged in an alternate interval with the adjacent layer of nanosheets of the first channel. The manufacturing method provided by the application is used for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] The gate stack of a ring gate transistor is formed not only on the top and sidewall of the channel, but also on the bottom of the channel, so that the ring gate transistor has higher gate control ability and other advantages compared with planar transistors and fin field effect transistors.

[0003] However, in the case that the semiconductor device includes two types of ring gate transistors formed on the substrate, and the channel materials of the two types of ring gate transistors are different, it is difficult to make the two types of ring gate transistors obtained by the existing manufacturing method have good conductivity at the same time. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method thereof, which are used to reduce the integration difficulty of a first ring gate transistor and a second ring gate transistor while making the first ring gate transistor and the second ring gate transistor included in the semiconductor device have good conductivity in the case that the channel materials of the first ring gate transistor and the second ring gate transistor are different.

[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor device, which includes:

[0006] A substrate, the substrate having a first region and a second region.

[0007] A first ring gate transistor formed on the first region. The first ring gate transistor includes a first channel, a first gate stack, and a first gate sidewall. Along the length direction of the first channel, the first channel includes a first channel region and second channel regions located on both sides of the first channel region. The first gate stack surrounds the outer periphery of the first channel region. The first gate sidewall spans on the second channel regions. The first channel has a thickness of the portion of each layer of nanosheet located in the second channel region greater than the portion located in the first channel region.

[0008] And a second ring gate transistor formed on the second region. The first channel has a material different from that of a second channel included in the second ring gate transistor. Along the thickness direction of the substrate, any layer of nanosheet of the second channel is arranged alternately and spaced apart from the adjacent layer of nanosheet of the first channel.

[0009] Compared with the prior art, the semiconductor device provided by the application has the first channel of the first ring gate transistor and the second channel of the second ring gate transistor, and the at least one nanosheet of the first channel is different in material from the at least one nanosheet of the second channel, so that in the actual manufacturing process of the semiconductor device provided by the application, the first ring gate transistor and the second ring gate transistor can be manufactured by using the first semiconductor layer for manufacturing the first channel and the second semiconductor layer for manufacturing the second channel as the channel layer and the sacrificial layer.

[0010] In the case of the above, along the thickness direction of the substrate, the row where any layer of the nanosheet of the second channel is located is alternately and separately arranged with the row where the adjacent layer of the nanosheet of the first channel is located. In addition, the thickness of each layer of the nanosheet of the first channel located in the second channel region is greater than the thickness of the portion located in the first channel region. Based on this, for the second ring gate transistor, the thickness of the second semiconductor layer for manufacturing the second channel in the actual manufacturing process meets the manufacturing requirements, that is, the thickness of the second semiconductor layer is smaller than the thickness of the first semiconductor layer at this time, so as to inhibit the short channel effect of the second ring gate transistor. In addition, because the thickness of the first semiconductor layer as the sacrificial layer is large, the height of the gap released by removing the first semiconductor layer on the second region is large, so that the second gate stack included in the second ring gate transistor can be normally filled in the above gap, so that the second ring gate transistor has good conductive performance. For the first ring gate transistor, although the thickness of the second semiconductor layer as the sacrificial layer is small, so that the height of the gap released by removing the second semiconductor layer on the first region is small, the height of the gap can be increased by thinning the first semiconductor layer on the first region, so as to facilitate the filling of the first gate stack, and reduce the integration difficulty of the above first ring gate transistor and second ring gate transistor. At the same time, after the remaining part of the first semiconductor layer on the first region forms the nanosheet included in the first channel, the thickness of each layer of the nanosheet of the first channel located in the first channel region is smaller than the thickness of the portion located in the second channel region, and the first gate stack is wrapped around the outer periphery of the first channel region, so that the short channel effect of the first ring gate transistor can be inhibited, and the first ring gate transistor also has good conductive performance.

[0011] The application further provides a semiconductor device manufacturing method, which comprises the following steps:

[0012] A substrate is provided, and the substrate has a first region and a second region.

[0013] The first ring gate transistor is formed on the first region, and the second ring gate transistor is formed on the second region. The first ring gate transistor comprises a first channel, a first gate stack and a first gate sidewall. Along the length direction of the first channel, the first channel comprises a first channel region and second channel regions located on both sides of the first channel region. The first gate stack is wrapped around the outer periphery of the first channel region. The first gate sidewall is transversely arranged on the second channel region. The first channel has a thickness of the portion where each layer of nanosheet is located in the second channel region greater than the portion where each layer of nanosheet is located in the first channel region. The material of the first channel is different from the material of the second channel comprised by the second ring gate transistor. Along the thickness direction of the substrate, any row of nanosheet of the second channel is alternately arranged with the adjacent row of nanosheet of the first channel.

[0014] Compared with the prior art, the semiconductor device manufacturing method provided by the present application has the same beneficial effects as the semiconductor device provided by the present application, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and are included to further explain the present application and its preferred embodiments and no limitation of the present application is intended to be represented thereby. In the drawings:

[0016] Figure 1 Fig. 1 and Fig. 2 are schematic diagrams of the first and second structures after forming the film layer for manufacturing the first semiconductor material layer and the second semiconductor material layer on the substrate in the embodiment of the present application;

[0017] Figure 2 Fig. 3 and Fig. 4 are schematic diagrams of the third and fourth structures after forming the film layer for manufacturing the first semiconductor material layer and the second semiconductor material layer on the substrate in the embodiment of the present application;

[0018] Figure 3 Fig. 5 is a schematic diagram of the structure after forming the strain buffer layer on the semiconductor substrate in the embodiment of the present application;

[0019] Figure 4 Fig. 6 is a schematic diagram of the structure after forming the first fin structure and the second fin structure in the embodiment of the present application;

[0020] Figure 5 Fig. 7 is a schematic diagram of the structure after forming the shallow trench isolation in the embodiment of the present application;

[0021] Figure 6 Fig. 8 is a schematic diagram of the structure after forming the first sacrificial gate, the first gate sidewall, the second sacrificial gate and the second gate sidewall in the embodiment of the present application;

[0022] Figure 7Fig. 1 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after forming a first sacrificial gate and a first gate sidewall in the embodiment of the present application;

[0023] Figure 8 Fig. 2 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after removing at least part of the first fin portion and the second fin portion in the source formation region and the drain formation region in the embodiment of the present application;

[0024] Figure 9 Fig. 3 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after selectively etching the two side edge regions of the second semiconductor material layer included in the first fin portion in the embodiment of the present application;

[0025] Figure 10 Fig. 4 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after forming a first inner sidewall under the mask action of the covering layer in the embodiment of the present application;

[0026] Figure 11 Fig. 5 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after selectively etching the two side edge regions of the first semiconductor material layer included in the second fin portion in the embodiment of the present application;

[0027] Figure 12 Fig. 6 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after forming a second inner sidewall under the mask action of the covering layer in the embodiment of the present application;

[0028] Figure 13 Fig. 7 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after forming a first source region and a first drain region under the mask action of the covering layer in the embodiment of the present application;

[0029] Figure 14 Fig. 8 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first fin portion and the second fin portion in the direction of B-B' after forming a second inner sidewall in the case of forming the first source region and the first drain region in the embodiment of the present application;

[0030] Figure 15 Fig. 9 is a schematic structural sectional view of a semiconductor device according to an embodiment of the present application, wherein the (1) and (2) parts are respectively schematic structural sectional views of the structure at the first channel formation portion and the second channel formation portion in the direction of B-B' after forming a first source region, a first drain region, a second source region and a second drain region in the embodiment of the present application;

[0031] Figure 16 Fig. 1 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0032] Figure 17 Fig. 2 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0033] Figure 18 Fig. 3 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0034] Figure 19 Fig. 4 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0035] Figure 20 Fig. 5 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0036] Figure 21 Fig. 6 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0037] Figure 22 Fig. 7 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0038] Figure 23 Fig. 8 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0039] Figure 24 Fig. 9 is a structural cross-sectional view along the B-B' direction of the semiconductor device according to the present application;

[0040] Figure 25 FIGS. 1 and 2 are schematic structural cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, taken along the B-B' direction at the first and second ring gate transistors, respectively, before the first semiconductor layer is removed from the second region;

[0041] Figure 26 FIGS. 3 and 4 are schematic structural cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, taken along the B-B' direction at the first and second channel formation portions, respectively, after the first semiconductor layer is removed from the second region;

[0042] Figure 27 FIGS. 5 and 6 are schematic structural cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, taken along the B-B' direction at the second channel formation portion, respectively, after the first semiconductor layer is removed from the second region and part of the release layer is removed;

[0043] Figure 28 FIGS. 7 and 8 are schematic structural cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, taken along the B-B' direction at the first and second channel formation portions, respectively, after the second ring gate transistor is formed;

[0044] Figure 29 FIGS. 9 and 10 are schematic structural cross-sectional views of a semiconductor device according to an embodiment of the present disclosure, taken along the B-B' direction at the second channel formation portion, respectively, after the second ring gate transistor is formed;

[0045] Figure 30 FIG. 11 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that the following description is merely exemplary and is not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0047] In the drawings, various schematic structural views according to embodiments of the present disclosure are shown. These drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0048] In the context of the present disclosure, when one layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element. In addition, if one layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0049] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0050] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0051] The gate stack included in the ring gate transistor is not only formed on the top and sidewall of the channel, but also formed on the bottom of the channel, so that the ring gate transistor has higher gate control ability and other advantages compared with planar transistors and fin field effect transistors. Based on this, when the NMOS transistor and the PMOS transistor included in the CMOS device both adopt the ring gate transistor, the working performance of the CMOS device can be improved.

[0052] In the case that the channel included in the ring gate transistor has at least one nanosheet layer, the crystal orientation of the channel included in the ring gate transistor is usually a

[100] crystal orientation. At this time, the channel included in the ring gate transistor is conducive to the transmission of electrons but not conducive to the transmission of holes. Based on this, because the channel carriers of the NMOS transistor are electrons and the channel carriers of the PMOS transistor are holes, in the case that the ring gate transistor including the

[100] crystal orientation channel is applied to the above-mentioned CMOS device, the above-mentioned ring gate transistor is only conducive to improving the electron mobility of the NMOS transistor but not conducive to the hole mobility of the PMOS transistor, thereby causing the working performance of the CMOS device to which the ring gate transistor is applied to be poor. On the basis of the above, because high-mobility channel materials such as germanium silicon have higher carrier mobility, in the case that the channel included in the PMOS transistor has at least one nanosheet layer, the channel included in the PMOS transistor can be made of high-mobility channel materials such as germanium silicon to improve the hole mobility of the PMOS transistor. Based on this, even if the device structures of the NMOS transistor and the PMOS transistor included in the CMOS device are both the above-mentioned ring gate transistor, the channel carrier mobility of the NMOS transistor is better than that of the PMOS transistor, and the difference between the corresponding carrier mobilities of the two can be reduced by the way of manufacturing the channel of the PMOS transistor by using the above-mentioned high-mobility channel material, so that both types of transistors have good conductive performance at the same time.

[0053] However, in the actual manufacturing process, when the above-mentioned CMOS device is manufactured by the way that the channel material of the NMOS transistor and the channel material of the PMOS transistor are mutually channel layers and sacrificial layers, the channel of one of the NMOS transistor and the PMOS transistor will be thicker, and the gate stack of the transistor with the thicker channel will be difficult to fill in the area between adjacent nanosheets and the area between the nanosheet and the substrate. Specifically, it can be understood that, as Figure 25As shown in the middle (2) part, the gate stack included in the ring gate transistor has a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The channel included in the ring gate transistor has each layer of nanosheet surrounded by a corresponding layer of gate dielectric layer, and thus the height of the gap between adjacent nanosheets needs to be greater than or equal to the sum of the thickness of the two layers of gate dielectric layer and the thickness of the gate electrode. Based on this, when the ring gate transistor is prepared, the thickness of the sacrificial layer for forming the above-mentioned gap is relatively large. However, in order to suppress the short channel effect, the thickness of the channel of the ring gate transistor is usually small, and thus when the same ring gate transistor is prepared, in order to simultaneously satisfy the suppression of the short channel effect and the normal filling of the gate stack, the thickness of the channel layer needs to be smaller than the thickness of the above-mentioned sacrificial layer. Based on the above, in the case of manufacturing the above-mentioned CMOS device by taking the channel material of the NMOS transistor and the channel material of the PMOS transistor as the channel layer and the sacrificial layer, for the above-mentioned NMOS transistor, the thickness of the channel material layer of the NMOS transistor needs to be small, and the thickness of the channel material layer of the PMOS transistor used as the sacrificial layer needs to be large, so as to simultaneously satisfy the suppression of the short channel effect of the NMOS transistor and the normal filling of the gate stack included in the NMOS transistor in the corresponding gap. However, at this time, for the PMOS transistor, because the thickness of the channel material layer of the PMOS transistor is large, it is difficult to suppress the short channel effect of the PMOS transistor. Moreover, because the thickness of the channel material layer of the NMOS transistor used as the sacrificial layer is small, the height of the gap between adjacent nanosheets and the gap between the nanosheet and the substrate of the PMOS transistor is small, which cannot satisfy the normal filling of the gate stack included in the PMOS transistor, thereby resulting in poor conductivity of the PMOS transistor. Conversely, if the manufacturing requirements of the PMOS transistor are met, the above-mentioned problems will occur in the NMOS transistor.

[0054] In summary, when the device structures of the above-mentioned NMOS transistor and PMOS transistor are both ring gate transistors, and the channels included in the two types of ring gate transistors both have at least one layer of nanosheet, it is difficult to simultaneously obtain the NMOS transistor and the PMOS transistor with good conductivity by using the existing manufacturing method. Moreover, it can be understood that as long as the materials of the channels included in the two types of ring gate transistors are different, and the two types of ring gate transistors are manufactured by taking the channel material of one type of ring gate transistor as the channel layer and the channel material of the other type of ring gate transistor as the sacrificial layer during the manufacturing process, the above-mentioned technical problems will occur.

[0055] To solve the above technical problems, the embodiment of the present application provides a semiconductor device and a manufacturing method thereof. In the semiconductor device provided by the embodiment of the present application, along the thickness direction of the substrate, any layer of nanosheet of the second channel is arranged alternately with the adjacent layer of nanosheet of the first channel. And, the thickness of the part of each layer of nanosheet of the first channel located in the second channel region is greater than the part located in the first channel region, so that in the case that the material of the first channel is different from the material of the second channel, the integration difficulty of the first ring gate transistor and the second ring gate transistor is reduced, and the first ring gate transistor and the second ring gate transistor included in the semiconductor device both have good conductive performance.

[0056] As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), Figure 25 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), Figure 28 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), and Figure 29 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), the embodiment of the present application provides a semiconductor device, which comprises a substrate, a first ring gate transistor and a second ring gate transistor.

[0057] As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), Figure 25 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), Figure 28 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), and Figure 29 As shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), the above-mentioned substrate has a first region 12 and a second region 13. The above-mentioned first ring gate transistor is formed on the first region 12. The first ring gate transistor comprises a first channel 37, a first gate stack 39 and a first gate sidewall 23. Along the length direction of the first channel 37 (the direction is parallel to B-B’ direction), the first channel 37 comprises a first channel region 371 and a second channel region 372 located on both sides of the first channel region 371. The first gate stack 39 is wrapped around the outer periphery of the first channel region 371. The first gate sidewall 23 is transversely arranged on the second channel region 372. The thickness of the part of each layer of nanosheet of the first channel 37 located in the second channel region 372 is greater than the part located in the first channel region 371. The above-mentioned second ring gate transistor is formed on the second region 13. The material of the first channel 37 is different from the material of the second channel 38 included in the second ring gate transistor. Along the thickness direction of the substrate 11, any layer of nanosheet of the second channel 38 is arranged alternately with the adjacent layer of nanosheet of the first channel 37.

[0058] Specifically, as shown in the sectional view of FIG. 1 (1) and FIG. 1 (2), Figure 1 and Figure 2As shown in sections (1) and (2), the substrate 11 can be any semiconductor substrate, such as a silicon substrate, a germanium-silicon substrate, or a germanium substrate, without any other structures formed thereon. Alternatively, the substrate can also be a semiconductor substrate with some structures formed thereon. For example, the substrate may include a semiconductor substrate and a strain buffer structure formed on the semiconductor substrate. The strain buffer structure is located at least between the first channel and the semiconductor substrate or at least between the second channel and the semiconductor substrate. The material of the strain buffer structure can be germanium-silicon (the germanium content can be 10% to 60%) or similar materials. In this case, such as Figure 3 As shown, in the process of manufacturing the semiconductor device provided in this embodiment of the invention, a strain buffer layer 14 for manufacturing a strain buffer structure can be first formed on a semiconductor substrate 111, and corresponding semiconductor material layers for manufacturing a first channel and a second channel can be alternately formed on the strain buffer layer 14. This strain buffer layer can provide stress to the semiconductor material layers to generate strain in the first and second channels formed by the semiconductor material layers, thereby improving the carrier mobility of the first and second channels and further improving the conductivity of the semiconductor device. Then, during the manufacturing process of the semiconductor device, in steps such as forming the first fin structure, the second fin structure, the first source region, and the first drain region, the remaining portion of the strain buffer layer after selective etching or other operations forms the strain buffer structure. Wherein, if the thickness of the strain buffer layer is small and the first semiconductor layer for manufacturing the first channel is the lowest layer in the first channel formation portion, the strain buffer structure can be located only between the second channel and the semiconductor substrate. When the strain buffer layer is thin and the second semiconductor layer forming the second channel is the lowest film layer in the second channel formation, the strain buffer structure can be located only between the first channel and the semiconductor substrate. When the strain buffer layer is thick, the strain buffer structure can include a first strain buffer portion covering the semiconductor substrate, and a second strain buffer portion formed between the first channel and the second channel and the first strain buffer portion, and in a fin-like shape.

[0059] Regarding the aforementioned first gate-ring transistor, in terms of conductivity type, it can be either an N-type or a P-type gate-ring transistor. Structurally, the first gate-ring transistor further includes a first source region and a first drain region. A first channel is located between the first source region and the first drain region. The first channel region is in contact with the first source region and the first drain region through a second channel region. Furthermore, as... Figure 25As shown in section (1), because the thickness of each nanosheet in the first channel 37 located in the second channel region 372 is greater than that located in the first channel region 371, the contact area between the first channel 37 and the first source region 28 and the first drain region 29 is larger. This helps to reduce the contact resistance and series resistance between the first channel 37 and the first source region 28 and the first drain region 29, thereby improving the conductivity of the first ring gate transistor. The materials of the first source region 28, the first drain region 29, and the first channel 37 can be silicon, germanium silicon, germanium, group III-V semiconductor materials, etc.

[0060] The first ring gate transistor includes a first channel with nanosheets that can be one layer or multiple layers. The specific number of nanosheet layers in the first channel can be set according to the actual application scenario and is not specifically limited here. Each nanosheet layer in the first channel has a gap between itself and the substrate. When the first channel has at least two nanosheet layers, there is also a gap between adjacent nanosheet layers. Specifically, since the thickness of each nanosheet layer in the first channel region is less than the thickness in the second channel region, and in the actual manufacturing process, if the channel materials of the first ring gate transistor and the second ring gate transistor serve as channel layers and sacrificial layers respectively, the gaps between adjacent first channel layers and between the bottom first channel layer and the substrate can be set with reference to the specifications of the first gate stack. The gaps between adjacent second channel layers and between the bottom second channel layer and the substrate can be set according to the thickness of the nanosheets in the second channel and are not specifically limited here.

[0061] like Figure 25 As shown in section (1), the first gate stack 39 of the first ring gate transistor may include a first gate dielectric layer 391 and a first gate 392 located on the first gate dielectric layer 391. The first gate dielectric layer 391 surrounds the outer periphery of each nanosheet included in the first channel 37. Alternatively, the first gate dielectric layer 391 may also be formed on a portion of the substrate exposed in the first gate formation region. The first gate formation region is the region corresponding to the first gate stack 39. The material of the first gate dielectric layer 391 may be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the first gate 392 may be a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0062] like Figure 6 and Figure 25As shown in the middle (1) part, the first gate sidewall 23 included in the first ring gate transistor can be formed only on both sides of the first gate stack 39 along the length direction (the direction parallel to B-B'). Alternatively, the first gate sidewall can be wrapped on the sidewall of the first gate stack. The material of the first gate sidewall can be an insulating material such as silicon oxide or silicon nitride.

[0063] As for the second ring gate transistor, the conductive type of the second ring gate transistor can be the same as or different from the conductive type of the first ring gate transistor. For example, in the case where the first ring gate transistor is a P-type ring gate transistor, the second ring gate transistor can also be a P-type ring gate transistor, or the second ring gate transistor can also be an N-type ring gate transistor. For another example, in the case where the first ring gate transistor is an N-type ring gate transistor, the second ring gate transistor can also be an N-type ring gate transistor, or the second ring gate transistor can also be a P-type ring gate transistor. The second ring gate transistor also includes a second source region, a second drain region, and a second gate stack from the structural aspect. The second channel is formed between and respectively with the second source region and the second drain region. The materials of the second source region, the second drain region, and the second channel can be set by referring to the materials of the first source region, the first drain region, and the first channel described above. Specifically, the materials of the second source region and the second drain region can be the same as or different from the materials of the first source region and the first drain region, respectively. The material of the second channel can be any one of the semiconductor materials different from the material of the first channel. For example, the material of the first channel can be Si 1-x Ge x , and the material of the second channel can be Si 1-y Ge y . In the above case, if a Ge-based material is used to prepare an NMOS transistor, the NMOS transistor will have problems such as poor interface state, low N-type impurity solid concentration, and fast diffusion, so a semiconductor material such as germanium silicon with a lower Ge content is generally used to manufacture the conductive channel of the NMOS transistor. Using germanium silicon or germanium to manufacture the conductive channel of the PMOS transistor can improve the carrier mobility of the conductive channel of the PMOS transistor. Based on this, if the first ring gate transistor is an NMOS transistor and the second ring gate transistor is a PMOS transistor, 0≤x≤0.8, 0.2≤y≤1, and y-x≥0.2. Moreover, if the first ring gate transistor is a PMOS transistor and the second ring gate transistor is an NMOS transistor, 0.2≤x≤1, 0.2≤y≤0.8, and x-y≥0.2, so as to improve the hole mobility of the PMOS transistor and further reduce the difference between the carrier mobilities of the two types of ring gate transistors and improve the conductive performance of the semiconductor device in the case where the conductive types of the first ring gate transistor and the second ring gate transistor are opposite.

[0064] The specific difference of the Ge content in the channel of the PMOS transistor and the NMOS transistor can be set according to the application scenario, and is not specifically limited here. It can be understood that, within a certain range, the greater the difference of the Ge content in the channel of the two types of ring-gate transistors, the more conducive to reducing the difference in carrier mobility of the two types of ring-gate transistors.

[0065] As for the second gate stack and the second gate sidewall included in the second ring-gate transistor. The second gate sidewall can be formed only on both sides of the second gate stack along the length direction, or the second gate sidewall can be wrapped around the sidewall of the second gate stack. The second gate sidewall spans the two side edge regions of the second channel along the length direction. The second gate stack surrounds the outer periphery of the second channel. Wherein, as shown in the (2) part of FIG. 1 and FIG. 2, and the (1) and (2) parts of FIG. 3 and FIG. 4, the second gate stack 40 includes a second gate dielectric layer 401 and a second gate electrode 402 formed on the second gate dielectric layer 401. The second gate dielectric layer 401 can be formed only on the outer periphery of the second channel, and can also be formed on the part of the substrate exposed in the second gate formation region. The second gate formation region corresponds to the region where the second gate stack 40 is located. The materials of the second gate stack 40 and the second gate sidewall 25 can refer to the materials of the first gate stack and the first gate sidewall described above, respectively. Figure 25 and Figure 28 As shown in the (2) part of FIG. 1 and FIG. 2, and the (1) and (2) parts of FIG. 3 and FIG. 4, the second gate stack 40 includes a second gate dielectric layer 401 and a second gate electrode 402 formed on the second gate dielectric layer 401. The second gate dielectric layer 401 can be formed only on the outer periphery of the second channel, and can also be formed on the part of the substrate exposed in the second gate formation region. The second gate formation region corresponds to the region where the second gate stack 40 is located. The materials of the second gate stack 40 and the second gate sidewall 25 can refer to the materials of the first gate stack and the first gate sidewall described above, respectively. Figure 29

[0066] It should be noted that the number of nanosheets possessed by the first channel can be equal to the number of nanosheets possessed by the second channel, or can not be equal. Wherein, as described above, in the actual manufacturing process, if the channel materials of the first ring-gate transistor and the second ring-gate transistor are mutually channel layers and sacrificial layers, as shown in the (2) part of FIG. 1 and FIG. 2, and the (1) and (2) parts of FIG. 3 and FIG. 4, the number of nanosheets possessed by the first channel and the second channel can be equal. Figure 1 and Figure 2 As shown in the (2) part of FIG. 1 and FIG. 2, and the (1) and (2) parts of FIG. 3 and FIG. 4, the second gate stack 40 includes a second gate dielectric layer 401 and a second gate electrode 402 formed on the second gate dielectric layer 401. The second gate dielectric layer 401 can be formed only on the outer periphery of the second channel, and can also be formed on the part of the substrate exposed in the second gate formation region. The second gate formation region corresponds to the region where the second gate stack 40 is located. The materials of the second gate stack 40 and the second gate sidewall 25 can refer to the materials of the first gate stack and the first gate sidewall described above, respectively. Figure 25 Figure 1 As shown in the (2) part of FIG. 1 and FIG. 2, and the (1) and (2) parts of FIG. 3 and FIG. 4, the second gate stack 40 includes a second gate dielectric layer 401 and a second gate electrode 402 formed on the second gate dielectric layer 401. The second gate dielectric layer 401 can be formed only on the outer periphery of the second channel, and can also be formed on the part of the substrate exposed in the second gate formation region. The second gate formation region corresponds to the region where the second gate stack 40 is located. The materials of the second gate stack 40 and the second gate sidewall 25 can refer to the materials of the first gate stack and the first gate sidewall described above, respectively. Figure 2

[0067] ​​​In addition, as described above, in actual application, the first ring gate transistor and the second ring gate transistor can be manufactured by using the first semiconductor layer for manufacturing the first channel and the second semiconductor layer for manufacturing the second channel as the channel layer and the sacrifice layer. And the first gate stack can be filled by thinning the first semiconductor layer on the first region. In this case, after the thinning process, the thickness difference between the part of the nanosheet of the first channel in the first channel region and the nanosheet of the second channel can be set according to the thickness of the nanosheet of the second channel and the thickness of the first gate stack in the actual application scenario. For example, the thickness difference between the part of the nanosheet of the first channel in the first channel region and the nanosheet of the second channel can be less than or equal to a preset threshold. The preset threshold can be set according to the critical dimension of the semiconductor device, the thickness of the nanosheet of the second channel, and the thickness of the first gate stack. For example, the preset threshold can be 0-5 nm.

[0068] In addition, as Figures 1 to 29 indicated, in actual application, the first ring gate transistor and the second ring gate transistor can be manufactured by using the first semiconductor layer 35 for manufacturing the first channel 37 and the second semiconductor layer 36 for manufacturing the second channel 38 as the channel layer and the sacrifice layer. Based on this, the top of the part of the substrate 11 under the first channel region 371 is not in the same plane as the top of the part of the substrate 11 under the second channel 38. Specifically, as shown in part (1) of Figure 21 if the film layer at the bottom layer in the first channel forming part and the second channel forming part is the first semiconductor layer 35, the part of the release layer corresponding to the first gate forming area needs to be removed at the same time as the second semiconductor layer on the first region 12 is removed, so as to release the bottom layer first semiconductor layer 35 on the first region 12. At this time, since the release layer is a film layer formed by etching the substrate, the top of the part of the substrate under the first channel region is lower than the top of the part of the substrate under the second channel. As shown in Figure 27 if the film layer at the bottom layer in the first channel forming part and the second channel forming part is the second semiconductor layer, the part of the release layer corresponding to the second gate forming area needs to be removed at the same time as the first semiconductor layer on the second region 13 is removed, so as to release the bottom layer second semiconductor layer on the second region 13. At this time, the top of the part of the substrate under the first channel region is higher than the top of the part of the substrate under the second channel 38.

[0069] Further, the material and / or thickness of the first gate stack and the second gate stack can be the same or different. When the material and / or thickness of the first gate stack and the second gate stack are different, the first ring gate transistor and the second ring gate transistor have different absolute values of threshold voltage, which provides more and more flexible integration solutions for multi-threshold integration.

[0070] From the above, in the semiconductor device provided by the embodiments of the present application, the first channel of the first ring gate transistor has at least one layer of nanosheet with a material different from that of at least one layer of nanosheet of the second channel of the second ring gate transistor. Therefore, in the process of manufacturing the semiconductor device provided by the embodiments of the present application, the first ring gate transistor and the second ring gate transistor can be manufactured by using the first semiconductor layer for manufacturing the first channel and the second semiconductor layer for manufacturing the second channel as the channel layer and the sacrificial layer.

[0071] In the case of the above, Figure 25 in the (1) and (2) parts, Figure 28 in the (2) part, and Figure 29As shown, along the thickness direction of the substrate, the rows containing any nanosheet layer of the second channel 38 are alternately spaced with the rows containing adjacent nanosheet layers of the first channel 37. Furthermore, the portion of each nanosheet layer of the first channel 37 located in the second channel region 372 is thicker than the portion located in the first channel region 371. Based on this, for the second ring gate transistor, the thickness of the second semiconductor layer used to manufacture the second channel 38 during actual manufacturing meets the manufacturing requirements; that is, the thickness of the second semiconductor layer is relatively small to suppress the short-channel effect of the second ring gate transistor. Moreover, because the thickness of the first semiconductor layer, which serves as a sacrificial layer, is relatively large, the gap height released by removing the first semiconductor layer on the second region 13 is relatively large. Therefore, the second gate stack 40 included in the second ring gate transistor can normally fill the aforementioned gap, resulting in good conductivity of the second ring gate transistor. For the first ring-gate transistor, although the thickness of the second semiconductor layer, which serves as a sacrificial layer, is relatively small, resulting in a small gap height released by removing the second semiconductor layer on the first region 12, the gap height can be increased by thinning the first semiconductor layer on the first region 12. This facilitates the filling of the first gate stack 39 and reduces the integration difficulty of the first and second ring-gate transistors. Simultaneously, by thinning the first semiconductor layer on the first region 12, so that the remaining portion of the first semiconductor layer forms the nanosheets included in the first channel 37, the portion of each nanosheet in the first channel 37 located within the first channel region 371 is thinner than the portion located within the second channel region 372. Since the first gate stack 39 surrounds the outer periphery of the first channel region 371, the short-channel effect of the first ring-gate transistor can be suppressed, giving the first ring-gate transistor good conductivity.

[0072] In one example, such as Figure 25 As shown in (1), the first gate-ring transistor may further include a first inner sidewall 26. The first inner sidewall 26 is located between the first gate stack 39 and the first source region 28 included in the first gate-ring transistor, and between the first gate stack 39 and the first drain region 29 included in the first gate-ring transistor. In this case, the first inner sidewall 26 and the first gate sidewall 23 can separate the first gate stack 39 from the first source region 28 and the first drain region 29, respectively, facilitating the formation of the first gate stack 39. Furthermore, during the manufacturing process, such as Figure 20 and Figure 21As shown in part (1), the first inner wall 26 can also isolate the second semiconductor layer 36 on the first region 12 from the first source region 28 and the first drain region 29 respectively, so as to prevent the etchant removed from the second semiconductor layer 36 on the first region 12 from affecting the first source region 28 and the first drain region 29 when the material of the second semiconductor layer 36 is the same as or similar to the material of the first source region 28 and the first drain region 29. While improving the formation quality of the first source region 28 and the first drain region 29, it is also beneficial to control the length of the first gate stack formed subsequently, and further improve the conductivity of the first ring gate transistor.

[0073] Specifically, the width of the first inner wall (the width direction of the first inner wall is parallel to the length direction of the first channel) can be set according to the length requirements of the first channel and the length of the first grid stack in the actual application scenario, and is not specifically limited here. The material of the first inner wall can be an insulating material such as silicon oxide or silicon nitride.

[0074] It should be noted that when the materials of the first source region and the first drain region of the first ring gate transistor have a certain etching selectivity ratio with the material of the second semiconductor layer, the first ring gate transistor may not include the first inner sidewall, and the length of the first gate stack can also be controlled.

[0075] In one example, such as Figure 25 As shown in section (2), the second ring gate transistor may further include a second inner sidewall 27. The second inner sidewall 27 is located between the second gate stack 40 and the second source region 30 included in the second ring gate transistor, and between the second gate stack 40 and the second drain region 31 included in the second ring gate transistor.

[0076] Specifically, the beneficial effects and materials of the second inner wall can be referenced from those of the first inner wall described above, and will not be repeated here. The width of the second inner wall can be set according to the length of the second channel and the length requirements of the second grid stack in the actual application scenario, and is not specifically limited here.

[0077] It should be noted that when the materials of the second source region and the second drain region included in the second ring gate transistor have a certain etching selectivity ratio with the material located in the first semiconductor layer, the second ring gate transistor may not include the second inner sidewall, and the length of the second gate stack can also be controlled.

[0078] For example, such as Figure 25 As shown in sections (1) and (2), when the first ring gate transistor further includes a first inner sidewall 26 and the second ring gate transistor further includes a second inner sidewall 27, the thickness of the second inner sidewall 27 is greater than the thickness of the first inner sidewall 26. In this case, as Figures 1 to 29As shown, in actual application process, the manufacturing of the first ring gate transistor and the second ring gate transistor is realized by the way that the first semiconductor layer 35 for manufacturing the first channel 37 and the second semiconductor layer 36 for manufacturing the second channel 38 are channel layer and sacrifice layer to each other. Based on this, as shown in part (1) of Figure 18 and Figure 20 , for the first ring gate transistor, the second semiconductor layer 36 on the first region 12 is the sacrifice layer, so the first inner side wall 26 formed on both sides of the remaining part of the second semiconductor layer 36 on the first region 12 during manufacturing has a thickness equal to the thickness of the second semiconductor layer 36. As shown in part (2) of Figure 18 and Figure 20 , for the second ring gate transistor, the first semiconductor layer 35 on the second region 13 is the sacrifice layer, so the first inner side wall 26 formed on both sides of the remaining part of the first semiconductor layer 35 on the second region 13 during manufacturing has a thickness equal to the thickness of the first semiconductor layer 35. And the thickness of the first semiconductor layer 35 is greater than the thickness of the second semiconductor layer 36, so the thickness of the second inner side wall 27 is greater than the thickness of the first inner side wall 26.

[0079] In an example, in the case that the material of the first channel contains germanium, the first ring gate transistor can further include a first interface layer. The first interface layer at least surrounds the outer periphery of the first channel region. The first gate stack is formed on the first interface layer. Specifically, the first channel made of semiconductor material containing germanium is prone to form a germanium monoxide layer on its surface, thereby increasing the dangling bonds of the interface, so that the interface state of the first channel is high. Based on this, forming the first interface layer at least on the outer periphery of the first channel region can improve the interface state of the first channel, further improve the carrier mobility of the first channel, and thus improve the conductive performance of the first ring gate transistor. The material and thickness of the first interface layer can be set according to actual application scenarios. For example, the material of the first interface layer can be silicon, etc. The thickness of the first interface layer can be 0.5 nm to 1.5 nm. In addition, when the thickness difference between the part of the nanosheet of the first channel located between the first channel region and the second channel region is less than or equal to the thickness of the first interface layer, the first interface layer can only surround the outer periphery of the first channel region. At this time, the part of the first interface layer close to the second channel region can cover the second channel region exposed to the sidewall of the first gate formation region. When the thickness difference between the part of the nanosheet of the first channel located between the first channel region and the second channel region is greater than the thickness of the first interface layer, the first interface layer surrounds the outer periphery of the first channel region and the sidewall of the second channel region exposed to the first gate formation region.

[0080] In one example, when the material of the second channel contains germanium, the second ring gate transistor can further include a second interface layer. The second interface layer surrounds the outer periphery of the second channel, and the second gate stack included in the second ring gate transistor is formed on the second interface layer.

[0081] Specifically, the material and thickness of the second interface layer, and the beneficial effects of the second interface layer can refer to the material and thickness of the first interface layer described above, and the beneficial effects of the first interface layer, which will not be repeated here.

[0082] In some cases, as shown in parts (1) and (2) of Figure 5 , and Figure 25 , the semiconductor device further includes a shallow trench isolation 17 and a dielectric layer 32. The shallow trench isolation 17 is used to isolate different active regions on the substrate 11. The thickness of the shallow trench isolation 17 can be set according to actual conditions. The material of the shallow trench isolation 17 can be SiN, Si3N4, SiO2 or SiCO, etc. The dielectric layer 32 covers the substrate 11, and the top of the dielectric layer 32 is flush with the top of the first gate stack 39 and the second gate stack 40. In actual manufacturing process, the dielectric layer 32 can protect the first source region 28, the first drain region 29, the second source region 30 and the second drain region 31 from subsequent operations such as removing the second semiconductor layer on the first region 12 and the first semiconductor layer on the second region 13, thereby improving the yield of the semiconductor device. The material of the dielectric layer 32 can be silicon oxide or silicon nitride, etc.

[0083] As shown in Figure 30 , the present application also provides a manufacturing method of a semiconductor device. The manufacturing process will be described below according to the perspective view or sectional view of the operation shown in Figures 1 to 29 . Specifically, the manufacturing method of the semiconductor device includes:

[0084] First, a substrate is provided. The substrate has a first region and a second region. Specifically, the specific structure and material of the first substrate can refer to the foregoing.

[0085] As shown in Figure 25 part (1) and (2) of Figure 28 part (2), Figure 29As shown, a first ring-gate transistor is formed on a first region 12, and a second ring-gate transistor is formed on a second region 13. The first ring-gate transistor includes a first channel 37, a first gate stack 39, and a first gate sidewall 23. Along the length of the first channel 37, the first channel 37 includes a first channel region 371 and second channel regions 372 located on both sides of the first channel region 371. The first gate stack 39 surrounds the outer periphery of the first channel region 371. The first gate sidewall 23 spans across the second channel region 372. The portion of each nanosheet in the first channel 37 located in the second channel region 372 is thicker than the portion located in the first channel region 371. The first channel 37 and the second channel 38 included in the second ring-gate transistor are made of different materials. Along the thickness direction of the substrate, rows containing any nanosheet in the second channel 38 are alternately spaced with rows containing adjacent nanosheets in the first channel 37.

[0086] Specifically, as mentioned above, the first-ring-gate transistor and the second-ring-gate transistor can have the same or opposite conductivity types. Information regarding the various structures and materials of the first-ring-gate transistor and the second-ring-gate transistor can be found in the preceding text.

[0087] In one example, forming a first ring gate transistor on the first region and forming a second ring gate transistor on the second region may include the following steps:

[0088] like Figure 20 As shown, a first channel forming portion 33 and a first gate sidewall 23 are formed on a first region 12, and a second channel forming portion 34 with at least the same structure as the first channel forming portion 33 is formed on a second region 13. Along the thickness direction of the substrate (perpendicular to the A-A' and B-B' directions), both the first channel forming portion 33 and the second channel forming portion 34 include a release layer and alternating layers of a first semiconductor layer 35 and a second semiconductor layer 36. The thickness of the first semiconductor layer 35 is greater than the thickness of the second semiconductor layer 36. Along the length direction of the first channel forming portion 33 (parallel to the B-B' direction), the first gate sidewall 23 spans across the two side edge regions of the first channel forming portion 33.

[0089] Specifically, the fact that the first channel forming part and the second channel forming part have the same structure means that the material, specifications and number of layers of each membrane layer included in the first channel forming part and the second channel forming part are the same, as are the relative positions of each membrane layer.

[0090] The length extension directions of the first channel forming portion and the second channel forming portion may be the same or different.

[0091] In addition, the first semiconductor layer included in the first channel forming part is used to manufacture the first channel, and the second semiconductor layer included in the second channel forming part is used to manufacture the second channel, so the material of the first semiconductor layer is the same as that of the first channel, and the thickness of the first semiconductor layer can be set according to the thickness of the second channel region and the specifications of the second gate stack. The material of the second semiconductor layer is the same as that of the second channel, and the thickness of each layer of the second semiconductor layer can be set according to the thickness of the corresponding layer of nanosheet included in the second channel. In addition, in addition to the release layer, whether the film layer located at the topmost layer and the bottommost layer in the first channel forming part and the second channel forming part is the first semiconductor layer or the second semiconductor layer can be set according to the actual application scenario, which is not limited here. For example: as shown in (1) and (2) of Figure 20 , the film layer located at the bottommost layer in the first channel forming part 33 and the second channel forming part 34 can be the first semiconductor layer 35. In this case, as shown in (1) of Figure 1 , and (1) and (2) of Figure 20 , the film layer located at the topmost layer in the first channel forming part 33 and the second channel forming part 34 can be the second semiconductor layer 36. Or, as shown in (2) of Figure 1 , the film layer located at the topmost layer in the first channel forming part and the second channel forming part can also be the first semiconductor layer.

[0092] Or, as shown in (1) and (2) of Figure 2 , and Figure 27 , the film layer located at the bottommost layer in the first channel forming part and the second channel forming part can also be the second semiconductor layer. In this case, as shown in (1) of Figure 2 , and Figure 27 , the film layer located at the topmost layer in the first channel forming part and the second channel forming part can be the first semiconductor layer. Or, as shown in (2) of Figure 2 , the film layer located at the topmost layer in the first channel forming part and the second channel forming part can also be the second semiconductor layer.

[0093] Further, the length of the first gate sidewall across the two side edge regions of the first channel forming part determines the length of the second channel region included in the subsequently formed first channel, so the position and length of the first gate sidewall across the first channel forming part can be set according to the position and length of the second channel region.

[0094] In addition, the release layer is formed by etching the substrate, and the presence of the release layer is beneficial to release the nanosheet at the bottommost layer in the first channel or the second channel. Specifically, the material of the release layer is the same as that of the substrate, and the thickness of the release layer can be set according to the actual application scenario.

[0095] In practical applications, the manufacturing processes of the first channel forming portion and the second channel forming portion differ depending on the formation process of the first gate stack included in the first ring gate transistor and the second gate stack included in the second ring gate transistor. For example, when the first gate stack and the second gate stack are manufactured using a back-gate process, in addition to forming the first channel forming portion and the first gate sidewall on the first region, a first source region and a first drain region are also formed on both sides of the first channel forming portion along the length direction. Furthermore, in addition to forming the second channel forming portion on the second region, a second source region, a second drain region, and a second gate sidewall are also formed on the second region. The second source region and the second drain region are respectively formed on both sides of the second channel forming portion along the length direction. The second gate sidewall spans the edge regions on both sides of the second channel forming portion along the length direction. In this case, forming the first channel forming portion and the first gate sidewall on the first region, and forming a second channel forming portion on the second region with at least the same structure as the first channel forming portion, may include the following steps:

[0096] like Figure 5 As shown, a first fin 18 is formed on a first region 12, and a second fin 19 with the same structure as the first fin 18 is formed on a second region 13. Both the first fin 18 and the second fin 19 include a source forming region, a drain forming region, and a transition region located between the source forming region and the drain forming region.

[0097] Specifically, a first channel forming portion will be formed based on the first fin, and a second channel forming portion will be formed based on the second fin. Therefore, the first fin and the second fin can be configured according to the corresponding information of the first channel forming portion and the second channel forming portion, respectively. For example: Figure 5 As shown, along the thickness direction of the substrate, both the first fin 18 and the second fin 19 include a release material layer and a first semiconductor material layer 20 and a second semiconductor material layer 21 alternately stacked on the release material layer. Specifically, apart from the release material layer, the bottom layer and the top layer of the first fin 18 and the second fin 19 may be either the first semiconductor material layer 20 or the second semiconductor material layer 21, depending on the bottom layer and the top layer of the first channel forming portion and the second channel forming portion.

[0098] Furthermore, the thicknesses of the first semiconductor material layer and the second semiconductor material layer, as well as the thickness difference between them, can be referred to the preceding text. For example, the thickness of the first or second semiconductor material layer can be from 6 nm to 18 nm. The absolute value of the thickness difference between the first and second semiconductor material layers can be from 2 nm to 12 nm.

[0099] Furthermore, the first fin portion and the second fin portion can be formed simultaneously by the same film layer, so as to simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device. Alternatively, the first fin portion and the second fin portion can be formed respectively in different operation steps.

[0100] In actual application, as shown in parts (1) and (2) of FIGS. Figure 1 and Figure 2 , a surface of the substrate 11 can be alternately formed with film layers for manufacturing the first semiconductor material layer and the second semiconductor material layer by epitaxial growth and other processes. When the substrate 11 includes a semiconductor substrate and a strain buffer structure, as shown in part (1) of FIG. Figure 3 , a strain buffer layer 14 can be formed on the semiconductor substrate 111 before the film layers are formed. The material and thickness of the strain buffer layer 14 can refer to the foregoing. As shown in part (2) of FIG. Figure 4 , photolithography and etching processes can be used to etch from the top of the film layers downward to the semiconductor substrate or the strain buffer layer, so as to form the first fin structure 15 on the first region 12 and the second fin structure 16 on the second region 13. When the thickness of the strain buffer layer is greater than or equal to the thickness of the shallow trench isolation to be formed subsequently, the etching process is to etch downward to the strain buffer layer. When the thickness of the strain buffer layer is less than the thickness of the shallow trench isolation to be formed subsequently, the etching process is to etch downward to the semiconductor substrate. As shown in part (2) of FIG. Figure 5 , deposition and etching processes can be used to form the shallow trench isolation 17 on the portions of the substrate exposed outside the first fin structure and the second fin structure. The top of the shallow trench isolation 17 is lower than the bottom of the bottommost film layer in the first semiconductor material layer 20 and the second semiconductor material layer 21. The portions of the first fin structure and the second fin structure exposed outside the shallow trench isolation 17 are the first fin portion 18 and the second fin portion 19, respectively. The portions of the substrate etched and exposed outside the shallow trench isolation 17 form a release material layer.

[0101] As shown in parts (1) and (2) of FIGS. Figure 6 and Figure 7 , the first sacrificial gate 22 and the first gate sidewall 23 are formed around the transition region included in the first fin portion 18, and the second sacrificial gate 24 and the second gate sidewall 25 are formed around the transition region included in the second fin portion 19. The first gate sidewall 23 is located at least on both sides of the first sacrificial gate 22 in the length direction. The second gate sidewall 25 is located at least on both sides of the second sacrificial gate 24 in the length direction.

[0102] In actual application, chemical vapor deposition or other process can be used to deposit gate material for forming the first and second sacrificial gates on the first and second fins and the substrate (or shallow trench isolation). Then, dry etching can be used to etch the gate material so that the remaining part of the gate material has a length equal to the length of the transition region included in the first and second fins, thereby obtaining the first and second sacrificial gates. The gate material can be amorphous silicon, polysilicon or other material that is easy to remove. Figure 6 and Figure 7 As shown in (1) and (2) of FIG. 2, after the first and second sacrificial gates 22 and 24 are formed, the first and second gate sidewalls 23 and 25 can be formed on the sidewalls of the first and second sacrificial gates 22 and 24, respectively, by using the above method. The positional relationship between the first gate sidewall 23 and the first sacrificial gate 22, the positional relationship between the second gate sidewall 25 and the second sacrificial gate 24, and the material of the first and second gate sidewalls 23 and 25 can refer to the foregoing description.

[0103] As shown in (1) and (2) of FIG. 2, after the first and second sacrificial gates 22 and 24 are formed, the first and second gate sidewalls 23 and 25 can be formed on the sidewalls of the first and second sacrificial gates 22 and 24, respectively, by using the above method. The positional relationship between the first gate sidewall 23 and the first sacrificial gate 22, the positional relationship between the second gate sidewall 25 and the second sacrificial gate 24, and the material of the first and second gate sidewalls 23 and 25 can refer to the foregoing description. Figure 15 As shown in (1) and (2) of FIG. 2, after the first and second sacrificial gates 22 and 24 are formed, the first and second gate sidewalls 23 and 25 can be formed on the sidewalls of the first and second sacrificial gates 22 and 24, respectively, by using the above method. The positional relationship between the first gate sidewall 23 and the first sacrificial gate 22, the positional relationship between the second gate sidewall 25 and the second sacrificial gate 24, and the material of the first and second gate sidewalls 23 and 25 can refer to the foregoing description.

[0104] In actual application, ion implantation or other process can be used to directly process the source and drain formation regions of the first fin and the source and drain formation regions of the second fin under the mask of the cover layer, thereby forming the first source and drain regions of the first fin and the second source and drain regions of the second fin. In this case, the first cover layer can be formed on the second region first. Then, the first source and drain regions can be formed on the first region under the mask of the first cover layer. Then, the first cover layer is removed, and the second cover layer is formed on the first region. Finally, the second source and drain regions are formed on the second region under the mask of the second cover layer, and the second cover layer is removed. Alternatively, the second source and drain regions can be formed first, and then the first source and drain regions can be formed.

[0105] In addition, etching and epitaxial growth can be used to form the first and second source and drain regions. In this case, as shown in (1) and (2) of FIG. 2, the first and second source and drain regions can be formed by using epitaxial growth under the mask of the first and second cover layers, respectively. Figure 8 and Figure 15As shown in part (1), the formation of the first source region 28 and the first drain region 29 of the first ring gate transistor, which is formed at least within the source formation region and the drain formation region of the first fin, includes the steps of: removing at least a portion of the first fin 18 located within the source formation region and the drain formation region; and forming the first source region 28 and the first drain region 29 using an epitaxial growth process.

[0106] In practical applications, such as Figure 8 As shown in section (1), under the masking effect of the first sacrificial gate 22 and the first gate sidewall 23, dry etching or other processes can be used to remove only the portions of the first semiconductor material layer 20 and the second semiconductor material layer 21 located within the source and drain formation regions of the first fin. Alternatively, the entire portion of the first fin located within the source and drain formation regions can be removed. Figure 15 As shown in section (1), an epitaxial growth process is then used to form a first source region 28 and a first drain region 29 on both sides of the transition region included in the first fin along the length direction.

[0107] When the second source region and the second drain region are formed by etching and epitaxial growth, such as Figure 8 and Figure 15 As shown in section (2), the second source region 30 and the second drain region 31 of the second ring gate transistor formed at least within the source formation region and drain formation region of the second fin include the steps of: removing at least a portion of the second fin located within the source formation region and drain formation region; and forming the second source region 30 and the second drain region 31 using an epitaxial growth process.

[0108] In practical applications, such as Figure 8 As shown in section (2), under the masking effect of the second sacrificial gate 24 and the second gate sidewall 25, dry etching or other processes can be used to remove only the portions of the first semiconductor material layer 20 and the second semiconductor material layer 21 located within the source and drain formation regions of the second fin 19. Alternatively, the portions of the second fin located within the source and drain formation regions can be completely removed. Figure 15 As shown in section (2), an epitaxial growth process is then used to form a second source region 30 and a second drain region 31 on both sides of the transition region included in the second fin along the length direction.

[0109] It should be noted that when the aforementioned first source region and other regions are formed using etching and epitaxial growth methods, such as... Figure 8As shown in parts (1) and (2) of FIG. 1, the first fin 18 and the second fin 19 can be simultaneously processed in the source formation region and the drain formation region; then the first source region and the first drain region, and the second source region and the second drain region can be formed in different operation steps. Alternatively, the first fin and the second fin can be removed in the corresponding regions respectively under the mask of the corresponding cover layer, and then the first source region and the first drain region, and the second source region and the second drain region can be formed respectively.

[0110] In an example, when the first ring gate transistor further includes the first inner side wall, after the at least part of the first fin in the source formation region and the drain formation region is removed, and before the first source region and the first drain region are formed by the epitaxial growth process, the method for manufacturing the semiconductor device can further include the step of: Figure 9 As shown in part (1) of FIG. 2, the two side edge regions of the second semiconductor material layer 21 included in the first fin are selectively etched along the length direction of the first fin. As shown in part (2) of FIG. 2, the first inner side wall 26 is formed on the two sides of the remaining part of the second semiconductor material layer 21 included in the first fin along the length direction. Figure 10 Figure 17 As shown in part (1) of FIG. 2, the two side edge regions of the second semiconductor material layer 21 included in the first fin are selectively etched along the length direction of the first fin. As shown in part (2) of FIG. 2, the first inner side wall 26 is formed on the two sides of the remaining part of the second semiconductor material layer 21 included in the first fin along the length direction.

[0111] In actual application, the two side edge regions of the second semiconductor material layer included in the first fin can be selectively etched along the length direction of the first fin by using dry etching or wet etching process. The etching process and etchant used in the etching process can be determined according to the material of the first semiconductor material layer and the second semiconductor material layer. For example, when the material of the first semiconductor material layer is germanium-silicon and the material of the second semiconductor material layer is silicon, the wet etching process can be used to selectively etch the two side edge regions of the second semiconductor material layer along the length direction by using ammonia or tetramethylammonium hydroxide solution. Since the etchant only has etching effect on the second semiconductor material layer included in the first fin, the side wall of the remaining part of the second semiconductor material layer included in the first fin is concave inward relative to the side wall of the first semiconductor material layer included in the first fin after selective etching. Finally, the first inner side wall can be formed by using chemical phase deposition and etching process.

[0112] In an example, when the second ring gate transistor further includes the second inner side wall, after the at least part of the second fin in the source formation region and the drain formation region is removed, and before the second source region and the second drain region are formed by the epitaxial growth process, the method for manufacturing the semiconductor device can further include the step of: Figure 11 As shown in part (2) of FIG. 3, the two side edge regions of the first semiconductor material layer 20 included in the second fin are selectively etched along the length direction of the second fin. As shown in part (3) of FIG. 3, the second inner side wall 27 is formed on the two sides of the remaining part of the first semiconductor material layer 20 included in the second fin along the length direction. Figure 12 ​, Figure 14 and Figure 18 As shown in section (2), second inner sidewalls 27 are formed on both sides along the length direction of the remaining portion of the first semiconductor material layer 20 included in the second fin. Specifically, the formation method of the second inner sidewalls 27 can refer to the formation method of the first inner sidewalls described above, and will not be repeated here.

[0113] It should be noted that, in the case where the first ring-gate transistor includes a first inner sidewall and the second ring-gate transistor includes a second inner sidewall, such as Figure 18 In parts (1) and (2), the first inner wall 26 and the second inner wall 27 can be formed in different steps, and then the first source region 28 and the first drain region 29, as well as the second source region 30 and the second drain region 31 can be formed in different steps. Or, as Figure 9 , Figure 10 , Figures 13 to 15 As shown in parts (1) and (2), the first inner wall 26, the first source region 28, and the first drain region 29 can be formed first, followed by the formation of the second inner wall 27, the second source region 30, and the second drain region 31. Alternatively, as... Figure 11 , Figure 12 , Figures 15 to 17 As shown in parts (1) and (2), the first inner wall 26, the first source region 28 and the first drain region 29 can be formed after the second inner wall 27, the second source region 30 and the second drain region 31 are formed.

[0114] like Figure 19 As shown, after forming the first source region 28, the first drain region 29, the second source region 30, and the second drain region 31, a dielectric layer 32 covering the substrate can be formed using processes such as chemical vapor deposition and planarization. The top of the dielectric layer 32 is flush with the top of the first sacrificial gate 22 and the second sacrificial gate 24.

[0115] like Figure 20 As shown, the first sacrificial gate and / or the second sacrificial gate are removed. The portion of the first fin located within the transition region is the first channel forming portion 33, and the portion of the second fin located within the transition region is the second channel forming portion 34.

[0116] In practical applications, after removing the first and second sacrificial gates, the portions of the first and second fins located within the transition region are exposed, facilitating the subsequent formation of the first channel based on the first semiconductor layer included in the first channel forming portion, and facilitating the formation of the second channel based on the second semiconductor layer included in the second channel forming portion. Based on this, the removal order of the first and second sacrificial gates can be determined according to the formation sequence of the first and second channels and actual requirements.

[0117] For example: Figure 20As shown, the first and second sacrificial gates can be removed simultaneously. For example, as shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor. Figures 21 to 25 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor. Figure 26 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor. Figure 29 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor.

[0118] The following describes the subsequent manufacturing process by taking the manufacturing sequence of first forming the first channel and the first gate stack, and then forming the second channel and the second gate stack as an example:

[0119] As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor. Figure 21 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor.

[0120] In actual application, the first and second semiconductor layers included in the first and second channel forming portions are channel layers and sacrificial layers, and the two film layers are alternately and spacedly arranged. As shown in (1) of FIG. 6, when the film layer located at the bottom of the first and second channel forming portions is the first semiconductor layer 35 except the release layer, the part of the second semiconductor layer included in the first channel forming portion 33 and located in the first gate forming area needs to be selectively removed to ensure that the first semiconductor layer 35 at the bottom of the first area 12 is released. If the film layer located at the bottom of the first and second channel forming portions is the second semiconductor layer except the release layer, only the part of the second semiconductor layer included in the first channel forming portion and located in the first gate forming area needs to be selectively removed. Figure 21 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor.

[0121] As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor. Figure 22 As shown in (1) and (2) of FIG. 6, the first sacrificial gate can be removed first. Then, the second sacrificial gate 24 is removed after the first channel 37 is formed, or after the first gate-all-around transistor is formed. The second channel 38 and the second gate stack 40 are sequentially formed to obtain the second gate-all-around transistor.

[0122] In practical applications, for the first gate-ring transistor, the thickness of the second semiconductor layer is relatively small. Therefore, the height of the gap released by removing at least the second semiconductor layer in the first region is small. Thus, it is necessary to thin the portion of the first semiconductor layer in the first channel forming portion corresponding to the first gate forming region to increase the height of the gap, allowing the first gate stack to fill the gap properly. The method used for thinning can be determined based on the material of the first semiconductor layer. For example, if the first semiconductor layer is made of silicon, sacrificial oxidation or atomic layer etching can be used for thinning. For example, if the first semiconductor layer is made of germanium-silicon, oxidation or quasi-atomic layer etching can be used for thinning. For instance, an oxidizing solution such as nitric acid or hydrogen peroxide can be used to selectively oxidize the portion of the first semiconductor layer in the first channel forming portion corresponding to the first gate forming region to form a sacrificial oxide layer. Then, a solution such as hydrogen fluoride is used to remove the sacrificial oxide layer. This process is repeated until the remaining portion of each first semiconductor layer in the first channel forming portion forms the corresponding nanosheet of the first channel.

[0123] In this process, since only the portion of the first semiconductor layer in the first channel forming portion corresponding to the first gate forming region is thinned, the thickness of the portion of the first semiconductor layer in the first channel forming portion located below the first gate sidewall remains unchanged, and this portion forms the second channel region included in the first channel. The remaining portion of the first semiconductor layer in the first channel forming portion located within the first gate forming region has a smaller thickness, and this portion forms the first channel region included in the first channel.

[0124] like Figure 23 As shown in section (1), the first gate stack 39 surrounding the first channel region 371 can then be formed by processes such as atomic layer deposition.

[0125] like Figure 24 As shown in sections (1) and (2), after thinning the portion of the first semiconductor layer included in the first channel forming portion corresponding to the first gate forming region, the manufacturing method of the semiconductor device further includes the step of: at least selectively removing the portion of the first semiconductor layer included in the second channel forming portion located within the second gate forming region, such that the second semiconductor layer included in the second channel forming portion forms a second channel 38. The second gate forming region corresponds to the region where the second gate stack of the second ring gate transistor is located.

[0126] In practical applications, as mentioned above, the first semiconductor layer and the second semiconductor layer included in the first channel forming portion and the second channel forming portion serve as the channel layer and the sacrificial layer, respectively, and these two film layers are alternately spaced. For example... Figure 24As shown in section (2), if, apart from the release layer, the lowermost film layer in the first channel forming portion and the second channel forming portion is the first semiconductor layer, then only the portion of the first semiconductor layer in the second channel forming portion located within the second gate forming region needs to be selectively removed. For example... Figure 27 As shown, if the lowest film layer in the first channel forming portion and the second channel forming portion, excluding the release layer, is the second semiconductor layer, then it is necessary to selectively remove the portion of the first semiconductor layer and the release layer included in the second channel forming portion located in the second gate forming region to ensure that the lowest second semiconductor layer 36 on the second region 13 is released.

[0127] Because the first semiconductor layer is relatively thick, the height of the gap released by removing the first semiconductor layer in the second region is relatively large. Therefore, as Figure 25 As shown, a second gate stack 40 can be formed directly on the outer periphery of the formed second channel 38 using processes such as atomic layer deposition.

[0128] Or, such as Figure 26 As shown in sections (1) and (2), the operation of forming the second channel 38 can be performed after forming the first channel forming portion and the first gate sidewall 23 on the first region 12, and forming at least a second channel forming portion with the same structure as the first channel forming portion on the second region 13, and before at least selectively removing the portion of the second semiconductor layer 36 included in the first channel forming portion located within the first gate forming region. After forming the second ring gate transistor, the operation of at least removing the second semiconductor layer 36 on the first region 12, the above-described thinning process, and the formation operation of the first gate stack are performed sequentially in the above manner.

[0129] Compared with the prior art, the semiconductor device manufacturing method provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the embodiments of the present invention, and will not be repeated here.

[0130] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0131] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate having a first region and a second region; a first ring gate transistor formed on the first region; the first ring gate transistor includes a first channel, a first gate stack, and a first gate sidewall; along a length direction of the first channel, the first channel includes a first channel region, and second channel regions located on both sides of the first channel region; the first gate stack is wrapped around an outer periphery of the first channel region, and the first gate stack is in direct contact with the first channel region; the first gate sidewall is transversely arranged on the second channel region; the first channel has a thickness of a portion of each layer nanosheet located in the second channel region greater than a portion of each layer nanosheet located in the first channel region; the portions of the first channel are integrally continuous; and a second ring gate transistor formed on the second region; a material of the first channel is different from a material of a second channel included in the second ring gate transistor; along a thickness direction of the substrate, any row of nanosheets located in the second channel is alternately spaced apart from an adjacent row of nanosheets located in the first channel.

2. The semiconductor device according to claim 1, wherein a conductivity type of the second ring gate transistor is opposite to a conductivity type of the first ring gate transistor; and / or, a thickness difference between a portion of the nanosheet of the first channel located in the first channel region and the nanosheet of the second channel is less than or equal to a preset threshold value.

3. The semiconductor device of claim 1, wherein The material of the first channel is Si 1-x Ge x The material of the second channel is Si 1-y Ge y ; if the first ring gate transistor is an NMOS transistor, and the second ring gate transistor is a PMOS transistor, 0≤x≤0.8, 0.2≤y≤1, and y-x≥0.2; if the first ring gate transistor is a PMOS transistor, and the second ring gate transistor is an NMOS transistor, 0.2≤x≤1, 0.2≤y≤0.8, and x-y≥0.

2.

4. The semiconductor device according to claim 3, wherein in a case where a material of the first channel contains germanium, the first ring gate transistor further includes a first interface layer; the first interface layer at least wraps around an outer periphery of the first channel region, and the first gate stack is formed on the first interface layer; and / or, in a case where a material of the second channel contains germanium, the second ring gate transistor further includes a second interface layer; the second interface layer wraps around an outer periphery of the second channel, and a second gate stack included in the second ring gate transistor is formed on the second interface layer.

5. The semiconductor device according to any one of Claims 1 to 4, wherein the first ring gate transistor further includes a first inner sidewall; the first inner sidewall is located between the first gate stack and a first source region included in the first ring gate transistor, and between the first gate stack and a first drain region included in the first ring gate transistor; and / or, the second ring gate transistor further includes a second inner sidewall; the second inner sidewall is located between a second gate stack included in the second ring gate transistor and a second source region, and between the second gate stack and a second drain region included in the second ring gate transistor.

6. The semiconductor device of claim 5, wherein, in a case where the first ring gate transistor further includes a first inner sidewall, and the second ring gate transistor further includes a second inner sidewall, a thickness of the second inner sidewall is greater than a thickness of the first inner sidewall.

7. The semiconductor device according to any one of claims 1 to 4, wherein The portion of the substrate under the first channel region is not in the same plane as the top of the portion of the substrate under the second channel.

8. The semiconductor device according to any one of Claims 1 to 4, wherein The substrate includes a semiconductor substrate, and a strain buffer structure formed on the semiconductor substrate; the strain buffer structure is at least between the first channel and the semiconductor substrate, or at least between the second channel and the semiconductor substrate.

9. A method of manufacturing a semiconductor device, characterized by Comprising: Providing a substrate; The substrate has a first region and a second region; Forming a first ring gate transistor on the first region, and forming a second ring gate transistor on the second region; the first ring gate transistor includes a first channel, a first gate stack, and a first gate sidewall; along the length direction of the first channel, the first channel includes a first channel region, and second channel regions on both sides of the first channel region; the first gate stack surrounds the outer periphery of the first channel region, and the first gate stack is in direct contact with the first channel region; The first gate sidewall spans on the second channel region; the first channel has a thickness of each layer of nanosheet located in the second channel region greater than that of the first channel region; the portions of the first channel are integrally continuous; the first channel and the second channel included in the second ring gate transistor are different in material; along the thickness direction of the substrate, any row of nanosheets of the second channel is alternately spaced with the adjacent row of nanosheets of the first channel.

10. The method of manufacturing a semiconductor device according to Claim 9, wherein The forming a first ring gate transistor on the first region, and forming a second ring gate transistor on the second region includes: Forming a first channel forming portion and the first gate sidewall on the first region, and forming at least a second channel forming portion identical in structure to the first channel forming portion on the second region; along the thickness direction of the substrate, the first channel forming portion and the second channel forming portion each include a release layer, and a first semiconductor layer and a second semiconductor layer alternately stacked on the release layer; the thickness of the first semiconductor layer is greater than that of the second semiconductor layer; along the length direction of the first channel forming portion, the first gate sidewall spans on both side edge regions of the first channel forming portion; At least selectively removing the portion of the second semiconductor layer included in the first channel forming portion within a first gate forming region; the first gate forming region corresponds to the region where the first gate stack is located; Thinning the portion of the first semiconductor layer included in the first channel forming portion corresponding to the first gate forming region, so that the remaining portion of each layer of the first semiconductor layer included in the first channel forming portion forms the corresponding layer of nanosheet included in the first channel.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein After forming a first channel forming portion and a first gate sidewall in the first region, and forming at least a second channel forming portion with the same structure as the first channel forming portion in the second region, before selectively removing the portion of the second semiconductor layer included in the first channel forming portion located within the first gate forming region; or, after thinning the portion of the first semiconductor layer included in the first channel forming portion corresponding to the first gate forming region, the method of manufacturing the semiconductor device further includes: At least the portion of the first semiconductor layer included in the second channel forming portion located within the second gate forming region is selectively removed, such that the second semiconductor layer included in the second channel forming portion forms the second channel; the second gate forming region corresponds to the region where the second gate stack included in the second ring gate transistor is located.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein When the bottommost film layer in the first channel forming portion and the second channel forming portion is the second semiconductor layer, the selective removal of the portion of the first semiconductor layer in the second channel forming portion located within the second gate forming region is: selectively removing the portion of the first semiconductor layer and the release layer in the second channel forming portion located within the second gate forming region.

13. The method of manufacturing a semiconductor device according to Claim 10, wherein The method of forming a first channel forming portion and a first gate sidewall on the first region, and forming a second channel forming portion on the second region with at least the same structure as the first channel forming portion, includes: A first fin is formed in the first region, and a second fin with the same structure as the first fin is formed in the second region; both the first fin and the second fin include a source forming region, a drain forming region, and a transition region located between the source forming region and the drain forming region; The first fin includes a transition region in which a first sacrificial gate and a first gate sidewall are formed on the outer periphery, and the second fin includes a transition region in which a second sacrificial gate and a second gate sidewall are formed on the outer periphery; the first gate sidewall is located at least on both sides of the first sacrificial gate along the length direction; the second gate sidewall is located at least on both sides of the second sacrificial gate along the length direction. The first source region and the first drain region of the first ring gate transistor are formed at least in the source formation region and the drain formation region included in the first fin, and the second source region and the second drain region of the second ring gate transistor are formed at least in the source formation region and the drain formation region included in the second fin, respectively. Remove the first sacrificial gate and / or the second sacrificial gate; the portion of the first fin located within the transition region is the first channel forming portion, and the portion of the second fin located within the transition region is the second channel forming portion.

14. The method of manufacturing a semiconductor device according to Claim 13, wherein Along the thickness direction of the substrate, both the first fin and the second fin include a release material layer and a first semiconductor material layer and a second semiconductor material layer alternately stacked on the release material layer; forming the first source region and the first drain region in the first fin portion includes: removing at least part of the first fin portion located in the source formation region and the drain formation region; and forming the first source region and the first drain region by an epitaxial growth process; forming the second source region and the second drain region in the second fin portion includes: removing at least part of the second fin portion located in the source formation region and the drain formation region; and forming the second source region and the second drain region by an epitaxial growth process.

15. The method of manufacturing a semiconductor device according to Claim 14, wherein After the removing at least part of the first fin portion located in the source formation region and the drain formation region, and before the forming the first source region and the first drain region by an epitaxial growth process, the method further includes: selectively etching two side edge regions of a second semiconductor material layer included in the first fin portion along a length direction of the first fin portion; forming first inner side walls on both sides of the remaining part of the second semiconductor material layer along the length direction of the first fin portion; and / or, After the removing at least part of the second fin portion located in the source formation region and the drain formation region, and before the forming the second source region and the second drain region by an epitaxial growth process, the method further includes: selectively etching two side edge regions of a first semiconductor material layer included in the second fin portion along a length direction of the second fin portion; forming second inner side walls on both sides of the remaining part of the first semiconductor material layer along the length direction of the second fin portion.

16. The method of manufacturing a semiconductor device according to Claim 14, wherein the thickness of the first semiconductor material layer or the second semiconductor material layer is 6 nm to 18 nm; and / or, the absolute value of the thickness difference between the first semiconductor material layer and the second semiconductor material layer is 2 nm to 12 nm.

17. The method of manufacturing a semiconductor device according to Claim 10, wherein In the case where the film layer located at the bottommost layer in the first channel formation portion and the second channel formation portion is the first semiconductor layer, the at least selectively removing the part of the second semiconductor layer included in the first channel formation portion and located in the first gate formation region is: selectively removing the part of the second semiconductor layer and the release layer included in the first channel formation portion and located in the first gate formation region.

18. The method of manufacturing a semiconductor device according to Claim 10, wherein The second ring gate transistor and the first ring gate transistor are opposite in conductive type.

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