A chip testing method, device, electronic device and storage medium

Abstract

The present application provides a chip testing method, device, electronic device, and storage medium. The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data. The programmable memory includes a plurality of storage units. The method first obtains the storage information of the plurality of storage units, determines a target storage unit from the plurality of storage units according to the storage information, and obtains target patch data from the target storage unit. Then, according to the target patch data, it determines a target test subject of the chip. The target test subject includes a target test platform or a chip in at least two test platforms. Then, according to the target test subject, it determines target operation data from the chip operation data and at least two platform operation data. Finally, it calls the target operation data to test the chip. The present application realizes that the operation data of the same version adapts to the test requirements of various test platforms.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly to a chip testing method, device, electronic device, and storage medium. Background Art

[0002] Chip verification through a hardware emulation platform (EMU platform) can greatly improve the emulation efficiency, so it is widely used in verifying extremely large-scale chip designs. Boot ROM is a small piece of masked ROM or write-protected flash memory inside an embedded processor chip, containing the first code executed by the processor when powered on or reset. The development, testing, and debugging of Boot ROM need to be carried out on multiple EMU platforms. However, the testing focus of each EMU platform is different, so each EMU platform needs to maintain a set of ROM source code versions. Specifically, when testing on a certain platform, the ROM source code of that version is compiled. However, with a large number of versions, chaos is likely to occur, and time and effort are required for version maintenance and release, resulting in low testing efficiency.

[0003] Therefore, there is a technical problem of too many ROM source code versions in the existing chip testing process, which needs to be improved. Summary of the Invention

[0004] Embodiments of this application provide a chip testing method, device, electronic device, and storage medium to alleviate the technical problem of too many ROM source code versions in the existing chip testing process.

[0005] To solve the above technical problems, embodiments of this application provide the following technical solutions:

[0006] This application provides a chip testing method. The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data, and each platform operation data is applicable to a different test platform. The programmable memory includes a plurality of storage units, and the storage units are used to store patch data. The chip testing method includes:

[0007] Obtain the storage information of the plurality of storage units, and according to the storage information, determine a target storage unit from the plurality of storage units, and obtain target patch data from the target storage unit;

[0008] According to the target patch data, determine the target test subject of the chip, and the target test subject includes a target test platform or the chip in at least two of the test platforms;

[0009] Determine target operation data from the chip operation data and the at least two platform operation data according to the target test subject, where the target operation data includes the target platform operation data in the at least two platform operation data or the chip operation data;

[0010] Invoke the target operation data to test the chip.

[0011] Meanwhile, the present application also provides a chip testing device. The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data, and each platform operation data is applicable to a different test platform. The programmable memory includes a plurality of storage units, and the storage units are used to store patch data. The chip testing device includes:

[0012] An acquisition module, configured to acquire the storage information of the plurality of storage units, determine a target storage unit from the plurality of storage units according to the storage information, and acquire target patch data from the target storage unit;

[0013] A first determination module, configured to determine the target test subject of the chip according to the target patch data, where the target test subject includes a target test platform in at least two of the test platforms or the chip;

[0014] A second determination module, configured to determine target operation data from the chip operation data and the at least two platform operation data according to the target test subject, where the target operation data includes the target platform operation data in the at least two platform operation data or the chip operation data;

[0015] An invocation module, configured to invoke the target operation data to test the chip.

[0016] The present application also provides an electronic device, including a memory and a processor; the memory stores an application program, and the processor is configured to run the application program in the memory to perform the operations in the chip testing method described in any one of the above.

[0017] The present application also provides a computer-readable storage medium, on which a computer program is stored, and the computer program is executed by a processor to implement the chip testing method described in any one of the above.

[0018] Beneficial effects: The present application provides a chip testing method, device, electronic device, and storage medium. The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data, and each platform operation data is applicable to a different test platform. The programmable memory includes multiple storage units, and the storage units are used to store patch data. The chip testing method first obtains the storage information of multiple storage units, determines a target storage unit from the multiple storage units according to the storage information, and obtains target patch data from the target storage unit. Then, according to the target patch data, the target test subject of the chip is determined. The target test subject includes the target test platform or the chip in at least two test platforms. Then, according to the target test subject, the target operation data is determined from the chip operation data and at least two platform operation data. The target operation data includes the target platform operation data or the chip operation data in at least two platform operation data. Finally, the target operation data is called to test the chip. In the present application, the chip operation data and at least two platform operation data are uniformly set in the read-only memory of the chip, that is, the operation data is a uniformly compiled version. Then, a programmable memory is set in the chip, and the test subject is determined by patching. Moreover, different types of operation data can be called in different test subjects to test the chip, realizing that the same version of operation data meets the test requirements of various test platforms, thus eliminating the need to compile different versions of operation data for each test platform. Description of the Drawings

[0019] The following will, by way of a detailed description of the specific embodiments of the present application in conjunction with the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0020] Figure 1 It is a schematic diagram of the scenario of the video display system provided by the embodiment of the present application.

[0021] Figure 2 It is the first flow chart of the chip testing method provided by the embodiment of the present application.

[0022] Figure 3 It is a schematic diagram of the structures of the test platform and the chip in the chip testing method provided by the embodiment of the present application.

[0023] Figure 4 It is a schematic diagram of the storage table in the programmable memory in the chip testing method provided by the embodiment of the present application.

[0024] Figure 5 It is the second flow chart of the chip testing method provided by the embodiment of the present application.

[0025] Figure 6 It is a schematic diagram of the structure of the chip testing device provided by the embodiment of the present application.

[0026] Figure 7 This is a schematic structural diagram of the electronic device provided by the embodiment of the present application. Specific embodiments

[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0028] It should be noted that the terms "first", "second", "third", "fourth", etc. (if any) in the present application are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0029] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the scenario of the test information acquisition system provided by the embodiment of the present application. This application scenario includes a chip 10 and a test platform 20; where:

[0030] The chip 10 can be a single chip including only integrated circuits, or an integrated chip that starts from the system function of an electronic system, tightly combines the system model, processing mechanism, chip structure, circuits at all levels, and device design, and completes the functions of the entire system on a single chip;

[0031] The test platform 20 is an Emulator platform, or an EMU platform, that is, a hardware simulation platform, which can be regarded as the hardwareization of a software simulator. It is a simulation platform that verifies the functions and performance of a chip by simulating the chip environment through software operations and can be used for verifying chips of extremely large scale.

[0032] The chip 10 and the test platform 20 transmit data and signals through an interface to achieve data interaction between the two, where:

[0033] The chip 10 includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data, and each platform operation data is applicable to different test platforms. The programmable memory includes a plurality of storage units for storing patch data. During testing, the test platform 20 first obtains the storage information of the plurality of storage units, determines the target storage unit from the plurality of storage units according to the storage information, and obtains the target patch data from the target storage unit. Then, according to the target patch data, the target test subject of the chip is determined. The target test subject includes the target test platform or the chip in at least two test platforms. Then, according to the target test subject, the target operation data is determined from the chip operation data and the at least two platform operation data. The target operation data includes the target platform operation data or the chip operation data in the at least two platform operation data. Finally, the target operation data is called to test the chip 10, and whether the various functions of the chip 10 meet the expectations is judged by analyzing the relevant test results in the test platform 20.

[0034] It should be noted that Figure 1 The schematic diagram of the system scenario shown is only an example. The services and scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of the system and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0035] Please refer to Figure 2 , Figure 2 which is the first process schematic diagram of the chip testing method provided by the embodiments of the present application. The method includes:

[0036] S201: Obtain the storage information of the plurality of storage units, determine the target storage unit from the plurality of storage units according to the storage information, and obtain the target patch data from the target storage unit.

[0037] With the continuous development of process technology and application fields, on the one hand, the complexity of chip design is constantly increasing, and on the other hand, the requirements for the chip R & D cycle are becoming more and more strict. This requires that various verification works of the chip need to be carried out as early as possible and efficiently to ensure that the actual functional characteristics of the chip design are consistent with the functional characteristics defined in the design specification. For example Figure 3As shown, in large-scale chip verification, a hardware emulation platform (EMU platform) is often used as the test platform 20 to test and verify the chip 10. After downloading the software code and test files related to the chip 10 to the test platform 20, the test platform 20 simulates the operation of the chip 10 according to these software codes, and simulates the output of the chip 10 under the same conditions according to the conditions in the test files. After the test, it is determined whether the various functions of the chip 10 meet the expectations based on the test output results.

[0038] In this application, the chip 10 can be an embedded processor chip. The chip 10 includes a read-only memory 11 and a programmable memory 12. The read-only memory 11 includes chip operation data and at least two platform operation data. The chip operation data refers to the general code related to the chip during testing, and the platform operation data refers to the code related to the test platform during testing. The programmable memory 12 includes a plurality of storage units, and the storage units are used to store patch data. The read-only memory 11 is a Boot ROM, which is a small piece of masked ROM or write-protected flash memory inside the embedded processor chip. The code stored in the Boot ROM contains the first code executed by the processor when powered on or reset. The programmable memory 12 is a one-time programmable memory EFUSE. The Boot ROM determines where to load the next part of the execution code according to the relevant information of the patch data in the EFUSE.

[0039] Data and signals are transmitted between the chip and the test platform through an interface to achieve data interaction between the two. When the chip is tested on the platform, depending on the different test stages, the required test subject is also different. The test subject can be the chip itself or the test platform. When the test platform is the test subject, the relevant code in the chip, that is, the platform operation data, needs to be downloaded to the test platform, and the test platform simulates the operation of the chip according to these codes. When the chip is the test subject, the relevant code in the chip, that is, the chip operation data, is directly called for testing, and there is no need to place the relevant code in the test platform. Usually, when the chip is tested on a certain test platform, the test platform is used as the test subject first, and then the chip itself is used as the test subject after the test on the test platform is completed.

[0040] To ensure that the design and manufacturing results of the chip meet expectations, the chip needs to be tested on multiple different hardware simulation platforms, such as the Palladium Z1 platform, the ZEBU platform, the VCS platform, etc. When testing and validating on different test platforms, the focuses of the tests are also different. For example, some test platforms focus on validating the startup process, and some test platforms focus on validating the initialization of the physical layer, etc. When the test subject is the chip, since the invocation and execution of the chip operation data are both carried out in the chip and are independent of the test platform, the chip operation data can be compatible with all test platforms simultaneously. When the test subject is the test platform, it is necessary to use the test platform to simulate the operation of the chip. Due to different test focuses, the information such as the set parameters and trigger conditions required on different test platforms will be different, resulting in different platform operation data required for each test platform. For different test platforms, it is necessary to download the platform operation data corresponding to the test platform to the test platform before normal testing can be carried out. Therefore, in this application, the chip operation data can be compatible with multiple test platforms simultaneously, while the platform operation data of each platform is applicable to different test platforms. The chip operation data and at least two platform operation data are both compiled based on Jenkins and released as a complete version in the read-only memory.

[0041] During chip testing, first, initialization is performed, and then the storage information of multiple storage units is obtained from the programmable memory. According to the storage information, the target storage unit is determined from the multiple storage units, and the target patch data is obtained from the target storage unit. The target patch data includes a permission identifier, a patch running address, and a test subject identifier. In the target patch data, the permission identifier is used to indicate whether the target patch data is eligible to participate in address matching. The patch running address is used to indicate the position of the data to be run in the read-only memory after matching. The test subject identifier is used to indicate on which test subject the chip is being tested. When the permission identifier of the target patch data is "eligible", if the patch running address is equal to a certain original running address of each running data in the read-only memory, the CPU core of the chip will access the original running address and read out the running data corresponding to the original running address as the next execution code. When the permission identifier of the target patch data is "not eligible", the current running data is continued to be called as the next execution code for testing. That is, the target patch data is used to represent the relevant information of the next execution code in the read-only memory.

[0042] In one embodiment, S201 specifically includes: determining, according to the stored information, the storage units in the programmable memory that store patch data as target storage units; and obtaining target patch data from the target storage units. The programmable memory includes multiple storage units. During testing, according to requirements, write operations are performed on some of the storage units to write patch data, and other storage units are not processed. Then, the stored information of each storage unit is obtained, and only the storage units written with patch data are used as target storage units, and target patch data is obtained from them.

[0043] S202: Determine the target test entity of the chip according to the target patch data. The target test entity includes the target test platform or the chip in at least two test platforms.

[0044] In one embodiment, S202 specifically includes: judging whether the target patch data is valid according to the permission identifier of the target patch data; when the target patch data is valid, if the test entity identifier is zero, determining the chip as the target test entity; when the target patch data is valid, if the test entity identifier is not zero, determining the target test platform from at least two test platforms according to the test entity identifier and the preset test platform identifier, and using the target test platform as the target test entity.

[0045] The programmable memory includes multiple storage units, and the storage units are used to store patch data. A storage table is set in the programmable memory. The storage table includes multiple storage units, and each storage unit can be used to store patch data. The specific format of the storage table is as Figure 4 shown. Each storage unit includes a first storage area and a second storage area. Taking a 32-bit memory as an example, the address range of the first storage area is represented by OFFSET + 0x0 to OFFSET + 0x1FF, and the address range of the second storage area is represented by OFFSET + 0x200 to OFFSET + 0x3FF. Among them, the 0th to 1st bits of the first storage area are the permission storage area, which is used to store the permission identifier, represented by "EN"; the 2nd to 16th bits are the address storage area, which is used to store the patch running address, represented by "ADDRESS0[14:0]" to "ADDRESS127[14:0]"; the 17th to 31st bits are the reserved storage bits for other data, represented by "Reserved"; all bits of the second storage area are the data storage area, which is used to store the test entity identifier, represented by "DATA0[31:0]" to "DATA127[31:0]".

[0046] The programmable memory of the present application is a one-time programmable memory EFUSE. When writing data to a storage cell, the permission identifier of the target patch data consists of 2 bits, supporting two modifications. It can make the permission identifier valid or set the permission identifier to invalid again. The permission identifier is defaulted to 2'b00, indicating that the patch running address is invalid; when the permission identifier is 2'b01 or 2'b10, it indicates that the patch running address is valid and participates in the matching of the original running address; when the permission identifier is 2'b11, it indicates that the patch running address is invalid and does not participate in the matching of the original running address. Subsequently, when determining whether the target patch data is valid, it is directly judged according to the specific values of the 2-bit data of the permission identifier. Only when the target patch data is valid, will the subsequent target test subject determination operation be performed. After determining the next running code according to the target patch data, the permission identifier of the target patch data can be written as invalid, and the writing operation can be performed on other storage cells to obtain different target patch data. That is, the present application can flexibly adapt to different target test subjects by writing different target patch data and setting different permissions for the target patch data.

[0047] When testing the chip, first select whether to write patch data in the storage cells of the programmable memory and how to write the patch data according to the test requirements. For example, when wanting to test on the Palladium Z1 platform, write the patch running address 0x5ff01ffc in the address storage area of the target storage cell in the storage table, write the test subject identifier 0x563157ac in the data storage area, and write the permission identifier as valid. Then, after obtaining the target patch data, since the target patch data is valid and the test subject identifier is not zero, the test subject identifier is compared with the preset test platform identifiers of each test platform. If the test subject identifier is the same as a certain preset test platform identifier, the corresponding test platform is taken as the target test platform. For example, if the target test subject is determined to be the Palladium Z1 platform according to 0x563157ac, then the Palladium Z1 platform is determined as the target test subject. When wanting to test the chip itself, set the test subject identifier to zero in the data storage area, that is, do not perform a write operation on the data storage area to keep its default value 0, and directly determine the chip as the target test subject.

[0048] S203: Determine the target running data from the chip running data and at least two platform running data according to the target test subject. The target running data includes the chip running data or the whole of the chip running data and the target platform running data.

[0049] In one embodiment, S203 specifically includes: when the target test subject is a chip, determining the chip operation data as the target operation data; when the target test subject is a target test platform, determining, from at least two platform operation data, the target platform operation data applicable to the target test platform, and determining the target platform operation data as the target operation data. When the target test subject is a chip, it means that the invocation and execution of the relevant operation data are both carried out in the chip and are independent of the test platform. Therefore, the chip operation data is directly determined as the target operation data. When the target test subject is a certain test platform, the platform operation data corresponding to this test platform needs to be downloaded to the test platform before normal testing can be carried out. Therefore, the entire target platform operation data corresponding to this test platform is determined as the target operation data.

[0050] S204: Invoke the target operation data to test the chip.

[0051] In one embodiment, S204 specifically includes: when the target test subject is a chip, invoking the chip operation data to test the chip; when the target test subject is a target test platform, determining the target operation address of the target platform operation data according to the patch operation address in the target patch data, and invoking the target platform operation data to test the chip based on the target operation address. When the target test subject is a chip, the chip operation data is directly invoked on the chip for testing. When the target test subject is a certain test platform, the target platform operation data needs to be invoked for testing. When invoking, the address of the target platform operation data needs to be obtained first. Therefore, the patch operation address in the target patch data is obtained first, and this patch operation address is matched with the multiple original operation addresses of each operation data in the read-only memory. The code in each operation data may include multiple logical operations or instructions, etc., so there are multiple original operation addresses. When the patch operation address is equal to a certain original operation address, this original operation address is used as the target operation address, and the target platform operation data is invoked from the target operation address on the test platform to test the chip.

[0052] In one embodiment, after the step of invoking the target platform operation data to test the chip based on the target operation address, it further includes: after the target platform operation data finishes running, invoking the chip operation data to continue testing the chip. When the target platform operation data finishes running, it means that the testing that needs to be carried out on the current test platform is completed, and the next stage requires testing on the chip itself. Then, the chip operation data is invoked to continue testing the chip.

[0053] After the entire test process on a certain test platform is completed and testing is to be carried out again on other test platforms, select again whether to burn patch data in the storage units of the programmable memory and how to burn the patch data according to the test requirements, and then execute the above steps S201 to S204 again until testing is completed on all test platforms.

[0054] In the current chip testing method, for each test platform, the chip operation data and the platform operation data corresponding to this test platform are released as an overall version. Then, for multiple test platforms, multiple versions are required, resulting in too many versions, low testing efficiency, and inconvenience for maintenance.

[0055] As can be seen from the above analysis, in the chip testing method of the present application, first obtain the storage information of multiple storage units, determine the target storage unit from the multiple storage units according to the storage information, and obtain the target patch data from the target storage unit. The target patch data includes a permission identifier, a patch operation address, and a test subject identifier. Then, according to the target patch data, determine the target test subject of the chip. The target test subject includes the target test platform or the chip in at least two test platforms. Then, according to the target test subject, determine the target operation data from the chip operation data and the operation data of at least two platforms. The target operation data includes the chip operation data or the whole of the chip operation data and the target platform operation data. Finally, call the target operation data to test the chip. In the present application, the chip operation data and the operation data of at least two platforms are uniformly set in the read-only memory of the chip, that is, the operation data is a uniformly compiled version. Then, a programmable memory is set in the chip, and the test subject is determined by patching. Different types of operation data can be called in different test subjects for chip testing, so there is no need to compile different versions of operation data for each test platform.

[0056] The test platform in the present application can be used for hardware simulation of various embedded processor chips. Among them, the embedded processor chip can be an in-vehicle system-level chip. The in-vehicle system-level chip is installed on various means of transportation and is used to connect with other electronic devices and process the interaction signaling between it and other electronic devices to assist the means of transportation in realizing various functions such as video display, audio playback, navigation, and reverse. Of course, the test platform can also be used for hardware simulation of other types of chips, and the present application is not limited thereto.

[0057] As Figure 5 shown, it is the second flow schematic diagram of the chip testing method provided by the embodiment of the present application. The method includes:

[0058] S501: Start.

[0059] S502: Read-Only Memory Initialization. Initialize the chip architecture, which can be the Aarch64 architecture or other architectures, and disable memories such as Icache, Dcache, and Stack align.

[0060] S503: Read the Test Subject Identification. Obtain the target patch data from the target storage unit in the programmable memory. When the target patch data is valid, obtain the patch running address (platform base) and the test subject identification (platform code) of the target patch data, and read the corresponding test subject identification at the patch running address. For example, read the test subject identification 0x563157ac at the patch running address 0x5ff01ffc.

[0061] S504: Determine Whether the Test Subject Identification is Not 0. If so, execute S505: Read the Specific Value of the Test Subject Identification. When the specific value of the test subject identification is 0x563157ac, which is not 0, it indicates that the test subject is a certain test platform.

[0062] S506: Determine Which Test Platform the Test Subject Is. First, obtain the preset test platform identifications of the first test platform, the second test platform, and the third test platform. When the test subject identification 0x563157ac is the same as a certain preset test platform identification, use this test platform as the target test subject. The platform running data includes the first platform running data, the second platform running data, and the third platform running data respectively. Obtain the platform running data of this test platform, that is, the relevant configuration file, from the read-only memory, and then execute the special initialization part of the corresponding test platform according to the platform running data.

[0063] S507: Execute Other Running Data. After the platform running data is executed, call the chip running data to perform platform serial port initialization, UFG / EMMC / USB initialization, load certificates, load and verify the SBL firmware, etc.

[0064] After the judgment in S504, if not, directly execute S507: Execute Other Running Data. When the specific value of the test subject identification is 0, it indicates that the test subject is the chip itself, and directly call the chip running data to perform platform serial port initialization, UFG / EMMC / USB initialization, load certificates, load and verify the SBL firmware, etc.

[0065] After S507, execute S508: End. Jump to SBL.

[0066] As can be seen from the above steps, in this application, the chip operating data and at least two platform operating data are uniformly set in the read-only memory of the chip, that is, the operating data is a uniformly compiled version. Then, a programmable memory is set in the chip, and by patching, different types of operating data are called in different test subjects for chip testing, realizing that the same version of operating data adapts to the test requirements of various test platforms, so that there is no need to compile different versions of operating data for each test platform.

[0067] Based on the method described in the above embodiment, this embodiment will be further described from the perspective of the chip testing device. Please refer to Figure 6 , Figure 6 Specifically describes the chip testing device provided in the embodiment of the present application. The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operating data and at least two platform operating data, and each platform operating data is applicable to different test platforms. The programmable memory includes a plurality of storage units, and the storage units are used to store patch data. The device may include:

[0068] An acquisition module 110, configured to acquire the storage information of a plurality of storage units, determine a target storage unit from the plurality of storage units according to the storage information, and acquire target patch data from the target storage unit;

[0069] A first determination module 120, configured to determine a target test subject of the chip according to the target patch data, where the target test subject includes the target test platform or the chip in at least two test platforms;

[0070] A second determination module 130, configured to determine target operating data from the chip operating data and at least two platform operating data according to the target test subject, where the target operating data includes the target platform operating data or the chip operating data in at least two platform operating data;

[0071] An invocation module 140, configured to invoke the target operating data to test the chip.

[0072] In one embodiment, the acquisition module 110 includes:

[0073] A first determination sub-module, configured to determine the storage unit storing patch data in the programmable memory as the target storage unit according to the storage information;

[0074] A first acquisition sub-module, configured to acquire target patch data from the target storage unit.

[0075] In one embodiment, the target patch data includes a permission identifier, a patch running address, and a test subject identifier. The first determination module 120 includes:

[0076] A judgment sub-module, configured to judge whether the target patch data is valid according to the permission identifier of the target patch data;

[0077] A second determination sub-module, configured to, when the target patch data is valid, if the test subject identifier is zero, determine the chip as the target test subject;

[0078] A third determination sub-module, configured to, when the target patch data is valid, if the test subject identifier is not zero, determine a target test platform from at least two test platforms according to the test subject identifier and the preset test platform identifier, and use the target test platform as the target test subject.

[0079] In one embodiment, the second determination module 130 includes:

[0080] A fourth determination sub-module, configured to, when the target test subject is a chip, determine the chip operation data as the target operation data;

[0081] A fifth determination sub-module, configured to, when the target test subject is the target test platform, determine target platform operation data applicable to the target test platform from at least two platform operation data, and determine the target platform operation data as the target operation data.

[0082] In one embodiment, the calling module 140 includes:

[0083] A first calling sub-module, configured to, when the target test subject is a chip, call the chip operation data to test the chip;

[0084] A second calling sub-module, configured to, when the target test subject is the target test platform, determine the target operation address of the target platform operation data according to the patch operation address in the target patch data, and call the target platform operation data based on the target operation address to test the chip.

[0085] In one embodiment, the second calling sub-module is configured to, when the target test subject is the target test platform, match the patch operation address with multiple original operation addresses of each operation data in the read-only memory; and determine the original operation address equal to the patch operation address as the target operation address.

[0086] In one embodiment, the calling module 140 further includes a third calling sub-module. The third calling sub-module works after the second calling sub-module. The third calling sub-module is configured to, after the target platform operation data finishes running, call the chip operation data to continue testing the chip.

[0087] Different from the prior art, the chip testing device provided in this application first obtains the storage information of multiple storage units, determines the target storage unit from the multiple storage units according to the storage information, and obtains the target patch data from the target storage unit. The target patch data includes a permission identifier, a patch running address, and a test subject identifier. Then, according to the target patch data, the target test subject of the chip is determined. The target test subject includes the target test platform or the chip in at least two test platforms. Then, according to the target test subject, the target running data is determined from the chip running data and the at least two platform running data. The target running data includes the chip running data or the whole of the chip running data and the target platform running data. Finally, the target running data is called to test the chip. In this application, the chip running data and the at least two platform running data are uniformly set in the read-only memory of the chip, that is, the running data is a uniformly compiled version. Then, a programmable memory is set in the chip, and different types of running data are called in different test subjects by patching to perform chip testing, realizing that the same version of running data adapts to the test requirements of various test platforms, so that there is no need to compile different versions of running data for each test platform.

[0088] Correspondingly, an embodiment of this application also provides an electronic device, such as Figure 7 shown. The electronic device may include a radio frequency (RF) circuit 701, a memory 702 including one or more computer-readable storage media, an input unit 703, a display unit 704, a sensor 705, an audio circuit 706, a WiFi module 707, a processor 708 including one or more processing cores, and a power supply 709, etc. Those skilled in the art can understand that Figure 7 the structure of the electronic device shown in

[0089] does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine some components, or arrange different components. Among them:

[0090] The display unit 704 can be used to display information input by the user or information provided to the user, as well as various graphical user interfaces of the server. These graphical user interfaces can be composed of graphics, text, icons, videos, and any combination thereof.

[0091] The electronic device may further include at least one sensor 705, such as a light sensor, a motion sensor, and other sensors. The audio circuit 706 includes a speaker, and the speaker can provide an audio interface between the user and the electronic device.

[0092] WiFi belongs to short - range wireless transmission technology. Through the WiFi module 707, the electronic device can help the user send and receive emails, browse the web, and access streaming media, etc. It provides the user with wireless broadband Internet access. Although Figure 7 the WiFi module 707 is shown, it can be understood that it does not belong to an essential component of the electronic device and can be omitted entirely within the scope of not changing the essence of the application as needed.

[0093] The processor 708 is the control center of the electronic device. It connects various parts of the entire mobile phone using various interfaces and circuits. By running or executing software programs and / or modules stored in the memory 702, and by calling data stored in the memory 702, it executes various functions of the electronic device and processes data, thereby monitoring the mobile phone as a whole.

[0094] The electronic device also includes a power supply 709 (such as a battery) that powers each component. Preferably, the power supply can be logically connected to the processor 708 through a power management system, thereby realizing functions such as management of charging, discharging, and power consumption management through the power management system.

[0095] Although not shown, the electronic device may further include a camera, a Bluetooth module, etc., which will not be elaborated here. Specifically, in this embodiment, the processor 708 in the server will, according to the following instructions, load the executable files corresponding to the processes of one or more application programs into the memory 702, and the processor 708 will run the application programs stored in the memory 702 to achieve the following functions:

[0096] Obtain the storage information of multiple storage units. According to the storage information, determine the target storage unit from the multiple storage units, and obtain the target patch data from the target storage unit; according to the target patch data, determine the target test subject of the chip, where the target test subject includes the target test platform in at least two test platforms or the chip; according to the target test subject, determine the target running data from the chip running data and at least two platform running data, where the target running data includes the target platform running data in at least two platform running data or the chip running data; call the target running data to test the chip.

[0097] In the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the detailed descriptions above, and details will not be repeated here.

[0098] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling relevant hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0099] Therefore, an embodiment of the present application provides a computer-readable storage medium, which stores multiple instructions that can be loaded by a processor to implement the following functions:

[0100] Obtain the storage information of multiple storage units, determine a target storage unit from the multiple storage units according to the storage information, and obtain target patch data from the target storage unit; determine a target test entity of the chip according to the target patch data, where the target test entity includes the target test platform in at least two test platforms or the chip; determine target operation data from the chip operation data and at least two platform operation data according to the target test entity, where the target operation data includes the target platform operation data in at least two platform operation data or the chip operation data; call the target operation data to test the chip.

[0101] For the specific implementation of each of the above operations, reference may be made to the previous embodiments, and details will not be repeated here.

[0102] Among them, the computer-readable storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), a magnetic disk or an optical disc, etc.

[0103] Since the instructions stored in the computer-readable storage medium can execute the steps in any method provided by the embodiments of the present application, the beneficial effects achievable by any method provided by the embodiments of the present application can be achieved. For details, reference may be made to the previous embodiments, and details will not be repeated here.

[0104] The above has introduced in detail a chip testing method, device, electronic device, and storage medium provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip testing method, characterized in that, The chip includes a read-only memory and a programmable memory. The read-only memory includes chip operation data and at least two platform operation data, and each platform operation data is applicable to a different test platform. The programmable memory includes a plurality of storage units, and the storage units are used to store patch data. The chip testing method includes: Obtain the storage information of the plurality of storage units. According to the storage information, determine a target storage unit from the plurality of storage units, and obtain target patch data from the target storage unit; According to the target patch data, determine the target test subject of the chip. The target test subject includes the target test platform or the chip in at least two of the test platforms; According to the target test subject, determine target operation data from the chip operation data and the at least two platform operation data. The target operation data includes the target platform operation data in the at least two platform operation data or the chip operation data; Call the target operation data to test the chip.

2. The chip testing method according to claim 1, characterized in that, The step of determining a target storage unit from the plurality of storage units according to the storage information and obtaining target patch data from the target storage unit includes: According to the storage information, determine the storage units storing patch data in the programmable memory as target storage units; Obtain target patch data from the target storage unit.

3. The chip testing method according to claim 1, wherein, The target patch data includes a permission identifier, a patch operation address, and a test subject identifier. The step of determining the target test subject of the chip according to the target patch data includes: According to the permission identifier of the target patch data, determine whether the target patch data is valid; When the target patch data is valid, if the test subject identifier is zero, determine the chip as the target test subject; When the target patch data is valid, if the test subject identifier is not zero, determine a target test platform from at least two of the test platforms according to the test subject identifier and a preset test platform identifier, and use the target test platform as the target test subject.

4. The chip testing method according to claim 3, wherein, The step of determining target operation data from the chip operation data and the at least two platform operation data according to the target test subject includes: When the target test subject is the chip, determine the chip operation data as the target operation data; When the target test subject is the target test platform, determine the target platform operation data applicable to the target test platform from the at least two platform operation data, and determine the target platform operation data as the target operation data.

5. The chip testing method according to claim 4, wherein, The step of calling the target operation data to test the chip includes: When the target test subject is the chip, call the chip operation data to test the chip; When the target test subject is the target test platform, according to the patch operation address in the target patch data, determine the target operation address of the target platform operation data, and call the target platform operation data to test the chip based on the target operation address.

6. The chip testing method according to claim 5, characterized in that, When the target test subject is a target test platform, the step of determining the target running address of the target platform running data according to the patch running address in the target patch data includes: When the target test subject is a target test platform, matching the patch running address with multiple original running addresses of each running data in the read-only memory; Determining the original running address equal to the patch running address as the target running address.

7. The chip testing method according to claim 5, wherein After the step of testing the chip by calling the target platform running data based on the target running address, it further includes: After the target platform running data finishes running, calling the chip running data to continue testing the chip.

8. A chip testing device, characterized in that, The chip includes a read-only memory and a programmable memory. The read-only memory includes chip running data and at least two platform running data, and each platform running data is applicable to different test platforms. The programmable memory includes a plurality of storage units, and the storage units are used to store patch data. The chip testing device includes: An acquisition module, configured to acquire the storage information of the plurality of storage units, determine a target storage unit from the plurality of storage units according to the storage information, and acquire target patch data from the target storage unit; A first determination module, configured to determine the target test subject of the chip according to the target patch data, and the target test subject includes a target test platform or the chip in at least two of the test platforms; A second determination module, configured to determine target running data from the chip running data and the at least two platform running data according to the target test subject, and the target running data includes the target platform running data or the chip running data in the at least two platform running data; A calling module, configured to call the target running data to test the chip.

9. An electronic device, characterized in that, It includes a memory and a processor; the memory stores an application program, and the processor is configured to run the application program in the memory to execute the operations in the chip testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and the computer program is executed by the processor to implement the chip testing method according to any one of claims 1 to 7.

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