Multi-bit cmos digital-analog hybrid accumulator based on dynamic latching comparators

Abstract

The application provides a multi-bit CMOS digital-analog hybrid accumulator based on a dynamic latch comparator, which adopts N same multi-input improved dynamic latch comparators and an OR gate to realize 2 N bit binary input and N bit binary output accumulation operation, wherein each multi-input improved dynamic latch comparator comprises two groups of input transistors, 2 N input transistors, and thus 2 N bit digital signal input and accumulation can be realized, non-idealities in ADC use and conversion process are avoided, and thus the operation error is greatly reduced. Meanwhile, since the digital signal-analog signal-digital signal conversion process is avoided in the accumulation process, the digital signal-digital signal accumulation process is directly realized, the operation speed is improved, and the operation energy consumption is reduced, and thus the operation energy efficiency is improved. The comparator also adopts a Charge Steering design, a capacitor and a switch tube are added at a tail current MOS tube, and thus the power consumption of the comparator is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of accumulator technology, specifically relating to a multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator. Background Technology

[0002] Multiplication Accumulation (MAC) is a commonly used operation in machine learning, where multiplication involves multiplying two binary numbers and accumulation involves adding multiple binary numbers together. Achieving high energy efficiency is crucial in in-memory computing, and mixed-signal computing offers higher energy efficiency than purely digital operations; therefore, many accumulation circuits are implemented using mixed-signal methods.

[0003] Charge domain accumulation is a common accumulation implementation method in in-memory computing circuits. For example... Figure 8 As shown, the accumulator circuit has n inputs, each corresponding to a 1-bit binary number. When switch S0 is on and switch S1 is off, the top plate of each capacitor either does not accumulate charge or accumulates charge according to its corresponding binary number. No charge is accumulated when the input is 0, and charge is accumulated when the input is 1. Once the capacitors have accumulated enough charge, switch S0 is off and switch S1 is on, connecting the top plates of all capacitors. A voltage between 0 and the power supply voltage is formed based on the amount of charge on the top plates. This voltage is converted into a digital code by the ADC, thus enabling the accumulation of multiple binary values.

[0004] Figure 9 This is a StrongARM Latch comparator, which compares two input voltages V. in1 and V in2 The value of the clock CLK is calculated and the comparison result is given. When the clock CLK is 0, the entire dynamic latch comparator is reset. When CLK changes from 0 to 1, M1 and M2 discharge, and the discharge rate depends on V. in1 and V in2 The size; due to the different discharge speeds of M1 and M2, one of the transistors in M3 and M4 turns on first, which in turn triggers positive feedback, pulling one end of the differential output terminal to 0 and the other end to 1.

[0005] Due to deviations in circuit manufacturing processes, Figure 8The actual capacitance value of each capacitor in the ADC is not equal to the design value, which will cause a deviation in the voltage of the capacitor's top plate after charge accumulation. In addition, the ADC will also have conversion errors due to manufacturing process deviations, power supply voltage fluctuations, and temperature changes. Since a SAR ADC is generally used here, the most significant errors are offset error and gain error. Offset error is caused by the misalignment of the comparator in the SAR ADC, resulting in a fixed difference between the actual and ideal output. Gain error is caused by parasitic capacitance in the SAR ADC, resulting in a linear error between the actual and ideal transfer characteristic curves. These non-ideal factors can lead to errors in the accumulation operation. Summary of the Invention

[0006] This invention is made to solve the above-mentioned problems, and its purpose is to provide a mixed-signal accumulator that can avoid accumulation calculation errors caused by non-ideal factors in the manufacturing process. The invention adopts the following technical solution:

[0007] This invention provides a multi-bit CMOS mixed-signal accumulator based on dynamic latch comparators, characterized by comprising: N comparators, N≥2; and N-1 NOR gates, wherein all comparators are multi-input improved dynamic latch comparators with two sets of input transistors M3<2. N -1:0> and M4<2 N -1:0>, each group contains N input transistors, and each comparator has input nodes DIP and DIN, a clock node CLKC, and output nodes COP and CON. The input node DIP is connected to the input transistor M3<2. N Corresponding to -1:0>, the input node DIN corresponds to the input transistor M4<2. N -1:0> Correspondingly, both are 2 N The N-bit digital input is accumulated by N output nodes COP, and the N-bit digital output is obtained. The clock node CLKC of the first comparator is connected to the clock signal. The output nodes COP and CON of the k-th comparator are respectively connected to the two input terminals of the k-th NOR gate. The output terminal of the k-th NOR gate is connected to the clock node CLKC of the (k+1)-th comparator, where 1≤k≤N-1.

[0008] The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator provided by this invention may also have the following technical features: N=3, the three comparators are comparator COMP1, comparator COMP2, and comparator COMP3, the input node DIP includes input node DIP<7:0>, the input node DIN includes input node DIN<7:0>, the input node DIN<7:4> of comparator COMP1 is connected to 0, and the input node DIN<3:2> is connected to 1. <1> Connecting to 1, the output node CON of comparator COMP1 is also connected to the input nodes DIN<7:4> of comparator COMP2 and DIN<7:4> of comparator COMP3, respectively. The input node DIN<3:2> of comparator COMP2 is connected to 0, and the input node DIN... <1> Following point 1, the output node CON of comparator COMP2 is also connected to the input node DIN<3:2> of comparator COMP3, and the input node DIN of comparator COMP3... <1> Continuing from 0.

[0009] The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator provided by this invention may also have the following technical features: the multi-input improved dynamic latch comparator further includes: transistor M1, transistor M2, and a fixed capacitor C. T Bias transistor M5, bias transistor M6, transistor M7, transistor M8, transistor M9, transistor M 10 Transistor M 11 Transistor M 12 Transistor M 13 Transistor M 14 Non-inverting buffers B1 and B2, with the source of transistor M1 connected to power supply V. DD The drain of transistor M2 is connected to the source of transistor M2, and its gate serves as clock node CLKC. The gate of transistor M2 serves as clock node CLKCN, which is the inverted version of clock node CLKC. The source of input transistor M3<7:0> is connected to the drain of transistor M2, and its drain is connected to the source of transistor M7. Its gate serves as input node DIP<7:0>. The source of input transistor M4<7:0> is connected to the drain of transistor M2, and its drain is connected to the source of transistor M8. Its gate serves as input node DIN<7:0>. The source of transistor M5 is connected to the drain of transistor M2, and its drain is connected to the source of transistor M7. Its gate is connected to the control terminal OS. The source of transistor M6 is connected to the drain of transistor M2, and its drain is connected to the source of transistor M8. Its gate is connected to the control terminal OSN. The source of transistor M7 is also connected to transistor M... 13The drain of transistor M8 is connected to the source of transistor M. 14 The drain of transistor M7, the input terminal of non-inverting buffer B1, the gate of transistor M8, and the drain of transistor M... 11 The drain of transistor M9, the drain of transistor M 10 The gates of transistors M8, M8, and M7 are connected to the same node. The drain of transistor M8, the input of the in-phase buffer B2, and the gate of transistor M7 are also connected. 10 The drain of the transistor M 12 The drain of transistor M9 and the gate of transistor M9 are connected to the same node. The output of non-inverting buffer B1 serves as output node COP, and the output of non-inverting buffer B2 serves as output node CON. 11 The gate and the transistor M 13 The gate of the transistor is connected and serves as the clock node CLKCN. 12 The gate and the transistor M 14 The gates of transistors M9 and M are connected. 10 The transistor M 11 The transistor M 12 The transistor M 13 and the transistor M 14 The source electrodes are all grounded.

[0010] The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator provided by this invention may also have the following technical features, wherein transistor M1, transistor M2, bias transistor M5, bias transistor M6, transistor M7, transistor M8, transistor M9, and transistor M... 10 The transistor M 11 The transistor M 12 The transistor M 13 The transistor M 14 Both the input transistor M3<7:0> and the input transistor M4<7:0> are MOS transistors.

[0011] The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator provided by the present invention may also have the following technical features: the input transistors M3<7:0> and M4<7:0> are both PMOS transistors with the same size; the bias transistors M5 and M6 have the same size, and their width-to-length ratio is half that of the input transistors M3<7:0>.

[0012] Invention Function and Effect

[0013] The multi-bit CMOS mixed-signal accumulator based on dynamic latch comparators according to the present invention employs N (N is any positive integer greater than 1) identical multi-input improved dynamic latch comparators to achieve 2 N This is an accumulation operation with 2-bit binary input and N-bit binary output, where the multi-input improved dynamic latch comparator contains two sets of 2... N For the input transistor, therefore, it is possible to achieve 2 on both sides. N The input and accumulation of 10-bit digital signals eliminates the need for an ADC, thus avoiding the non-ideals inherent in ADC conversion and significantly reducing computational errors, resulting in more accurate accumulation results. Furthermore, by directly implementing digital-to-digital accumulation without the digital-to-analog-to-digital signal conversion process, the computation speed is increased and energy consumption is reduced, thereby improving computational efficiency. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of a multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in an embodiment of the present invention;

[0015] Figure 2 This is a circuit diagram illustrating the operation of the multi-input improved dynamic latch comparator during the reset phase in an embodiment of the present invention.

[0016] Figure 3 This is a circuit diagram showing the operation of the multi-input improved dynamic latch comparator during the amplification stage in an embodiment of the present invention.

[0017] Figure 4 This is a circuit diagram showing the operation of the multi-input improved dynamic latch comparator in the stable phase in an embodiment of the present invention.

[0018] Figure 5 This is a timing diagram of the operation process of the multi-input improved dynamic latch comparator in this embodiment of the invention;

[0019] Figure 6 This is a schematic diagram of the successive approximation process of a multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in an embodiment of the present invention;

[0020] Figure 7 This is a timing diagram of the operation process of the multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in an embodiment of the present invention;

[0021] Figure 8 This is a circuit diagram for charge domain accumulation operations in the prior art;

[0022] Figure 9 This is a circuit diagram of the StrongARM dynamic latch comparator in the prior art. Detailed Implementation

[0023] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following describes the multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in detail with reference to the embodiments and accompanying drawings.

[0024] <Example>

[0025] Figure 1 This is a circuit diagram of a multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in this embodiment. Box B shows the circuit diagram of a multi-input improved dynamic latch comparator.

[0026] like Figure 1 As shown, the multi-bit CMOS mixed-signal accumulator A1 (hereinafter referred to as accumulator A1) based on dynamic latch comparators in this embodiment consists of three identical multi-input improved dynamic latch comparators COMP1 to COMP3 (hereinafter referred to as comparators COMP1, etc.) and two NAND gates D1 to D2.

[0027] The circuit structure of each comparator is as follows: Figure 1 The components shown in frame B include: transistors M1 and M2, and a fixed capacitor C. T Input transistors M3<7:0>, M4<7:0>, bias transistors M5 and M6, and transistors M7 to M6. 14 Non-inverting buffers B1 and B2. All transistors are MOS transistors, and the input transistors are PMOS transistors.

[0028] The connection method is as follows: the source of transistor M1 is connected to the power supply V. DD The drain is connected to the source of transistor M2, and the gate is connected out as the clock node CLKC. Fixed capacitor C T The transistor is connected between the source and drain of transistor M1. The gate of transistor M2 is connected as the clock node CLKCN, which is the inverted version of CLKC. The drain of transistor M2 is connected to the input transistors, etc. The source of input transistor M3<7:0> is connected to the drain of transistor M2, and the drain is connected to the source of transistor M7. The gate serves as the input node DIP<7:0>. The source of input transistor M4<7:0> is connected to the drain of transistor M2, and the drain is connected to the source of transistor M8. The gate serves as the input node DIN<7:0>. The source of transistor M5 is connected to the drain of transistor M2, and the drain is connected to the source of transistor M7. The gate is connected to the control terminal OS. The source of transistor M6 is connected to the drain of transistor M2, and the drain is connected to the source of transistor M8. The gate is connected to the control terminal OSN. The source of transistor M7 is also connected to transistor M... 13The drain of transistor M8 and the source of transistor M8 are also connected to transistor M. 14 The drain of transistor M7, the input of non-inverting buffer B1, the gate of transistor M8, and transistor M... 11 The drain of transistor M9, the drain of transistor M 10 The gates of transistors M8 and M7 are connected to the same node. The drain of transistor M8, the input of the in-phase buffer B2, the gate of transistor M7, and transistor M... 10 The drain of the transistor M 12 The drain of transistor M1 and the gate of transistor M9 are connected to the same node. The output of non-inverting buffer B1 serves as the output node COP, and the output of non-inverting buffer B2 serves as the output node CON. 11 Gate and transistor M 13 The gate of transistor M is connected to the clock node CLKCN. 12 Gate and transistor M 14 The gates of transistors M9 and M1 are connected together and connected out as the clock node CLKCN. 14 The source electrodes are all grounded.

[0029] All transistors in this circuit are MOSFETs, and all input transistors are PMOS transistors, all of the same size. Each input transistor supports a single bit of digital input (0 or 1). Bias transistors M5 and M6 are identical in size, with a width-to-length ratio half that of the input transistors. OS is 0 to turn M5 on, and OSN is 1 to turn M6 off. This ensures that the two sides of the comparator do not generate the same discharge current under any circumstances, thus avoiding metastability. The function of M6 is to ensure equal parasitic capacitance on both sides. Input DIN <7> The value is always 1, so that M4 <7> It is in the off state because the right side does not require eight transistors in the on state, M4. <7> The existence of this is also to balance the parasitic capacitance on the left and right sides.

[0030] Furthermore, as can be seen from the above structure, the comparator in this embodiment is a dynamic latch comparator based on StrongARM Latch, employing the Charge Steering design method, and adding a capacitor C to the tail current MOSFET. T This effectively reduces power consumption.

[0031] Each comparator has: two input nodes DIP and DIN, one clock node CLKC, and two output nodes COP and CON.

[0032] The three comparators COMP1 to COMP3 are connected as follows: the clock node CLKC of comparator COMP1 is connected to the clock signal; the two output nodes COP and CON of comparator COMP1 are connected to the two input terminals of NOR gate D1, respectively; the output terminal of NOR gate D1 is connected to the clock node CLKC of comparator COMP2. The two output nodes COP and CON of comparator COMP2 are connected to the two input terminals of NOR gate D2, respectively; the output terminal of NOR gate D2 is connected to the clock node CLKC of comparator COMP3.

[0033] The input nodes DIP<7:0> of the three comparators COMP1 to COMP3 are connected together, which are also the 8-bit binary inputs of accumulator A1. The output node CON of comparator COMP1 is connected to the input nodes DIN<7:4> of comparator COMP2 and DIN<7:4> of comparator COMP3, respectively. The output node CON of comparator COMP2 is connected to the input node DIN<3:2> of comparator COMP3. The input node DIN<7:4> of comparator COMP1 is connected to 0 (low level), and the input nodes DIN<3:2> and DIN<4:0> are connected to each other. <1> Connect 1 (high level). Connect the input node DIN<3:2> of comparator COMP2 to 0. <1> Continuing from point 1, the input node DIN of comparator COMP3... <1> Continuing from 0.

[0034] The three output nodes COP of the three comparators COMP1 to COMP3 are 3-bit binary outputs, which are also the outputs of accumulator A1.

[0035] Figures 2-4 The circuit diagrams show the working process of the multi-input improved dynamic latch comparator in three stages.

[0036] like Figures 2-4 As shown, the comparators COMP1 to COMP3 operate in three phases: Reset Phase, Amplification Phase, and Setting Phase.

[0037] Figure 2 This shows the reset phase, in which CLKC = 1, CLKCN = 0, and the two parasitic capacitances C p The top plate and two nodes OUTP and OUTN are discharged to GND, therefore COP and CON are 0. During this stage, the tail capacitor C... T The base plate is connected to V DD And by V DD Charge it.

[0038] Figure 3This shows the amplification phase, in which CLKC becomes 0, CLKCN becomes 1, and nodes OUTN and C... p The top plate is disconnected from GND, C T The base plate from the connection V DD It becomes the source connected to M3<7:0> and M4<7:0>, and M5 and M6. At this stage, C... T The charge on the base plate will be transferred to C through M3, M4, M5, and M6. p The top plate is charged. When a certain C P Top plate voltage V CP Reaching the threshold voltage V of M5 and M6 th5,6 At that time, one of M5 and M6 is turned on, while the other remains off.

[0039] Figure 4 This shows the steady-state phase, in which CLKC = 0 and CLKCN = 1. Assuming M5 is on and M6 is off, when the voltage V at this node... OUTP Reaching the threshold voltage V of M7 and M8 th7,8 At this time, charge will accumulate at node OUTP, causing M8 to conduct and M7 to remain off. Finally, the voltage V at node OUTP... OUTP The voltage V at node OUTN is higher than 0. OUTN Keep it at 0.

[0040] Accumulator A1 converts an 8-bit digital input into a 3-bit binary output based on the number of 0s and 1s in the input. For example, if the input is 00000000, the output is 111; if the input is 00111100, the output is 100, and so on. Accumulator A1 has nine input states (0 to 8 1s), but only eight output states. One state is discarded because the probability of an all-zero input is very small, only 1 / 256.

[0041] Figure 5 This is a timing diagram of the operation of the multi-input improved dynamic latch comparator in this embodiment. S01 shows the CLKC voltage, and S02 shows the parasitic capacitance C. p Top plate voltage, S03 shows the comparator output OUT P OUT N The terminal voltages, S04 shows the comparison results of the comparator, COP and CON.

[0042] As described above, accumulator A1 contains three comparators COMP1 to COMP3, each with two input nodes DIP and DIN, one clock node CLKC, and two output nodes COP and CON. Figure 5As shown, in the initial stage, CLKC is 0, and the two outputs of the comparator in this embodiment, COP and CON, are both 0. When the falling edge of CLKC arrives, the comparator begins to compare the number of 0s in the two digital inputs. If the number of 0s in DIP is greater than the number of 0s in DIN, the two outputs will be COP = 1 and CON = 0, respectively. If the number of 0s in DIP is less than or equal to the number of 0s in DIN, the two outputs will be the opposite of the previous case, i.e., COP = 0 and CON = 1. When the rising edge of CLKC occurs, the comparator is reset.

[0043] The accumulator A1 works similarly to a SAR ADC. The input from DIN will gradually approach the input from DIP, eventually determining the input value of DIP.

[0044] Figure 6 This is a schematic diagram of the successive approximation process of the multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in this embodiment.

[0045] Figure 6 The numbers in the middle are binary numbers, indicating how many of the eight transistors in M4<7:0> are currently in the on state. Since M4<7:0> are connected in parallel, M4<7:4> can represent a 3-bit MSB, and M4<3:2> can represent MSB-1. <1> It can represent LSB. In Figure 6 In the diagram, a hollow arrow indicates that the last comparison result is 1, and the number of transistors in the on state controlled by DIN should be increased; a solid arrow indicates that the last comparison result is 0, and the number of transistors in the on state controlled by DIN should be decreased. This process ultimately determines the number of 0s or 1s in the input of accumulator A1.

[0046] Figure 7 This is a timing diagram of the operation of the multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator in this embodiment. S01 shows the CLKC1 voltage (i.e., the CLKC voltage of comparator COMP1, hereinafter the same), and S02 shows the OUT... <3> The output result (i.e., the COP output of comparator COMP1, the same below), S03 shows the CLKC2 voltage, and S04 shows the OUT. <2> The output results are shown in S05, which displays the CLKC3 voltage, and S06, which displays the OUT voltage. <1> The output result.

[0047] like Figure 7 As shown, when the falling edge of CLKC arrives, comparator COMP1 starts comparing, and during the comparison delay time t... de1Afterwards, comparator COMP1 completes the comparison, and its outputs COP and CON change from 00 to 01 and then to 10, respectively. This causes the output of NOR gate D1 to change from 0 to 1, activating the next comparator COMP2. When the rising edge of CLKC arrives, comparator COMP1 is reset, and its outputs COP and CON change from 01 or 10 to 00, causing the output of NOR gate D1 to change from 1 to 0, thus resetting the next comparator COMP2. Comparators COMP2-3 and NOR gate D2 work similarly, and will not be described further.

[0048] In other words, traditional mixed-signal accumulator circuits often convert digital signals into analog signals, accumulate the analog signals, and then convert the accumulated result back into a digital signal; however, the accumulator A1 in this embodiment does not have the process of converting digital signals into analog signals and analog signals into digital signals, but directly performs accumulation operations on the digital input signal.

[0049] Meanwhile, traditional dynamic latch comparators have only one pair of input MOSFETs, and the input signal is an analog signal. However, the multi-input improved dynamic latch comparators COMP1-COMP3 used in the accumulator A1 of this embodiment have eight pairs of input MOSFETs, and the inputs on both sides are 8-bit digital signals. Compared with the traditional structure, the multi-input improved dynamic latch comparators COMP1-COMP3 also add a capacitor and a switching transistor at the tail current MOSFET.

[0050] Functions and effects of the embodiments

[0051] The multi-bit CMOS mixed-signal accumulator based on dynamic latch comparators provided in this embodiment employs three identical multi-input improved dynamic latch comparators to achieve accumulation operations with 8-bit binary input and 3-bit binary output. Each multi-input improved dynamic latch comparator contains two sets of eight pairs of input transistors, thus enabling the input and accumulation of 8-bit digital signals from both sides. This avoids the need for an ADC, thereby avoiding the non-ideals inherent in the ADC conversion process and significantly reducing computational errors, resulting in more accurate accumulation results. Furthermore, since the digital-to-analog-to-digital signal conversion process is avoided during accumulation, directly realizing the digital-to-digital signal accumulation process, the computational speed is improved and the energy consumption is reduced, thus enhancing the energy efficiency of the operation.

[0052] In the embodiment, the multi-input improved dynamic latch comparator also adopts a charge steering design, which adds a capacitor and a switching transistor at the tail current MOSFET, thereby greatly reducing the power consumption of the comparator.

[0053] The above embodiments are only used to illustrate specific implementations of the present invention, and the present invention is not limited to the scope of the description of the above embodiments.

[0054] In the above embodiment, three identical multi-input improved dynamic latch comparators, each containing 8 pairs of input transistors, are used to implement an accumulator with 8-bit digital input and 3-bit digital output. Alternatively, N multi-input improved dynamic latch comparators can be used, each containing 2... N To achieve 2 N An accumulator with N-bit digital input and N-bit digital output, where N is any positive integer greater than 1, can also achieve the technical effect of this invention. Furthermore, the multi-input improved dynamic latch comparator can be modified from a structure using PMOS transistors as input transistors to a structure using NMOS transistors as input transistors. In the structure using NMOS transistors as input transistors, the multi-input improved dynamic latch comparator is connected to DIP<2 N -1:0> and DIN<2 N The transistor with a configuration of -1:0> changes from PMOS to NMOS, and the remaining transistors are in NP mode, as well as the tail current transistor and capacitor C. T Corresponding changes were also made to compare the number of 0s or 1s in the input digital signal in a manner that complements the above embodiments.

Claims

1. A multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator, characterized in that, include: N comparators, N≥2; as well as N-1 NOR gates, The comparators described herein are all multi-input improved dynamic latch comparators, with two sets of input transistors M3<2. N -1:0> and M4<2 N -1:0>, each group contains N input transistors. Each comparator has input nodes DIP and DIN, a clock node CLKC, and output nodes COP and CON. The input node DIP and the input transistor M3<2 N Corresponding to -1:0>, the input node DIN corresponds to the input transistor M4<2 N -1:0> Correspondingly, both are 2 N Number input, The N output nodes COP are used as the accumulated result, and the result is output as an N-digit number. The clock node CLKC of the first comparator is connected to the clock signal. The output nodes COP and CON of the kth comparator are respectively connected to the two input terminals of the kth NOR gate, and the output terminal of the kth NOR gate is connected to the clock node CLKC of the (k+1)th comparator, where 1≤k≤N-1.

2. The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator according to claim 1, characterized in that: in, N=3, and the three comparators are COMP1, COMP2, and COMP3. The input node DIP includes the input node DIP<7:0>. The input node DIN includes the input node DIN<7:0>. The comparator COMP1 has its input node DIN<7:4> connected to 0, input node DIN<3:2> connected to 1, and input node DIN... <1> Following 1, The output node CON of comparator COMP1 is also connected to the input nodes DIN<7:4> of comparator COMP2 and DIN<7:4> of comparator COMP3, respectively. The input node DIN<3:2> of the comparator COMP2 is connected to 0, and the input node DIN... <1> Following 1, The output node CON of comparator COMP2 is also connected to the input node DIN<3:2> of comparator COMP3. The input node DIN of the comparator COMP3 <1> Continuing from 0.

3. The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator according to claim 2, characterized in that: in, The multi-input improved dynamic latch comparator also includes: transistor M1, transistor M2, and a fixed capacitor C. T Bias transistor M5, bias transistor M6, transistor M7, transistor M8, transistor M9, transistor M 10 Transistor M 11 Transistor M 12 Transistor M 13 Transistor M 14 In-phase buffer B1, in-phase buffer B2, The source of transistor M1 is connected to power supply V. DD The drain is connected to the source of transistor M2, and the gate serves as the clock node CLKC. The gate of transistor M2 serves as clock node CLKCN, which is the inverse of clock node CLKC. The source of the input transistor M3<7:0> is connected to the drain of the transistor M2, and the drain is connected to the source of the transistor M7. The gate serves as the input node DIP<7:0>. The source of the input transistor M4<7:0> is connected to the drain of the transistor M2, and the drain is connected to the source of the transistor M8. The gate serves as the input node DIN<7:0>. The source of transistor M5 is connected to the drain of transistor M2, the drain of transistor M2 is connected to the source of transistor M7, and the gate is connected to the control terminal OS. The source of transistor M6 is connected to the drain of transistor M2, the drain of transistor M2 is connected to the source of transistor M8, and the gate is connected to the control terminal OSN. The source of transistor M7 is also connected to transistor M 13 The drain electrode, The source of transistor M8 is also connected to transistor M 14 The drain electrode, The drain of transistor M7, the input terminal of the non-inverting buffer B1, the gate of transistor M8, and transistor M 11 The drain of transistor M9, the drain of transistor M 10 The gates are connected to the same node. The drain of transistor M8, the input terminal of the in-phase buffer B2, the gate of transistor M7, and transistor M 10 The drain of the transistor M 12 The drain of the transistor and the gate of the transistor M9 are connected to the same node. The output of the in-phase buffer B1 serves as the output node COP. The output of the in-phase buffer B2 serves as the output node CON. The transistor M 11 The gate and the transistor M 13 The gate is connected and serves as the clock node CLKCN. The transistor M 12 The gate and the transistor M 14 The gate is connected and serves as the clock node CLKCN. The transistor M9, the transistor M 10 The transistor M 11 The transistor M 12 The transistor M 13 and the transistor M 14 The source electrodes are all grounded.

4. The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator according to claim 3, characterized in that: in, The transistors M1, M2, M5, M6, M7, M8, M9, and M1 are described. 10 The transistor M 11 The transistor M 12 The transistor M 13 The transistor M 14 Both the input transistor M3<7:0> and the input transistor M4<7:0> are MOS transistors.

5. The multi-bit CMOS mixed-signal accumulator based on a dynamic latch comparator according to claim 4, characterized in that: in, The input transistor M3<2 N-1 :0> and the input transistor M4<2 N-1 All are PMOS transistors, and all are the same size. The bias transistors M5 and M6 have the same dimensions, and their width-to-length ratio is less than that of the input transistor M3. N -1 Half of :0>.

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