Memory systems, memory devices, and methods performed by memory systems

Abstract

The present disclosure provides a method, apparatus, system, and device including a computer readable medium for managing error correction coding in a memory system. In one embodiment, a memory system includes a system controller configured to communicate with a host device and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code circuit (ECC circuit) configured to perform error correction coding on received data, the data received from at least one of the system controller or the at least one memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory system, and particularly to error correction coding in a memory system, a memory device, and a method performed by a memory system. BACKGROUND

[0002] Some memory systems include a system controller and a memory device that communicate with each other via a circuit board. In some cases, the system controller error correction encodes data to or from the memory device, which causes large data transfers via the circuit board. This can result in high power consumption and high operating temperatures.

[0003] SUMMARY

[0004] The present disclosure describes systems and techniques for managing error correction coding in a memory system (e.g., a solid state drive (SSD)), in particular by implementing error correction code circuitry (ECC circuitry) in a memory device (e.g., a flash memory device), thereby reducing data transfers via a circuit board and isolating heat sources in the memory system, which can greatly reduce power consumption and increase heat dissipation.

[0005] One embodiment of the present disclosure provides a memory system, including a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory, and a memory controller coupled to the at least one memory, the memory controller including error correction code circuitry (ECC circuitry) configured to error correction encode received data, the data being received from at least one of the system controller or the at least one memory.

[0006] In some embodiments, the memory controller is coupled to the system controller via a first type of electrical connection, the memory controller is coupled to the at least one memory via a second type of electrical connection, and the second type of electrical connection has an impedance that is less than an impedance of the first type of electrical connection. The second type of electrical connection can have a lower operating power consumption than the first type of electrical connection.

[0007] In some embodiments, the memory system further includes an electrical connection board. The system controller and the memory device can be disposed on the electrical connection board, respectively. The first type of electrical connection can be implemented through a shared bus of the electrical connection board. The second type of electrical connection can be implemented through an internal bus in the memory device.

[0008] In some embodiments, the memory system is configured as a solid state drive (SSD), and the system controller includes an SSD controller, and the memory device includes flash memory.

[0009] In some embodiments, the system controller includes: a first interface configured to communicate with the host device via a third type of electrical connection according to a first interface protocol, wherein the impedance of the second type of electrical connection is less than the impedance of the third type of electrical connection; and a second interface configured to communicate with the memory controller via the first type of electrical connection according to a second interface protocol.

[0010] In some embodiments, the first type of electrical connection is the same as the third type of electrical connection. In some embodiments, the first interface protocol includes a bus interface protocol, and the second interface protocol includes a flash interface protocol.

[0011] In some embodiments, the memory controller includes: a third interface configured to communicate with the system controller via the first type of electrical connection according to the second interface protocol. The second interface and the third interface can be customized and different from the first interface. The system controller can include a data processor configured to communicate with the memory controller via the second interface and the third interface according to the second interface protocol. The data processor can include the second interface and can be formed as a separate chip in the system controller. The at least one memory and the memory controller can be formed as separate chips packaged in the memory device.

[0012] In some embodiments, the memory controller is configured to: receive the data from the system controller via the first type of electrical connection; encode the data using the ECC circuitry to obtain encoded data, the encoded data having a greater size than the data; and write the encoded data in the at least one memory via the second type of electrical connection.

[0013] In some embodiments, the memory controller is configured to: read the data from the at least one memory via the second type of electrical connection; decode the data using the ECC circuitry to obtain decoded data, the decoded data having a smaller size than the data; and send the decoded data to the system controller via the first type of electrical connection.

[0014] In some embodiments, the memory controller is configured to read soft bits of the data from the at least one memory via the second type of electrical connection, decode the soft bits of the data using the ECC circuitry according to a soft-decision decoding algorithm to obtain decoded data, the decoded data having a smaller size than the data, and send the decoded data to the system controller via the first type of electrical connection.

[0015] In some embodiments, the ECC circuitry in the memory controller is memory-side ECC circuitry. The system controller can include system-side ECC circuitry having stronger decoding capability than the memory-side ECC circuitry in the memory controller, and the memory-side ECC circuitry can be configured to decode data according to a weaker decoding algorithm, and the system-side ECC circuitry in the system controller is configured to decode data according to a stronger decoding algorithm.

[0016] In some embodiments, the memory-side ECC circuitry in the memory controller has a smaller area than the system-side ECC circuitry in the system controller.

[0017] In some embodiments, the weaker decoding algorithm includes a bit-flipping related algorithm, and the stronger decoding algorithm includes a min-sum related algorithm.

[0018] In some embodiments, the memory controller is configured to send the data to the system controller in response to a determination that the memory-side ECC circuitry failed to decode the data according to the weaker decoding algorithm. The system controller is configured to decode the data using the system-side ECC circuitry according to the stronger decoding algorithm, send a request to the memory controller to read soft bits of the data from the at least one memory in response to a determination that the system-side ECC circuitry failed to decode the data according to the stronger decoding algorithm, and decode the soft bits of the data using the system-side ECC circuitry according to the stronger decoding algorithm to obtain decoded data, the decoded data having a smaller size than the data, in response to receiving the soft bits of the data from the memory controller. The memory controller is configured to send the soft bits of the data to the system controller without decoding the soft bits of the data using the memory-side ECC circuitry.

[0019] In some embodiments, the memory system includes a plurality of memory devices including the memory device. Each of the plurality of memory devices is coupled to the system controller and includes: an individual memory; and an individual memory controller coupled to the individual memory, the individual memory controller including a corresponding ECC circuit configured to perform a corresponding error correction coding on corresponding data received from at least one of the individual memory or the system controller.

[0020] In some embodiments, the system controller includes a plurality of data processors, each of the plurality of data processors configured to communicate with an individual memory device of the plurality of memory devices.

[0021] In some embodiments, the corresponding ECC circuit in the individual memory controller of each of the plurality of memory devices is a memory-side ECC circuit, and each of the plurality of data processors includes a system-side ECC circuit having a stronger decoding capability than the memory-side ECC circuit.

[0022] In some embodiments, the memory system further includes a memory access controller configured to control data transfer between the system controller and at least one memory device of the plurality of memory devices.

[0023] In some embodiments, the memory system further includes a second memory device coupled to both the system controller and the memory device. The second memory device can have a faster response speed than the memory device.

[0024] In some embodiments, the memory device includes a flash memory, and the second memory device includes a Dynamic Random Access Memory (DRAM).

[0025] In some embodiments, the system controller includes an internal controller configured to control data transfer between the system controller and the second memory device.

[0026] In some embodiments, the at least one memory includes a plurality of memories each coupled to the memory controller, and the ECC circuit is configured to perform error correction coding on corresponding data associated with each of the plurality of memories.

[0027] Another embodiment of the present disclosure provides a memory device, including at least one memory; and a memory controller coupled to the at least one memory. The memory controller includes a memory interface configured to communicate with a system controller via a first type of electrical connection, wherein the memory controller is coupled to the at least one memory via a second type of electrical connection having a smaller impedance than the first type of electrical connection; and an Error Correction Code Circuit (ECC circuit) configured to perform error correction coding on received data based on at least one of a read command or a write command received by the system controller from a host device, the data being received from at least one of the system controller or the at least one memory.

[0028] Yet another embodiment of the present disclosure provides a method performed by a memory system. The method includes receiving, by a system controller of the memory system, data from a host device coupled to the system controller; sending, by the system controller, the data to a memory device of the memory system via a first type of electrical connection; encoding, by an Error Correction Code Circuit (ECC circuit) in a memory controller of the memory device, the data to obtain encoded data, the encoded data having a larger size than the data; and writing, by the memory controller, the encoded data in at least one memory of the memory device. The memory controller is coupled to the at least one memory via a second type of electrical connection having a smaller impedance than the first type of electrical connection.

[0029] In some embodiments, the method further includes obtaining, by the memory controller, specified data from the at least one memory via the second type of electrical connection; decoding, by the ECC circuit in the memory controller, the specified data to obtain decoded specified data, the decoded specified data having a smaller size than the specified data; and sending, by the memory controller, the decoded specified data to the system controller via the first type of electrical connection.

[0030] In some embodiments, the method further includes: obtaining, by the memory controller, specified data from the at least one memory via the second type of electrical connection; in response to determining that the ECC circuit in the memory controller fails to decode the specified data, sending, by the memory controller, the specified data to the system controller via the first type of electrical connection; and decoding, by a second ECC circuit in the system controller, the specified data, the second ECC circuit having a stronger decoding capability than the ECC circuit.

[0031] In some embodiments, the method further includes: in response to determining that the second ECC circuit fails to decode the specified data, sending, by the system controller, a request to the memory controller to read soft bits of the specified data from the at least one memory; sending, by the memory controller, the soft bits of the specified data to the system controller without using the ECC circuit to decode the soft bits of the specified data; and decoding, by the second ECC circuit in the system controller, the soft bits of the specified data to obtain decoded specified data, the decoded specified data having a smaller size than the specified data.

[0032] In some embodiments, the method further includes: sending, by the system controller, the decoded specified data to the host device.

[0033] Embodiments of the techniques described above include methods, systems, computer program products, and computer-readable media. In one example, a method can be performed by a memory system including a system controller and at least one memory device, and the method can include the above-described acts, e.g., acts for managing error correction coding in the memory system. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described acts. One such computer-readable medium stores instructions that, when executed by one or more processors, are configured to cause the one or more processors to perform the above-described acts.

[0034] Embodiments of the present disclosure provide systems, methods, and techniques for managing error correction coding in a memory system, which can reduce power consumption and provide better heat dissipation. For example, by integrating ECC circuitry into a memory device, the amount of data transfer via an electrical connection board can be greatly reduced, which can reduce the power consumption of the memory system. Furthermore, moving at least part of the ECC encoding capability from a system controller to a memory device in the memory system can spread out (or separate) heat sources (or power sources) in the overall memory system and increase heat dissipation in the system controller.

[0035] The techniques can be implemented for any type of memory system or controller coupled with one or more memory devices. For example, the techniques can be applied in a solid state disk (SSD) architecture including an SSD controller and one or more flash memory devices. The techniques can be implemented in the design and fabrication of digital integrated circuits (ICs).

[0036] The techniques can be applied to various types of volatile memory devices or systems or non-volatile memory devices or systems, such as NAND flash memory devices or systems, or NOR flash memory devices or systems, resistive random-access memory (RRAM) devices or systems, phase-change random-access memory (PCRAM) devices or systems, etc. The techniques can be applied to two-dimensional (2D) memory devices or systems, or three-dimensional (3D) memory devices or systems. The techniques can be applied to various memory types, such as single-level cell (SLC) devices or systems, multi-level cell (MLC) devices, such as 2-level cell devices or systems, triple-level cell (TLC) devices or systems, quad-level cell (QLC) devices or systems, or penta-level cell (PLC) devices or systems. Additionally or alternatively, the techniques can be applied to various types of devices or systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), universal flash storage (UFS), solid state disks (SSDs), embedded systems, etc.

[0037] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, embodiments, and advantages will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 An example including a host device and a memory system is shown.

[0039] Figure 2An example memory system is shown that includes a system controller with ECC circuitry and a memory device without ECC circuitry.

[0040] Figure 3 An example memory system is shown that includes a system controller without ECC circuitry and a memory device with ECC circuitry.

[0041] Figure 4 An example interface protocol is shown for a customized interface of a system controller and a memory device. Figure 3

[0042] Figure 5 An example is shown of a process for encoding data using ECC circuitry in a memory controller after receiving the data from a system controller.

[0043] Figure 6 An example is shown of a process for decoding data using ECC circuitry in a memory controller before sending the decoded data to a system controller.

[0044] Figure 7 An example memory system is shown that includes a system controller with strong ECC circuitry and a memory device with weak ECC circuitry.

[0045] Figure 8 An example is shown of a process for decoding data by a memory system. Figure 7

[0046] Figure 9 Another example memory system is shown that includes a system controller and a memory device with ECC circuitry and multiple memories.

[0047] REFERENCE NUMERALS

[0048] 100: system

[0049] 110, 700: memory system

[0050] 112: system controller

[0051] 113, 214, 314, 714, 914: processor

[0052] 114: internal memory

[0053] 116: memory device

[0054] 120: host device

[0055] 200, 300, 900: SSD

[0056] 202, 302, 702, 902: printed circuit board ​​

[0057] 204, 304, 704, 904: DRAM / memory device

[0058] 210, 310, 710, 910: SSD controller

[0059] 211, 213, 215, 311, 313, 315, 333, 333a, 333b, 711, 713, 715, 733, 733a, 733b, 911, 913, 915, 933: electrical connections

[0060] 212, 312, 712, 912: host interface

[0061] 216, 316, 716, 916: direct memory access controller

[0062] 218, 318, 718, 918: DRAM controller

[0063] 220, 220a, 220b, 334, 334a, 334b, 734, 734a, 734b, 934: flash controller

[0064] 222, 222a, 222b, 338, 338a, 338b, 938: ECC circuitry

[0065] 230, 230a, 230b, 330, 330a, 330b, 730, 730a, 730b, 930: flash memory / memory device

[0066] 320, 320a, 320b, 720, 720a, 720b, 920: flash data processor

[0067] 332, 332a, 332b, 732, 732a, 732b, 932, 932-1, 932-2, 932-n: flash memory

[0068] 322, 322a, 322b, 336, 336a, 336b, 722, 722a, 722b, 736, 736a, 736b, 922, 936: custom interface

[0069] 400: interface agreement

[0070] 500, 600, 800: process

[0071] 502, 504, 506, 508, 602, 604, 606, 801, 802, 804, 806, 807, 808, 810, 812, 814, 816: step

[0072] 738, 738a, 738b: weaker ECC circuitry

[0073] 724, 724a, 724b: stronger ECC circuitry. DETAILED DESCRIPTION

[0074] Figure 1 An example of a system 100 including a memory system 110 and a host device 120 is shown. The memory system 110 includes a system controller 112 and at least one memory device 116. The system controller 112 includes a processor 113 and an internal memory 114.

[0075] In some implementations, the memory system 110 is a storage system. For example, the memory system 110 can be an embedded Multi-Media Card (eMMC), a Secure Digital (SD) card, a Solid State Disk (SSD), or some other suitable storage system. In some implementations, the memory system 110 is a smart watch, a digital camera, or a media player. In some implementations, the memory system 110 is a client device coupled to a host device 120. For example, the memory system 110 is an SD card in a digital camera or a media player that is the host device 120.

[0076] The system controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some implementations, the system controller 112 is a controller for the memory system 110. The following sections describe various techniques based on implementations in which the system controller 112 is a memory system controller. However, the techniques described in the following sections are also applicable in implementations in which the system controller 112 is another type of controller different from a memory system controller.

[0077] The processor 113 is configured to execute instructions and process data. The instructions include firmware instructions and / or other program instructions stored in the internal memory 114 as firmware code and / or other program code, respectively. The data include program data corresponding to the firmware and / or other programs executed by the processor, as well as other suitable data. In some implementations, the processor 113 is a general-purpose microprocessor or an application-specific microcontroller. The processor 113 can also be referred to as a central processing unit (CPU).

[0078] The processor 113 accesses instructions and data from the internal memory 114. In some implementations, the internal memory 114 is a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM). For example, in some implementations, when the memory system 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some implementations, when the memory system 110 is a digital camera or a media player, the internal memory 114 is a DRAM.

[0079] In some implementations, the internal memory 114 is a cache memory included in the system controller 112, as illustrated in Figure 1 The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113, and / or data requested by the processor 113 during runtime.

[0080] The system controller 112 transfers instruction codes and / or data from the memory device 116 to the internal memory 114. In some implementations, the memory device 116 is a non-volatile memory device configured for long-term storage of instructions and / or data, such as a NAND flash memory device or some other suitable non-volatile memory device. In implementations where the memory device 116 is a NAND flash memory device, the memory system 110 is a flash memory device, such as a flash memory card, and the system controller 112 is a NAND flash controller. In some implementations, when the memory system 110 is an eMMC or an SD card, the memory device 116 is a NAND flash. In some implementations, when the memory system 110 is a digital camera, the memory device 116 is an SD card. In some implementations, when the memory system 110 is a media player, the memory device 116 is a hard disk.

[0081] For purposes of illustration, the following figures and corresponding descriptions use an SSD as an example memory system, such as the memory system 110 of Figure 1 , use an SSD controller as an example system controller, such as the system controller 112 of Figure 1 , and use a flash memory device as an example memory device, such as the memory device 116 of Figure 1 .

[0082] Figure 2 An example memory system, such as an SSD 200, is shown. The SSD 200 can be Figure 1The SSD 200 includes a system controller (e.g., SSD controller 210) and multiple memory devices including DRAM 204 and flash memory 230a and flash memory 230b (collectively referred to as flash memory 230 or individually referred to as flash memory 230). DRAM 204 has a faster response time than flash memory 230 and can be configured to store cached data for SSD controller 210 or flash memory 230.

[0083] Each of the memory devices 204 and 230 may be Figure 1 The memory device 116. Each of the memory devices 204 and 230 may be a die or a chip. The memory system 200 may be a multi-chip package formed on an electrical connection board (e.g., a printed circuit board (PCB) 202). The PCB 202 may include a shared bus that provides an electrical connection 213 between the SSD controller 210 and the memory devices 204 and 230, such that the SSD controller 210 can communicate with each of the memory devices 204 and 230.

[0084] like Figure 2 As shown, the SSD controller 210 includes components configured to connect to a host device (e.g., via an electrical connection 211) Figure 1 The host interface 212 communicates with the host device 120. Electrical connection 211 may also be provided by a shared bus. Electrical connection 211 may be the same as electrical connection 213. The host interface 212 may communicate with the host device according to an interface protocol (e.g., a bus interface protocol such as a non-interface protocol). The SSD controller 210 may receive read or write commands from the host device via the host interface 212 to read data from or write data to at least one of the memory devices 204 and 230.

[0085] In some implementation schemes, such as Figure 2 As shown, the SSD controller 210 includes a processor 214 and multiple controllers for the memory device. The processor 214 may be... Figure 1The memory controller includes a DRAM controller 218 and a flash controller 220a, a flash controller 220b (collectively, flash controllers 220 or individually, flash controller 220). The DRAM controller 218 is configured to communicate with the DRAM 204 and control data transfers between the SSD controller 210 and the DRAM 204. The flash controllers 220 are configured to communicate with the flash memory 230 and control data transfers between the SSD controller 210 and the flash memory 230. The SSD controller 210 can also include a memory access controller, such as a direct memory access (DMA) controller 216. The DMA controller 216 is configured to control data transfers between the SSD controller 210 and the memory devices 204, 230. For example, the DMA controller 216 can arbitrate data transfers to or from the memory devices 204, 230 according to criteria, such as priority.

[0086] The SSD controller 210 includes an internal bus coupled to components in the SSD controller 210, including the host interface 212, the processor 214, the DMA controller 216, the DRAM controller 218, and the flash controllers 220. Each of the components can be a chip, and the SSD controller 210 can be a multi-chip package configured on the PCB 202. The internal bus provides electrical connections 215 for the components so that the components can communicate with each other via the electrical connections 215. The internal bus in the SSD controller 210 is different from the shared bus on the PCB 202. The electrical connections 215 in the SSD controller 210 can have lower impedance, such as lower resistance or lower capacitance, or both, than the electrical connections 211, 213 on the PCB 202. As a result, the electrical connections 215 incur less operational power consumption than the electrical connections 211, 213.

[0087] In some embodiments, as Figure 2As shown in FIG. 1, each flash controller 220a, 220b includes ECC circuitry 222a, 222b (collectively, ECC circuitry 222 or individually, ECC circuitry 222). The ECC circuitry 222 can include an ECC encoder and an ECC decoder. The ECC circuitry 222 can be implemented based on an ECC scheme, such as a Reed Solomon code scheme, a Bose-Chaudhuri-Hocquenghem (BCH) code scheme, a low-density parity check (LDPC) code scheme, a Turbo Code scheme, or any combination thereof.

[0088] The flash controller 220 can receive data to be stored into the corresponding flash memory 230 from the host device, e.g., via the host interface 212. The ECC encoder in the flash controller 220 can then be configured to generate a codeword by encoding the data, e.g., by using an ECC encoding scheme. In some examples, the flash controller 220 receives a K-bit data word, and the ECC encoder can encode the K-bit data word into an N-bit codeword, where N = K + P, and P is the number of parity bits for the K-bit data word. The flash controller 220 can then store (e.g., program or write) the N-bit codeword into the corresponding flash memory 230 via the electrical connections 213 on the PCB 202.

[0089] The flash controller 220 can also receive encoded data (e.g., codewords) from the corresponding flash memory 230 via the electrical connections 213 on the PCB 202, and the ECC decoder in the flash controller 220 can be configured to decode the encoded data to detect and correct (up to the error correction capability of the ECC scheme) any bit errors that can exist in the data. If the ECC decoder is unable to correct a threshold count of bit errors in the encoded data, it indicates that the result of decoding the encoded data fails the ECC decode test or the ECC decoder fails to decode the encoded data. If the ECC decoder is able to correct bit errors in the encoded data, it indicates that the encoded data passes the ECC test or the ECC decoder successfully decodes the encoded data, and the encoded data is decoded to become decoded data (e.g., a data word). The flash controller 220 can then send the decoded data to the host device, e.g., via the host interface 212. In some examples, the flash controller 220 receives an N-bit codeword including P parity bits for a K-bit data word from the corresponding flash memory 230 via the electrical connections 213 on the PCB 202. The ECC decoder in the flash controller 220 can decode the N-bit codeword to obtain the K-bit data word in the SSD controller 210.

[0090] In some implementations, if the result of decoding the encoded data fails the ECC decoding test, the flash controller 220 can perform a soft decision decoding algorithm, for example, to decode the encoded data from the soft bits read from the corresponding flash memory 230. The number of soft bits (e.g., m) determines the number of read operations from the corresponding flash memory 230. For example, for an N-bit codeword, the total number of bits read from the corresponding flash memory 230 can be N*(l+m) bits. This means that a large number of bits are transferred via electrical connections on the PCB 202, which can result in large power consumption.

[0091] In some implementations, the SSD controller 210 operates at a high frequency with high throughput, for example, for multi-channel flash memory access, which can result in high power consumption and high operating temperature of the SSD 200.

[0092] Figure 3 An example memory system, for example, an SSD 300, is shown that addresses the above-mentioned high power consumption and / or high operating temperature issues, for example, by removing the ECC encoding capability from the system controller to the memory device.

[0093] Similar to the SSD 200 of Figure 2 The SSD 300 includes an SSD controller 310 and a plurality of memory devices including a DRAM 304 (e.g., the DRAM 204 of Figure 2 ) and flash memory devices 330a, 330b (collectively, flash memory 330 or individually, flash memory 330). The SSD 300 can be the memory system 110 of Figure 1 The SSD controller 310 can be the system controller 112 of Figure 1 and the memory devices 304, 330 can be the memory devices 116 of Figure 1 .

[0094] The SSD controller 310 and the memory devices 304, 330 can be configured on an electrical connection board (e.g., a PCB 302). The PCB 302 can be the PCB 202 of Figure 2 The PCB 302 can include a shared bus. The SSD controller 310 can communicate with each of the memory devices 304, 330 through electrical connections 313 provided by the shared bus on the PCB 302. The memory devices 304, 330 can also communicate with each other via the shared bus. For example, the DRAM 304 can communicate with at least one of the flash memories 330 via the shared bus without going through the SSD controller 310.

[0095] SSD controller 310 is configured to execute instructions (e.g., firmware instructions) and control the overall operation of SSD 300. Similar to... Figure 2 The SSD controller 210 and SSD controller 310 may include a host interface 312, for example, Figure 2 The host interface 212, the host interface 312 being configured to be connected via an electrical connection 311 (e.g., Figure 2 Electrical connection 211) and host device (e.g., Figure 1 The SSD controller 310 communicates with the host device 120. Electrical connection 311 may be the same as electrical connection 313 and is provided by a shared bus of PCB 302. Host interface 312 may communicate with the host device according to an interface protocol (e.g., a bus interface protocol or a non-interface protocol). SSD controller 310 may receive read or write commands from the host device via host interface 312 to read data from or write data to at least one of the memory devices 304 and 330.

[0096] In addition, similar to Figure 2 The SSD controller 210 includes a processor 314, a DMA controller 316, and a DRAM controller 318. The processor 314 can be... Figure 1 The processor 113. The DRAM controller 318 is configured to communicate with the DRAM 304 and control data transfer between the SSD controller 310 and the DRAM 304. The DRAM controller 318 may be similar to... Figure 2 The DRAM controller 218. The DMA controller 316 may be similar to... Figure 2 The DMA controller 216 is configured to control data transfers between the SSD controller 310 and the memory devices 304 and 330. For example, the DMA controller 316 can arbitrate data transfers to or from the memory devices 304 and 330 based on criteria (e.g., priority).

[0097] The SSD controller 310 may also include an internal bus coupled to components within the SSD controller 310. Each component may be a die or a chip, and the SSD controller 310 may be a multi-chip package configured on a PCB 302. The internal bus provides electrical connections 315 to the components, for example, Figure 2The electrical connections 215 of the SSD 200 enable the components to communicate with each other via the electrical connections 315. The internal buses in the SSD controller 310 are different from the shared buses on the PCB 302. The electrical connections 315 in the SSD controller 310 can have lower impedance, e.g., lower resistance or lower capacitance or both, than the electrical connections 311, 313 on the PCB 302. As a result, the electrical connections 315 cause less operational power consumption than the electrical connections 311, 313.

[0098] Unlike the SSD 200, Figure 2 The SSD 300 removes the ECC circuit from the SSD controller 310 and includes the ECC circuit in the flash memory devices 330. As shown in Figure 3 Each flash memory device 330a, 330b includes flash memory 332a, 332b (collectively, flash memory 332 or individually, flash memory 332) and a flash controller 334a, 334b (collectively, flash controller 334 or individually, flash controller 334), as shown in Figure 2 The flash memory 332 can be the flash memory 230.

[0099] Each flash memory and each flash controller of the flash memory 332 and the flash controller 334 can be a die or a chip, and the flash memory 330b can be a multi-chip package configured on the PCB 302. The flash memory 332 and the flash controller 334 in the flash memory device 330 can be coupled to each other via electrical connections 333a, 333b (collectively, electrical connections 333 or individually, electrical connections 333) in the flash memory device 330. The electrical connections 333 can be metal wires or metal balls. The electrical connections 333 can have the same or less impedance than the electrical connections 315 in the SSD controller 310. The electrical connections 333 in the flash memory device 330 can have substantially less impedance than the electrical connections 313 on the PCB 302. The electrical connections 333 can have substantially less area or size than the electrical connections 313. As a result, transferring the same amount of data via the electrical connections 333 in the flash memory device 330 can cause less power consumption and heat than via the electrical connections 313 on the PCB 302.

[0100] Each flash controller 334a, 334b includes a custom interface 336a, 336b (collectively, custom interfaces 336 or individually, custom interface 336) and an ECC circuit 338a, 338b (collectively, ECC circuits 338 or individually, ECC circuit 338). The custom interface 336 is configured to enable the flash controller 334 or the flash memory device 330 to communicate with the SSD controller 310 and transfer data between the flash memory device 330 or the flash memory 332 and the SSD controller 310. The ECC circuit 338 is configured to compute ECC bits for data received from at least one of the SSD controller 310 or the flash memory 332. The ECC circuit 338 can be similar to the ECC circuit 222 of FIG. 2. Figure 2 In some implementations, the ECC circuit 338 includes an ECC encoder and an ECC decoder. The ECC circuit 338 can be implemented based on an ECC scheme, such as a Reed-Solomon code scheme, a Bose-Chaudhuri-Hocquenghem (BCH) code scheme, a Low-Density Parity-Check (LDPC) code scheme, a Turbo code scheme, or any combination thereof. As discussed in more detail below, an ECC decoder (e.g., an LDPC decoder) can perform hard-decision decoding or soft-decision decoding or both, for example, based on input data log-likelihood ratio (LLR) reliabilities.

[0101] For each flash memory device 330a, 330b, the SSD controller 310 includes an individual flash data processor 320a, 320b (collectively, flash data processors 320 or individually, flash data processor 320). Each flash data processor 320 can be an individual die or chip packaged in the SSD controller 310. The flash data processor 320 is different from the flash data processor 220 of FIG. 2. Figure 2The flash data processors 320 are configured to buffer data to or from the corresponding flash memory devices 330 and / or process data to or from the corresponding flash memory devices 330. For example, the flash data processors 320 can perform one or more operations including data encryption, data randomization, and data scrambling. Each flash data processor 320 can include a customized interface 322a, a customized interface 322b (collectively, customized interfaces 322 or individually, a customized interface 322). The customized interfaces 322 in the flash data processors 320 correspond to the customized interfaces 336 in the flash controllers 334 and are configured to transfer data between the flash data processors 320 or the SSD controller 310 and the flash controllers 334 or the flash memory devices 330.

[0102] The customized interfaces 322 in the SSD controller 310 and the customized interfaces 336 in the flash memory devices 330 can communicate with each other according to an interface agreement. The interface agreement can be implemented in any suitable format and with any suitable number of pins. In some examples, the interface agreement can be the same as a flash interface agreement (e.g., different from a non-flash interface agreement). In some examples, the number of pins in the interface agreement can be less than the number of pins of the flash interface agreement. In some examples, the interface agreement can be a high-speed communication agreement, such as a communication agreement with a serializer / deserializer (SerDes).

[0103] Figure 4 An example interface agreement 400 for the customized interfaces 322, 336 of the SSD controller 310 and the flash memory devices 330 is shown. Figure 3 The interface agreement 400 can have at least one of the pins including IO pins for data input / output (I / O) ports, DQS pins for data strobe (e.g., for double data rate (DDR) mode), a CE# pin for chip enable, an ALE pin for address latch enable, a CLE pin for command latch enable, a WE# pin for write enable, a RE# pin for read enable, a WP# pin for write protect, and a R / B# pin for ready / busy status. Each of the customized interfaces 322, 336 can have the same type of pins coupled to each other via the electrical connections 313 on the PCB 302.

[0104] Referring back to Figure 3 Unlike the error correction encoding in the SSD controller 210, the error correction encoding in the SSD controller 310 is performed by the flash data processors 320.Figure 2 The SSD 300 is configured to perform ECC error correction encoding in the flash memory devices 330 (as shown in more detail in Figure 5 and Figure 6 ), which can reduce the amount of data transfer via the PCB 302 (e.g., via the electrical connections 313).

[0105] Figure 5 An example of a process 500 performed by a memory system (e.g., the SSD 300 of the system 100) is shown. In the process 500, the memory system encodes data using ECC circuitry (e.g., the ECC circuitry 338 of the SSD 300) in a memory controller (e.g., the flash controller 334 of the SSD 300) of a memory device (e.g., the flash memory device 330 of the SSD 300) after receiving the data from a system controller (e.g., the SSD controller 310 of the system 100). Figure 3 Figure 3 Figure 3 Figure 3 Figure 3

[0106] At 502, the system controller obtains a K-bit data word. The K-bit data word can be obtained from a host device (e.g., the host device 120 of the system 100) via a host interface (e.g., the host interface 312 of the system 100). The host device can send a write command for storing the K-bit data word in the memory device. The write command can include a logical address for storing the K-bit data word. The system controller can include a processor (e.g., the processor 314 of the system 100) configured to process the write command to determine a corresponding physical address mapped with the logical address. The system controller can also include a data processor (e.g., the flash data processor 320 of the system 100) configured to buffer and / or process the K-bit data word, for example, by performing data encryption, data randomization, and data scrambling. The system controller can send the K-bit data word to the memory device based on the determined physical address associated with the write command. Figure 3 Figure 1 Figure 3 Figure 3

[0107] At 504, the system controller sends the K-bit data word to the memory controller in the memory device via a first type of electrical connection (e.g., the electrical connections 313 on the PCB 302 of the system 100). The system controller and the memory controller can communicate via a customized interface (e.g., the customized interface 322 and the customized interface 336) according to an interface agreement (e.g., the interface agreement 400 of the system 100). Figure 3 Figure 4

[0108] ​​​​​​​​​​​At 506, the ECC circuit in the memory controller encodes a K-bit data word to obtain an N-bit codeword, where N = K + P, and P is a number of parity bits for the K-bit data word.

[0109] At 508, the memory controller programs (or writes) the N-bit codeword to at least one memory in the memory device via a second type of electrical connection (e.g., electrical connections 333 in the flash memory device 330 of the SSD 300), Figure 3 The second type of electrical connection can have substantially less impedance than the first type of electrical connection. Thus, in operation, the second type of electrical connection causes substantially less power consumption and / or heat than the first type of electrical connection. Figure 3

[0110] In the process 500, the ECC encoding is after data transfer via the first type of electrical connection, where only the K-bit data word is transferred from the system controller to the memory device via the first type of electrical connection. In contrast, in the SSD 200, Figure 2 the ECC encoding is before data transfer via the first type of electrical connection, where the N-bit codeword is transferred from the system controller to the memory device via the first type of electrical connection. For example, if the ECC encoding is implemented with an LDPC encoding scheme, the code rate K / N can be equal to 0.9, which means that 10% of data transfer via the first type of electrical connection can be reduced. Thus, compared to the SSD 200, Figure 2 the SSD 300 enables reducing the amount of data transfer via the first type of electrical connection, which reduces power consumption. In addition, moving the ECC circuit from the system controller to the memory device can reduce power supply in the memory controller, which can increase heat dissipation and reduce operating temperature. Figure 3

[0111] Referring back to Figure 3 , the ECC decoder in the ECC circuit 338 can be an LDPC decoder configured to perform a hard-decision decoding algorithm or a soft-decision decoding algorithm or both, e.g., based on input data log-likelihood ratio (LLR) reliabilities. The LLR reliabilities can be associated with threshold voltage variations of stored bits, e.g., due to read interference or any other memory reliability effects.

[0112] In a hard-decision decoding algorithm, the ECC decoder is configured to assign an LLR to each input bit before decoding. The sign (+ or -) of the LLR is determined by the hard bit value (1 or 0), and the value of the LLR means a reliability level. For example, as shown in Table 1 below, data bit 1 maps to -7 for the LLR, and data bit 0 maps to +7 for the LLR.

[0113] Table 1. Hard-decision decoding​​

[0114]

[0115] In soft decision decoding algorithms, the ECC decoder is configured to assign one or more LLR options, e.g., 4 LLR options, for each data bit prior to decoding. With more LLR options, the correction capability of the ECC decoder can be optimized.

[0116] Table 2. 1-bit soft decision decoding

[0117]

[0118] For example, as illustrated in Table 2, a hard bit corresponds to 4 LLR options. If the hard bit has a value of 1, the hard bit corresponds to two soft bits of 1 and 0 each associated with individual LLR options of -5 and -2. If the hard bit has a value of 0, the hard bit corresponds to two soft bits of 0 and 1 each associated with individual LLR options of +2 and +5. Soft bit 0 means a higher error rate (and thus a lower reliability level, such as -2 or +2), and soft bit 1 means a lower error rate (and thus a higher reliability level, such as -5 or +5). Thus, to decode each data bit in a codeword as 1 or 0, the data bit can be read from memory 4 times, e.g., with a series of sequential read voltages, based on the number of LLR options (or the number of soft bits corresponding to the data bit), which can optimize the correction capability of the ECC decoder. Each data bit in a codeword has the same number of LLR options or soft bits.

[0119] In operation, the flash controller 334 receives a codeword (e.g., encoded data) read from the flash memory 332 via electrical connections 333 in the flash memory device 330. An ECC decoder in the ECC circuit 338 of the flash controller 334 is configured to decode the codeword to detect and correct (up to the error correction capability of the ECC scheme) any bit errors that can be present in the codeword. If the ECC decoder is unable to correct a threshold count of bit errors in the codeword, it indicates that the result of decoding the codeword fails the ECC decode test or the ECC decoder fails to decode the codeword. If the ECC decoder is able to correct bit errors in the codeword, it indicates that the codeword passes the ECC decode test, and the codeword is decoded to become decoded data (e.g., a data word). The flash controller 334 can then send the decoded data to the SSD controller 310 via electrical connections 313 on the PCB 302.

[0120] If the codeword fails the ECC decoding test, the flash controller 334 can perform a soft-decision decoding algorithm, such as decoding the soft bits of the codeword read from the flash memory 332. The number of soft bits (e.g., m) of each data bit in the codeword determines the number of read operations from the flash memory 332. For example, for an N-bit codeword, the number of bits read from the flash memory 332 can be N*m bits according to the soft-decision decoding algorithm. Together with the number of bits read in the hard-decision decoding algorithm, the total number of bits read from the flash memory 332 can be N*(1+m) bits to the flash controller 334 in the flash memory device 330.

[0121] Figure 6 This illustrates the role of memory systems (e.g., Figure 3 An example of process 600 performed by the SSD 300. In process 600, the memory system sends data to the system controller (e.g., SSD 300). Figure 3 The SSD controller 310) previously used a memory device (e.g., Figure 3 The memory controller of the flash memory device 330 (e.g., Figure 3 The ECC circuit in the flash controller 334 (e.g., Figure 3 The ECC circuit 338 is used to decode the data. The ECC circuit is configured to decode according to the hard-decision decoding algorithm and the soft-decision decoding algorithm as described above.

[0122] At 602, the memory controller obtains the hard-decision decoding algorithm and the soft-decision decoding algorithm from at least one memory in the memory device (e.g., Figure 3 The flash memory 332 reads an N-bit codeword (1+m) times, where m represents the number of soft bits or LLR options for each bit in the N-bit codeword. That is, there exists a connection via internal electrical connections within the memory device (e.g., Figure 3 The total number of N*(1+m) bits transferred from the memory to the memory controller via electrical connections 333 in the flash memory device 330.

[0123] At position 604, the ECC circuit in the memory controller decodes the N-bit codeword to obtain the K-bit data word, where N = K + P, and P is the corresponding bit used for the K-bit data word.

[0124] At 606, the memory controller is connected to the memory device via an external electrical connection between the system controller and the memory device (e.g., Figure 3 Electrical connection 313 on PCB 302 sends a K-bit data word to the system controller. The external electrical connection between the system controller and the memory device has substantially greater impedance than the internal electrical connection in the memory device.

[0125] In process 600, ECC decoding occurs before data transmission via an external electrical connection, where only K-bit data words (decoded data) are transferred from the memory device to the system controller via the external electrical connection. In contrast, in... Figure 2 In the SSD200, as discussed above, ECC decoding occurs after data transmission via external electrical connection, where (K+P)(1+m) bits are transferred from the memory device to the system controller via external electrical connection. Therefore, compared to Figure 2 SSD 200, Figure 3 The SSD300 enables a reduction in data transfers via external electrical connections by significantly reducing power consumption of the memory system or system controller. Specifically, for multi-channel memory access, the system controller operates at high throughput at high frequencies, and compared to the SSD 200, the SSD 300 significantly reduces power consumption and increases heat dissipation.

[0126] Higher ECC encoding capabilities may require a larger ECC circuit area, which could affect the packaging of the ECC circuit within the memory device. In some implementations, the memory system may separate the ECC encoding capability between the system controller and the memory controller within the memory device. In this way, the ECC circuit within the memory device can be smaller, which can be beneficial for packaging the memory device. For example, the system controller may have higher processing power than the memory device. The system controller may include stronger ECC circuitry configured for high error bit count frames, and the memory controller within the memory device may include weaker ECC circuitry configured for lower error bit count frames.

[0127] Figure 7 An example memory system 700 is shown, comprising a system controller with strong ECC circuitry and memory devices with weaker ECC circuitry. The system controller (e.g., an SSD controller 710) and memory devices (e.g., DRAM 704 and flash memory devices 730a and 730b) are collectively referred to as flash memory 730 or individually as flash memory 730. The SSD 700 may be... Figure 1 The memory system 110 and SSD controller 710 can be Figure 1 The system controller 112, and the memory device 704 and memory device 730 can be Figure 1 The memory device 116. Similar to... Figure 3 The SSD 300, SSD controller 710, and memory devices 704 and 730 can be configured on an electrical connection board (e.g., PCB 702). PCB 702 can be... Figure 3PCB 302. The PCB 702 can include a shared bus. The SSD controller 710 can communicate with each of the memory devices 704, 730 through electrical connections 713 provided by the shared bus on the PCB 702.

[0128] Similar to the SSD controller 310 of Figure 3 , the SSD controller 710 can include a host interface 712, e.g., Figure 3 , the host interface 312, configured to communicate with a host device, e.g., Figure 3 , the host device 120, via electrical connections 711, e.g., Figure 1 , the electrical connections 311. The electrical connections 711 can be the same as the electrical connections 713 and provided by the shared bus of the PCB 702. The host interface 712 can communicate with the host device according to an interface agreement, e.g., a bus interface agreement such as a nonvolatile memory express interface agreement.

[0129] Also similar to the SSD controller 310 of Figure 3 , the SSD controller 710 includes a processor 714, a DMA controller 716, and a DRAM controller 718. The processor 714 can be the processor 113 of Figure 1 . The DRAM controller 718 is configured to communicate with the DRAM 704 and control data transfers between the SSD controller 710 and the DRAM 704. The DRAM controller 718 can be the DRAM controller 318 of Figure 3 . The DMA controller 716 can be configured to control data transfers between the SSD controller 710 and the memory devices 704, 730. For example, the DMA controller 716 can arbitrate data transfers to or from the memory devices 704, 730 according to criteria, e.g., priority.

[0130] The SSD controller 710 can also include an internal bus coupled to components in the SSD controller 710. Each of the components can be a chip, and the SSD controller 710 can be a multi-chip package configured on the PCB 702. The internal bus provides electrical connections 715, e.g., Figure 3 , the electrical connections 315, so that the components can communicate with each other via the electrical connections 715. The internal bus in the SSD controller 710 is different from the shared bus on the PCB 702. The electrical connections 715 in the SSD controller 710 can have lower impedance, e.g., lower resistance or lower capacitance or both, than the electrical connections 711, 713 on the PCB 702. As a result, the electrical connections 715 cause less operational power consumption than the electrical connections 711, 713.

[0131] As Figure 7As shown in FIG. 7, each flash memory device 730a, 730b includes flash memory 732a, 732b (collectively, flash memory 732 or individually, flash memory 732), a flash controller 734a, and a flash controller 734b (collectively, flash controller 734 or individually, flash controller 734). The flash memory 732 can be Figure 3 the flash memory 332 of the SSD 300, or Figure 2 the flash memory 230 of the SSD 200.

[0132] Each of the flash memory and each of the flash controller in the flash memory 732 and the flash controller 734 can be a die or a chip, and the flash memory device 730 can be a multi-chip package configured on the PCB 702. The flash memory 732 and the flash controller 734 in the flash memory device 730 can be coupled to each other via electrical connections 733a, 733b (collectively, electrical connections 733 or individually, electrical connections 733) in the flash memory device 730. The electrical connections 733 can be Figure 3 the electrical connections 333. The impedance of the electrical connections 733 can be the same as or less than the impedance of the electrical connections 715 in the SSD controller 710. The impedance of the electrical connections 733 in the flash memory device 730 can be substantially less than the impedance of the electrical connections 713 on the PCB 702. Thus, transferring the same amount of data via the electrical connections 733 in the flash memory device 730 can cause less power consumption and heat than via the electrical connections 713 on the PCB 702.

[0133] Unlike the SSD 300 of Figure 3 the SSD 200, the SSD 700 includes ECC circuitry in both the SSD controller 710 and the flash controller 734 in the flash memory device 730. The flash controller 734 can include weaker ECC circuitry for hard-decision decoding algorithms for low error bit count frames, and the SSD controller 710 can include stronger ECC circuitry for hard-decision decoding algorithms and / or soft-decision decoding algorithms for high error bit count frames.

[0134] For example, a weaker ECC circuit can perform a weaker decoding algorithm, such as a bit-flipping related algorithm. A stronger ECC circuit can perform a stronger decoding algorithm, such as a min-sum related algorithm. The weaker ECC circuit can have a smaller area than the stronger ECC circuit. Table 3 is an example of characteristics of ECC circuits (e.g., 4 KB LDPC based circuits) implementing a min-sum related algorithm and a bit-flipping related algorithm. It is shown that for hard decision decoding, the bit-flipping related algorithm can achieve a frame error rate (FER) of 10"3at 200 error bits per 4 KB frame 200, while the min-sum algorithm can achieve a FER of 10"8at 240 bits per 4 KB frame. Further, the min-sum algorithm can perform 1-bit soft decision decoding to achieve a FER of 10"8at 480 bits per 4 KB frame. The ECC circuit implementing the bit-flipping related algorithm can have an area that is 5 times smaller than the area of the ECC circuit implementing the min-sum related algorithm.

[0135] Table 3 ECC circuit characteristics under different algorithms

[0136]

[0137] As shown in Figure 7 Each flash controller 734a, 734b includes a custom interface 736a, 736b (collectively, custom interfaces 736 or individually, custom interface 736) and a weaker ECC circuit 738a, 738b (collectively, weaker ECC circuits 738 or individually, weaker ECC circuit 738). The custom interface 736 is configured to enable the flash controller 734 or the flash memory device 730 to communicate with the SSD controller 710 and transfer data between the flash memory device 730 or the flash memory 732 and the SSD controller 710. The weaker ECC circuit 738 is configured to compute ECC bits for data received from at least one of the SSD controller 710 or the flash memory 732. The weaker ECC circuit 738 includes an ECC encoder and an ECC decoder. The weaker ECC circuit 338 can be implemented based on an ECC scheme, such as a Reed-Solomon code scheme, a Bose-Chaudhuri-Hocquenghem (BCH) code scheme, a Low-Density Parity-Check (LDPC) code scheme, a Turbo code scheme, or any combination thereof. As discussed above, the weaker ECC circuit 738 can perform a weaker decoding algorithm that only performs hard decision decoding, such as a bit-flipping related algorithm. In this way, the weaker ECC circuit 738 can have a smaller area size.

[0138] Similar to Figure 3The SSD controller 310 includes individual flash data processors 720a and 720b (collectively referred to as flash data processor 720 or individually referred to as flash data processor 720) for each flash memory device 730a and 730b. Each flash data processor 720 may include customized interfaces 722a and 722b (collectively referred to as customized interface 722 or individually referred to as customized interface 722). The customized interface 722 in the flash data processor 720 corresponds to the customized interface 736 in the flash controller 734 and is configured to transfer data between the flash data processor 720 or SSD controller 710 and the flash controller 734 or flash memory device 730. The customized interface 322 in the SSD controller 310 and the customized interface 336 in the flash memory device 330 may be configured according to an interface protocol (e.g., ...). Figure 4 The interface protocol 400 communicates with each other. The interface protocol 400 can be implemented in any suitable format and with any suitable number of pins. In some instances, the interface protocol 400 may be the same as a flash interface protocol (e.g., with a non-flash interface protocol). In some instances, the interface protocol 400 may have a fewer pins than a flash interface protocol. In some instances, the interface protocol 400 may be a high-speed communication protocol, such as a communication protocol with a serializer / deserializer (SerDes).

[0139] Unlike Figure 3 The SSD controller 310 and SSD controller 710 include, in each flash data processor 720a and flash data processor 720b corresponding to flash memory devices 730a and 730b, strong ECC circuitry 724a and 724b (collectively referred to as strong ECC circuitry 724 or individually referred to as strong ECC circuitry 724). In addition to buffering data to or from flash memory device 730, and / or processing data to or from flash memory device 730, the flash data processor 720 may also use the strong ECC circuitry 724 for error correction coding. The flash data processor 720 may be implemented as a die or chip packaged within the SSD controller 710.

[0140] In some implementations, the stronger ECC circuit 724 includes an ECC encoder and an ECC decoder. In some implementations, the stronger ECC circuit 724 may include only an ECC decoder. The stronger ECC circuit 724 may be implemented based on an ECC scheme, such as the Reed-Solomon code scheme, the Bosch-Joher-Hokungamme (BCH) code scheme, the Low-Density Parity Pairing (LDPC) code scheme, the Turbo code scheme, or any combination thereof. As discussed above, the stronger ECC circuit 724 may perform stronger decoding algorithms, such as the minimum and correlation algorithm, which may perform both hard-decision decoding and soft-decision decoding. The stronger ECC circuit 724 may perform hard-decision decoding or soft-decision decoding, or both, for example, based on the reliability of the input data log-likelihood ratio (LLR).

[0141] Figure 8 Showing the use of by Figure 7 An example of a process 800 for decoding data in a memory system 700. Process 800 begins, for example, at 801 by receiving a read command from a host device via a host interface 712. The read command instructs the reading of an N-bit codeword from at least one flash memory 732.

[0142] At 802, the flash controller 734 obtains (e.g., reads) an N-bit codeword from flash memory 732 via internal electrical connection 733 in flash memory device 730. The weaker ECC circuit 738 then decodes the N-bit codeword according to a weaker decoding algorithm, such as a bit-transformation correlation algorithm.

[0143] At 804, the flash controller 734 determines whether the result of decoding the N-bit codeword is a pass of the ECC test by the weaker ECC circuit 738 or whether the weaker ECC circuit 738 fails to decode the N-bit codeword. The determination may include determining whether erroneous bits in the N-bit codeword can be corrected by the corresponding bits in the N-bit codeword via the weaker ECC circuit 738.

[0144] If the flash controller 734 determines that the N-bit codeword passes the ECC test and is decoded to obtain a K-bit data word, then at 806, the flash controller sends the K-bit data word to the flash data processor 720 in the SSD controller 710 via the external electrical connection 713 on the PCB 702. The flash data processor 720 does not need to use the stronger ECC circuit 724 to perform any decoding, and process 800 ends at step 807. The SSD controller 710 can then send the decoded K-bit data word to the host device via the host interface 712 in response to a read command.

[0145] If the flash controller 734 determines that the result of decoding the N-bit codeword fails the ECC test of the weaker ECC circuit 738 or the weaker ECC circuit 738 fails to decode the N-bit codeword, at 808, the flash controller 734 sends the N-bit codeword to the SSD controller 710, e.g., the flash data processor 720, via the external electrical connection 713 on the PCB 702. The stronger ECC circuit 724 in the flash data processor 720 then decodes the N-bit codeword according to a stronger decoding algorithm, e.g., the min-sum related algorithm. The decoding of the N-bit codeword is hard-decision decoding.

[0146] At 810, the SSD controller 710, e.g., the flash data processor 720, determines whether the result of decoding the N-bit codeword passes the ECC test of the stronger ECC circuit 724 or the stronger ECC circuit 724 can decode the N-bit codeword. If the N-bit codeword passes the ECC test and is decoded by the stronger ECC circuit 724 to obtain a K-bit data word, the process 800 ends at step 807. The SSD controller 710 can then send the decoded K-bit data word to the host device via the host interface 712 in response to a read command.

[0147] If the N-bit codeword fails the ECC test, at 812, the SSD controller 710 informs the flash controller 734 to read the N-bit codeword with soft bits from the flash memory 732, e.g., by sending a request to the flash controller 734. The number of soft bits for each data bit in the N-bit codeword determines the number of times the N-bit codeword is read from the flash memory 732, e.g., by a corresponding series of sequential read voltages.

[0148] At 814, the flash controller 734 sends the soft bits of the N-bit codeword directly to the SSD controller 710, e.g., the flash data processor 720, via the electrical connection 713 on the PCB 702, bypassing the weaker ECC circuit 738. That is, the weaker ECC circuit 738 does not perform any decoding on the soft bits of the N-bit codeword.

[0149] At 816, the stronger ECC circuit 724 in the flash data processor 720 decodes the soft bits of the N-bit codeword, e.g., according to the min-sum related algorithm, to obtain a K-bit data word. The decoding is soft-decision decoding. The process 800 then ends at step 807. The SSD controller 710 can then send the decoded K-bit data word to the host device via the host interface 712 in response to a read command.

[0150] In some implementations, the SSD controller 710 receives a write command from the host device via the host interface 712. The write command indicates that a K-bit data word is to be stored in the flash memory 732. The SSD controller 710 (e.g., the flash data processor 720) can send the K-bit data word directly to the flash controller 734 in the corresponding flash memory device 730 that includes the flash memory 732, thereby bypassing the stronger ECC circuit 724. The flash controller 734 can encode the K-bit data word using the weaker ECC circuit 738 to obtain an N-bit codeword. The flash controller 734 can then program or write the N-bit codeword in the flash memory 732. In some implementations, if the weaker ECC circuit 738 does not have the capability to encode the K-bit data word, the SSD controller 710 can use the stronger ECC circuit 724 to encode the K-bit data word to obtain an N-bit codeword, and then send the N-bit codeword to the flash controller 734 for storage in the flash memory 732.

[0151] Figure 9 Another example memory system, such as the SSD 900, is shown that includes a system controller (e.g., the SSD controller 910) and memory devices (e.g., the DRAM 904 and the flash memory device 930). The SSD 900 can be a memory system 110 of Figure 1 , the SSD controller 910 can be a system controller 112 of Figure 1 , and the memory device 930 can be a memory device 116 of Figure 1 .

[0152] The SSD 900 is similar to the SSD 300 of Figure 3 or the SSD 700 of Figure 7 except that the SSD 900 provides the flash memory device 930 with multiple flash memories 932-1, 932-2,..., 932-n (collectively, the flash memories 932 or individually, a flash memory 932) instead of providing each flash memory with a flash controller having an ECC circuit (e.g., as shown in Figure 3 and Figure 7 .

[0153] The flash memory device 930 includes a flash controller 934 having an ECC circuit 938 configured to perform error correction encoding on at least one of the flash memories 932. The flash controller 934 can also include a customized interface 936 configured to communicate with the SSD controller 910, such as the customized interface 336 of Figure 3 or the customized interface 736 of Figure 7customization interface 736. The flash controller 934 can be implemented as a die or a chip. Each flash memory 932 can be an individual die or chip. The flash controller 934 and the flash memories 932 can be packaged in a flash memory device 930. The flash memory device 930 can include internal electrical connections 933 coupling the flash controller 934 to each of the flash memories 932, for example Figure 3 the electrical connections 333 or Figure 7 the electrical connections 733.

[0154] Similar to the SSD 300 of Figure 3 or the SSD 700 of Figure 7 , the SSD controller 910 and the memory devices 904, 930 can be configured on an electrical connection board (e.g., a PCB 902). The PCB 902 can be the PCB 302 of Figure 3 or the PCB 702 of Figure 7 . The PCB 902 can include a shared bus. The SSD controller 910 can communicate with each of the memory devices 904, 930 through electrical connections 913 provided by the shared bus on the PCB 902.

[0155] Similar to the SSD controller 310 of Figure 3 or the SSD controller 710 of Figure 7 , the SSD controller 910 includes a host interface 912, for example, Figure 3 the host interface 312 of Figure 7 or the host interface 712 of Figure 1 . The host interface 912 can be configured to communicate with a host device (e.g., the host device 120) via electrical connections 911 (e.g., Figure 3 the electrical connections 311 of Figure 7 or the electrical connections 711 of . The host interface 912 can communicate with the host device according to an interface agreement (e.g., a bus interface agreement such as a non-volatile interface agreement).

[0156] Figure 1 Also similar to the SSD controller 310 of Figure 3 or the SSD controller 710 of Figure 7 , the SSD controller 910 includes a processor 914, a DMA controller 916, and a DRAM controller 918. The processor 914 can be the processor 113 of Figure 3 . The DRAM controller 918 is configured to communicate with the DRAM 904 and control data transfer between the SSD controller 910 and the DRAM 904. The DRAM controller 918 can be the DRAM controller 318 of Figure 7 . The DMA controller 916 is configured to communicate with the memory devices 904, 930 and control data transfer between the SSD controller 910 and the memory devices 904, 930. The DMA controller 916 can be the DMA controller 316 ofDRAM controller 718. DMA controller 916 can be configured to control data transfers between SSD controller 910 and memory devices 904, memory devices 930. In some implementations, flash memory devices 930 (e.g., flash controller 934) include a DMA controller that can arbitrate data transfers to or from multiple flash memories 932 according to criteria (e.g., priority).

[0157] SSD controller 910 can also include an internal bus coupled to components in SSD controller 910. Each of the components can be a chip, and SSD controller 910 can be a multi-chip package configured on PCB 902. The internal bus provides electrical connections 915, e.g., Figure 3 electrical connections 315, or Figure 4 electrical connections 715, so that the components can communicate with each other via electrical connections 915.

[0158] SSD controller 910 includes a flash data processor 920 for flash memory devices 930. In some implementations, flash data processor 920 can be similar to Figure 7 flash data processor 320, and can be configured to buffer data to or from flash memory devices 930, and / or process data to or from flash memory devices 930. Flash data processor 920 can include a customized interface 922 that corresponds to a customized interface 936 in flash controller 934. Customized interface 922 is configured to transfer data between flash data processor 920 or SSD controller 910 and flash controller 934 or flash memory devices 930. Customized interface 922 in SSD controller 910 and customized interface 936 in flash memory devices 930 can communicate with each other according to an interface agreement (e.g., Figure 7 interface agreement 400). The interface agreement can be implemented in any suitable format and with any suitable number of pins. In some examples, the interface agreement can be the same as a flash interface agreement (e.g., different from a non-flash interface agreement). In some examples, the interface agreement can have a smaller number of pins than a flash interface agreement. In some examples, the interface agreement can be a high-speed communication agreement, e.g., a communication agreement with a serializer / deserializer (SerDes).

[0159] In some implementations, flash data processor 920 can be similar to Figure 7 flash data processor 720. Flash data processor 920 can include ECC circuitry with stronger encoding capabilities than ECC circuitry 938 in flash controller 934. The ECC circuitry in flash data processor 920 can be similar to ​strong ECC circuit 724. The ECC circuit 938 can be similar to ​ ECC circuit 737.

[0160] The disclosed and other examples can be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer readable medium, for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of them. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0161] The system can also include code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0162] A computer program (also known as a program, software, software application, instructions for operation, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more instructions that are a part of an operating system). A program can be stored in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0163] The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows can also be performed by special purpose logic circuitry, and / or devices can be implemented as special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0164] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, magneto-optical disks, and optical disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0165] Although this document can describe many specifics, these should not be construed as limiting the scope of the claimed disclosure or application, but merely as describing particular implementations, some of which can not be necessarily ready for commercialization. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described herein in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor inhibiting the operations from being performed in serial or in parallel, or in a different order, to achieve desirable results.

[0166] Only a few examples and embodiments are disclosed. Variations, modifications, and enhancements to the described examples and embodiments and other embodiments can be made based upon the disclosure.

Claims

1. A memory system, comprising: The system controller is configured to communicate with the host device; as well as A memory device, coupled to the system controller, the memory device comprising: At least one memory; and A memory controller, coupled to the at least one memory, the memory controller including an error correction code circuit configured to perform error correction encoding on received data, the received data being received from the system controller or at least one of the at least one memory; The memory controller is coupled to the system controller via a first type of electrical connection. The memory controller is coupled to the at least one memory via a second type of electrical connection, and The impedance of the second type of electrical connection is less than the impedance of the first type of electrical connection; The error correction code circuit in the memory controller is a memory-side error correction code circuit. The system controller includes a system-side error correction code circuit, which has a stronger decoding capability than the memory-side error correction code circuit in the memory controller. The memory-side error correction code circuit is configured to decode data according to a weaker decoding algorithm, and the system-side error correction code circuit in the system controller is configured to decode data according to a stronger decoding algorithm.

2. The memory system according to claim 1 further includes an electrical connection board. The system controller and the memory device are respectively configured on the electrical connection board. The first type of electrical connection is implemented through a shared bus of the electrical connection board, and The second type of electrical connection is implemented via an internal bus in the memory device.

3. The memory system according to claim 1, wherein the system controller comprises: A first interface is configured to communicate with the host device via a third type of electrical connection according to a first interface protocol, wherein the impedance of the second type of electrical connection is less than the impedance of the third type of electrical connection. as well as The second interface is configured to communicate with the memory controller via an electrical connection of the first type according to the second interface protocol.

4. The memory system of claim 3, wherein the memory controller comprises: The third interface is configured to communicate with the system controller via an electrical connection of the first type according to the second interface protocol.

5. The memory system of claim 1, wherein the memory controller is configured to: The received data is received from the system controller via the first type of electrical connection; The error correction code circuit is used to encode the received data to obtain encoded data, the encoded data having a larger size than the received data; and The encoded data is written to the at least one memory via the second type of electrical connection.

6. The memory system of claim 1, wherein the memory controller is configured to: The received data is read from the at least one memory via the second type of electrical connection; The error correction code circuit is used to decode the received data to obtain decoded data, which has a smaller size than the received data. as well as The decoded data is transmitted to the system controller via the first type of electrical connection.

7. The memory system of claim 1, wherein the memory controller is configured to: The soft bits of the received data are read from the at least one memory via the second type of electrical connection; The error correction code circuit is used to decode the soft bits of the received data according to a soft-decision decoding algorithm to obtain decoded data, the decoded data having a smaller size than the received data; and The decoded data is transmitted to the system controller via the first type of electrical connection.

8. The memory system according to claim 1, wherein: The memory controller is configured to: In response to the determination that the memory-side error correction code circuit has failed to decode the received data according to the weaker decoding algorithm, the received data is sent to the system controller, and The system controller is configured as follows: The system-side error correction code circuit is used to decode the received data according to the stronger decoding algorithm. In response to the determination that the system-side error correction code circuit has failed to decode the received data according to the stronger decoding algorithm, a request to read the soft bits of the received data from the at least one memory is sent to the memory controller. as well as In response to receiving the soft bits of the received data from the memory controller, the system-side error correction code circuit decodes the soft bits of the received data according to the stronger decoding algorithm to obtain decoded data, the decoded data having a smaller size than the received data, and The memory controller is configured to: Without using the memory-side error correction code circuit to decode the soft bits of the received data, the soft bits of the received data are sent to the system controller.

9. The memory system of claim 1, comprising a plurality of memory devices, wherein the plurality of memory devices includes the memory devices. Each of the plurality of memory devices is coupled to the system controller and includes: Individual memory; as well as An individual memory controller, coupled to the individual memory, includes a corresponding error correction code circuit configured to perform corresponding error correction encoding on received corresponding data, the corresponding data being data received from at least one of the individual memory or the system controller.

10. The memory system of claim 9, wherein the system controller includes a plurality of data processors, each of the plurality of data processors being configured to communicate with an individual memory device among the plurality of memory devices.

11. The memory system of claim 10, wherein the corresponding error correction code circuit in the individual memory controller of each of the plurality of memory devices is a memory-side error correction code circuit, and Each of the plurality of data processors includes a system-side error correction code circuit, which has a stronger decoding capability than the memory-side error correction code circuit.

12. The memory system of claim 1, further comprising a second memory device, the second memory device being coupled to both the system controller and the memory device. The second memory device has a faster response speed than the memory device.

13. The memory system of claim 1, wherein the at least one memory comprises a plurality of memories, each of the plurality of memories being coupled to the memory controller, and The error correction code circuit is configured to perform error correction coding on the corresponding data associated with each of the plurality of memories.

14. A memory device, comprising: At least one memory; as well as A memory controller, coupled to the at least one memory, The memory controller includes: A memory interface is configured to communicate with a system controller via a first type of electrical connection, wherein the memory controller is coupled to the at least one memory via a second type of electrical connection having a lower impedance than the first type of electrical connection; and The error correction code circuit is configured to perform error correction coding on received data based on at least one of a read command or a write command received from the host device via the system controller, wherein the received data is received from at least one of the system controller or the at least one memory. The error correction code circuit in the memory controller is a memory-side error correction code circuit. The system controller includes a system-side error correction code circuit, which has a stronger decoding capability than the memory-side error correction code circuit in the memory controller. The memory-side error correction code circuit is configured to decode data according to a weaker decoding algorithm, and the system-side error correction code circuit in the system controller is configured to decode data according to a stronger decoding algorithm.

15. A method executed by a memory system, the method comprising: Data is received from a host device coupled to the system controller via the system controller of the memory system; The system controller transmits the received data to the memory device of the memory system via a first type of electrical connection; The received data is encoded by an error correction code circuit in the memory controller of the memory device to obtain encoded data, the encoded data having a larger size than the received data; as well as The encoded data is written into at least one memory of the memory device by the memory controller. The memory controller is coupled to the at least one memory via a second type of electrical connection, the second type of electrical connection having a lower impedance than the first type of electrical connection; The specified data is obtained from the at least one memory via the memory controller through the second type of electrical connection; In response to the determination that the error correction code circuit in the memory controller has failed to decode the specified data, the specified data is sent to the system controller via the memory controller through the first type of electrical connection; as well as The specified data is decoded by a second error correction code circuit in the system controller, the second error correction code circuit having a stronger decoding capability than the error correction code circuit.

16. The method performed by a memory system according to claim 15, further comprising: The specified data is obtained from the at least one memory via the memory controller through the second type of electrical connection; The specified data is decoded by the error correction code circuit in the memory controller to obtain decoded specified data, wherein the decoded specified data has a smaller size than the specified data. as well as The decoded specified data is transmitted to the system controller via the memory controller through the first type of electrical connection.

17. The method performed by a memory system according to claim 15, further comprising: In response to the determination that the second error correction code circuit has failed to decode the specified data, a request to read the soft bits of the specified data from the at least one memory is sent to the memory controller via the system controller; Without using the error correction code circuit to decode the soft bits of the specified data, the soft bits of the specified data are sent to the system controller via the memory controller; as well as The soft bits of the specified data are decoded by the second error correction code circuit in the system controller to obtain decoded specified data, which has a smaller size than the specified data.

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