Memory and method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-22
- Publication Date
- 2026-08-07
AI Technical Summary
随着DRAM等存储器尺寸的不断微缩，存储器制程工艺的难度不断增大，且存储器内部的应力也不断增加，从而降低了存储器的良率
[0048]本公开提供的存储器及其形成方法，先形成层间间隔层和牺牲层组交替堆叠的堆叠层于衬底的顶面，然后将所述牺牲层组中的第二牺牲层替换为栅极层、以及包覆所述栅极层的沟道层，一方面，通过形成包括第一牺牲层、第二牺牲层和第三牺牲层的牺牲层组，能够减小所述堆叠层内部的应力，从而有助于增加所述堆叠层的堆叠高度、以及所述存储器的存储容量，进而改善所述存储器的良率及性能；另一方面，通过替换牺牲层的方式形成所述沟道层和所述栅极层，从而使得所述存储器中晶体管的形成无需进行复杂的外延生长以及掺杂工艺，在简化所述存储器的制造工艺的同时，还能进一步提高所述存储器的良率。另外，本公开一些实施例的存储单元1T1C(1个晶体管1个电容器)、并结合采用沟道全环绕(Channel-All-Around，CAA)结构，能够提高所述存储器的集成度，并进一步改善所述存储器的良率。
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Figure CN115188715B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a memory and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] For memory devices such as DRAM, the pursuit has always been for faster response times, lower power consumption, and higher storage density. As the size of memory devices such as DRAM continues to shrink, the difficulty of memory manufacturing processes is constantly increasing, and the stress inside the memory is also constantly increasing, thereby reducing the yield of memory devices.
[0004] Therefore, simplifying the manufacturing process of memory and improving memory yield are urgent technical problems that need to be solved. Summary of the Invention
[0005] This disclosure provides some embodiments of the memory and the method for forming the memory, which are used to simplify the memory manufacturing process and improve the memory yield.
[0006] According to some embodiments, this disclosure provides a method for forming a memory, including the following steps:
[0007] A stacked layer is formed on the surface of a substrate. The stacked layer includes interlayer isolation layers spaced apart along a first direction and a group of sacrificial layers located between adjacent interlayer isolation layers. The group of sacrificial layers includes a first sacrificial layer, a second sacrificial layer and a third sacrificial layer stacked sequentially along the first direction. The stacked layer includes a transistor region. The first direction is a direction perpendicular to the top surface of the substrate.
[0008] Remove the second sacrificial layer from the transistor region to form a first void;
[0009] A gate layer and a channel layer covering the gate layer are formed within the first gap.
[0010] In some embodiments, the first sacrificial layer and the third sacrificial layer are both made of low dielectric constant materials, and the second sacrificial layer is made of undoped polycrystalline silicon.
[0011] In some embodiments, the stacked layer further includes a bit line region located on one side of the transistor region along a second direction, wherein the second direction is parallel to the top surface of the substrate; the specific steps for forming the first gap include:
[0012] The second sacrificial layer of the bit line region and the transistor region is removed to form a first trench;
[0013] A filling layer is formed that completely fills the first trench;
[0014] Remove the fill layer, the first sacrificial layer, and the third sacrificial layer from the bit line region to form a second trench;
[0015] A first isolation layer is formed, filling the second trench;
[0016] The filler layer in the transistor region is removed to form the first void.
[0017] In some embodiments, the specific steps for removing the second sacrificial layer from the bit line region and the transistor region include:
[0018] The filling layer, the first sacrificial layer, and the third sacrificial layer of the bit line region are removed using a lateral etching process.
[0019] In some embodiments, the specific steps of forming a gate layer within the first gap and a channel layer covering the gate layer include:
[0020] A channel layer is formed covering the inner wall of the first void;
[0021] A gate dielectric layer covering the surface of the channel layer is formed within the first gap;
[0022] A gate layer is formed within the first gap, covering the surface of the gate dielectric layer.
[0023] In some embodiments, after forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps:
[0024] Remove the first isolation layer and the interlayer isolation layer in the bit line region to form a second gap that exposes the first end of the channel layer;
[0025] A source electrode covering the first end of the channel layer and a bit line extending along the first direction are formed in the second gap, the bit line continuously covering the surface of the source electrodes spaced apart along the first direction.
[0026] In some embodiments, after forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps:
[0027] Remove the first isolation layer and the interlayer isolation layer in the bit line region, and remove part of the first sacrificial layer, the third sacrificial layer and the interlayer isolation layer in the transistor region to form a second gap that exposes the channel layer;
[0028] A source electrode covering the first end of the channel layer and a bit line extending along the first direction are formed in the second gap, the bit line continuously covering the surface of the source electrodes spaced apart along the first direction.
[0029] In some embodiments, the stacked layer further includes a capacitor region, which is distributed along the second direction on opposite sides of the transistor region. After forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps:
[0030] The sacrificial layer group in the capacitor region is removed to form a third gap that exposes the second end of the channel layer, the second end being distributed opposite to the first end along the second direction;
[0031] A drain electrode covering the second end of the channel layer and a capacitor electrically connected to the drain electrode are formed within the third gap.
[0032] In some embodiments, the stacked layer further includes a capacitor region, which is distributed along the second direction on opposite sides of the transistor region. After forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps:
[0033] The sacrificial layer group in the capacitor region is removed, and a portion of the first sacrificial layer and the third sacrificial layer in the transistor region are removed to form a third gap exposing the second end of the channel layer, wherein the second end and the first end are distributed opposite to each other along the second direction;
[0034] A drain electrode covering the second end of the channel layer and a capacitor electrically connected to the drain electrode are formed within the third gap.
[0035] In some embodiments, the channel layer is made of an oxide semiconductor material.
[0036] According to other embodiments, this disclosure also provides a memory formed using the memory formation method described above; the memory includes:
[0037] Substrate;
[0038] A stacked structure is located on the substrate, the stacked structure including memory cells spaced apart along a first direction, wherein the first direction is a direction perpendicular to the top surface of the substrate;
[0039] The memory cell includes a transistor and a capacitor located on one side of the transistor along a second direction. The transistor includes a gate layer, a channel layer covering the gate layer, and a drain electrode located at the end of the channel layer. The drain electrode is electrically connected to the capacitor. The second direction is a direction parallel to the top surface of the substrate.
[0040] In some embodiments, the channel layer includes a first end and a second end that are distributed opposite to each other along the second direction, and the drain electrode is located at the second end of the channel layer;
[0041] The projection of the drain electrode on the top surface of the substrate partially overlaps with the projection of the channel layer on the top surface of the substrate.
[0042] In some embodiments, the channel layer includes a first end and a second end that are distributed opposite to each other along the second direction, and the drain electrode is located at the second end of the channel layer;
[0043] The projection of the drain electrode on the top surface of the substrate is in contact with the projection of the channel layer on the top surface of the substrate, but they do not overlap.
[0044] In some embodiments, the channel layer includes a first end and a second end distributed opposite to each other along a second direction, the drain electrode being located at the second end of the channel layer, the second direction being a direction parallel to the top surface of the substrate; the transistor further includes:
[0045] A source electrode is located at the first end of the channel layer, and the projection of the source electrode on the top surface of the substrate partially overlaps with the projection of the channel layer on the top surface of the substrate.
[0046] In some embodiments, the channel layer includes a first end and a second end distributed opposite to each other along a second direction, the drain electrode being located at the second end of the channel layer, the second direction being a direction parallel to the top surface of the substrate; the transistor further includes:
[0047] The source electrode is located at the first end of the channel layer, and the projection of the source electrode on the top surface of the substrate is in contact with the projection of the channel layer on the top surface of the substrate without overlapping.
[0048] The memory and its formation method disclosed herein first form a stacked layer consisting of alternating interlayer spacers and sacrificial layers on the top surface of a substrate. Then, the second sacrificial layer in the sacrificial layer group is replaced with a gate layer and a channel layer covering the gate layer. On one hand, by forming a sacrificial layer group including a first, second, and third sacrificial layer, the stress inside the stacked layer can be reduced, thereby helping to increase the stacking height and storage capacity of the memory, and thus improving the yield and performance of the memory. On the other hand, by replacing the sacrificial layer to form the channel layer and the gate layer, the formation of transistors in the memory does not require complex epitaxial growth and doping processes, simplifying the memory manufacturing process and further improving the memory yield. Furthermore, some embodiments of this disclosure utilize a 1T1C memory cell (1 transistor and 1 capacitor) combined with a Channel-All-Around (CAA) structure, which can improve the integration density of the memory and further improve its yield. Attached Figure Description
[0049] Appendix Figure 1 This is a flowchart of a method for forming a memory according to a specific embodiment of this disclosure;
[0050] Appendix Figure 2 -Appendix Figure 12 This is a schematic diagram of the main process structure in the formation of the memory according to a specific embodiment of the present disclosure;
[0051] Appendix Figure 13 -Appendix Figure 14 This is a schematic diagram of the memory structure in a specific embodiment of this disclosure. Detailed Implementation
[0052] The specific embodiments of the memory and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0053] This specific embodiment provides a method for forming a memory, with appended... Figure 1 This is a flowchart illustrating the method for forming a memory according to a specific embodiment of this disclosure, with appended... Figure 2 -Appendix Figure 12 This is a schematic diagram of the main process structure in the formation of the memory according to a specific embodiment of this disclosure. Among them, Figure 2 This is a top view schematic diagram of the memory structure formed in one embodiment of this specific implementation. Figures 3-11 This is the memory formation process in this specific embodiment. Figure 1 A cross-sectional diagram of position aa in the diagram. Figure 12 This is a schematic diagram of the storage unit structure in this specific embodiment. For example... Figures 1-12As shown, the method for forming the memory includes:
[0054] Step S11: A stacked layer is formed on the surface of the substrate 30. The stacked layer includes interlayer isolation layers 20 spaced apart along a first direction D1, and sacrificial layer groups 32 located between adjacent interlayer isolation layers 20. The sacrificial layer groups 32 include a first sacrificial layer 321, a second sacrificial layer 322, and a third sacrificial layer 323 sequentially stacked along the first direction D1. The stacked layer includes a transistor region TP, wherein the first direction D1 is a direction perpendicular to the top surface of the substrate 30. Figure 3 As shown.
[0055] Specifically, the substrate 30 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 30 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 30 is used to support the device structure thereon. The top surface of the substrate 30 refers to the surface of the substrate 30 facing the stacked layer.
[0056] In one example, the interlayer isolation layer 20, the first sacrificial layer 321, the second sacrificial layer 322, and the third sacrificial layer 323 can be alternately deposited on the top surface of the substrate 30 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form an interlayer isolation layer 30 and a sacrificial layer group 32 that are alternately stacked along the first direction D1. The more layers of interlayer isolation layer 20 and sacrificial layer group 32 that are alternately deposited, the larger the storage capacity of the formed memory. The second sacrificial layer 322 is used to subsequently form the channel layer and the gate layer. In one embodiment, the height of the second sacrificial layer 322 along the first direction D1 is 50 nm to 80 nm.
[0057] In one embodiment, the interlayer isolation layer 20 is made of a nitride material (e.g., silicon nitride). The sacrificial layer group 32 is composed of at least two different materials to reduce stress within the stacked layers while facilitating subsequent selective etching. The first sacrificial layer 321 and the third sacrificial layer 323 may be made of the same material, and both the first sacrificial layer 321 and the third sacrificial layer 323 should have a high etch selectivity ratio compared to the second sacrificial layer 322 to facilitate subsequent selective etching. To reduce the manufacturing cost of the memory and simplify the manufacturing process, in one example, the first sacrificial layer 321 and the third sacrificial layer 323 are made of the same material, and the etch selectivity ratio between the first sacrificial layer 321 and the second sacrificial layer 322 should be greater than 3.
[0058] In some embodiments, the first sacrificial layer 321 and the third sacrificial layer 323 are both made of low-dielectric-constant materials, and the second sacrificial layer 322 is made of undoped polysilicon. The sacrificial layer group 32 is formed using a low-dielectric-constant material and undoped polysilicon, and the sacrificial layer 32 is alternately stacked with the interlayer isolation layer 20 made of a nitride material (e.g., silicon nitride). This further reduces the stress within the stacked layers and also improves the etching selectivity between different material layers within the sacrificial layer group 32. The low-dielectric-constant material refers to a material with a dielectric constant less than 3. For example, the low-dielectric-constant material can be, but is not limited to, one or more combinations of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass).
[0059] In one embodiment, a substrate isolation layer 31 may be provided between the substrate 30 and the stacked layer to isolate the substrate 30 from the stacked layer and further reduce the stress between the substrate 30 and the stacked layer. The substrate isolation layer 31 may be made of an insulating dielectric material such as an oxide (e.g., silicon dioxide).
[0060] Step S12: Remove the second sacrificial layer 322 of the transistor region TP to form a first gap.
[0061] Step S13: A gate layer 81 and a channel layer 70 covering the gate layer 81 are formed within the first gap, as follows: Figure 8 As shown.
[0062] In some embodiments, the stacked layer further includes a bit line region BP located on one side of the transistor region TP along a second direction D2, wherein the second direction D2 is parallel to the top surface of the substrate 30; the specific steps for forming the first gap include:
[0063] The second sacrificial layer 322 of the bit line region BP and the transistor region TP is removed to form a first trench 40, as shown below. Figure 4 As shown;
[0064] A filling layer 50 is formed to fill the first trench 40, such as... Figure 5 As shown;
[0065] The fill layer 50, the first sacrificial layer 321 and the third sacrificial layer 323 of the bit line region BP are removed to form a second trench;
[0066] Forming a first isolation layer 60 that fills the second trench, such as Figure 6 As shown;
[0067] The filling layer of the transistor region BP is removed to form the first void.
[0068] To simplify the formation process of the first gap, in some embodiments, the specific steps for removing the second sacrificial layer 322 of the bit line region BP and the transistor region TP include:
[0069] The filling layer 50, the first sacrificial layer 321, and the third sacrificial layer 323 of the bit line region BP are removed by a lateral etching process.
[0070] Specifically, a wet etching process can be used to remove the second sacrificial layer 322 located between the bit line region BP and the transistor region TP, forming the first trench 40 located between the first sacrificial layer 321 and the third sacrificial layer 323, such as... Figure 4 As shown. The first trench 40 extends along the second direction D2 from the bit line region BP to the transistor region TP. Then, an insulating dielectric material such as an oxide (e.g., silicon dioxide) can be deposited in the first trench 40 using a lateral atomic layer deposition process to form the filling layer 50 that fills the first trench 40, such as... Figure 5 As shown. Next, a lateral etching process is used to remove the fill layer 50, the first sacrificial layer 321, the third sacrificial layer 323, and the interlayer isolation layer 20 in the bit line region BP, forming a second trench in the bit line region BP that penetrates the stacked layers along the first direction D1. Then, an insulating dielectric material such as a nitride (e.g., silicon nitride) is deposited in the second trench to form the first isolation layer 60 that fills the second trench, such as... Figure 6 As shown. Then, the fill layer of the transistor region TP is removed, and the first gap is formed in the transistor region TP between the first sacrificial layer 321 and the third sacrificial layer 323.
[0071] The first isolation layer 60 serves two purposes: firstly, it defines the position of the subsequently formed channel layer 70; secondly, it supports the stacked layers to prevent them from tipping over or collapsing during the subsequent transistor formation process. In one embodiment, the first isolation layer 60 and the interlayer isolation layer 20 can be made of the same material, so that the first isolation layer 60 and the interlayer isolation layer 20 can be removed simultaneously during the bit line formation process, thereby simplifying the bit line formation process.
[0072] In some embodiments, the specific steps of forming a gate layer 81 and a channel layer 70 covering the gate layer 81 within the first gap include:
[0073] A channel layer 70 is formed covering the inner wall of the first void, such as... Figure 7 As shown;
[0074] A gate dielectric layer 80 is formed within the first gap, covering the surface of the channel layer 70, such as... Figure 8 As shown;
[0075] A gate layer 81 is formed within the first gap, covering the surface of the gate dielectric layer 80, such as... Figure 8 As shown.
[0076] Specifically, an atomic layer deposition process can be used to deposit channel material within the first void, and a back etching process can be used to remove part of the channel material, leaving only the channel material covering the inner wall of the first void, forming the channel layer 70. Figure 7 As shown. In one embodiment, the thickness of the channel layer 70 is 20nm to 40nm to reserve sufficient space for the subsequent formation of the gate layer 81, thereby reducing the process difficulty of forming the gate layer 81. Next, a high dielectric constant material is deposited on the surface of the channel layer 70 to form the gate dielectric layer 80. In one embodiment, the thickness of the gate dielectric layer 80 is 20nm to 40nm to reserve sufficient space for the subsequent formation of the gate layer 81. The material of the gate dielectric layer 80 can be any one or a combination of two or more of SiO2, HfO, and Al2O3. Afterward, an atomic layer deposition process can be used to deposit a gate material such as tungsten metal or TiN on the surface of the gate dielectric layer 80 to form the gate layer 81, such as... Figure 8 As shown.
[0077] In one embodiment, the stacked layer may further include a third direction D3 (see...). Figure 2The first gap contains a plurality of transistor regions TP spaced apart, with a transistor isolation layer 21 between adjacent transistor regions TP for isolating adjacent transistor regions TP. The specific steps of forming a gate layer 81 covering the surface of the gate dielectric layer 80 within the first gap may include: depositing gate material within the first gap to form word lines 24 extending along the third direction D3 and continuously covering the plurality of transistor regions, wherein the word lines 24 located within the transistor regions serve as the gate layer 81. The ends of the word lines 24 extend out of the transistor regions along the third direction D3 to facilitate electrical connection with word line plugs 25. The plurality of word lines 24 are spaced apart along the first direction D1, and the ends of the plurality of word lines 24 extending out of the transistor regions along the third direction D3 form a stepped structure to facilitate signal extraction from each word line 24. The stepped structure refers to the situation where, for any two adjacent word lines 24 along the first direction D1, the word line 24 closer to the substrate 30 protrudes out of the other word line 24 along the third direction D3. In this specific embodiment, "multiple" refers to two or more items.
[0078] In some embodiments, the channel layer 70 is made of an oxide semiconductor material. The oxide semiconductor material can be converted between a conductor and an insulator. Using an oxide semiconductor material to form the channel layer 70 eliminates the need for complex doping processes, thereby simplifying the memory fabrication process. The oxide semiconductor material is any one or a combination of two or more of In₂O₃ (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride).
[0079] In some embodiments, after forming a gate layer 81 and a channel layer 70 covering the gate layer 81 within the first gap, the following steps are further included:
[0080] Remove the first isolation layer 60 and the interlayer isolation layer 20 from the bit line region BP to form a second gap that exposes the first end of the channel layer 70;
[0081] A source electrode 90 covering the first end of the channel layer 70 and a bit line 23 extending along the first direction D1 are formed in the second gap, the bit line 23 continuously covering the surface of the source electrodes 90 arranged at intervals along the first direction D1.
[0082] For example, a wet etching process or a dry etching process can be used to remove the interlayer isolation layer 20 and the first isolation layer 60 of the bit line region BP, forming a second void that exposes the first end of the channel layer 70. Then, an atomic layer deposition process can be used to deposit bit line material (e.g., conductive material such as tungsten metal or TiN) into the second void to form the source electrode 90 covering the first end of the channel layer, and simultaneously form the bit line 23 extending along the first direction D1. The bit line 23 continuously covers the surface of the source electrodes 90 spaced apart along the first direction D1, and multiple bit lines 23 are spaced apart along the third direction D3. Since only the interlayer isolation layer 20 and the first isolation layer 60 of the bit line region BP are removed to simplify the etching process, the source electrode 90 only covers the side surface of the channel layer 70, so that the projection of the channel layer 70 on the top surface of the substrate 30 and the projection of the source electrode 90 on the top surface of the substrate 30 are in direct contact and do not overlap. In addition, since the bit line 23 and the source electrode 90 are formed simultaneously in a single deposition process, there is no contact interface between the bit line 23 and the source electrode 90, thereby reducing or even avoiding the contact resistance between the bit line 23 and the source electrode 90, and further improving the electrical performance of the memory.
[0083] In other embodiments, after forming the gate layer 81 and the channel layer 70 covering the gate layer 81 within the first gap, the following steps are further included:
[0084] Remove the first isolation layer 60 and the interlayer isolation layer 20 of the bit line region BP, and remove part of the first sacrificial layer 321, the third sacrificial layer 323 and the interlayer isolation layer 20 of the transistor region TP to form a second gap that exposes the channel layer 70;
[0085] A source electrode 90 covering the first end of the channel layer 70 and a bit line 23 extending along the first direction D1 are formed within the second gap. The bit line 23 continuously covers the surface of the source electrodes 90 spaced apart along the first direction D1, such as... Figure 9 and Figure 12 As shown.
[0086] For example, a wet etching process or a dry etching process can be used to remove the first isolation layer 60 and the interlayer isolation layer 20 of the bit line region BP, and to remove part of the first sacrificial layer 321, the third sacrificial layer 323 and the interlayer isolation layer 20 of the transistor region TP, forming a second void that exposes the channel layer 70. Then, an atomic layer deposition process can be used to deposit bit line material (e.g., conductive material such as tungsten metal or TiN) in the second void to form the source electrode 90 covering the first end of the channel layer, and simultaneously form the bit line 23 extending along the first direction D1. The bit line 23 continuously covers the surface of the source electrodes 90 spaced along the first direction D1, and multiple bit lines 23 are spaced along the third direction D3. Since both the bit line region BP and the transistor region TP are etched during the etching process, the source electrode 90 covers the first end of the channel layer 70 (i.e., the source electrode 90 covers the side surface, part of the bottom surface, and part of the top surface of the channel layer). This causes the projection of the channel layer 70 onto the top surface of the substrate 30 to partially overlap with the projection of the source electrode 90 onto the top surface of the substrate 30, thereby reducing the size of the memory. Furthermore, since the bit line 23 and the source electrode 90 are formed simultaneously in a single deposition process, there is no contact interface between the bit line 23 and the source electrode 90. This reduces or even eliminates the contact resistance between the bit line 23 and the source electrode 90, further improving the electrical performance of the memory.
[0087] In some embodiments, the stacked layer further includes a capacitor region CP, which is distributed along the second direction D2 on opposite sides of the transistor region TP. After forming the gate layer 81 and the channel layer 70 covering the gate layer 81 in the first gap, the following steps are further included:
[0088] The sacrificial layer group 32 of the capacitor region CP is removed, forming a third void 100 that exposes the second end of the channel layer 70, such as... Figure 10 As shown, the second end and the first end are distributed relative to each other along the second direction D2;
[0089] A drain electrode 111 covering the second end of the channel layer 70 and a capacitor electrically connected to the drain electrode 111 are formed in the third gap.
[0090] For example, after forming the third void, a lower electrode material (e.g., conductive material such as tungsten metal or TiN) is deposited within the third void to form the drain electrode 111 covering the second end of the channel layer 70, and simultaneously a lower electrode layer 110 electrically connected to the drain electrode 111 is formed. Then, a dielectric layer 221 covering the surface of the lower electrode layer 110 and an upper electrode layer 222 covering the surface of the dielectric layer 221 are formed, thereby forming the capacitor including the lower electrode layer 110, the dielectric layer 221, and the upper electrode layer 222. Since only the sacrificial layer group 32 of the capacitor region CP is removed to simplify the etching process, the drain electrode 111 only covers the side surface of the channel layer 70, so that the projection of the channel layer 70 on the top surface of the substrate 30 and the projection of the drain electrode 111 on the top surface of the substrate 30 are in direct contact without overlapping. In addition, since the lower electrode layer 110 and the drain electrode 111 are formed simultaneously in a single deposition process, there is no contact interface between the lower electrode layer 110 and the drain electrode 111. This reduces or even eliminates the contact resistance between the lower electrode layer 110 and the drain electrode 111, thereby further improving the electrical performance of the memory.
[0091] In other embodiments, the stacked layer further includes a capacitor region CP, which is distributed along the second direction D2 on opposite sides of the transistor region TP. After forming the gate layer 81 and the channel layer 70 covering the gate layer 81 in the first gap, the following steps are further included:
[0092] The sacrificial layer group 32 of the capacitor region CP is removed, and a portion of the first sacrificial layer 321 and the third sacrificial layer 323 of the transistor region TP are removed to form a third gap exposing the second end of the channel layer 70. The second end and the first end are distributed opposite to each other along the second direction D2.
[0093] A drain electrode 111 covering the second end of the channel layer 70 and a capacitor electrically connected to the drain electrode 111 are formed within the third gap, such as... Figure 11 and Figure 12 As shown.
[0094] For example, after forming the third void, a lower electrode material (e.g., conductive material such as tungsten metal or TiN) is deposited within the third void to form the drain electrode 111 covering the second end of the channel layer 70, and simultaneously a lower electrode layer 110 is formed that is in contact with and electrically connected to the drain electrode 111. Then, a dielectric layer 221 covering the surface of the lower electrode layer 110 and an upper electrode layer 222 covering the surface of the dielectric layer 221 are formed, thereby forming the capacitor including the lower electrode layer 110, the dielectric layer 221, and the upper electrode layer 222. Since both the capacitor region CP and the transistor region TP are etched during the etching process, the drain electrode 111 covers the second end of the channel layer 70 (i.e., the drain electrode 111 covers the side, part of the bottom surface, and part of the top surface of the channel layer 70). This causes the projection of the channel layer 70 onto the top surface of the substrate 30 to partially overlap with the projection of the drain electrode 111 onto the top surface of the substrate 30, thereby reducing the size of the memory. Furthermore, since the lower electrode layer 110 and the drain electrode 111 are formed simultaneously in a single deposition process, there is no contact interface between the lower electrode layer 110 and the drain electrode 111. This reduces or even eliminates the contact resistance between the lower electrode layer 110 and the drain electrode 111, further improving the electrical performance of the memory.
[0095] In another embodiment, when removing the sacrificial layer group 32 of the capacitor region CP, the first sacrificial layer 321 and the third sacrificial layer 323 of the transistor region TP can be removed simultaneously; then, a drain electrode 111 covering the second end of the channel layer 70 and a capacitor electrically connected to the drain electrode 111 are formed in the third gap, and an air gap is formed between the drain electrode 111 and the source electrode 90, thereby further reducing the resistance inside the memory.
[0096] This specific embodiment also provides a memory, attached... Figure 13 -Appendix Figure 14 This is a schematic diagram of the memory structure according to a specific embodiment of this disclosure. Figure 13 This is a top view of the memory structure described in this specific embodiment. Figure 14 yes Figure 13 A cross-sectional schematic diagram at position aa. The memory provided in this specific embodiment can be adopted as follows: Figures 1-12 The memory is formed using the method shown. For example... Figures 13-14 As shown, the memory includes:
[0097] Substrate 30;
[0098] A stacked structure is located on the substrate 30, the stacked structure includes memory cells arranged at intervals along a first direction D1, wherein the first direction D1 is a direction perpendicular to the top surface of the substrate 30;
[0099] The memory cell includes a transistor and a capacitor located on one side of the transistor along a second direction D2. The transistor includes a gate layer 81, a channel layer 70 covering the gate layer 81, and a drain electrode 111 located at the end of the channel layer 70. The drain electrode 111 is electrically connected to the capacitor. The second direction D2 is a direction parallel to the top surface of the substrate 30.
[0100] In some embodiments, the channel layer 70 includes a first end and a second end that are distributed opposite to each other along the second direction D2, and the drain electrode 111 is located at the second end of the channel layer 70;
[0101] The projection of the drain electrode 111 on the top surface of the substrate 30 partially overlaps with the projection of the channel layer 70 on the top surface of the substrate 30.
[0102] In some embodiments, the channel layer 70 includes a first end and a second end that are distributed opposite to each other along the second direction D2, and the drain electrode 111 is located at the second end of the channel layer 70;
[0103] The projection of the drain electrode 111 on the top surface of the substrate 30 is in contact with the projection of the channel layer 70 on the top surface of the substrate 30, but they do not overlap.
[0104] In some embodiments, the channel layer 70 includes a first end and a second end distributed opposite to each other along a second direction D2, the drain electrode 111 is located at the second end of the channel layer 70, and the second direction D2 is a direction parallel to the top surface of the substrate 30; the transistor further includes:
[0105] The source electrode 90 is located at the first end of the channel layer 70, and the projection of the source electrode 90 on the top surface of the substrate 30 partially overlaps with the projection of the channel layer 70 on the top surface of the substrate 30.
[0106] In some embodiments, the channel layer 70 includes a first end and a second end distributed opposite to each other along a second direction, the drain electrode 111 is located at the second end of the channel layer 70, and the second direction D2 is a direction parallel to the top surface of the substrate 30; the transistor further includes:
[0107] The source electrode 90 is located at the first end of the channel layer 70. The projection of the source electrode 90 on the top surface of the substrate 30 is in contact with the projection of the channel layer 70 on the top surface of the substrate 30 without overlapping.
[0108] The memory and its formation method provided in this specific embodiment first form a stacked layer consisting of alternating interlayer spacers and sacrificial layers on the top surface of a substrate. Then, the second sacrificial layer in the sacrificial layer group is replaced with a gate layer and a channel layer covering the gate layer. On the one hand, by forming a sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer, the stress inside the stacked layer can be reduced, thereby helping to increase the stacking height of the stacked layer and the storage capacity of the memory, thus improving the yield and performance of the memory. On the other hand, by replacing the sacrificial layer to form the channel layer and the gate layer, the formation of transistors in the memory does not require complex epitaxial growth and doping processes, simplifying the manufacturing process of the memory and further improving the yield of the memory. In addition, the memory cell 1T1C (one transistor and one capacitor) in some embodiments of this disclosure, combined with the use of a channel-all-around (CAA) structure, can improve the integration density of the memory and further improve the yield of the memory.
[0109] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a memory, characterized in that, Includes the following steps: A stacked layer is formed on the surface of a substrate. The stacked layer includes interlayer isolation layers spaced apart along a first direction, and a group of sacrificial layers located between adjacent interlayer isolation layers. The group of sacrificial layers includes a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked sequentially along the first direction. The stacked layer includes a transistor region. The first direction is perpendicular to the top surface of the substrate. The first sacrificial layer and the third sacrificial layer are both made of low dielectric constant materials, and the second sacrificial layer is made of undoped polysilicon. Remove the second sacrificial layer from the transistor region to form a first void; A gate layer and a channel layer covering the gate layer are formed within the first gap.
2. The method for forming a memory according to claim 1, characterized in that, The stacked layer further includes a bit line region located on one side of the transistor region along a second direction, the second direction being a direction parallel to the top surface of the substrate; The specific steps for forming the first gap include: The second sacrificial layer of the bit line region and the transistor region is removed to form a first trench; A filling layer is formed that completely fills the first trench; Remove the fill layer, the first sacrificial layer, and the third sacrificial layer from the bit line region to form a second trench; A first isolation layer is formed, filling the second trench; The filler layer in the transistor region is removed to form the first void.
3. The method for forming a memory according to claim 2, characterized in that, The specific steps for removing the second sacrificial layer from the bit line region and the transistor region include: The filling layer, the first sacrificial layer, and the third sacrificial layer of the bit line region are removed using a lateral etching process.
4. The method for forming a memory according to claim 1, characterized in that, The specific steps of forming a gate layer and a channel layer covering the gate layer within the first gap include: A channel layer is formed covering the inner wall of the first void; A gate dielectric layer covering the surface of the channel layer is formed within the first gap; A gate layer is formed within the first gap, covering the surface of the gate dielectric layer.
5. The method for forming a memory according to claim 2, characterized in that, After forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps: Remove the first isolation layer and the interlayer isolation layer in the bit line region to form a second gap that exposes the first end of the channel layer; A source electrode covering the first end of the channel layer and a bit line extending along the first direction are formed in the second gap, the bit line continuously covering the surface of the source electrodes spaced apart along the first direction.
6. The method for forming a memory according to claim 5, characterized in that, After forming a gate layer and a channel layer covering the gate layer within the first gap, the method further includes the following steps: Remove the first isolation layer and the interlayer isolation layer in the bit line region, and remove part of the first sacrificial layer, the third sacrificial layer and the interlayer isolation layer in the transistor region to form a second gap that exposes the channel layer; A source electrode covering the first end of the channel layer and a bit line extending along the first direction are formed in the second gap, the bit line continuously covering the surface of the source electrodes spaced apart along the first direction.
7. The method for forming a memory according to claim 5 or 6, characterized in that, The stacked layer further includes a capacitor region, which is distributed along the second direction on opposite sides of the transistor region. After forming a gate layer and a channel layer covering the gate layer within the first gap, the following steps are further included: The sacrificial layer group in the capacitor region is removed to form a third gap that exposes the second end of the channel layer, the second end being distributed opposite to the first end along the second direction; A drain electrode covering the second end of the channel layer and a capacitor electrically connected to the drain electrode are formed within the third gap.
8. The method for forming a memory according to claim 5 or 6, characterized in that, The stacked layer further includes a capacitor region, which is distributed along the second direction on opposite sides of the transistor region. After forming a gate layer and a channel layer covering the gate layer within the first gap, the following steps are further included: The sacrificial layer group in the capacitor region is removed, and a portion of the first sacrificial layer and the third sacrificial layer in the transistor region are removed to form a third gap exposing the second end of the channel layer, wherein the second end and the first end are distributed opposite to each other along the second direction; A drain electrode covering the second end of the channel layer and a capacitor electrically connected to the drain electrode are formed within the third gap.
9. The method for forming a memory according to claim 1, characterized in that, The channel layer is made of oxide semiconductor material.
10. A memory, characterized in that, The memory is formed using the method for forming a memory as described in claim 1; the memory comprises: Substrate; A stacked structure is located on the substrate, the stacked structure including memory cells spaced apart along a first direction, wherein the first direction is a direction perpendicular to the top surface of the substrate; The memory cell includes a transistor and a capacitor located on one side of the transistor along a second direction. The transistor includes a gate layer, a channel layer covering the gate layer, and a drain electrode located at the end of the channel layer. The drain electrode is electrically connected to the capacitor. The second direction is a direction parallel to the top surface of the substrate.
11. The memory according to claim 10, characterized in that, The channel layer includes a first end and a second end that are distributed opposite to each other along the second direction, and the drain electrode is located at the second end of the channel layer; The projection of the drain electrode on the top surface of the substrate partially overlaps with the projection of the channel layer on the top surface of the substrate.
12. The memory according to claim 10, characterized in that, The channel layer includes a first end and a second end that are distributed opposite to each other along the second direction, and the drain electrode is located at the second end of the channel layer; The projection of the drain electrode on the top surface of the substrate is in contact with the projection of the channel layer on the top surface of the substrate, but they do not overlap.
13. The memory according to claim 10, characterized in that, The channel layer includes a first end and a second end distributed opposite to each other along a second direction, the drain electrode is located at the second end of the channel layer, and the second direction is a direction parallel to the top surface of the substrate; the transistor further includes: a source electrode located at the first end of the channel layer, the projection of the source electrode on the top surface of the substrate partially overlapping the projection of the channel layer on the top surface of the substrate.
14. The memory according to claim 10, characterized in that, The channel layer includes a first end and a second end distributed opposite to each other along a second direction. The drain electrode is located at the second end of the channel layer. The second direction is a direction parallel to the top surface of the substrate. The transistor further includes a source electrode located at the first end of the channel layer. The projection of the source electrode on the top surface of the substrate is in contact with the projection of the channel layer on the top surface of the substrate and does not overlap.
Citation Information
Patent Citations
Memory and forming method thereof
CN115188714A