Transistor, manufacturing method and display panel

Abstract

The application discloses a transistor, a preparation method and a display panel, relates to the technical field of semiconductor devices, and can improve the carrier mobility of the transistor and can be mass-produced. The transistor comprises a gate, a semiconductor layer, a drain and a source, a first insulating layer and a second insulating layer. The gate comprises a plurality of hollow regions which are spaced apart from each other. The semiconductor layer comprises at least a first part which is filled in the hollow regions. The drain and the source are arranged on two sides of the semiconductor layer in the thickness direction, respectively. The first insulating layer is arranged on the surface of the gate which is close to the source in the thickness direction. The second insulating layer is arranged on the surface of the gate which is close to the drain in the thickness direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a transistor, a preparation method and a display panel. BACKGROUND

[0002] At present, the transistor of vertical structure generally adopts MIS structure, i.e. metal-insulator-semiconductor field effect transistor. The technical core of the vertical transistor adopting the MIS structure lies in the patterned net-shaped source electrode, which is required to be thin and rough, so as to realize higher light transmittance and form a larger injection barrier when contacting with the light emitting unit, so as to change the Fermi level under the influence of the electric field and realize the switching function of the gate voltage.

[0003] However, the extremely thin net-shaped source electrode of the existing vertical transistor reduces the carrier mobility of the transistor and is difficult to mass-scale production. SUMMARY

[0004] The embodiments of the present application provide a transistor, a preparation method and a display panel, which can improve the carrier mobility of the transistor and can be mass-scale produced.

[0005] In a first aspect, the embodiments of the present application provide a transistor, comprising:

[0006] a gate electrode, the gate electrode comprising a plurality of hollowed regions spaced from each other;

[0007] a semiconductor layer, the semiconductor layer comprising at least a first part filled in the hollowed regions;

[0008] a drain electrode and a source electrode respectively arranged on two sides of the semiconductor layer in the thickness direction;

[0009] a first insulating layer arranged on a surface of the gate electrode in the thickness direction close to the source electrode;

[0010] a second insulating layer arranged on a surface of the gate electrode in the thickness direction close to the drain electrode.

[0011] In some embodiments, the semiconductor layer further comprises a second part, the second part and the first part are arranged in a stacked manner in the thickness direction, and a projection of the second part on a plane where the gate electrode is located covers the first part and the second part.

[0012] In some embodiments, the second part is arranged between the gate electrode and the source electrode, and / or the second part is arranged between the gate electrode and the drain electrode.

[0013] In some embodiments, the transistor further comprises:

[0014] a light emitting structure;

[0015] The light-emitting structure is disposed between the semiconductor layer and the drain, or the light-emitting structure is disposed between the semiconductor layer and the source.

[0016] In some embodiments, the light-emitting structure comprises:

[0017] a hole transport layer;

[0018] a light-emitting layer;

[0019] an electron transport layer;

[0020] The light-emitting layer is disposed between the hole transport layer and the electron transport layer, and the electron transport layer is disposed between the light-emitting layer and the semiconductor layer.

[0021] In some embodiments, the gate electrode comprises a plurality of hollow regions.

[0022] In some embodiments, the material work function of the gate electrode is greater than the material work function of the semiconductor layer.

[0023] In some embodiments, the material work function of the gate electrode is greater than 3eV.

[0024] In some embodiments, the gate electrode comprises a metal layer and at least two metal oxide layers disposed on both sides of the metal layer, and the material work function of the metal oxide layers is greater than the material work function of the metal layer; and / or,

[0025] The gate electrode comprises a stack of at least two different metal materials.

[0026] In some embodiments, the size of the hollow region is less than or equal to 1μm.

[0027] In some embodiments, the material of the semiconductor layer is a p-type material, and the gate electrode is used to access a positive voltage signal; or,

[0028] The material of the semiconductor layer is an n-type material, and the gate electrode is used to access a negative voltage signal.

[0029] In a second aspect, the present application provides a preparation method of a transistor, comprising:

[0030] The semiconductor layer, the source, the drain, the first insulating layer, the second insulating layer and the gate are arranged respectively, wherein the drain and the source are arranged on two sides of the semiconductor layer in the thickness direction, the gate comprises a plurality of hollow regions spaced from each other, the semiconductor layer comprises at least a first part filled in the hollow regions, the first insulating layer is arranged on the surface of the gate close to the source in the thickness direction, and the second insulating layer is arranged on the surface of the gate close to the drain in the thickness direction.

[0031] In some embodiments, the semiconductor layer, the source, the drain, the first insulating layer, the second insulating layer and the gate are arranged respectively, comprising:

[0032] The source is arranged.

[0033] The light-emitting structure is arranged on one side of the source.

[0034] The support ball layer is arranged on the side of the light-emitting structure away from the source, wherein the support ball layer comprises a plurality of support balls, and the support balls are dispersed on the surface of the light-emitting structure away from the source.

[0035] The first insulating layer, the gate and the second insulating layer are arranged in sequence, wherein the first insulating layer, the gate and the second insulating layer are sequentially filled between adjacent support balls.

[0036] The support ball layer is removed to form the hollow regions in the regions where the support balls are located.

[0037] The semiconductor layer and the drain are arranged respectively, so that the first part of the semiconductor layer is filled in the hollow regions, and the drain is located on the side of the semiconductor layer away from the source.

[0038] In a third aspect, the embodiments of the present application provide a display panel, comprising:

[0039] A plurality of transistors as described in the first aspect.

[0040] The transistor provided by the embodiment of the present application is characterized in that the first part of the semiconductor layer is filled in the hollow area of the gate electrode to form a vertical conductive channel on the semiconductor layer, and the source electrode and the drain electrode are arranged on the two sides of the semiconductor layer respectively, so that the current direction of the conductive channel is along the connection direction of the source electrode and the drain electrode to form a vertical structure transistor. Compared with the conventional vertical transistor, the vertical conductive channel can be used without the need of using an extremely thin source electrode, and the source electrode and the drain electrode can be made of conventional conductive materials, which can avoid the reduction of the channel carrier mobility caused by the use of the extremely thin source electrode, and can improve the mass production and facilitate the large-scale production of the transistor. In addition, compared with the conventional vertical transistor, the vertical structure transistor obtained by arranging the vertical conductive channel can reduce the size of the transistor while ensuring the conductive performance of the transistor, that is, the area occupied by the transistor can be reduced, and the transistor can be used for more flexible circuit layout. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A schematic structural diagram of a transistor provided by the embodiment of the present application is shown in the figure;

[0042] Figure 2 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0043] Figure 3 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0044] Figure 4 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0045] Figure 5 A schematic structural diagram of a transistor provided by the embodiment of the present application is shown in the figure;

[0046] Figure 6 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0047] Figure 7 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0048] Figure 8 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0049] Figure 9 A schematic structural diagram of a transistor provided by the embodiment of the present application is shown in the figure;

[0050] Figure 10 A schematic structural diagram of another transistor provided by the embodiment of the present application is shown in the figure;

[0051] Figure 11Another schematic structural diagram of a transistor provided by an embodiment of the present application is shown in FIG. 2B.

[0052] Figure 12 A schematic flow chart of a preparation method of a transistor provided by an embodiment of the present application is shown in FIG. 3B.

[0053] Figure 13 A schematic flow chart of another preparation method of a transistor provided by an embodiment of the present application is shown in FIG. 4B.

[0054] Figure 14 A schematic structural diagram of a display panel provided by an embodiment of the present application is shown in FIG. 5B.

[0055] Figure 15 A schematic structural diagram of a display device provided by an embodiment of the present application is shown in FIG. 6B. DETAILED DESCRIPTION

[0056] In order to better understand the technical solutions provided by the embodiments of the present application, the technical solutions of the embodiments of the present application are described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present application, rather than limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0057] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more than two.

[0058] At present, the vertical structure transistor generally adopts MIS structure, i.e. metal-insulator-semiconductor field effect transistor. The technical core of the vertical transistor adopting the MIS structure lies in the patterned net-shaped source electrode, which requires the source electrode to be thin and rough, so as to realize higher light transmittance and form a larger injection barrier when contacting the light-emitting unit, so as to change the Fermi level under the influence of the electric field and realize the switching function of the gate voltage. However, the extremely thin net-shaped source electrode of the existing vertical transistor reduces the carrier mobility of the transistor and is difficult to mass-produce.

[0059] In view of this, embodiments of this application provide a transistor, a fabrication method, and a display panel, which can improve the carrier mobility of the transistor and enable mass production.

[0060] A first aspect of the embodiments of this application provides a transistor, Figure 1 This is a schematic structural diagram of a transistor provided for an embodiment of this application. For example... Figure 1 As shown, the transistor includes: a gate 400, which includes a plurality of spaced-apart cutout regions; a semiconductor layer 100, which includes at least a first portion 110 filled in the cutout regions; a drain 200 and a source 300, respectively disposed on opposite sides of the semiconductor layer 100 in the thickness direction; a first insulating layer 510 disposed on the surface of the gate 400 near the source 300 in the thickness direction; and a second insulating layer 520 disposed on the surface of the gate 400 near the drain 200 in the thickness direction. The gate 400 is used to form a conductive channel in the contact region between the gate 400 and the semiconductor layer 100, pointing from the drain 200 to the source 300, when an electrical signal is applied. This can be understood as the conductive channel being formed in the first portion 110, which is used to form the conductive channel. In some examples, the gate 400 is used to form a conductive channel in the contact region between the gate 400 and the semiconductor layer 100, pointing from the source 300 to the drain 200, when an electrical signal is applied. A conductive channel pointing from drain 200 to source 300, or vice versa, is a vertical conductive channel, whereas conductive channels in traditional semiconductors are horizontal. For example, when a high voltage is applied to source 300 and a low voltage is applied to drain 200, and the transistor is turned on when a voltage is applied to gate 400, the current flowing through the conductive channel flows from source 300 to drain 200. Conversely, when a low voltage is applied to source 300 and a high voltage is applied to drain 200, and the transistor is turned on when a voltage is applied to gate 400, the current flowing through the conductive channel from drain 200 to source 300. Therefore, a conductive channel pointing from drain 200 to source 300, or vice versa, is used to implement a vertically oriented conductive channel. Figure 1 The arrows in the conductive channel region shown represent the direction of current flowing through the conductive channel. The direction of current flowing through the conductive channel can be determined by the magnitude of the voltage applied to the source 300 and drain 200. Figure 1 The indicated current direction is a double-headed arrow, but this application does not impose specific limitations on the embodiments.

[0061] like Figure 1As shown, the first insulating layer 510 can be arranged between the source electrode 300 and the gate electrode 400, and the second insulating layer 520 can be arranged between the drain electrode 200 and the gate electrode 400. In the on state of the transistor, the arrangement of the first insulating layer 510 and the second insulating layer 520 can avoid the carriers in the semiconductor layer 100 flowing to the source electrode 300 or the drain electrode 200 through the gate electrode 400. For example, Figure 1 As shown, the drain-source current Ids flows from the drain electrode 200 to the source electrode 300 through the conductive channel formed in the contact region of the gate electrode 400 and the semiconductor layer 100. For example, when the gate electrode 400 is not connected to the electrical signal, the carrier depletion region 101 can be formed in the contact region of the gate electrode 400 and the semiconductor layer 100; after the gate electrode 400 is connected to the electrical signal, the carrier depletion region 101 is reduced, the carriers move from the conductive channel, and the drain electrode 200 and the source electrode 300 can be turned on to realize the switching function of the transistor. The contact region of the gate electrode 400 and the semiconductor layer 100 can form a Schottky barrier, and the size of the voltage signal connected to the gate electrode 400 can control the height of the barrier, thereby changing the width of the carrier depletion region 101 of the conductive channel, and further realizing the on and off of the conductive channel.

[0062] The transistor provided by the embodiment of the present application can form a vertical conductive channel on the semiconductor layer 100 by filling the first part 110 of the semiconductor layer 100 in the hollow region of the gate electrode 400, and the source electrode 300 and the drain electrode 200 are arranged on both sides of the semiconductor layer 100, respectively. Then, the current direction of the conductive channel is along the direction from the source electrode 300 to the drain electrode 200, or the current direction of the conductive channel is along the direction from the drain electrode 200 to the source electrode 300, which can be called as a vertical conductive channel or a vertical structure conductive channel.

[0063] It should be noted that the vertical structure of the transistor generally adopts the MIS structure, and the technical core of the vertical transistor adopting the MIS structure lies in the patterned net-shaped source electrode, which requires the source electrode to be thin and rough, so as to realize high light transmittance and form a large injection barrier when contacting the light-emitting unit, so as to change the Fermi level under the influence of the electric field and realize the switching function of the gate voltage. In order to obtain an extremely thin source electrode, a two-dimensional material is usually used to prepare the source electrode, and the two-dimensional material can be understood as a single-atom layer structure film. Common source electrode materials include CNT (carbon nanotube), SLG (graphene), Ag nanowire and other two-dimensional materials. However, the interface between the channel of the two-dimensional material and the insulating dielectric layer will form many trapping states, causing channel carrier scattering, seriously affecting the motion of the carriers enriched at the interface, and greatly reducing the mobility of the transistor. The performance of the vertical transistor depends largely on the type and quality of the dielectric layer material. Although the dielectric layer with high dielectric constant has good quality, it is expensive and rare, and does not have market advantages. The preparation method of two-dimensional materials such as carbon nanotubes and graphene is usually solution, nano-imprinting and other means, which cannot be mass-produced, and will affect the mass production application of the transistor.

[0064] To solve the above problems, the transistor provided by the embodiment of the present application is characterized in that the first part 110 of the semiconductor layer 100 is filled in the hollow area of the gate 400 to form a vertical conductive channel on the semiconductor layer 100, and the source electrode 300 and the drain electrode 200 are arranged on the two sides of the semiconductor layer 100, respectively. The current direction of the conductive channel is along the connection direction of the source electrode 300 and the drain electrode 200, so as to form a vertical structure transistor. Compared with the traditional vertical transistor, the vertical conductive channel can be used without using an extremely thin source electrode, and the source electrode and the drain electrode can be prepared by using conventional conductive materials, which can avoid reducing the channel carrier mobility by using an extremely thin source electrode, and can improve the mass production and facilitate the large-scale production of the transistor. In addition, compared with the traditional vertical transistor, the vertical structure transistor obtained by arranging the vertical conductive channel can reduce the size of the transistor while ensuring the conductive performance of the transistor, that is, the area occupied by the transistor can be reduced, and the transistor can be used for more flexible circuit layout.

[0065] In some embodiments, Figure 2 Another schematic structural diagram of a transistor is provided by the embodiment of the present application. As shown in Figure 2 The semiconductor layer 100 further includes a second part 120, and the second part 120 and the first part 110 are arranged in a stacked manner in the thickness direction. The second part 120 covers the first part 110 and the second part 120 in the orthographic projection on the plane where the gate 400 is located.

[0066] In some embodiments, the second part is arranged between the gate and the source electrode. For example, Figure 2In some embodiments, the second portion 120 is disposed close to the source electrode 300.

[0067] In some embodiments, the second portion 120 can also be disposed between the gate electrode 400 and the drain electrode 200, for example, as shown in FIG. 1C. Figure 1 As shown in FIG. 1C, the second portion is disposed close to the drain electrode 200.

[0068] In some embodiments, the semiconductor layer 100 is disposed with the first portion 110 between the second portions 120, i.e., the first portion 110 is disposed on both sides of the second portions 120. For example, as shown in FIG. 1D, the semiconductor layer 100 is disposed with the first portion 110 between the second portions 120. Figure 3 FIG. 1E shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 3 As shown in FIG. 1E, the semiconductor layer 100 is disposed with the second portion 120 close to the source electrode 300 and close to the drain electrode 200.

[0069] In some embodiments, the semiconductor layer 100 is disposed apart from the gate electrode 400. For example, as shown in FIG. 1F, the semiconductor layer 100 is disposed apart from the gate electrode 400. Figure 4 FIG. 1G shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 4 As shown in FIG. 1G, the orthographic projection of the gate electrode 400 on the source electrode 300 does not overlap with the orthographic projection of the semiconductor layer 100 on the source electrode 300.

[0070] It should be noted that the number of hollowed-out regions of the transistor shown in FIG. 1H is only illustrative and is not a specific limitation of the embodiments of the present application. Figures 1 to 4 It should be noted that the number of hollowed-out regions of the transistor shown in FIG. 1H is only illustrative and is not a specific limitation of the embodiments of the present application.

[0071] It should be noted that the transistor provided by the embodiments of the present application can be used as a driving device in a driving circuit of a display panel and can be applied to a liquid crystal display panel, an organic light-emitting display panel or other types of display panels, which are not specifically limited by the embodiments of the present application.

[0072] For example, as shown in FIG. 2A, the semiconductor layer 100 is disposed with the first portion 110 between the second portions 120. Figure 5 FIG. 2A shows a schematic structural diagram of a transistor according to an embodiment of the present application. Figure 6 FIG. 2B shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 7 FIG. 2C shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 8 FIG. 2D shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 9 FIG. 2E shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figure 10 FIG. 2F shows a schematic structural diagram of another transistor according to an embodiment of the present application. Figures 5-10As shown, the gate electrode 400 is a connection body, and a plurality of hollow regions are arranged on the gate electrode 400, and the first part 110 of the semiconductor layer 100 is filled in the hollow regions. The number of the hollow regions can be multiple, and the number of the hollow regions can be set according to the number requirement of the conductive channel. The conductive channel is formed in the hollow region. The hollow region can be any shape, for example Figures 5-9 the hollow region is a rectangle, Figure 10 the hollow region is a circle. Then Figures 5-10 As shown, the gate electrode 400 is in a grid shape, and the first part 110 of the semiconductor layer 100 can be filled in the hollow region in the grid shape. Figures 5-7 The shape of the hollow region is only a schematic representation and is not a specific limitation of the present application.

[0073] In some embodiments, the transistor can further include a light-emitting structure arranged between the semiconductor layer 100 and the drain electrode 200. The light-emitting structure can also be arranged between the semiconductor layer 100 and the source electrode 300. The light-emitting structure can include a hole transport layer, a light-emitting layer, and an electron transport layer stacked in sequence. The light-emitting layer is arranged between the hole transport layer and the electron transport layer, and the electron transport layer is arranged between the light-emitting layer and the semiconductor layer. The combination of the organic light-emitting diode and the transistor can obtain an organic light-emitting transistor. The organic light-emitting transistor can be used to prepare a display panel. The driving circuit of the display panel prepared by using the organic light-emitting transistor can be provided with one less driving transistor. The occupied space of the driving circuit can be reduced, the aperture ratio of the display panel can be increased, the light-emitting area of the display panel can be increased, and thus the light-emitting efficiency and brightness of the display panel can be improved.

[0074] Exemplarily, Figure 11 Another schematic structural diagram of a transistor is provided for the embodiments of the present application. As shown, Figure 11 The transistor further includes a substrate layer 600 and a light-emitting structure 700. The light-emitting structure 700 can include an electron transport layer ETL, a light-emitting layer EML, a hole transport layer HTL, and a hole injection layer HIL. The light-emitting structure 700 is arranged between the drain electrode 200 and the semiconductor layer 100. A gate-source voltage Vgs can be formed between the source electrode 300 and the gate electrode 400, and a source-drain voltage Vds can be formed between the drain electrode 200 and the source electrode 300.

[0075] Exemplarily, Figure 11The organic light-emitting transistor shown can be understood as an organic light-emitting diode with a gate 400 inserted in the middle. When the gate 400 is not connected to a voltage, the metal of the gate 400 and the semiconductor layer are in Schottky contact, with a large potential barrier. The contact area between the gate 400 and the semiconductor layer 100 is in a carrier depletion region. The source 300 can act as a cathode for driving the light-emitting structure 700 to emit light, and the drain 200 can act as an anode for driving the light-emitting structure 700 to emit light. When the gate 400 is not connected to a voltage, the source 300 and the drain 200 are not conductive, and the organic light-emitting transistor does not work. In the case of applying a voltage to the gate 400, the Schottky barrier changes under the action of the electric field, and carriers can pass through the gate 400 to reach the light-emitting layer EML, meet the charges from the drain 200, and emit light. The organic light-emitting transistor works normally.

[0076] As an example, as shown in the figure, the source 300 is connected to ground, and the gate 400 and the drain 200 are connected to a positive voltage. When the gate-source voltage Vgs reaches the threshold voltage, the Schottky gate opens, and the holes injected from the source 300 end can pass through the gate 400 to reach the light-emitting layer EML, meet the electrons from the drain 200 end, and recombine to emit light. Figure 11

[0077] In some embodiments, the work function of the material of the gate 400 is greater than the work function of the material of the semiconductor layer 100. The work function of the material of the gate 400 is greater than 3eV.

[0078] In some embodiments, the gate 400 includes a metal layer and at least two metal oxide layers arranged on both sides of the metal layer. The work function of the material of the metal oxide layer is greater than the work function of the material of the metal layer.

[0079] In some embodiments, the size of the hollow region is less than or equal to 1 μm, and the size of the hollow region determines the size of the conductive channel. It should be noted that the length of the conductive channel is the size in the direction of the flow of current in the conductive channel, and the width of the conductive channel is the size perpendicular to the length direction. The width-to-length ratio of the conductive channel can determine the electrical performance of the device.

[0080] It should be noted that a key point for the metal-semiconductor field effect transistor to work is to have a reliable and stable Schottky gate to control the on and off of the channel. To construct a stable and reliable Schottky gate, two conditions need to be met: first, select two suitable conductor and semiconductor materials with obvious work function difference as the gate and the conductive channel respectively, which can theoretically form a strong Schottky barrier; second, the size of the holes between the grid-shaped or comb-shaped gates needs to be controlled within a certain range, usually in the sub-micron level, so as to ensure that the device can be turned on smoothly, and the on-state current of the device will not be limited.

[0081] ​For example, the transistor of the embodiment of the present application can be made of MoOx (molybdenum oxide, x can be a natural number greater than 0) and Au (gold) with high work function to form a symmetrical stacked gate. The material work function of MoOx is 6.6 eV, and the material work function of Au is 5.1 eV. The MoOx and Au form an ohmic contact. The work function of the semiconductor layer 100 can be lower than the material work function of the gate. The material work function of the semiconductor layer 100 is generally less than 3 eV, and the material work function of the gate 400 is greater than 3 eV, so that a stable Schottky barrier can be formed. The structure of the gate 400 can be MoOx-Au-MoOx, wherein the thickness of Au is about 10 nm, and the thickness of MoOx on both sides is 120 nm.

[0082] In some embodiments, the gate 400 includes a stack of at least two layers of different metal materials. The gate can also be a single layer of gold or a stack of gold and other metal materials, which is not specifically limited in the embodiment of the present application.

[0083] In some embodiments, the material of the semiconductor layer 100 is a p-type material, and the gate 400 is used to input a positive voltage signal.

[0084] In some embodiments, the material of the semiconductor layer 100 is an n-type material, and the gate 400 is used to input a negative voltage signal.

[0085] For example, the material of the drain 200 and the source 300 can be at least one of ITO (indium tin oxide), gold, silver, aluminum, magnesium, etc. The drain 200 can be made of a transparent electrode ITO, and a patterned electrode can be prepared on the substrate by etching.

[0086] For example, the materials of the hole injection layer HIL, the hole transport layer HTL, and the light emitting layer EML can be selected from the common material system of organic light emitting diodes, such as Alq3, Ir(ppy)3, Firpic (light emitting material), NPB, Bphen, TPBi (electron transport layer material), CBP, TAPC (hole transport layer material), etc. High-mobility organic transport materials and high-efficiency light emitting layer materials can be selected. The organic materials can be prepared by vacuum evaporation. The selection and thickness adjustment of each film layer material will affect the device performance and light emitting color.

[0087] For example, the semiconductor layer 100 can be made of a high-mobility p-type material, such as C60, ZnO, a-IGZO, etc. C60 can be prepared by evaporation with a thickness of about 100 nm.

[0088] In a second aspect, the embodiment of the present application provides a preparation method of a transistor, comprising:

[0089] The semiconductor layer, the source electrode, the drain electrode, the first insulating layer, the second insulating layer and the gate electrode are respectively arranged, wherein the drain electrode and the source electrode are respectively arranged on two sides of the semiconductor layer in the thickness direction, the gate electrode comprises a plurality of hollow regions spaced from each other, the semiconductor layer at least comprises a first part filled in the hollow region, the first insulating layer is arranged on the surface of the gate electrode close to the source electrode in the thickness direction, and the second insulating layer is arranged on the surface of the gate electrode close to the drain electrode in the thickness direction.

[0090] The transistor prepared by the preparation method of the transistor provided in the embodiments of the present application is prepared by filling the first part 110 of the semiconductor layer 100 in the hollow region of the gate electrode 400 to form a vertical conductive channel on the semiconductor layer 100, and the source electrode 300 and the drain electrode 200 are respectively arranged on two sides of the semiconductor layer 100, so that the current direction of the conductive channel is along the connection direction of the source electrode 300 and the drain electrode 200 to form a vertical structure transistor. Compared with the conventional vertical transistor, the vertical conductive channel can be used without using an extremely thin source electrode, the source electrode and the drain electrode can be prepared by using conventional conductive materials, the channel carrier mobility can be improved by avoiding the use of an extremely thin source electrode, and the mass production can be improved to facilitate the large-scale production of the transistor. In addition, compared with the conventional vertical transistor, the vertical structure transistor obtained by arranging the vertical conductive channel can reduce the size of the transistor while ensuring the conductive performance of the transistor, that is, the area occupied by the transistor can be reduced, and the circuit layout can be more flexible.

[0091] In some embodiments, Figure 12 A schematic flowchart of a preparation method of a transistor is provided in the embodiments of the present application. As shown in Figure 12 The semiconductor layer, the source electrode, the drain electrode, the first insulating layer, the second insulating layer and the gate electrode are respectively arranged, comprising:

[0092] The source electrode 300 is arranged;

[0093] The light-emitting structure 700 is arranged on one side of the source electrode 300;

[0094] The support ball layer is arranged on the side of the light-emitting structure 700 away from the source electrode 300, wherein the support ball layer comprises a plurality of support balls PS, and the support balls PS are dispersed on the surface of the light-emitting structure 700 away from the source electrode 300;

[0095] The first insulating layer 510, the gate electrode 400 and the second insulating layer 520 are sequentially arranged, wherein the first insulating layer 510, the gate electrode 400 and the second insulating layer 520 are sequentially filled between adjacent support balls PS;

[0096] The support ball layer is removed to form a hollow region in the region where the support ball PS is located;

[0097] The semiconductor layer 100 and the drain 200 are arranged respectively, so that the first part 110 of the semiconductor layer 100 is filled in the hollowed area, and the drain 200 is located on the side of the semiconductor layer 100 away from the source 300.

[0098] For example, the support balls PS can be polystyrene nanoparticles, and the support ball layer can be obtained by spin-coating a polystyrene nanoparticle solution on the surface of the light-emitting structure 700, so that the support balls PS are uniformly dispersed on the surface of the light-emitting structure 700, and then the MoO3-Au-MoO3 gate electrode is evaporated. Due to the shielding effect of the support balls PS, the gate electrode 400 does not completely cover the light-emitting structure 700. After the support balls PS are removed by a mechanical peeling method, the gate electrode 400 in the form of a hole is left, and then the semiconductor layer 100 and the drain 200 can be normally evaporated.

[0099] For example, the support balls PS can be polystyrene nanoparticles, and the support ball layer can be obtained by spin-coating a polystyrene nanoparticle solution on the surface of the light-emitting structure 700, so that the support balls PS are uniformly dispersed on the surface of the light-emitting structure 700, and then the MoO3-Au-MoO3 gate electrode is evaporated. Due to the shielding effect of the support balls PS, the gate electrode 400 does not completely cover the light-emitting structure 700. After the support balls PS are removed by a mechanical peeling method, the gate electrode 400 in the form of a hole is left, and then the semiconductor layer 100 and the drain 200 can be normally evaporated. Figure 13 A schematic flowchart of another method for manufacturing a transistor is provided in the embodiments of the present application. As shown in Figure 13 The first insulating layer 510, the gate electrode 400 and the second insulating layer 520 are sequentially stacked, and the shapes of the first insulating layer 510, the gate electrode 400 and the second insulating layer 520 at the positions close to the support balls PS are matched with each other.

[0100] In a third aspect, the embodiments of the present application provide a display panel, Figure 14 A schematic structural diagram of a display panel is provided in the embodiments of the present application. As shown in Figure 14 The display panel provided in the embodiments of the present application includes a plurality of transistors 1000 as described in the first aspect. The transistor described in the first aspect can be a driving transistor or an organic light-emitting transistor. The transistor 1000 can be used as a driving device in the circuit of the display panel, and the transistor 1000 can also be used as a light-emitting device of the display panel to directly realize display. The electrical performance of the transistor 1000 described in the first aspect is better than that of a conventional vertical transistor, the transistor occupies less space than a horizontal channel transistor, and is also conducive to large-scale mass production. Therefore, the display panel can have better display effect, larger display aperture ratio, larger brightness and light-emitting efficiency.

[0101] In a fourth aspect, the embodiments of the present application provide a display device, Figure 15 A schematic structural diagram of a display device is provided in the embodiments of the present application. As shown in Figure 14 The display device provided in the embodiments of the present application includes the display panel 2000 as described in the third aspect.

[0102] The display device provided in the embodiments of the present application can be a smartphone, a tablet computer, a notebook computer, a television or other display, and the like, which is not specifically limited in the embodiments of the present application.

[0103] It should be noted that in the above examples, the description of each example has its own emphasis, and the parts not described in detail in a certain example can be seen from the related description of other examples.

[0104] The above examples are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0105] Although the preferred embodiments of the present specification have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present specification.

[0106] Obviously, those skilled in the art can make various modifications and variations to the present specification without departing from the spirit and scope of the present specification. Thus, if these modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalent technologies, the present specification also intends to include these modifications and variations.

Claims

1. A transistor, characterized in that, include: A gate, the gate comprising a plurality of spaced-apart cutout regions; A semiconductor layer, the semiconductor layer including at least a first portion filling the hollowed-out region; The drain and source are respectively disposed on both sides of the semiconductor layer in the thickness direction; A first insulating layer is disposed on the surface of the gate electrode on the side close to the source electrode in the thickness direction; A second insulating layer is disposed on the surface of the gate electrode on the side close to the drain electrode in the thickness direction; Light-emitting structure; The light-emitting structure is disposed between the semiconductor layer and the drain electrode, or the light-emitting structure is disposed between the semiconductor layer and the source electrode; The light-emitting structure includes: a hole transport layer, a light-emitting layer, and an electron transport layer; the light-emitting layer is disposed between the hole transport layer and the electron transport layer, and the electron transport layer is disposed between the light-emitting layer and the semiconductor layer; The work function of the gate material is greater than the work function of the semiconductor layer. A Schottky barrier is formed at the contact area between the gate and the semiconductor layer. When a voltage is applied to the gate, the Schottky barrier is changed by the electric field modulation, and charge carriers can pass through the gate to reach the light-emitting layer and emit light when they meet the charge from the drain. The gate includes a metal layer and at least two metal oxide layers, the metal oxide layers being disposed on both sides of the metal layer, and the work function of the metal oxide layers being greater than the work function of the metal layer. The first insulating layer, the gate, and the second insulating layer, which are stacked in sequence, are shaped to match each other at positions close to the support spheres. During fabrication, the support spheres are dispersed on the surface of the light-emitting structure away from the source electrode. The first insulating layer, the gate, and the second insulating layer are sequentially filled between adjacent support spheres. After removing the support spheres, the hollow area is formed in the region where the support spheres are located.

2. The transistor according to claim 1, characterized in that, The semiconductor layer further includes a second portion, which is stacked with the first portion in the thickness direction, and the orthogonal projection of the second portion onto the plane where the gate is located covers the first portion and the second portion.

3. The transistor according to claim 2, characterized in that, The second portion is disposed between the gate and the source, and / or the second portion is disposed between the gate and the drain.

4. The transistor according to claim 1, characterized in that, The gate includes multiple hollow areas.

5. The transistor according to claim 1, characterized in that, The work function of the gate material is greater than 3 eV.

6. The transistor according to claim 1, characterized in that, The gate comprises at least two layers of different metallic materials stacked together.

7. The transistor according to claim 1, characterized in that, The size of the hollowed-out area is less than or equal to 1 μm.

8. The transistor according to claim 1, characterized in that, The semiconductor layer is made of a p-type material, and the gate is used to receive a positive voltage signal; or... The semiconductor layer is made of an n-type material, and the gate is used to receive a negative voltage signal.

9. A method for fabricating a transistor, characterized in that, The method for fabricating a transistor as described in any one of claims 1 to 8 comprises: A semiconductor layer, a source electrode, a light-emitting structure, a drain electrode, a first insulating layer, a second insulating layer, and a gate electrode are respectively provided. The drain electrode and the source electrode are respectively disposed on opposite sides of the semiconductor layer in the thickness direction. The gate electrode includes a plurality of spaced-apart cutout regions. The semiconductor layer includes at least a first portion filling the cutout regions. The first insulating layer is disposed on the surface of the gate electrode near the source electrode in the thickness direction. The second insulating layer is disposed on the surface of the gate electrode near the drain electrode in the thickness direction.

10. The method for fabricating a transistor according to claim 9, characterized in that, The method of respectively providing a semiconductor layer, a source electrode, a light-emitting structure, a drain electrode, a first insulating layer, a second insulating layer, and a gate electrode includes: Set the source pole; A light-emitting structure is provided on one side of the source electrode; A support ball layer is provided on the side of the light-emitting structure away from the source electrode, wherein the support ball layer includes a plurality of support balls, and the support balls are dispersed on the surface of the light-emitting structure away from the source electrode; The first insulating layer, the gate, and the second insulating layer are sequentially disposed, wherein the first insulating layer, the gate, and the second insulating layer are sequentially filled between adjacent support balls; Remove the supporting ball layer to form the hollow area in the region where the supporting ball is located; The semiconductor layer and the drain are respectively provided, such that the first portion of the semiconductor layer fills the hollow area, and the drain is located on the side of the semiconductor layer away from the source.

11. A display panel, characterized in that, include: Multiple transistors as described in any one of claims 1-8.

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