A spatially coupled LDPC code and its construction method and system
By adjusting the parity check matrix structure of spatially coupled LDPC codes to form a combination of diagonal bands and sub-diagonal structures, the problem of insufficient error correction capability of existing LDPC codes in the face of burst erasure errors is solved, the decoding performance is improved, and the decoding threshold is lowered.
Patent Information
- Application Number
- CN202210899252.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-28
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2042-07-28
AI Technical Summary
The existing spatially coupled LDPC code structure cannot meet the performance requirements of modern communication systems, especially the insufficient error correction capability when facing burst erasure errors.
A periodic time-varying spatially coupled LDPC code with a period of 2 is used. By adjusting the arrangement of the check matrix, a combination of a diagonal band structure and a sub-diagonal structure is formed to generate an asymmetric check matrix structure, and check nodes are added at both ends of the coupling chain.
The decoding performance is improved and the decoding threshold is lowered. Simulation results show that there is a gain of 0.9dB to 1.1dB at a bit error rate of 10-4.
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Figure CN115189697B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a spatially coupled LDPC code and a construction method and system thereof, belonging to the technical field of communications. Background Art
[0002] Gallager's proposal of LDPC codes in 1962 sparked a wave of research, but discussions were primarily focused on block codes. In 1987, Tanner began focusing on spatially coupled structures similar to convolution. With the rediscovery of LDPC codes in the 1990s, it was discovered that simple methods could be used to construct LDPC codes with convolutional properties, resulting in significant gains. Spatially coupled low-density parity-check codes (SC-LDPC) are a subclass of LDPC codes that enable high-capacity transmission over channels. SC-LDPC codes are constructed by coupling L disjoint LDPC code graphs. When L approaches infinity, spatially coupled low-density parity-check convolutional codes (SC-LDPC-CCs) are obtained. SC-LDPC codes combine the advantages of both regular and irregular LDPC codes. Their key feature is that they achieve the performance of irregular LDPC codes in the waterfall region while reducing the error floor while maintaining good waterfall performance.
[0003] Since the diagonal structure of SC-LDPC codes cannot meet current performance requirements, an improvement scheme for the SC-LDPC code structure is proposed. Summary of the Invention
[0004] The present invention provides a spatially coupled LDPC code and a construction method and system thereof, which solve the problems disclosed in the background technology.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a spatially coupled LDPC code, wherein the spatially coupled LDPC code is:
[0006]
[0007] is the matrix of each sub-LDPC code that constitutes the spatially coupled LDPC code, m s is the constraint length of the spatially coupled LDPC code.
[0008] Accordingly, a spatially coupled LDPC code construction method is to convert the time Placed at the bottom, 2 moments Place it from a position higher than time 1, and the rows and columns are not aligned with time 1 Overlap occurs, and so on; when the Position and original H i , i=0,1,2…, when the positions are the same, H i Cover. Every moment They are placed from the lower left to the upper right to form a diagonal structure. At this time, the spatially coupled LDPC structure is a combination of a diagonal band structure and a sub-diagonal structure.
[0009] Furthermore, a periodic time-varying spatially coupled LDPC code with a period of 2 is selected, and its exponential matrix P is:
[0010]
[0011] Furthermore, the spatially coupled LDPC code construction system converts the time Placed at the bottom, 2 moments Place it from a position higher than time 1, and the rows and columns are not aligned with time 1 Overlap occurs, and so on; when the Position and original H i , i=0,1,2…, when the positions are the same, H i Cover. Every moment They are placed from the lower left to the upper right to form a diagonal structure. At this time, the spatially coupled LDPC structure is a combination of a diagonal band structure and a sub-diagonal structure.
[0012] Furthermore, the spatially coupled LDPC code construction system selects a periodic time-varying spatially coupled LDPC code with a period of 2, and its exponential matrix P is:
[0013]
[0014] Accordingly, a computer-readable storage medium stores one or more programs: the one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform any one of the methods described above.
[0015] Accordingly, a computing device includes:
[0016] One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods. The beneficial effects achieved by the present invention are:
[0017] The parity check matrix generated by this method is simple, easy to implement, and has a clear structure. Compared to the traditional diagonal band structure, this method combines a subdiagonal structure and adds check nodes at both ends of the coupling chain, resulting in excellent decoding performance. Simulation analysis shows that the parity check matrix generated by this method has a lower threshold and significantly improves decoding performance, with a gain of 0.9dB to 1.1dB at a bit error rate of 10-4. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a comparison diagram of SC-LDPC decoding curves with a code length of 1500 in the present invention;
[0019] Figure 2 This is a comparison diagram of the SC-LDPC decoding curves of the present invention with a code length of 3000. DETAILED DESCRIPTION
[0020] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.
[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] The representation of traditional SC-LDPC code is as follows:
[0023]
[0024] is the matrix of each sub-LDPC code that makes up the SC-LDPC code, m s is the constraint length of the SC-LDPC code.
[0025] Can also be defined At the same time, it can be expressed as a symbolic matrix H(D) = [H0|D·H1|...|D T-1 ·H T-1 ], where each H(D) is H s The symbol matrix of , T is the period, when T = 1, the generated matrix is time-invariant, otherwise it is time-varying.
[0026] The exponential matrix P is the matrix of the exponent of D in H(D). The general exponential matrix expression is
[0027] The check matrix expression can be obtained from the exponential matrix.
[0028] The present invention improves the traditional SC-LDPC coding structure and proposes an improved structure. The improved SC-LDPC expression is as follows:
[0029]
[0030] In the present invention, the Placed at the bottom, 2 moments Place it from a position higher than time 1, and the rows and columns are not aligned with time 1 Overlap occurs, and so on. Position and original H i , i=0,1,2…, when the positions are the same, H i Cover. Every moment They are placed from the lower left to the upper right to form a diagonal structure. At this time, the SC-LDPC structure is a combination of a diagonal strip structure and a sub-diagonal structure.
[0031] In this implementation case, a periodic time-varying SC-LDPC code with a period of 2 is selected, and its exponential matrix P is
[0032] The present invention breaks the traditional structure of the SC-LDPC code, splits the diagonal band, and constructs an asymmetric structure, which also has good error correction capability when facing sudden erasure errors.
[0033] like Figure 1 As shown, this implementation case uses a check matrix with a code length of 1500 for simulation. The decoding threshold of the original check matrix is 1.253dB, and the decoding threshold of the check matrix obtained by the above structure is 1.241dB, which is reduced by 0.012dB. At the same time, the decoding curve is obtained by simulation.
[0034] like Figure 2 As shown, this implementation case uses a check matrix with a code length of 3000 for simulation. The decoding threshold of the original check matrix is 1.14dB, and the decoding threshold of the check matrix obtained by the above structure is 1.13dB, which is reduced by 0.01dB. At the same time, the decoding curve is obtained by simulation.
[0035] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
[0036] A computer-readable storage medium stores one or more programs, wherein the one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform a spatially coupled LDPC code construction method.
[0037] A computing device includes one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a spatially coupled LDPC code construction method.
[0038] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0039] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0040] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0041] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0042] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.
Claims
1. A method for constructing spatially coupled LDPC codes, characterized in that: The spatially coupled LDPC code is: ; are the sub-LDPC code matrices that make up the spatially coupled LDPC code, is the constraint length of the spatially coupled LDPC code; 1 moment Placed at the bottom, 2 moments Place it from a position higher than time 1, and the rows and columns are not aligned with time 1 Overlap occurs, and so on; when the Location and origin , i=0, 1, 2…, when the positions are the same, Will Cover; every moment They are placed from the lower left to the upper right to form a diagonal structure. At this time, the spatially coupled LDPC structure is a combination of a diagonal band structure and a sub-diagonal structure.
2. A method for constructing spatially coupled LDPC codes according to claim 1, characterized in that: A periodic time-varying spatially coupled LDPC code with a period of 2 is selected, and its exponential matrix P is: 。 3. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any one of the methods according to claim 1 or 2.
4. A computing device, characterized in that include: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing any of the methods according to claim 1 or 2.
Citation Information
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